Instance: TCM
Component: TCM
Base address: 0x40007000
IO Controller
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x6F44 0010 |
0x0000 0000 |
0x4000 7000 |
|
|
RO |
32 |
0x0000 0029 |
0x0000 0004 |
0x4000 7004 |
|
|
RW |
32 |
0x2000 0100 |
0x0000 0008 |
0x4000 7008 |
|
|
RW |
32 |
0xC00F F07F |
0x0000 000C |
0x4000 700C |
|
|
RW |
32 |
0xC0FF FFF8 |
0x0000 0010 |
0x4000 7010 |
|
|
RW |
32 |
0x6001 FFFF |
0x0000 0014 |
0x4000 7014 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x4000 7000 | Instance | 0x4000 7000 |
| Description | This register identifies the peripheral and its exact version. This register is strictly read-only. Any write to this register will trigger chip reset. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | MODID | Module identification contains a unique peripheral identification number. | RO | 0x6F44 | ||
| 15:12 | STDIPOFF | Standard IP registers offset. Value 0 indicates Standard IP registers are not present. Any other value between 1 to 15 indicates standard IP registers start from address offset 64 * STDIPOFF from base address. | RO | 0x0 | ||
| 11:8 | INSTIDX | Instance Index within the device. This will be a parameter to the RTL for modules that can have multiple instances. | RO | 0x0 | ||
| 7:4 | MAJREV | Major rev of the IP | RO | 0x1 | ||
| 3:0 | MINREV | Minor rev of the IP | RO | 0x0 | ||
| Address Offset | 0x0000 0004 | ||
| Physical Address | 0x4000 7004 | Instance | 0x4000 7004 |
| Description | This register identifies the peripheral and its exact version. This register is strictly read-only. Any write to this register will trigger chip reset. |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | ||
| 8:0 | GSKCNT | Number of gaskets | RO | 0b0 0010 1001 | ||
| Address Offset | 0x0000 0008 | ||
| Physical Address | 0x4000 7008 | Instance | 0x4000 7008 |
| Description | This register blocks writes to all the MMR of TCM once set. This register is protected by odd parity bit. It is sticky 1. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31 | RESERVED31 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0 | |||||||||||
| 30:29 | PAR | Parity bit. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. PAR[29] = ~WEN PAR[30] = ~SYNC |
RW | 0b01 | |||||||||||
| 28:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x0 0000 | |||||||||||
| 8 | SYNC | Program this bit to 0 before writing to WMCFG or any of the gasket enable MMR i.e. GSKEN0, GSKEN1 etc. Once the MMR writes are done, program this bit to 1 again. Then WEN can be programmed 1 to lock the configuration. Note: Do not toggle SYNC and WEN in the same cycle
|
RW | 1 | |||||||||||
| 7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||
| 0 | WEN | Write enable
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 000C | ||
| Physical Address | 0x4000 700C | Instance | 0x4000 700C |
| Description | This register is used to configure SRAM and VIMS watermark. This register is protected by odd parity bits. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | PAR | Parity bits. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. Bit 31 stores the odd parity of bits 23 to 16. PAR[29] = ~XOR(VIMSWM[7:0]) PAR[30] = ~XOR({[VIMSWM[9:8]], SRAMWM[15:12]}) PAR[31] = ~XOR(SRAMWM[21:16]) |
RW | 0b110 | ||
| 28:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 0000 | ||
| 19:12 | SRAMWM | SRAM Watermark. The address from (SRAM Base Address) to (SRAM Base Address + (SRAMWM + 1)<<10 - 1) is considered secure. The address from (SRAM Base Address + (SRAMWM + 1) <<10) to (SRAM Last Address) is considered Non-secure. |
RW | 0xFF | ||
| 11:7 | RESERVED7 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| 6:0 | VIMSWM | VIMS Watermark The address from (Flash Main Base Address) to (Flash Main Base Address + (VIMSWM + 1)<<13 - 1) is considered secure. The address from (Flash Main Base Address + (VIMSWM + 1)<<13) to (Flash Main Last Address) is considered Non-secure. |
RW | 0b111 1111 | ||
| Address Offset | 0x0000 0010 | ||
| Physical Address | 0x4000 7010 | Instance | 0x4000 7010 |
| Description | This register is used to store gasket configuration. This register is protected by odd parity bits. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | PAR | Parity bits. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. Bit 31 stores the odd parity of bits 23 to 16. PAR[29] = ~XOR(GSKEN0[7:0]) PAR[30] = ~XOR(GSKEN0[15:8]) PAR[31] = ~XOR(GSKEN0[23:16]) |
RW | 0b110 | ||
| 28:24 | RESERVED24 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b0 0000 | ||
| 23:0 | EN | Gasket enable. The gasket bit to IP mapping is given as follows :- [0] = DMA initiator gasket enable [1] = I2S initiator gasket enable [2] = HSM initiator gasket enable [3] = Radio target gasket enable [4] = AES target gasket enable [5] = I2S target gasket enable [6] = PDM target gasket enable [7] = AFA target gasket enable [8] = DMA target gasket enable [9] = CANFD target gasket enable [10] = APU target gasket enable [11] = APURAM target gasket enable [12] = GPIO target gasket enable [13] = SYSTIMER target gasket enable [14] = UART0 target gasket enable [15] = UART1 target gasket enable [16] = SPI0 target gasket enable [17] = SPI1 target gasket enable [18] = I2C0 target gasket enable [19] = EVTSVT target gasket enable [20] = ADC target gasket enable [21] = MICADC target gasket enable [22] = MICPGA target gasket enable [23] = CLKCTRL target gasket enable |
RW | 0xFF FFF8 | ||
| Address Offset | 0x0000 0014 | ||
| Physical Address | 0x4000 7014 | Instance | 0x4000 7014 |
| Description | This register is used to store gasket configuration. This register is protected by odd parity bits. | ||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:29 | PAR | Parity bits. Bit 29 stores the odd parity for bits 0 to 7. Bit 30 stores the odd parity of bits 8 to 15. Bit 31 stores the odd parity of bits 23 to 16. PAR[29] = ~XOR(GSKEN1[7:0]) PAR[30] = ~XOR(GSKEN1[15:8]) PAR[31] = ~XOR(GSKEN1[23:16]) |
RW | 0b011 | ||
| 28:17 | RESERVED17 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 16:0 | EN | Gasket enable. The gasket bit to IP mapping is given as follows :- [0] = LGPT target gasket enable [1] = FLASH target gasket enable [2] = VIMS target gasket enable [3] = HSM target gasket enable [4] = PMC target gasket enable [5] = CKMDIG target gasket enable [6] = RTC target gasket enable [7] = IOC target gasket enable [8] = SYS0 target gasket enable [9] = EVTULL target gasket enable [10] = PMUDIG target gasket enable [11] = DEBUGSS target gasket enable [12] = HSM mailbox 1 target gasket enable [13] = HSM mailbox 2 target gasket enable [14] = HSM mailbox 3 target gasket enable [15] = HSM mailbox 4 target gasket enable [16] = HSM config target gasket enable |
RW | 0b1 1111 1111 1111 1111 | ||
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