Instance: SRAMCTRL
Component: SRAMCTRL
Base address: 0x400C5000
System SRAM Controller
|
Register Name |
Type |
Register Width (Bits) |
Register Reset |
Address Offset |
Physical Address |
|
RO |
32 |
0x1A48 0010 |
0x0000 0000 |
0x400C 5000 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0100 |
0x400C 5100 |
|
|
RW |
32 |
0x0000 0000 |
0x0000 0110 |
0x400C 5110 |
|
|
RO |
32 |
0x0000 0000 |
0x0000 0114 |
0x400C 5114 |
| Address Offset | 0x0000 0000 | ||
| Physical Address | 0x400C 5000 | Instance | 0x400C 5000 |
| Description | This register identifies the peripheral |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:16 | MODID | Module identifier | RO | 0x1A48 | ||
| 15:12 | STDIPOFF | 64 B Standard IP MMR block 0: STDIP MMRs do not exist 1:15: These MMRs begin at offset 64*STDIPOFF from IP base address |
RO | 0x0 | ||
| 11:8 | INSTIDX | IP Instance number | RO | 0x0 | ||
| 7:4 | MAJREV | Major revision | RO | 0x1 | ||
| 3:0 | MINREV | Minor revision | RO | 0x0 | ||
| Address Offset | 0x0000 0100 | ||
| Physical Address | 0x400C 5100 | Instance | 0x400C 5100 |
| Description | Configuration Register |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | |||||||||||
| 31:9 | RESERVED9 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 0000 0000 0000 0000 | |||||||||||
| 8 | PARDBGEN | SRAM Parity Debug Enable.
|
RW | 0 | |||||||||||
| 7:1 | RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b000 0000 | |||||||||||
| 0 | PAREN | SRAM Parity Enable.
|
RW | 0 | |||||||||||
| Address Offset | 0x0000 0110 | ||
| Physical Address | 0x400C 5110 | Instance | 0x400C 5110 |
| Description | Parity error check debug address setting |
||
| Type | RW | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:20 | RESERVED20 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0x000 | ||
| 19:2 | ADDR | Debug Parity Error Address Offset.##br##When CFG.PARDBGEN is 1, this field is used to set a parity debug address offset. Writes within this address offset will force incorrect parity bits to be stored together with the data written. The following reads within this same address offset will thus result in parity errors to be generated. | RW | 0b00 0000 0000 0000 0000 | ||
| 1:0 | RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. | RO | 0b00 | ||
| Address Offset | 0x0000 0114 | ||
| Physical Address | 0x400C 5114 | Instance | 0x400C 5114 |
| Description | Parity error |
||
| Type | RO | ||
| Bits | Field Name | Description | Type | Reset | ||
| 31:0 | ADDR | Parity Error Address Offset.##br##This holds the address offset that first generated the parity error and an interrupt is generated. ##br##This register is 'Clear-On-Read' | RO | 0x0000 0000 | ||
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