FPB

Instance: FPB
Component: FPB
Base address: 0xE0002000


TOP:FPB Register Summary

Register Name

Type

Register Width (Bits)

Register Reset

Address Offset

Physical Address

FP_CTRL

32

0x1000 0080

0x0000 0000

0xE000 2000

FP_REMAP

32

0x0000 0000

0x0000 0004

0xE000 2004

FP_COMP0

32

0x0000 0000

0x0000 0008

0xE000 2008

FP_COMP1

32

0x0000 0000

0x0000 000C

0xE000 200C

FP_COMP2

32

0x0000 0000

0x0000 0010

0xE000 2010

FP_COMP3

32

0x0000 0000

0x0000 0014

0xE000 2014

FP_COMP4

32

0x0000 0000

0x0000 0018

0xE000 2018

FP_COMP5

32

0x0000 0000

0x0000 001C

0xE000 201C

FP_COMP6

32

0x0000 0000

0x0000 0020

0xE000 2020

FP_COMP7

32

0x0000 0000

0x0000 0024

0xE000 2024

FP_DEVARCH

32

0x4770 1A03

0x0000 0FBC

0xE000 2FBC

FP_DEVTYPE

32

0x0000 0000

0x0000 0FCC

0xE000 2FCC

FP_PIDR4

32

0x0000 0004

0x0000 0FD0

0xE000 2FD0

FP_PIDR5

32

0x0000 0000

0x0000 0FD4

0xE000 2FD4

FP_PIDR6

32

0x0000 0000

0x0000 0FD8

0xE000 2FD8

FP_PIDR7

32

0x0000 0000

0x0000 0FDC

0xE000 2FDC

FP_PIDR0

32

0x0000 0021

0x0000 0FE0

0xE000 2FE0

FP_PIDR1

32

0x0000 00BD

0x0000 0FE4

0xE000 2FE4

FP_PIDR2

32

0x0000 000B

0x0000 0FE8

0xE000 2FE8

FP_PIDR3

32

0x0000 0000

0x0000 0FEC

0xE000 2FEC

FP_CIDR0

32

0x0000 000D

0x0000 0FF0

0xE000 2FF0

FP_CIDR1

32

0x0000 0090

0x0000 0FF4

0xE000 2FF4

FP_CIDR2

32

0x0000 0005

0x0000 0FF8

0xE000 2FF8

FP_CIDR3

32

0x0000 00B1

0x0000 0FFC

0xE000 2FFC

TOP:FPB Register Descriptions

TOP:FPB:FP_CTRL

Address Offset 0x0000 0000
Physical Address 0xE000 2000 Instance 0xE000 2000
Description Provides FPB implementation information, and the global enable for the FPB unit
Type
Bits Field Name Description Type Reset
31:28 REV Flash Patch and Breakpoint Unit architecture revision RO 0x1
27:15 RES0 Reserved, RES0 RO 0b0 0000 0000 0000
14:12 NUM_CODE_14_12_ Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 RO 0b000
11:8 NUM_LIT Indicates the number of implemented literal address comparators. The Literal Address comparators are numbered from NUM_CODE to NUM_CODE + NUM_LIT - 1 RO 0x0
7:4 NUM_CODE_7_4_ Indicates the number of implemented instruction address comparators. Zero indicates no Instruction Address comparators are implemented. The Instruction Address comparators are numbered from 0 to NUM_CODE - 1 RO 0x8
3:2 RES0_1 Reserved, RES0 RO 0b00
1 KEY Writes to the FP_CTRL are ignored unless KEY is concurrently written to one RW 0
0 ENABLE Enables the FPB RW 0

TOP:FPB:FP_REMAP

Address Offset 0x0000 0004
Physical Address 0xE000 2004 Instance 0xE000 2004
Description Indicates whether the implementation supports Flash Patch remap and, if it does, holds the target address for remap
Type
Bits Field Name Description Type Reset
31:30 RES0 Reserved, RES0 RO 0b00
29 RMPSPT Indicates whether the FPB unit supports the Flash Patch remap function RO 0
28:5 REMAP Holds the bits[28:5] of the Flash Patch remap address RO 0x00 0000
4:0 RES0_1 Reserved, RES0 RO 0b0 0000

TOP:FPB:FP_COMP0

Address Offset 0x0000 0008
Physical Address 0xE000 2008 Instance 0xE000 2008
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP1

Address Offset 0x0000 000C
Physical Address 0xE000 200C Instance 0xE000 200C
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP2

Address Offset 0x0000 0010
Physical Address 0xE000 2010 Instance 0xE000 2010
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP3

Address Offset 0x0000 0014
Physical Address 0xE000 2014 Instance 0xE000 2014
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP4

Address Offset 0x0000 0018
Physical Address 0xE000 2018 Instance 0xE000 2018
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP5

Address Offset 0x0000 001C
Physical Address 0xE000 201C Instance 0xE000 201C
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP6

Address Offset 0x0000 0020
Physical Address 0xE000 2020 Instance 0xE000 2020
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_COMP7

Address Offset 0x0000 0024
Physical Address 0xE000 2024 Instance 0xE000 2024
Description Holds an address for comparison.
Type
Bits Field Name Description Type Reset
31:1 BPADDR Specifies bits[31:1] of the breakpoint instruction address RW 0b000 0000 0000 0000 0000 0000 0000 0000
0 BE Selects between remapping and breakpoint functionality RW 0

TOP:FPB:FP_DEVARCH

Address Offset 0x0000 0FBC
Physical Address 0xE000 2FBC Instance 0xE000 2FBC
Description Provides CoreSight discovery information for the FPB
Type
Bits Field Name Description Type Reset
31:21 ARCHITECT Defines the architect of the component. Bits [31:28] are the JEP106 continuation code (JEP106 bank ID, minus 1) and bits [27:21] are the JEP106 ID code. RO 0b010 0011 1011
20 PRESENT Defines that the DEVARCH register is present RO 1
19:16 REVISION Defines the architecture revision of the component RO 0x0
15:12 ARCHVER Defines the architecture version of the component RO 0x1
11:0 ARCHPART Defines the architecture of the component RO 0xA03

TOP:FPB:FP_DEVTYPE

Address Offset 0x0000 0FCC
Physical Address 0xE000 2FCC Instance 0xE000 2FCC
Description Provides CoreSight discovery information for the FPB
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 SUB Component sub-type RO 0x0
3:0 MAJOR Component major type RO 0x0

TOP:FPB:FP_PIDR4

Address Offset 0x0000 0FD0
Physical Address 0xE000 2FD0 Instance 0xE000 2FD0
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 SIZE See CoreSight Architecture Specification RO 0x0
3:0 DES_2 See CoreSight Architecture Specification RO 0x4

TOP:FPB:FP_PIDR5

Address Offset 0x0000 0FD4
Physical Address 0xE000 2FD4 Instance 0xE000 2FD4
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:0 RES0 Reserved, RES0 RO 0x0000 0000

TOP:FPB:FP_PIDR6

Address Offset 0x0000 0FD8
Physical Address 0xE000 2FD8 Instance 0xE000 2FD8
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:0 RES0 Reserved, RES0 RO 0x0000 0000

TOP:FPB:FP_PIDR7

Address Offset 0x0000 0FDC
Physical Address 0xE000 2FDC Instance 0xE000 2FDC
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:0 RES0 Reserved, RES0 RO 0x0000 0000

TOP:FPB:FP_PIDR0

Address Offset 0x0000 0FE0
Physical Address 0xE000 2FE0 Instance 0xE000 2FE0
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 PART_0 See CoreSight Architecture Specification RO 0x21

TOP:FPB:FP_PIDR1

Address Offset 0x0000 0FE4
Physical Address 0xE000 2FE4 Instance 0xE000 2FE4
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 DES_0 See CoreSight Architecture Specification RO 0xB
3:0 PART_1 See CoreSight Architecture Specification RO 0xD

TOP:FPB:FP_PIDR2

Address Offset 0x0000 0FE8
Physical Address 0xE000 2FE8 Instance 0xE000 2FE8
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 REVISION See CoreSight Architecture Specification RO 0x0
3 JEDEC See CoreSight Architecture Specification RO 1
2:0 DES_1 See CoreSight Architecture Specification RO 0b011

TOP:FPB:FP_PIDR3

Address Offset 0x0000 0FEC
Physical Address 0xE000 2FEC Instance 0xE000 2FEC
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 REVAND See CoreSight Architecture Specification RO 0x0
3:0 CMOD See CoreSight Architecture Specification RO 0x0

TOP:FPB:FP_CIDR0

Address Offset 0x0000 0FF0
Physical Address 0xE000 2FF0 Instance 0xE000 2FF0
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 PRMBL_0 See CoreSight Architecture Specification RO 0x0D

TOP:FPB:FP_CIDR1

Address Offset 0x0000 0FF4
Physical Address 0xE000 2FF4 Instance 0xE000 2FF4
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:4 CLASS See CoreSight Architecture Specification RO 0x9
3:0 PRMBL_1 See CoreSight Architecture Specification RO 0x0

TOP:FPB:FP_CIDR2

Address Offset 0x0000 0FF8
Physical Address 0xE000 2FF8 Instance 0xE000 2FF8
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 PRMBL_2 See CoreSight Architecture Specification RO 0x05

TOP:FPB:FP_CIDR3

Address Offset 0x0000 0FFC
Physical Address 0xE000 2FFC Instance 0xE000 2FFC
Description Provides CoreSight discovery information for the FP
Type
Bits Field Name Description Type Reset
31:8 RES0 Reserved, RES0 RO 0x00 0000
7:0 PRMBL_3 See CoreSight Architecture Specification RO 0xB1


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