Structure type to access the Nested Vectored Interrupt Controller (NVIC).
More...
#include <core_armv81mml.h>
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
§ ISER
| __IOM uint32_t NVIC_Type::ISER |
Offset: 0x000 (R/W) Interrupt Set Enable Register
§ RESERVED0
| uint32_t NVIC_Type::RESERVED0 |
§ ICER
| __IOM uint32_t NVIC_Type::ICER |
Offset: 0x080 (R/W) Interrupt Clear Enable Register
§ RSERVED1
| uint32_t NVIC_Type::RSERVED1 |
§ ISPR
| __IOM uint32_t NVIC_Type::ISPR |
Offset: 0x100 (R/W) Interrupt Set Pending Register
§ RESERVED2
| uint32_t NVIC_Type::RESERVED2 |
§ ICPR
| __IOM uint32_t NVIC_Type::ICPR |
Offset: 0x180 (R/W) Interrupt Clear Pending Register
§ RESERVED3
| uint32_t NVIC_Type::RESERVED3 |
§ IABR
| __IOM uint32_t NVIC_Type::IABR |
Offset: 0x200 (R/W) Interrupt Active bit Register
§ RESERVED4
| uint32_t NVIC_Type::RESERVED4 |
§ ITNS
| __IOM uint32_t NVIC_Type::ITNS |
Offset: 0x280 (R/W) Interrupt Non-Secure State Register
§ RESERVED5
| uint32_t NVIC_Type::RESERVED5 |
§ IPR [1/2]
| __IOM uint8_t NVIC_Type::IPR |
Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
§ RESERVED6
| uint32_t NVIC_Type::RESERVED6 |
§ STIR
| __OM uint32_t NVIC_Type::STIR |
Offset: 0xE00 ( /W) Software Trigger Interrupt Register
§ IPR [2/2]
| __IOM uint32_t NVIC_Type::IPR[124U] |
Offset: 0x300 (R/W) Interrupt Priority Register
The documentation for this struct was generated from the following files:
