Structure type to access the Instrumentation Trace Macrocell Register (ITM).
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#include <core_armv81mml.h>
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
§ u8
| __OM uint8_t ITM_Type::u8 |
Offset: 0x000 ( /W) ITM Stimulus Port 8-bit
§ u16
| __OM uint16_t ITM_Type::u16 |
Offset: 0x000 ( /W) ITM Stimulus Port 16-bit
§ u32
| __OM uint32_t ITM_Type::u32 |
Offset: 0x000 ( /W) ITM Stimulus Port 32-bit
§ PORT [1/3]
| __OM { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
§ RESERVED0
| uint32_t ITM_Type::RESERVED0 |
§ TER
| __IOM uint32_t ITM_Type::TER |
Offset: 0xE00 (R/W) ITM Trace Enable Register
§ RESERVED1
| uint32_t ITM_Type::RESERVED1 |
§ TPR
| __IOM uint32_t ITM_Type::TPR |
Offset: 0xE40 (R/W) ITM Trace Privilege Register
§ RESERVED2
| uint32_t ITM_Type::RESERVED2 |
§ TCR
| __IOM uint32_t ITM_Type::TCR |
Offset: 0xE80 (R/W) ITM Trace Control Register
§ RESERVED3
| uint32_t ITM_Type::RESERVED3 |
§ RESERVED4
| uint32_t ITM_Type::RESERVED4 |
§ LAR
| __OM uint32_t ITM_Type::LAR |
Offset: 0xFB0 ( /W) ITM Lock Access Register
§ LSR
| __IM uint32_t ITM_Type::LSR |
Offset: 0xFB4 (R/ ) ITM Lock Status Register
§ RESERVED5
| uint32_t ITM_Type::RESERVED5 |
§ DEVARCH
| __IM uint32_t ITM_Type::DEVARCH |
Offset: 0xFBC (R/ ) ITM Device Architecture Register
§ RESERVED6
| uint32_t ITM_Type::RESERVED6 |
§ DEVTYPE
| __IM uint32_t ITM_Type::DEVTYPE |
Offset: 0xFCC (R/ ) ITM Device Type Register
§ PID4
| __IM uint32_t ITM_Type::PID4 |
Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4
§ PID5
| __IM uint32_t ITM_Type::PID5 |
Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5
§ PID6
| __IM uint32_t ITM_Type::PID6 |
Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6
§ PID7
| __IM uint32_t ITM_Type::PID7 |
Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7
§ PID0
| __IM uint32_t ITM_Type::PID0 |
Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0
§ PID1
| __IM uint32_t ITM_Type::PID1 |
Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1
§ PID2
| __IM uint32_t ITM_Type::PID2 |
Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2
§ PID3
| __IM uint32_t ITM_Type::PID3 |
Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3
§ CID0
| __IM uint32_t ITM_Type::CID0 |
Offset: 0xFF0 (R/ ) ITM Component Identification Register #0
§ CID1
| __IM uint32_t ITM_Type::CID1 |
Offset: 0xFF4 (R/ ) ITM Component Identification Register #1
§ CID2
| __IM uint32_t ITM_Type::CID2 |
Offset: 0xFF8 (R/ ) ITM Component Identification Register #2
§ CID3
| __IM uint32_t ITM_Type::CID3 |
Offset: 0xFFC (R/ ) ITM Component Identification Register #3
§ PORT [2/3]
| __OM { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
§ PORT [3/3]
| __OM { ... } ITM_Type::PORT[32U] |
Offset: 0x000 ( /W) ITM Stimulus Port Registers
The documentation for this struct was generated from the following files:
