Modules

Here is a list of all modules:

[detail level 123]

CMSIS Core Instruction Interface
CMSIS SIMD Intrinsics
CMSIS Global Defines
▼Defines and Type Definitions	Type definitions and defines for Cortex-M processor based devices
Status and Control Registers	Core Register type definitions
Nested Vectored Interrupt Controller (NVIC)	Type definitions for the NVIC Registers
System Control Block (SCB)	Type definitions for the System Control Block Registers
System Controls not in SCB (SCnSCB)	Type definitions for the System Control and ID Register not in the SCB
System Tick Timer (SysTick)	Type definitions for the System Timer Registers
Instrumentation Trace Macrocell (ITM)	Type definitions for the Instrumentation Trace Macrocell (ITM)
Data Watchpoint and Trace (DWT)	Type definitions for the Data Watchpoint and Trace (DWT)
Trace Port Interface (TPI)	Type definitions for the Trace Port Interface (TPI)
Floating Point Unit (FPU)	Type definitions for the Floating Point Unit (FPU)
Core Debug Registers (CoreDebug)	Type definitions for the Core Debug Registers
Debug Control Block	Type definitions for the Debug Control Block Registers
Debug Identification Block	Type definitions for the Debug Identification Block Registers
Core register bit field macros	Macros for use with bit field definitions (xxx_Pos, xxx_Msk)
Core Definitions	Definitions for base addresses, unions, and structures
Backwards Compatibility Aliases	Register alias definitions for backwards compatibility
▼Functions and Instructions Reference
CMSIS Core Register Access Functions
NVIC Functions	Functions that manage interrupts and exceptions via the NVIC
FPU Functions	Function that provides FPU type
MVE Functions	Function that provides MVE type
SAU Functions	Functions that configure the SAU
Debug Control Functions	Functions that access the Debug Control Block
Debug Identification Functions	Functions that access the Debug Identification Block
SysTick Functions	Functions that configure the System
ITM Functions	Functions that access the ITM debug interface
▼Peripherals
[adc.h] Analog to Digital Converter
▼[apu.h] Algorithm Processing Unit (APU)
[apu.h] APU Vector Operations
[apu.h] APU Matrix Operations
[apu.h] APU Advanced Operations
[can.h] Controller Area Network
[gpio.h] General Purpose I/O
[i2c.h] Inter-Integrated Circuit
[i2s.h] Inter-IC Sound
[lpcmp.h] Low-Power Comparator
[lrfd.h] LRF Radio
Spi_api
[uart.h] Universal Asynchronous Receiver/Transmitter
[udma.h] Micro Direct Memory Access
▼System Control
[chipinfo.h] Chip Info
[ckmd.h] Clock Management Controller
[clkctl.h] IP Clock Control
[debug.h] Debug
[evtsvt.h] MCU Event Fabric
[flash.h] Flash
[pmctl.h] Power Management Controller
[setup.h] Setup
[ull.h] Ultra Low Leakage (ULL) Clock Domain
▼System CPU
[cpu.h] CPU
[interrupt.h] Interrupt
[systick.h] System Tick
▼Software Libraries
[sha256sw.h] SHA2 256/224 SW APIs	SHA2 256/224 SW APIs
[sha2sw_common.h] SHA2 SW Status codes	Status codes returned by the SHA2 SW module
[sha2sw_config.h] SHA2 SW Configuration Options	Build-time configuration options for the SHA2 SW module