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CC27xxDriverLibrary
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Type definitions for the Core Debug Registers. More...
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Data Structures | |
| struct | CoreDebug_Type |
Macros | |
| #define | CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define | CoreDebug_DHCSR_S_FPD_Pos 23U |
| #define | CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| #define | CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| #define | CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| #define | CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| #define | CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| #define | CoreDebug_DHCSR_S_SDE_Pos 20U |
| #define | CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| #define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define | CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define | CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define | CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define | CoreDebug_DHCSR_C_PMOV_Pos 6U |
| #define | CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define | CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define | CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define | CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define | CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define | CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define | CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define | CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define | CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define | CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define | CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define | CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define | CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define | CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define | CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define | CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define | CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define | CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define | CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define | CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define | CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define | CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define | CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define | CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| #define | CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| #define | CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| #define | CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| #define | CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| #define | CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| #define | CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| #define | CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define | CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define | CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define | CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define | CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define | CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define | CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define | CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define | CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define | CoreDebug_DEMCR_DWTENA_Pos 24U |
| #define | CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) |
| #define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define | CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define | CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define | CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define | CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define | CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define | CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define | CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define | CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define | CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define | CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define | CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define | CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define | CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define | CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define | CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define | CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define | CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define | CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define | CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define | CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define | CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define | CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define | CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define | CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define | CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define | CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define | CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define | CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define | CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define | CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define | CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define | CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define | CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define | CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define | CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define | CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define | CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define | CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define | CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define | CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define | CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define | CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define | CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define | CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define | CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define | CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define | CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define | CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define | CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define | CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define | CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define | CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define | CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define | CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define | CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define | CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define | CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define | CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define | CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define | CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define | CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define | CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define | CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define | CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define | CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define | CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define | CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define | CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define | CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define | CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define | CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define | CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define | CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define | CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define | CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define | CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define | CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define | CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define | CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define | CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define | CoreDebug_DSCSR_CDS_Pos 16U |
| #define | CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define | CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define | CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define | CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define | CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
Type definitions for the Core Debug Registers.
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define CoreDebug_DHCSR_S_FPD_Pos 23U |
| #define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) |
| #define CoreDebug_DHCSR_S_SUIDE_Pos 22U |
| #define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) |
| #define CoreDebug_DHCSR_S_NSUIDE_Pos 21U |
| #define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) |
| #define CoreDebug_DHCSR_S_SDE_Pos 20U |
| #define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) |
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define CoreDebug_DHCSR_C_PMOV_Pos 6U |
| #define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U |
| #define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U |
| #define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U |
| #define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U |
| #define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U |
| #define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U |
| #define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) |
| #define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U |
| #define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define CoreDebug_DEMCR_DWTENA_Pos 24U |
| #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) |
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |
| #define CoreDebug_DHCSR_DBGKEY_Pos 16U |
| #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) |
| #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U |
| #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) |
| #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U |
| #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U |
| #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) |
| #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U |
| #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) |
| #define CoreDebug_DHCSR_S_SLEEP_Pos 18U |
| #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) |
| #define CoreDebug_DHCSR_S_HALT_Pos 17U |
| #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) |
| #define CoreDebug_DHCSR_S_REGRDY_Pos 16U |
| #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U |
| #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) |
| #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U |
| #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) |
| #define CoreDebug_DHCSR_C_STEP_Pos 2U |
| #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) |
| #define CoreDebug_DHCSR_C_HALT_Pos 1U |
| #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) |
| #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U |
| #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) |
| #define CoreDebug_DCRSR_REGWnR_Pos 16U |
| #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) |
| #define CoreDebug_DCRSR_REGSEL_Pos 0U |
| #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) |
| #define CoreDebug_DEMCR_TRCENA_Pos 24U |
| #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) |
| #define CoreDebug_DEMCR_MON_REQ_Pos 19U |
| #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) |
| #define CoreDebug_DEMCR_MON_STEP_Pos 18U |
| #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) |
| #define CoreDebug_DEMCR_MON_PEND_Pos 17U |
| #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) |
| #define CoreDebug_DEMCR_MON_EN_Pos 16U |
| #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) |
| #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U |
| #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) |
| #define CoreDebug_DEMCR_VC_INTERR_Pos 9U |
| #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) |
| #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U |
| #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) |
| #define CoreDebug_DEMCR_VC_STATERR_Pos 7U |
| #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) |
| #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U |
| #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) |
| #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U |
| #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) |
| #define CoreDebug_DEMCR_VC_MMERR_Pos 4U |
| #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) |
| #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U |
| #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U |
| #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U |
| #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U |
| #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U |
| #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) |
| #define CoreDebug_DSCSR_CDS_Pos 16U |
| #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) |
| #define CoreDebug_DSCSR_SBRSEL_Pos 1U |
| #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) |
| #define CoreDebug_DSCSR_SBRSELEN_Pos 0U |
| #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) |