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CC27xxDriverLibrary
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Macros | |
| #define | __CMSIS_GCC_OUT_REG(r) "=r" (r) |
| #define | __CMSIS_GCC_RW_REG(r) "+r" (r) |
| #define | __CMSIS_GCC_USE_REG(r) "r" (r) |
| #define | __NOP() __ASM volatile ("nop") |
| No Operation. More... | |
| #define | __WFI() __ASM volatile ("wfi":::"memory") |
| Wait For Interrupt. More... | |
| #define | __WFE() __ASM volatile ("wfe":::"memory") |
| Wait For Event. More... | |
| #define | __SEV() __ASM volatile ("sev") |
| Send Event. More... | |
| #define | __BKPT(value) __ASM volatile ("bkpt "#value) |
| Breakpoint. More... | |
| #define | __CMSIS_GCC_OUT_REG(r) "=r" (r) |
| #define | __CMSIS_GCC_RW_REG(r) "+r" (r) |
| #define | __CMSIS_GCC_USE_REG(r) "r" (r) |
| #define | __NOP __builtin_arm_nop |
| No Operation. More... | |
| #define | __WFI __builtin_arm_wfi |
| Wait For Interrupt. More... | |
| #define | __WFE __builtin_arm_wfe |
| Wait For Event. More... | |
| #define | __SEV __builtin_arm_sev |
| Send Event. More... | |
| #define | __ISB() __builtin_arm_isb(0xF) |
| Instruction Synchronization Barrier. More... | |
| #define | __DSB() __builtin_arm_dsb(0xF) |
| Data Synchronization Barrier. More... | |
| #define | __DMB() __builtin_arm_dmb(0xF) |
| Data Memory Barrier. More... | |
| #define | __REV(value) __builtin_bswap32(value) |
| Reverse byte order (32 bit) More... | |
| #define | __REV16(value) __ROR(__REV(value), 16) |
| Reverse byte order (16 bit) More... | |
| #define | __REVSH(value) (int16_t)__builtin_bswap16(value) |
| Reverse byte order (16 bit) More... | |
| #define | __BKPT(value) __ASM volatile ("bkpt "#value) |
| Breakpoint. More... | |
| #define | __RBIT __builtin_arm_rbit |
| Reverse bit order of value. More... | |
Functions | |
| __STATIC_FORCEINLINE void | __ISB (void) |
| Instruction Synchronization Barrier. More... | |
| __STATIC_FORCEINLINE void | __DSB (void) |
| Data Synchronization Barrier. More... | |
| __STATIC_FORCEINLINE void | __DMB (void) |
| Data Memory Barrier. More... | |
| __STATIC_FORCEINLINE uint32_t | __REV (uint32_t value) |
| Reverse byte order (32 bit) More... | |
| __STATIC_FORCEINLINE uint32_t | __REV16 (uint32_t value) |
| Reverse byte order (16 bit) More... | |
| __STATIC_FORCEINLINE int16_t | __REVSH (int16_t value) |
| Reverse byte order (16 bit) More... | |
| __STATIC_FORCEINLINE uint32_t | __ROR (uint32_t op1, uint32_t op2) |
| Rotate Right in unsigned value (32 bit) More... | |
| __STATIC_FORCEINLINE uint32_t | __RBIT (uint32_t value) |
| Reverse bit order of value. More... | |
| __STATIC_FORCEINLINE uint8_t | __CLZ (uint32_t value) |
| Count leading zeros. More... | |
| __STATIC_FORCEINLINE int32_t | __SSAT (int32_t val, uint32_t sat) |
| Signed Saturate. More... | |
| __STATIC_FORCEINLINE uint32_t | __USAT (int32_t val, uint32_t sat) |
| Unsigned Saturate. More... | |
Access to dedicated instructions
| #define __CMSIS_GCC_RW_REG | ( | r | ) | "+r" (r) |
| #define __NOP | ( | ) | __ASM volatile ("nop") |
No Operation.
No Operation does nothing. This instruction can be used for code alignment purposes.
Referenced by __NVIC_SystemReset(), and ITM_SendChar().
| #define __WFI | ( | ) | __ASM volatile ("wfi":::"memory") |
Wait For Interrupt.
Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
| #define __WFE | ( | ) | __ASM volatile ("wfe":::"memory") |
Wait For Event.
Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs.
| #define __SEV | ( | ) | __ASM volatile ("sev") |
Send Event.
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
| #define __BKPT | ( | value | ) | __ASM volatile ("bkpt "#value) |
Breakpoint.
Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
| [in] | value | is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. |
| #define __CMSIS_GCC_OUT_REG | ( | r | ) | "=r" (r) |
| #define __CMSIS_GCC_RW_REG | ( | r | ) | "+r" (r) |
| #define __CMSIS_GCC_USE_REG | ( | r | ) | "r" (r) |
| #define __NOP __builtin_arm_nop |
No Operation.
No Operation does nothing. This instruction can be used for code alignment purposes.
| #define __WFI __builtin_arm_wfi |
Wait For Interrupt.
Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
| #define __WFE __builtin_arm_wfe |
Wait For Event.
Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs.
| #define __SEV __builtin_arm_sev |
Send Event.
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
| #define __ISB | ( | void | ) | __builtin_arm_isb(0xF) |
Instruction Synchronization Barrier.
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.
| #define __DSB | ( | void | ) | __builtin_arm_dsb(0xF) |
Data Synchronization Barrier.
Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.
| #define __DMB | ( | void | ) | __builtin_arm_dmb(0xF) |
Data Memory Barrier.
Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.
| #define __REV | ( | value | ) | __builtin_bswap32(value) |
Reverse byte order (32 bit)
Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
| [in] | value | Value to reverse |
Reverse byte order (16 bit)
Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
| [in] | value | Value to reverse |
| #define __REVSH | ( | value | ) | (int16_t)__builtin_bswap16(value) |
Reverse byte order (16 bit)
Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
| [in] | value | Value to reverse |
| #define __BKPT | ( | value | ) | __ASM volatile ("bkpt "#value) |
Breakpoint.
Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.
| [in] | value | is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint. |
| #define __RBIT __builtin_arm_rbit |
Reverse bit order of value.
Reverses the bit order of the given value.
| [in] | value | Value to reverse |
| __STATIC_FORCEINLINE void __ISB | ( | void | ) |
Instruction Synchronization Barrier.
Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.
References __ASM.
Referenced by __NVIC_DisableIRQ(), __set_CONTROL(), ARM_MPU_Disable(), ARM_MPU_Enable(), DCB_GetAuthCtrl(), DCB_SetAuthCtrl(), and IntSetPend().
| __STATIC_FORCEINLINE void __DSB | ( | void | ) |
Data Synchronization Barrier.
Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.
References __ASM.
Referenced by __NVIC_DisableIRQ(), __NVIC_SetVector(), __NVIC_SystemReset(), ARM_MPU_Disable(), ARM_MPU_Enable(), DCB_GetAuthCtrl(), and DCB_SetAuthCtrl().
| __STATIC_FORCEINLINE void __DMB | ( | void | ) |
Data Memory Barrier.
Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.
References __ASM.
Referenced by ARM_MPU_Disable(), and ARM_MPU_Enable().
| __STATIC_FORCEINLINE uint32_t __REV | ( | uint32_t | value | ) |
Reverse byte order (32 bit)
Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
| [in] | value | Value to reverse |
References __ASM, __CMSIS_GCC_OUT_REG, and __CMSIS_GCC_USE_REG.
| __STATIC_FORCEINLINE uint32_t __REV16 | ( | uint32_t | value | ) |
Reverse byte order (16 bit)
Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
| [in] | value | Value to reverse |
References __ASM, __CMSIS_GCC_OUT_REG, and __CMSIS_GCC_USE_REG.
| __STATIC_FORCEINLINE int16_t __REVSH | ( | int16_t | value | ) |
Reverse byte order (16 bit)
Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
| [in] | value | Value to reverse |
References __ASM, __CMSIS_GCC_OUT_REG, and __CMSIS_GCC_USE_REG.
| __STATIC_FORCEINLINE uint32_t __ROR | ( | uint32_t | op1, |
| uint32_t | op2 | ||
| ) |
Rotate Right in unsigned value (32 bit)
Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
| [in] | op1 | Value to rotate |
| [in] | op2 | Number of Bits to rotate |
Referenced by __set_FPSCR().
| __STATIC_FORCEINLINE uint32_t __RBIT | ( | uint32_t | value | ) |
Reverse bit order of value.
Reverses the bit order of the given value.
| [in] | value | Value to reverse |
References __ASM.
| __STATIC_FORCEINLINE uint8_t __CLZ | ( | uint32_t | value | ) |
Count leading zeros.
Counts the number of leading zeros of a data value.
| [in] | value | Value to count the leading zeros |
References __ASM, __CMSIS_GCC_OUT_REG, __CMSIS_GCC_USE_REG, __LDREXW(), __STATIC_FORCEINLINE, and __STREXW().
| __STATIC_FORCEINLINE int32_t __SSAT | ( | int32_t | val, |
| uint32_t | sat | ||
| ) |
Signed Saturate.
Saturates a signed value.
| [in] | val | Value to be saturated |
| [in] | sat | Bit position to saturate to (1..32) |
| __STATIC_FORCEINLINE uint32_t __USAT | ( | int32_t | val, |
| uint32_t | sat | ||
| ) |
Unsigned Saturate.
Saturates an unsigned value.
| [in] | val | Value to be saturated |
| [in] | sat | Bit position to saturate to (0..31) |
References __ASM, and __STATIC_FORCEINLINE.