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Macros
#define	__SAUREGION_PRESENT 0x0001U /* SAU present */

#define	__DSP_PRESENT 0x0001U /* DSP extension present */

#define	__Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */

#define	__CM33_REV 0x0001U /* Core revision */

#define	__MPU_PRESENT 0x0001U /* MPU present or not */

#define	__FPU_PRESENT 0x0001U /* FPU present or not */

#define	__VTOR_PRESENT 0x0001U /* VTOR present */

#define	__NVIC_PRIO_BITS 0x0004U /* 4 NVIC priority bits */

Enumerations
enum	IRQn { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SecureFault_IRQn = -9, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, CPUIRQ0_IRQn = 0, CPUIRQ1_IRQn = 1, CPUIRQ2_IRQn = 2, CPUIRQ3_IRQn = 3, CPUIRQ4_IRQn = 4, GPIO_COMB_IRQn = 5, LRFD_IRQ0_IRQn = 6, LRFD_IRQ1_IRQn = 7, DMA_DONE_COMB_IRQn = 8, AES_COMB_IRQn = 9, SPI0_COMB_IRQn = 10, UART0_COMB_IRQn = 11, I2C0_IRQ_IRQn = 12, LGPT0_COMB_IRQn = 13, LGPT1_COMB_IRQn = 14, ADC_COMB_IRQn = 15, CPUIRQ16_IRQn = 16, CPUIRQ17_IRQn = 17, LGPT2_COMB_IRQn = 18, LGPT3_COMB_IRQn = 19, I2S_IRQ_IRQn = 20, CAN_IRQ_IRQn = 21, UART1_COMB_IRQn = 22, SPI1_COMB_IRQn = 23, APU_IRQ_IRQn = 24, HSM_SEC_IRQ_IRQn = 25, HSM_NONSEC_IRQ_IRQn = 26, HSM_OTP_IRQ_IRQn = 27, AON_PMU_COMB_IRQn = 28, AON_CKM_COMB_IRQn = 29, AON_RTC_COMB_IRQn = 30, AON_LPCMP_IRQ_IRQn = 31, AON_IOC_COMB_IRQn = 32, SW0_IRQn = 33, SW1_IRQn = 34 }

Macro Definition Documentation

§ __SAUREGION_PRESENT

#define __SAUREGION_PRESENT 0x0001U /* SAU present */

#define __DSP_PRESENT 0x0001U /* DSP extension present */

#define __Vendor_SysTickConfig 0x0000U /* Set to 1 if different SysTick Config is used */

#define __CM33_REV 0x0001U /* Core revision */

#define __MPU_PRESENT 0x0001U /* MPU present or not */

#define __FPU_PRESENT 0x0001U /* FPU present or not */

#define __VTOR_PRESENT 0x0001U /* VTOR present */

#define __NVIC_PRIO_BITS 0x0004U /* 4 NVIC priority bits */

typedef enum IRQn IRQn_Type

enum IRQn