CC23x0R5DriverLibrary
aes.h
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31 
32 /*!****************************************************************************
33  * @file aes.h
34  *
35  * @brief AES module header for CC23X0R5 devices
36  *
37  * @anchor ti_devices_cc23x0r5_aes_overview
38  *
39  * This module provides the low-level functions used to access the LAES128
40  * crypto engine.
41  ******************************************************************************/
42 
43 #ifndef __AES_H__
44 #define __AES_H__
45 
46 #include <stdint.h>
47 
48 #include "../inc/hw_types.h"
49 #include "../inc/hw_memmap.h"
50 #include "../inc/hw_aes.h"
51 
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55 
56 #define AES_BLOCK_SIZE 16U
57 #define AES_BLOCK_SIZE_WORDS (AES_BLOCK_SIZE / 4U)
58 #define AES_BLOCK_SIZE_MULTIPLE_MASK 0xFFFFFFF0U
59 #define AES_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_BLOCK_SIZE_MULTIPLE_MASK)
60 #define AES_NON_BLOCK_SIZE_MULTIPLE_MASK 0x0000000FU
61 #define AES_NON_BLOCK_SIZE_MULTIPLE_LENGTH(len) ((len)&AES_NON_BLOCK_SIZE_MULTIPLE_MASK)
62 #define AES_GET_NUM_BLOCKS(len) ((len) >> 4)
63 #define AES_BLOCKS_TO_BYTES(numBlocks) ((numBlocks) << 4)
64 
65 #define AES_DOUBLE_BLOCK_SIZE_MULTIPLE_MASK (size_t)(0xFFFFFFE0UL)
66 
67 #define AES_IV_LENGTH_BYTES AES_BLOCK_SIZE
68 #define AES_TAG_LENGTH_BYTES AES_BLOCK_SIZE
69 
70 #define AES_128_KEY_LENGTH_BYTES (128U / 8U)
71 
72 #define IS_WORD_ALIGNED(ptr) (((uintptr_t)(ptr) << 30) == 0U)
73 
74 #define AES_ICLR_ALL \
75  ((uint32_t)AES_ICLR_AESDONE | (uint32_t)AES_ICLR_AESSTART | (uint32_t)AES_ICLR_CHADONE | (uint32_t)AES_ICLR_CHBDONE)
76 
77 typedef union
78 {
79  uint32_t words[4];
80  uint8_t bytes[16];
82 
94 void AESProcessAlignedBlocksCMAC(const uint32_t *input, uint32_t numBlocks);
95 
106 void AESProcessAlignedBlocksCTR(const uint32_t *input, uint32_t *output, uint32_t numBlocks);
107 
118 void AESProcessAlignedBlocksECB(const uint32_t *input, uint32_t *output, uint32_t numBlocks);
119 
135 void AESCopyBlock(void *dst, const void *src);
136 
145 __STATIC_INLINE void AESWriteKEY(const uint8_t key[16])
146 {
147  AESCopyBlock((void *)(AES_BASE + AES_O_KEY0), key);
148 }
149 
159 __STATIC_INLINE void AESWriteBUF(const uint8_t buf[16])
160 {
161  AESCopyBlock((void *)(AES_BASE + AES_O_BUF0), buf);
162 }
163 
173 __STATIC_INLINE void AESWriteBUF32(const uint32_t buf[4])
174 {
175  HWREG(AES_BASE + AES_O_BUF0) = buf[0];
176  HWREG(AES_BASE + AES_O_BUF1) = buf[1];
177  HWREG(AES_BASE + AES_O_BUF2) = buf[2];
178  HWREG(AES_BASE + AES_O_BUF3) = buf[3];
179 }
180 
189 __STATIC_INLINE void AESReadBUF(uint8_t buf[16])
190 {
191  AESCopyBlock(buf, (const void *)(AES_BASE + AES_O_BUF0));
192 }
193 
202 __STATIC_INLINE void AESReadBUF32(uint32_t buf[4])
203 {
204  buf[0] = HWREG(AES_BASE + AES_O_BUF0);
205  buf[1] = HWREG(AES_BASE + AES_O_BUF1);
206  buf[2] = HWREG(AES_BASE + AES_O_BUF2);
207  buf[3] = HWREG(AES_BASE + AES_O_BUF3);
208 }
209 
219 __STATIC_INLINE void AESWriteTXTXOR(const uint8_t txtxor[16])
220 {
221  AESCopyBlock((void *)(AES_BASE + AES_O_TXTX0), txtxor);
222 }
223 
233 __STATIC_INLINE void AESWriteTXTXOR32(const uint32_t txtxor[4])
234 {
235  HWREG(AES_BASE + AES_O_TXTX0) = txtxor[0];
236  HWREG(AES_BASE + AES_O_TXTX1) = txtxor[1];
237  HWREG(AES_BASE + AES_O_TXTX2) = txtxor[2];
238  HWREG(AES_BASE + AES_O_TXTX3) = txtxor[3];
239 }
240 
250 __STATIC_INLINE void AESReadTXTXBUF(uint8_t txtxbuf[16])
251 {
252  AESCopyBlock(txtxbuf, (const void *)(AES_BASE + AES_O_TXTXBUF0));
253 }
254 
264 __STATIC_INLINE void AESWriteTXT(const uint8_t txt[16])
265 {
266  AESCopyBlock((void *)(AES_BASE + AES_O_TXT0), txt);
267 }
268 
278 __STATIC_INLINE void AESWriteTXT32(const uint32_t txt[4])
279 {
280  HWREG(AES_BASE + AES_O_TXT0) = txt[0];
281  HWREG(AES_BASE + AES_O_TXT1) = txt[1];
282  HWREG(AES_BASE + AES_O_TXT2) = txt[2];
283  HWREG(AES_BASE + AES_O_TXT3) = txt[3];
284 }
285 
295 __STATIC_INLINE void AESReadTXT(uint8_t txt[16])
296 {
297  AESCopyBlock(txt, (const void *)(AES_BASE + AES_O_TXT0));
298 }
299 
309 __STATIC_INLINE void AESReadTXT32(uint32_t txt[4])
310 {
311  txt[0] = HWREG(AES_BASE + AES_O_TXT0);
312  txt[1] = HWREG(AES_BASE + AES_O_TXT1);
313  txt[2] = HWREG(AES_BASE + AES_O_TXT2);
314  txt[3] = HWREG(AES_BASE + AES_O_TXT3);
315 }
316 
325 __STATIC_INLINE void AESWriteTag(const uint8_t tag[16])
326 {
327  AESWriteTXT(tag);
328 }
329 
338 __STATIC_INLINE void AESWriteTag32(const uint32_t tag[4])
339 {
340  AESWriteTXT32(tag);
341 }
342 
351 __STATIC_INLINE void AESReadTag(uint8_t tag[16])
352 {
353  AESReadTXT(tag);
354 }
355 
364 __STATIC_INLINE void AESReadTag32(uint32_t tag[4])
365 {
366  AESReadTXT32(tag);
367 }
368 
388 __STATIC_INLINE void AESSetAUTOCFG(uint32_t autoCfg)
389 {
390  HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
391 }
392 
399 __STATIC_INLINE void AESClearAUTOCFGTrigger(void)
400 {
401  /* Read the current AUTOCFG value */
402  uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG);
403 
404  /* Clear the TRGECB bits */
405  autoCfg &= (uint32_t)~AES_AUTOCFG_TRGAES_M;
406 
407  HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
408 }
409 
416 __STATIC_INLINE void AESClearAUTOCFGBusHalt(void)
417 {
418  /* Read the current AUTOCFG value */
419  uint32_t autoCfg = HWREG(AES_BASE + AES_O_AUTOCFG);
420 
421  /* Clear the BUSHALT bit */
422  autoCfg &= (uint32_t)~AES_AUTOCFG_BUSHALT_M;
423 
424  HWREG(AES_BASE + AES_O_AUTOCFG) = autoCfg;
425 }
426 
436 __STATIC_INLINE uint32_t AESGetStatus(void)
437 {
438  return (HWREG(AES_BASE + AES_O_STA) & AES_STA_STATE_M);
439 }
440 
454 __STATIC_INLINE void AESSetTrigger(uint32_t triggerMask)
455 {
456  HWREG(AES_BASE + AES_O_TRG) = triggerMask;
457 }
458 
467 __STATIC_INLINE void AESAbort(void)
468 {
469  HWREG(AES_BASE + AES_O_ABORT) = AES_ABORT_ABORTAES_SET;
470 }
471 
479 __STATIC_INLINE void AESClearTXT(void)
480 {
481  HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M;
482 }
483 
491 __STATIC_INLINE void AESClearBUF(void)
492 {
493  HWREG(AES_BASE + AES_O_CLR) = AES_CLR_BUF_M;
494 }
495 
504 __STATIC_INLINE void AESClearTXTAndBUF(void)
505 {
506  HWREG(AES_BASE + AES_O_CLR) = AES_CLR_TXT_M | AES_CLR_BUF_M;
507 }
508 
517 __STATIC_INLINE void AESWriteIV(const uint8_t iv[16])
518 {
519  AESWriteTXT(iv);
520 }
521 
530 __STATIC_INLINE void AESWriteIV32(const uint32_t iv[4])
531 {
532  AESWriteTXT32(iv);
533 }
534 
541 __STATIC_INLINE void AESClearIV(void)
542 {
543  AESClearTXT();
544 }
545 
554 __STATIC_INLINE void AESReadIV(uint8_t iv[16])
555 {
556  AESReadTXT(iv);
557 }
558 
567 __STATIC_INLINE void AESReadIV32(uint32_t iv[4])
568 {
569  AESReadTXT32(iv);
570 }
571 
583 __STATIC_INLINE uint32_t AESGetRawInterruptStatus(void)
584 {
585  return HWREG(AES_BASE + AES_O_RIS);
586 }
587 
601 __STATIC_INLINE void AESSetInterrupt(uint32_t intFlags)
602 {
603  HWREG(AES_BASE + AES_O_ISET) = intFlags;
604 }
605 
618 __STATIC_INLINE void AESClearInterrupt(uint32_t intFlags)
619 {
620  HWREG(AES_BASE + AES_O_ICLR) = intFlags;
621 }
622 
634 __STATIC_INLINE uint32_t AESGetMaskedInterruptStatus(void)
635 {
636  return HWREG(AES_BASE + AES_O_MIS);
637 }
638 
651 __STATIC_INLINE void AESSetIMASK(uint32_t intFlags)
652 {
653  HWREG(AES_BASE + AES_O_IMASK) = intFlags;
654 }
655 
670 __STATIC_INLINE void AESSetupDMA(uint32_t dmaConfig)
671 {
672  HWREG(AES_BASE + AES_O_DMA) = dmaConfig;
673 }
674 
681 __STATIC_INLINE void AESDisableDMA(void)
682 {
683  HWREG(AES_BASE + AES_O_DMA) = AES_DMA_DONEACT_DIS | AES_DMA_TRGCHB_DIS | AES_DMA_TRGCHA_DIS;
684 }
685 
688 #ifdef __cplusplus
689 }
690 #endif
691 
692 #endif /* __AES_H__ */
Definition: aes.h:77
#define __STATIC_INLINE
Definition: cmsis_gcc.h:47