Hardware Architecture
=====================

The |DEVICELOW| Family
----------------------

Arm Cortex-M0+ (Device Core)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^

The device core (CM0+) is designed to run the wireless
protocol stack from the radio layer up to the user
application. By only using one core for the solution, the
|DEVICELOW| family is optimized for both cost and power.


Flash, RAM, and Peripherals
^^^^^^^^^^^^^^^^^^^^^^^^^^^

Depending on the model, devices in the |DEVICELOW| family
contain between |FLASH_SIZE_LOW|-|FLASH_SIZE_LOW_PLUS| of
in-system programmable flash memory and
|CC23XX_MIN_RAM_SIZE|-|CC23XX_MAX_RAM_SIZE| of SRAM. See
the table below for a breakdown each device. The |DEVICELOW|
also hosts a full range of peripherals including UART, I2C,
AES, RNG, temperature and battery monitors, timers,
and 1 SSI.

.. note::
    Within the SDK and related software tools, the CC2340R2 refers to the CC2340R2(1) device
    and the CC2340R5 refers to the CC2340R5(2) device. The precise device names are used
    in the following table.

.. table:: Flash and SRAM size for |DEVICE| devices

    +-------+--------------------+-----------------------------------------------+-------------------------+---------------------------+---------------------------+
    |       | |DEVICE_LOW|       | |DEVICE_LOW_PLUS_FLASH_DOWN|                  | |DEVICE_LOW_PLUS|       | |DEVICE_LOW_PLUS_AUTO|    | |DEVICE_LOW_PLUS_RAM_UP|  |
    +=======+====================+===============================================+=========================+===========================+===========================+
    |       |                    |                                               |                         |                           |                           |
    | Flash | |FLASH_SIZE_LOW|   | |FLASH_SIZE_LOW_PLUS_FLASH_DOWN|              |  |FLASH_SIZE_LOW_PLUS|  |  |FLASH_SIZE_LOW_PLUS|    | |FLASH_SIZE_LOW_PLUS|     |
    |       |                    |                                               |                         |                           |                           |
    +-------+--------------------+-----------------------------------------------+-------------------------+---------------------------+---------------------------+
    |       |                    |                                               |                         |                           |                           |
    | SRAM  |  |RAM_SIZE_LOW|    | |RAM_SIZE_LOW_PLUS_FLASH_DOWN|                |  |RAM_SIZE_LOW_PLUS|    |  |RAM_SIZE_LOW_PLUS|      | |RAM_SIZE_LOW_PLUS_RAM_UP||
    |       |                    |                                               |                         |                           |                           |
    +-------+--------------------+-----------------------------------------------+-------------------------+---------------------------+---------------------------+

The |DEVICEHIGH| Family
-----------------------

Arm Cortex-M33 (Device Core)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The Cortex-M33 (CM33) core within the |DEVICEHIGH| is responsible for both interfacing
to the radio hardware and implementing the PHY layer of the protocol stack with 
|STACK|. It translates instructions into bits that are sent over the air using 
the radio in an optimized manner for BLE performance and power-consumption.


Hardware Security Module
^^^^^^^^^^^^^^^^^^^^^^^^
The Hardware Security Module (HSM) is used to create an isolated environment
for cryptographic, key management, secure counters, and random number generation 
operations. The HSM supports energy-efficient operations for the following
functions: Key Agreement Schemes, Signature Processing, Message Authentication 
Codes, Block Cipher Modes of Operation, Hash Algorithms, and Random Number 
Generation.

The HSM has its own RAM that is not accessable to the rest of the system but the 
HSM does have the capability to access the system memory directly. The SimpleLink 
Low Power F3 SDK includes the necessary firmware and drivers for all the HSM 
operations and functions.

Trusted Firmware-M
^^^^^^^^^^^^^^^^^^
The |DEVICEHIGH| supports Trusted Firmware-M (TF-M) for Armv8-M that 
implements the Secure Processing Environment (SPE) for the CM33 that enables PSA 
(Platform Security Architecture) Certification. TF-M consists of: 

* Secure Boot to authenticate Non-Secure Processing Environment (NPSE) 
    and Secure Processing Environment (SPE) firmware image integrity.
* TF-M Core for controlling the isolation, communication and execution within SPE and with NSPE.
* Crypto, Internal Trusted Storage (ITS), Protected Storage (PS), and Firmware Update and Attestation Secure Services. 

This enables the device to have secure connections with cloud services and 
protect sensitive data, keys, and certificates.

Peripherals and Devices With or Without CAN
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The |DEVICEHIGH| also hosts a full range of peripherals across hardware variants including:

* 2x UART modules that uses universal asynchronous TX/RX functions with flexible baud-rate generation up to 3 MBPS and an IRDA SIR operation mode
* 2x SPI controllers and peripherals up to 12MHz with configurable phase and polarity
* 1x I2C to communicate with devices at 100KHz and 400KHz as a controller and/or a target
* 1x I2S for digital audio and pulse-density modulation microphones
* 1x VCE post-processing accelerator for fast and efficient Channel Sounding execution
* 1x Temperature and battery monitors
* 23 GPIOs, four with high-drive capability and ten with analog capabilities
* 1x 32-bit timer and 3x 16-bit timers
* 1x System timer
* 1x Watchdog timer
* 1x Real-time Clock
* 1x Low-power comparator
* 1x 12-bit ADC
* 1x Buck DC-DC converter
* The CAN-FD module supports both CAN (1Mbps) and CAN-FD (controllable 5Mbps with 64B/frame)

Table 5 below shows the notable device differences.

.. table:: Devices With/Without CAN and +20dBm Power Amplifier, Flash and SRAM Size
    
    +--------------+------------+----------------+---------------+---------------+
    | **Device**   | **CAN-FD** | **Flash (kB)** | **SRAM (kB)** | **+20dBm PA** |
    +==============+============+================+===============+===============+
    | CC2745P10-Q1 | Yes        | 1024           | 162           | Yes           |
    +--------------+------------+----------------+---------------+---------------+
    | CC2745R10-Q1 | Yes        | 1024           | 162           | No            |
    +--------------+------------+----------------+---------------+---------------+
    | CC2745R7-Q1  | Yes        | 768            | 128           | No            |
    +--------------+------------+----------------+---------------+---------------+
    | CC2744R7-Q1  | No         | 768            | 128           | No            |
    +--------------+------------+----------------+---------------+---------------+

Flash and RAM
^^^^^^^^^^^^^

As shown in Table 5 above, the |DEVICEHIGH_x10| contains |CC27XX_x10_FLASH_SIZE| 
of in-system programmable flash memory and |CC27XX_x10_NO_PARITY_RAM_SIZE| of 
no parity SRAM (or |CC27XX_x10_PARITY_RAM_SIZE| with parity), whereas the 
|DEVICEHIGH_x7| has |CC27XX_x7_FLASH_SIZE| flash memory and |CC27XX_x7_RAM_SIZE| 
of SRAM. The flash is split into erasable pages of |CC27XX_PAGE_SIZE|. The 
|DEVICEHIGH| also contains |CC27XX_CACHE_RAM| of cache SRAM that can be utilized 
to extend RAM capacity or can function as a normal cache to increase application 
performance. 

.. figure:: resources/fig-loki-high-block-diagram.png
    :name: fig-simplelink-loki-high-block-diagram
    :align: center

    SimpleLink™ |DEVICEHIGH| Block Diagram

.. _sec-programming-internal-flash-rom-bootloader:

Programming Internal Flash With the ROM Bootloader
--------------------------------------------------

The |DEVICE| internal flash memory can be programmed using
the bootloader located in device ROM. Both UART and SPI
protocols are supported. See the |TRM| for more details on
the programming protocol and requirements.

.. note:: Because the ROM bootloader uses predefined DIO
    pins for internal flash programming, allocate these
    pins in the board layout. The |TRM| has more details on
    the pins allocated to the bootloader based on the chip
    package type.

Startup Sequence
^^^^^^^^^^^^^^^^

For a complete description of the |DEVICE| reset sequence, see the |TRM|.

Resets
^^^^^^

.. note:: Reset on the |DEVICE| may only be done by using hard resets. A hard reset
          turns off and on the device, resetting all the registers and memory.
          On the other hand, a soft reset restarts the microcontroller without
          losing RAM content.

From the software, this reset can be accomplished using ``Power_reset()``
function call from the Power Manager driver (``Power.h``). 
For more information, please review |TI_DRIVERS_API| section.

.. code-block:: c

    // Import Power Driver definitions.
    #include <ti/drivers/Power.h>

    // Resets the system and causes it to reboot.
    Power_reset();

In CCS, select Board Reset (automatic) from the reset menu:

.. figure:: resources/fig-board-reset.png

    Board Reset