SPILPF3DMA Hardware attributes. More...

#include <SPILPF3DMA.h>

Data Fields
uint32_t	baseAddr
	SPI Peripheral's base address. More...

uint8_t	intNum

uint8_t	intPriority
	SPILPF3DMA Peripheral's interrupt priority. More...

uint32_t	swiPriority
	SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file. More...

uint8_t	powerID

uint16_t	defaultTxBufValue

uint32_t	rxChannelBitMask

uint32_t	txChannelBitMask

uint8_t	txChannelEvtMux

uint8_t	rxChannelEvtMux

volatile uDMAControlTableEntry *	dmaTxTableEntryPri

volatile uDMAControlTableEntry *	dmaRxTableEntryPri

volatile uDMAControlTableEntry *	dmaTxTableEntryAlt

volatile uDMAControlTableEntry *	dmaRxTableEntryAlt

int32_t	pociPinMux

int32_t	picoPinMux

int32_t	sclkPinMux

int32_t	csnPinMux

uint_least8_t	picoPin

uint_least8_t	pociPin

uint_least8_t	sclkPin

uint_least8_t	csnPin

uint32_t	minDmaTransferSize

Detailed Description

SPILPF3DMA Hardware attributes.

These fields, with the exception of intPriority, are used by driverlib APIs and therefore must be populated by driverlib macro definitions. For driverlib these definitions are found in:

inc/hw_memmap.h
inc/hw_ints.h
driverlib/udma.h

intPriority is the SPI peripheral's interrupt priority, as defined by the underlying OS. It is passed unmodified to the underlying OS's interrupt handler creation code, so you need to refer to the OS documentation for usage. For example, for SYS/BIOS applications, refer to the ti.sysbios.family.arm.m3.Hwi documentation for SYS/BIOS usage of interrupt priorities. If the driver uses the ti.dpl interface instead of making OS calls directly, then the HwiP port handles the interrupt priority in an OS specific way. In the case of the SYS/BIOS port, intPriority is passed unmodified to Hwi_create().

A sample structure is shown below:

const SPILPF3DMA_HWAttrs SPILPF3DMAobjects[] = {
    {
        .baseAddr = SPI0_BASE,
        .intNum = INT_SPI0,
        .intPriority = ~0,
        .swiPriority = 0,
        .powerMngrId = PERIPH_SPI0,
        .defaultTxBufValue = 0,
        .rxChannelBitMask = UDMA_CHAN_SPI0_RX,
        .txChannelBitMask = UDMA_CHAN_SPI0_TX,
        .picoPin = CONFIG_SPI0_POCI,
        .pociPin = CONFIG_SPI0_PICO,
        .clkPin = CONFIG_SPI0_CLK,
        .csnPin = CONFIG_SPI0_CSN
    },
    {
        .baseAddr = SPI1_BASE,
        .intNum = INT_SPI1,
        .intPriority = ~0,
        .swiPriority = 0,
        .powerMngrId = PERIPH_SPI1,
        .defaultTxBufValue = 0,
        .rxChannelBitMask = UDMA_CHAN_SPI1_RX,
        .txChannelBitMask = UDMA_CHAN_SPI1_TX,
        .picoPin = CONFIG_SPI1_POCI,
        .pociPin = CONFIG_SPI1_PICO,
        .clkPin = CONFIG_SPI1_CLK,
        .csnPin = CONFIG_SPI1_CSN
    },
};

Field Documentation

§ baseAddr

uint32_t SPILPF3DMA_HWAttrs::baseAddr

SPI Peripheral's base address.

§ intNum

uint8_t SPILPF3DMA_HWAttrs::intNum

SPILPF3DMA Peripheral's interrupt vector

§ intPriority

uint8_t SPILPF3DMA_HWAttrs::intPriority

SPILPF3DMA Peripheral's interrupt priority.

The Low Power F3 devices use either three or two priority bits, depending on the device. That means ~0 has the same effect as (7 << 5) or (3 << 6), respectively.

Setting the priority to 0 is not supported by this driver.

HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.

§ swiPriority

uint32_t SPILPF3DMA_HWAttrs::swiPriority

SPI SWI priority. The higher the number, the higher the priority. The minimum is 0 and the maximum is 15 by default. The maximum can be reduced to save RAM by adding or modifying Swi.numPriorities in the kernel configuration file.

§ powerID

uint8_t SPILPF3DMA_HWAttrs::powerID

Power driver ID for this SPI instance

§ defaultTxBufValue

uint16_t SPILPF3DMA_HWAttrs::defaultTxBufValue

Default TX value if txBuf == NULL

§ rxChannelBitMask

uint32_t SPILPF3DMA_HWAttrs::rxChannelBitMask

uDMA controlTable channel index

§ txChannelBitMask

uint32_t SPILPF3DMA_HWAttrs::txChannelBitMask

uDMA controlTable channel index

§ txChannelEvtMux

uint8_t SPILPF3DMA_HWAttrs::txChannelEvtMux

Mux ID for this SPI instance TX pin

§ rxChannelEvtMux

uint8_t SPILPF3DMA_HWAttrs::rxChannelEvtMux

Mux ID for this SPI instance RX pin

§ dmaTxTableEntryPri

volatile uDMAControlTableEntry* SPILPF3DMA_HWAttrs::dmaTxTableEntryPri

uDMA controlTable primary tx entry

§ dmaRxTableEntryPri

volatile uDMAControlTableEntry* SPILPF3DMA_HWAttrs::dmaRxTableEntryPri

uDMA controlTable primary tx entry

§ dmaTxTableEntryAlt

volatile uDMAControlTableEntry* SPILPF3DMA_HWAttrs::dmaTxTableEntryAlt

uDMA controlTable alternate tx entry

§ dmaRxTableEntryAlt

volatile uDMAControlTableEntry* SPILPF3DMA_HWAttrs::dmaRxTableEntryAlt

uDMA controlTable alternate rx entry

§ pociPinMux

int32_t SPILPF3DMA_HWAttrs::pociPinMux

POCI PIN mux value. Can be applied to either PICO or POCI

§ picoPinMux

int32_t SPILPF3DMA_HWAttrs::picoPinMux

PICO PIN mux value. Can be applied to either PICO or POCI

§ sclkPinMux

int32_t SPILPF3DMA_HWAttrs::sclkPinMux

SCLK PIN mux value for flow control

§ csnPinMux

int32_t SPILPF3DMA_HWAttrs::csnPinMux

CSN PIN mux value for flow control

§ picoPin

uint_least8_t SPILPF3DMA_HWAttrs::picoPin

SPI PICO pin

§ pociPin

uint_least8_t SPILPF3DMA_HWAttrs::pociPin

SPI POCI pin

§ sclkPin

uint_least8_t SPILPF3DMA_HWAttrs::sclkPin

SPI SCLK pin

§ csnPin

uint_least8_t SPILPF3DMA_HWAttrs::csnPin

CSN CSN pin

§ minDmaTransferSize

uint32_t SPILPF3DMA_HWAttrs::minDmaTransferSize

Minimum transfer size for DMA based transfer

The documentation for this struct was generated from the following file:

SPILPF3DMA.h

Data Fields