Macros
#define	SYSTIM_O_DESC 0x00000000U

#define	SYSTIM_O_IMASK 0x00000044U

#define	SYSTIM_O_RIS 0x00000048U

#define	SYSTIM_O_MIS 0x0000004CU

#define	SYSTIM_O_ISET 0x00000050U

#define	SYSTIM_O_ICLR 0x00000054U

#define	SYSTIM_O_IMSET 0x00000058U

#define	SYSTIM_O_IMCLR 0x0000005CU

#define	SYSTIM_O_EMU 0x00000060U

#define	SYSTIM_O_TIME250N 0x00000100U

#define	SYSTIM_O_TIME1U 0x00000104U

#define	SYSTIM_O_OUT 0x00000108U

#define	SYSTIM_O_CH0CFG 0x0000010CU

#define	SYSTIM_O_CH1CFG 0x00000110U

#define	SYSTIM_O_CH2CFG 0x00000114U

#define	SYSTIM_O_CH3CFG 0x00000118U

#define	SYSTIM_O_CH4CFG 0x0000011CU

#define	SYSTIM_O_CH0CC 0x00000120U

#define	SYSTIM_O_CH1CC 0x00000124U

#define	SYSTIM_O_CH2CC 0x00000128U

#define	SYSTIM_O_CH3CC 0x0000012CU

#define	SYSTIM_O_CH4CC 0x00000130U

#define	SYSTIM_O_TIMEBIT 0x00000134U

#define	SYSTIM_O_STATUS 0x00000140U

#define	SYSTIM_O_ARMSET 0x00000144U

#define	SYSTIM_O_ARMCLR 0x00000148U

#define	SYSTIM_O_CH0CCSR 0x0000014CU

#define	SYSTIM_O_CH1CCSR 0x00000150U

#define	SYSTIM_O_CH2CCSR 0x00000154U

#define	SYSTIM_O_CH3CCSR 0x00000158U

#define	SYSTIM_O_CH4CCSR 0x0000015CU

#define	SYSTIM_DESC_MODID_W 16U

#define	SYSTIM_DESC_MODID_M 0xFFFF0000U

#define	SYSTIM_DESC_MODID_S 16U

#define	SYSTIM_DESC_STDIPOFF_W 4U

#define	SYSTIM_DESC_STDIPOFF_M 0x0000F000U

#define	SYSTIM_DESC_STDIPOFF_S 12U

#define	SYSTIM_DESC_INSTIDX_W 4U

#define	SYSTIM_DESC_INSTIDX_M 0x00000F00U

#define	SYSTIM_DESC_INSTIDX_S 8U

#define	SYSTIM_DESC_MAJREV_W 4U

#define	SYSTIM_DESC_MAJREV_M 0x000000F0U

#define	SYSTIM_DESC_MAJREV_S 4U

#define	SYSTIM_DESC_MINREV_W 4U

#define	SYSTIM_DESC_MINREV_M 0x0000000FU

#define	SYSTIM_DESC_MINREV_S 0U

#define	SYSTIM_IMASK_OVFL 0x00000020U

#define	SYSTIM_IMASK_OVFL_M 0x00000020U

#define	SYSTIM_IMASK_OVFL_S 5U

#define	SYSTIM_IMASK_OVFL_EN 0x00000020U

#define	SYSTIM_IMASK_OVFL_DIS 0x00000000U

#define	SYSTIM_IMASK_EV4 0x00000010U

#define	SYSTIM_IMASK_EV4_M 0x00000010U

#define	SYSTIM_IMASK_EV4_S 4U

#define	SYSTIM_IMASK_EV4_EN 0x00000010U

#define	SYSTIM_IMASK_EV4_DIS 0x00000000U

#define	SYSTIM_IMASK_EV3 0x00000008U

#define	SYSTIM_IMASK_EV3_M 0x00000008U

#define	SYSTIM_IMASK_EV3_S 3U

#define	SYSTIM_IMASK_EV3_EN 0x00000008U

#define	SYSTIM_IMASK_EV3_DIS 0x00000000U

#define	SYSTIM_IMASK_EV2 0x00000004U

#define	SYSTIM_IMASK_EV2_M 0x00000004U

#define	SYSTIM_IMASK_EV2_S 2U

#define	SYSTIM_IMASK_EV2_EN 0x00000004U

#define	SYSTIM_IMASK_EV2_DIS 0x00000000U

#define	SYSTIM_IMASK_EV1 0x00000002U

#define	SYSTIM_IMASK_EV1_M 0x00000002U

#define	SYSTIM_IMASK_EV1_S 1U

#define	SYSTIM_IMASK_EV1_EN 0x00000002U

#define	SYSTIM_IMASK_EV1_DIS 0x00000000U

#define	SYSTIM_IMASK_EV0 0x00000001U

#define	SYSTIM_IMASK_EV0_M 0x00000001U

#define	SYSTIM_IMASK_EV0_S 0U

#define	SYSTIM_IMASK_EV0_EN 0x00000001U

#define	SYSTIM_IMASK_EV0_DIS 0x00000000U

#define	SYSTIM_RIS_OVFL 0x00000020U

#define	SYSTIM_RIS_OVFL_M 0x00000020U

#define	SYSTIM_RIS_OVFL_S 5U

#define	SYSTIM_RIS_OVFL_SET 0x00000020U

#define	SYSTIM_RIS_OVFL_CLR 0x00000000U

#define	SYSTIM_RIS_EV4 0x00000010U

#define	SYSTIM_RIS_EV4_M 0x00000010U

#define	SYSTIM_RIS_EV4_S 4U

#define	SYSTIM_RIS_EV4_SET 0x00000010U

#define	SYSTIM_RIS_EV4_CLR 0x00000000U

#define	SYSTIM_RIS_EV3 0x00000008U

#define	SYSTIM_RIS_EV3_M 0x00000008U

#define	SYSTIM_RIS_EV3_S 3U

#define	SYSTIM_RIS_EV3_SET 0x00000008U

#define	SYSTIM_RIS_EV3_CLR 0x00000000U

#define	SYSTIM_RIS_EV2 0x00000004U

#define	SYSTIM_RIS_EV2_M 0x00000004U

#define	SYSTIM_RIS_EV2_S 2U

#define	SYSTIM_RIS_EV2_SET 0x00000004U

#define	SYSTIM_RIS_EV2_CLR 0x00000000U

#define	SYSTIM_RIS_EV1 0x00000002U

#define	SYSTIM_RIS_EV1_M 0x00000002U

#define	SYSTIM_RIS_EV1_S 1U

#define	SYSTIM_RIS_EV1_SET 0x00000002U

#define	SYSTIM_RIS_EV1_CLR 0x00000000U

#define	SYSTIM_RIS_EV0 0x00000001U

#define	SYSTIM_RIS_EV0_M 0x00000001U

#define	SYSTIM_RIS_EV0_S 0U

#define	SYSTIM_RIS_EV0_SET 0x00000001U

#define	SYSTIM_RIS_EV0_CLR 0x00000000U

#define	SYSTIM_MIS_OVFL 0x00000020U

#define	SYSTIM_MIS_OVFL_M 0x00000020U

#define	SYSTIM_MIS_OVFL_S 5U

#define	SYSTIM_MIS_OVFL_SET 0x00000020U

#define	SYSTIM_MIS_OVFL_CLR 0x00000000U

#define	SYSTIM_MIS_EV4 0x00000010U

#define	SYSTIM_MIS_EV4_M 0x00000010U

#define	SYSTIM_MIS_EV4_S 4U

#define	SYSTIM_MIS_EV4_SET 0x00000010U

#define	SYSTIM_MIS_EV4_CLR 0x00000000U

#define	SYSTIM_MIS_EV3 0x00000008U

#define	SYSTIM_MIS_EV3_M 0x00000008U

#define	SYSTIM_MIS_EV3_S 3U

#define	SYSTIM_MIS_EV3_SET 0x00000008U

#define	SYSTIM_MIS_EV3_CLR 0x00000000U

#define	SYSTIM_MIS_EV2 0x00000004U

#define	SYSTIM_MIS_EV2_M 0x00000004U

#define	SYSTIM_MIS_EV2_S 2U

#define	SYSTIM_MIS_EV2_SET 0x00000004U

#define	SYSTIM_MIS_EV2_CLR 0x00000000U

#define	SYSTIM_MIS_EV1 0x00000002U

#define	SYSTIM_MIS_EV1_M 0x00000002U

#define	SYSTIM_MIS_EV1_S 1U

#define	SYSTIM_MIS_EV1_SET 0x00000002U

#define	SYSTIM_MIS_EV1_CLR 0x00000000U

#define	SYSTIM_MIS_EV0 0x00000001U

#define	SYSTIM_MIS_EV0_M 0x00000001U

#define	SYSTIM_MIS_EV0_S 0U

#define	SYSTIM_MIS_EV0_SET 0x00000001U

#define	SYSTIM_MIS_EV0_CLR 0x00000000U

#define	SYSTIM_ISET_OVFL 0x00000020U

#define	SYSTIM_ISET_OVFL_M 0x00000020U

#define	SYSTIM_ISET_OVFL_S 5U

#define	SYSTIM_ISET_OVFL_SET 0x00000020U

#define	SYSTIM_ISET_OVFL_NOEFF 0x00000000U

#define	SYSTIM_ISET_EV4 0x00000010U

#define	SYSTIM_ISET_EV4_M 0x00000010U

#define	SYSTIM_ISET_EV4_S 4U

#define	SYSTIM_ISET_EV4_SET 0x00000010U

#define	SYSTIM_ISET_EV4_NOEFF 0x00000000U

#define	SYSTIM_ISET_EV3 0x00000008U

#define	SYSTIM_ISET_EV3_M 0x00000008U

#define	SYSTIM_ISET_EV3_S 3U

#define	SYSTIM_ISET_EV3_SET 0x00000008U

#define	SYSTIM_ISET_EV3_NOEFF 0x00000000U

#define	SYSTIM_ISET_EV2 0x00000004U

#define	SYSTIM_ISET_EV2_M 0x00000004U

#define	SYSTIM_ISET_EV2_S 2U

#define	SYSTIM_ISET_EV2_SET 0x00000004U

#define	SYSTIM_ISET_EV2_NOEFF 0x00000000U

#define	SYSTIM_ISET_EV1 0x00000002U

#define	SYSTIM_ISET_EV1_M 0x00000002U

#define	SYSTIM_ISET_EV1_S 1U

#define	SYSTIM_ISET_EV1_SET 0x00000002U

#define	SYSTIM_ISET_EV1_NOEFF 0x00000000U

#define	SYSTIM_ISET_EV0 0x00000001U

#define	SYSTIM_ISET_EV0_M 0x00000001U

#define	SYSTIM_ISET_EV0_S 0U

#define	SYSTIM_ISET_EV0_SET 0x00000001U

#define	SYSTIM_ISET_EV0_NOEFF 0x00000000U

#define	SYSTIM_ICLR_OVFL 0x00000020U

#define	SYSTIM_ICLR_OVFL_M 0x00000020U

#define	SYSTIM_ICLR_OVFL_S 5U

#define	SYSTIM_ICLR_OVFL_CLR 0x00000020U

#define	SYSTIM_ICLR_OVFL_NOEFF 0x00000000U

#define	SYSTIM_ICLR_EV4 0x00000010U

#define	SYSTIM_ICLR_EV4_M 0x00000010U

#define	SYSTIM_ICLR_EV4_S 4U

#define	SYSTIM_ICLR_EV4_CLR 0x00000010U

#define	SYSTIM_ICLR_EV4_NOEFF 0x00000000U

#define	SYSTIM_ICLR_EV3 0x00000008U

#define	SYSTIM_ICLR_EV3_M 0x00000008U

#define	SYSTIM_ICLR_EV3_S 3U

#define	SYSTIM_ICLR_EV3_CLR 0x00000008U

#define	SYSTIM_ICLR_EV3_NOEFF 0x00000000U

#define	SYSTIM_ICLR_EV2 0x00000004U

#define	SYSTIM_ICLR_EV2_M 0x00000004U

#define	SYSTIM_ICLR_EV2_S 2U

#define	SYSTIM_ICLR_EV2_CLR 0x00000004U

#define	SYSTIM_ICLR_EV2_NOEFF 0x00000000U

#define	SYSTIM_ICLR_EV1 0x00000002U

#define	SYSTIM_ICLR_EV1_M 0x00000002U

#define	SYSTIM_ICLR_EV1_S 1U

#define	SYSTIM_ICLR_EV1_CLR 0x00000002U

#define	SYSTIM_ICLR_EV1_NOEFF 0x00000000U

#define	SYSTIM_ICLR_EV0 0x00000001U

#define	SYSTIM_ICLR_EV0_M 0x00000001U

#define	SYSTIM_ICLR_EV0_S 0U

#define	SYSTIM_ICLR_EV0_CLR 0x00000001U

#define	SYSTIM_ICLR_EV0_NOEFF 0x00000000U

#define	SYSTIM_IMSET_OVFL 0x00000020U

#define	SYSTIM_IMSET_OVFL_M 0x00000020U

#define	SYSTIM_IMSET_OVFL_S 5U

#define	SYSTIM_IMSET_OVFL_SET 0x00000020U

#define	SYSTIM_IMSET_OVFL_NOEFF 0x00000000U

#define	SYSTIM_IMSET_EV4 0x00000010U

#define	SYSTIM_IMSET_EV4_M 0x00000010U

#define	SYSTIM_IMSET_EV4_S 4U

#define	SYSTIM_IMSET_EV4_SET 0x00000010U

#define	SYSTIM_IMSET_EV4_NOEFF 0x00000000U

#define	SYSTIM_IMSET_EV3 0x00000008U

#define	SYSTIM_IMSET_EV3_M 0x00000008U

#define	SYSTIM_IMSET_EV3_S 3U

#define	SYSTIM_IMSET_EV3_SET 0x00000008U

#define	SYSTIM_IMSET_EV3_NOEFF 0x00000000U

#define	SYSTIM_IMSET_EV2 0x00000004U

#define	SYSTIM_IMSET_EV2_M 0x00000004U

#define	SYSTIM_IMSET_EV2_S 2U

#define	SYSTIM_IMSET_EV2_SET 0x00000004U

#define	SYSTIM_IMSET_EV2_NOEFF 0x00000000U

#define	SYSTIM_IMSET_EV1 0x00000002U

#define	SYSTIM_IMSET_EV1_M 0x00000002U

#define	SYSTIM_IMSET_EV1_S 1U

#define	SYSTIM_IMSET_EV1_SET 0x00000002U

#define	SYSTIM_IMSET_EV1_NOEFF 0x00000000U

#define	SYSTIM_IMSET_EV0 0x00000001U

#define	SYSTIM_IMSET_EV0_M 0x00000001U

#define	SYSTIM_IMSET_EV0_S 0U

#define	SYSTIM_IMSET_EV0_SET 0x00000001U

#define	SYSTIM_IMSET_EV0_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_OVFL 0x00000020U

#define	SYSTIM_IMCLR_OVFL_M 0x00000020U

#define	SYSTIM_IMCLR_OVFL_S 5U

#define	SYSTIM_IMCLR_OVFL_CLR 0x00000020U

#define	SYSTIM_IMCLR_OVFL_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_EV4 0x00000010U

#define	SYSTIM_IMCLR_EV4_M 0x00000010U

#define	SYSTIM_IMCLR_EV4_S 4U

#define	SYSTIM_IMCLR_EV4_CLR 0x00000010U

#define	SYSTIM_IMCLR_EV4_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_EV3 0x00000008U

#define	SYSTIM_IMCLR_EV3_M 0x00000008U

#define	SYSTIM_IMCLR_EV3_S 3U

#define	SYSTIM_IMCLR_EV3_CLR 0x00000008U

#define	SYSTIM_IMCLR_EV3_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_EV2 0x00000004U

#define	SYSTIM_IMCLR_EV2_M 0x00000004U

#define	SYSTIM_IMCLR_EV2_S 2U

#define	SYSTIM_IMCLR_EV2_CLR 0x00000004U

#define	SYSTIM_IMCLR_EV2_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_EV1 0x00000002U

#define	SYSTIM_IMCLR_EV1_M 0x00000002U

#define	SYSTIM_IMCLR_EV1_S 1U

#define	SYSTIM_IMCLR_EV1_CLR 0x00000002U

#define	SYSTIM_IMCLR_EV1_NOEFF 0x00000000U

#define	SYSTIM_IMCLR_EV0 0x00000001U

#define	SYSTIM_IMCLR_EV0_M 0x00000001U

#define	SYSTIM_IMCLR_EV0_S 0U

#define	SYSTIM_IMCLR_EV0_CLR 0x00000001U

#define	SYSTIM_IMCLR_EV0_NOEFF 0x00000000U

#define	SYSTIM_EMU_HALT 0x00000001U

#define	SYSTIM_EMU_HALT_M 0x00000001U

#define	SYSTIM_EMU_HALT_S 0U

#define	SYSTIM_EMU_HALT_STOP 0x00000001U

#define	SYSTIM_EMU_HALT_RUN 0x00000000U

#define	SYSTIM_TIME250N_VAL_W 32U

#define	SYSTIM_TIME250N_VAL_M 0xFFFFFFFFU

#define	SYSTIM_TIME250N_VAL_S 0U

#define	SYSTIM_TIME1U_VAL_W 32U

#define	SYSTIM_TIME1U_VAL_M 0xFFFFFFFFU

#define	SYSTIM_TIME1U_VAL_S 0U

#define	SYSTIM_OUT_OUT4 0x00000010U

#define	SYSTIM_OUT_OUT4_M 0x00000010U

#define	SYSTIM_OUT_OUT4_S 4U

#define	SYSTIM_OUT_OUT4_SET 0x00000010U

#define	SYSTIM_OUT_OUT4_CLR 0x00000000U

#define	SYSTIM_OUT_OUT3 0x00000008U

#define	SYSTIM_OUT_OUT3_M 0x00000008U

#define	SYSTIM_OUT_OUT3_S 3U

#define	SYSTIM_OUT_OUT3_SET 0x00000008U

#define	SYSTIM_OUT_OUT3_CLR 0x00000000U

#define	SYSTIM_OUT_OUT2 0x00000004U

#define	SYSTIM_OUT_OUT2_M 0x00000004U

#define	SYSTIM_OUT_OUT2_S 2U

#define	SYSTIM_OUT_OUT2_SET 0x00000004U

#define	SYSTIM_OUT_OUT2_CLR 0x00000000U

#define	SYSTIM_OUT_OUT1 0x00000002U

#define	SYSTIM_OUT_OUT1_M 0x00000002U

#define	SYSTIM_OUT_OUT1_S 1U

#define	SYSTIM_OUT_OUT1_SET 0x00000002U

#define	SYSTIM_OUT_OUT1_CLR 0x00000000U

#define	SYSTIM_OUT_OUT0 0x00000001U

#define	SYSTIM_OUT_OUT0_M 0x00000001U

#define	SYSTIM_OUT_OUT0_S 0U

#define	SYSTIM_OUT_OUT0_SET 0x00000001U

#define	SYSTIM_OUT_OUT0_CLR 0x00000000U

#define	SYSTIM_CH0CFG_RES 0x00000010U

#define	SYSTIM_CH0CFG_RES_M 0x00000010U

#define	SYSTIM_CH0CFG_RES_S 4U

#define	SYSTIM_CH0CFG_RES_NS 0x00000010U

#define	SYSTIM_CH0CFG_RES_US 0x00000000U

#define	SYSTIM_CH0CFG_REARM 0x00000008U

#define	SYSTIM_CH0CFG_REARM_M 0x00000008U

#define	SYSTIM_CH0CFG_REARM_S 3U

#define	SYSTIM_CH0CFG_REARM_EN 0x00000008U

#define	SYSTIM_CH0CFG_REARM_DIS 0x00000000U

#define	SYSTIM_CH0CFG_INP_W 2U

#define	SYSTIM_CH0CFG_INP_M 0x00000006U

#define	SYSTIM_CH0CFG_INP_S 1U

#define	SYSTIM_CH0CFG_INP_BOTH 0x00000004U

#define	SYSTIM_CH0CFG_INP_FALL 0x00000002U

#define	SYSTIM_CH0CFG_INP_RISE 0x00000000U

#define	SYSTIM_CH0CFG_MODE 0x00000001U

#define	SYSTIM_CH0CFG_MODE_M 0x00000001U

#define	SYSTIM_CH0CFG_MODE_S 0U

#define	SYSTIM_CH0CFG_MODE_CAPT 0x00000001U

#define	SYSTIM_CH0CFG_MODE_DIS 0x00000000U

#define	SYSTIM_CH1CFG_REARM 0x00000008U

#define	SYSTIM_CH1CFG_REARM_M 0x00000008U

#define	SYSTIM_CH1CFG_REARM_S 3U

#define	SYSTIM_CH1CFG_REARM_EN 0x00000008U

#define	SYSTIM_CH1CFG_REARM_DIS 0x00000000U

#define	SYSTIM_CH1CFG_INP_W 2U

#define	SYSTIM_CH1CFG_INP_M 0x00000006U

#define	SYSTIM_CH1CFG_INP_S 1U

#define	SYSTIM_CH1CFG_INP_BOTH 0x00000004U

#define	SYSTIM_CH1CFG_INP_FALL 0x00000002U

#define	SYSTIM_CH1CFG_INP_RISE 0x00000000U

#define	SYSTIM_CH1CFG_MODE 0x00000001U

#define	SYSTIM_CH1CFG_MODE_M 0x00000001U

#define	SYSTIM_CH1CFG_MODE_S 0U

#define	SYSTIM_CH1CFG_MODE_CAPT 0x00000001U

#define	SYSTIM_CH1CFG_MODE_DIS 0x00000000U

#define	SYSTIM_CH2CFG_REARM 0x00000008U

#define	SYSTIM_CH2CFG_REARM_M 0x00000008U

#define	SYSTIM_CH2CFG_REARM_S 3U

#define	SYSTIM_CH2CFG_REARM_EN 0x00000008U

#define	SYSTIM_CH2CFG_REARM_DIS 0x00000000U

#define	SYSTIM_CH2CFG_INP_W 2U

#define	SYSTIM_CH2CFG_INP_M 0x00000006U

#define	SYSTIM_CH2CFG_INP_S 1U

#define	SYSTIM_CH2CFG_INP_BOTH 0x00000004U

#define	SYSTIM_CH2CFG_INP_FALL 0x00000002U

#define	SYSTIM_CH2CFG_INP_RISE 0x00000000U

#define	SYSTIM_CH2CFG_MODE 0x00000001U

#define	SYSTIM_CH2CFG_MODE_M 0x00000001U

#define	SYSTIM_CH2CFG_MODE_S 0U

#define	SYSTIM_CH2CFG_MODE_CAPT 0x00000001U

#define	SYSTIM_CH2CFG_MODE_DIS 0x00000000U

#define	SYSTIM_CH3CFG_REARM 0x00000008U

#define	SYSTIM_CH3CFG_REARM_M 0x00000008U

#define	SYSTIM_CH3CFG_REARM_S 3U

#define	SYSTIM_CH3CFG_REARM_EN 0x00000008U

#define	SYSTIM_CH3CFG_REARM_DIS 0x00000000U

#define	SYSTIM_CH3CFG_INP_W 2U

#define	SYSTIM_CH3CFG_INP_M 0x00000006U

#define	SYSTIM_CH3CFG_INP_S 1U

#define	SYSTIM_CH3CFG_INP_BOTH 0x00000004U

#define	SYSTIM_CH3CFG_INP_FALL 0x00000002U

#define	SYSTIM_CH3CFG_INP_RISE 0x00000000U

#define	SYSTIM_CH3CFG_MODE 0x00000001U

#define	SYSTIM_CH3CFG_MODE_M 0x00000001U

#define	SYSTIM_CH3CFG_MODE_S 0U

#define	SYSTIM_CH3CFG_MODE_CAPT 0x00000001U

#define	SYSTIM_CH3CFG_MODE_DIS 0x00000000U

#define	SYSTIM_CH4CFG_REARM 0x00000008U

#define	SYSTIM_CH4CFG_REARM_M 0x00000008U

#define	SYSTIM_CH4CFG_REARM_S 3U

#define	SYSTIM_CH4CFG_REARM_EN 0x00000008U

#define	SYSTIM_CH4CFG_REARM_DIS 0x00000000U

#define	SYSTIM_CH4CFG_INP_W 2U

#define	SYSTIM_CH4CFG_INP_M 0x00000006U

#define	SYSTIM_CH4CFG_INP_S 1U

#define	SYSTIM_CH4CFG_INP_BOTH 0x00000004U

#define	SYSTIM_CH4CFG_INP_FALL 0x00000002U

#define	SYSTIM_CH4CFG_INP_RISE 0x00000000U

#define	SYSTIM_CH4CFG_MODE 0x00000001U

#define	SYSTIM_CH4CFG_MODE_M 0x00000001U

#define	SYSTIM_CH4CFG_MODE_S 0U

#define	SYSTIM_CH4CFG_MODE_CAPT 0x00000001U

#define	SYSTIM_CH4CFG_MODE_DIS 0x00000000U

#define	SYSTIM_CH0CC_VAL_W 32U

#define	SYSTIM_CH0CC_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH0CC_VAL_S 0U

#define	SYSTIM_CH1CC_VAL_W 32U

#define	SYSTIM_CH1CC_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH1CC_VAL_S 0U

#define	SYSTIM_CH2CC_VAL_W 32U

#define	SYSTIM_CH2CC_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH2CC_VAL_S 0U

#define	SYSTIM_CH3CC_VAL_W 32U

#define	SYSTIM_CH3CC_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH3CC_VAL_S 0U

#define	SYSTIM_CH4CC_VAL_W 32U

#define	SYSTIM_CH4CC_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH4CC_VAL_S 0U

#define	SYSTIM_TIMEBIT_VAL_W 16U

#define	SYSTIM_TIMEBIT_VAL_M 0x0000FFFFU

#define	SYSTIM_TIMEBIT_VAL_S 0U

#define	SYSTIM_TIMEBIT_VAL_BIT17 0x00008000U

#define	SYSTIM_TIMEBIT_VAL_BIT16 0x00004000U

#define	SYSTIM_TIMEBIT_VAL_BIT15 0x00002000U

#define	SYSTIM_TIMEBIT_VAL_BIT14 0x00001000U

#define	SYSTIM_TIMEBIT_VAL_BIT13 0x00000800U

#define	SYSTIM_TIMEBIT_VAL_BIT12 0x00000400U

#define	SYSTIM_TIMEBIT_VAL_BIT11 0x00000200U

#define	SYSTIM_TIMEBIT_VAL_BIT10 0x00000100U

#define	SYSTIM_TIMEBIT_VAL_BIT9 0x00000080U

#define	SYSTIM_TIMEBIT_VAL_BIT8 0x00000040U

#define	SYSTIM_TIMEBIT_VAL_BIT7 0x00000020U

#define	SYSTIM_TIMEBIT_VAL_BIT6 0x00000010U

#define	SYSTIM_TIMEBIT_VAL_BIT5 0x00000008U

#define	SYSTIM_TIMEBIT_VAL_BIT4 0x00000004U

#define	SYSTIM_TIMEBIT_VAL_BIT3 0x00000002U

#define	SYSTIM_TIMEBIT_VAL_BIT2 0x00000001U

#define	SYSTIM_TIMEBIT_VAL_NOBIT 0x00000000U

#define	SYSTIM_STATUS_SYNCUP 0x00000010U

#define	SYSTIM_STATUS_SYNCUP_M 0x00000010U

#define	SYSTIM_STATUS_SYNCUP_S 4U

#define	SYSTIM_STATUS_VAL 0x00000001U

#define	SYSTIM_STATUS_VAL_M 0x00000001U

#define	SYSTIM_STATUS_VAL_S 0U

#define	SYSTIM_STATUS_VAL_RUN 0x00000001U

#define	SYSTIM_STATUS_VAL_STOP 0x00000000U

#define	SYSTIM_ARMSET_CH4 0x00000010U

#define	SYSTIM_ARMSET_CH4_M 0x00000010U

#define	SYSTIM_ARMSET_CH4_S 4U

#define	SYSTIM_ARMSET_CH4_SET 0x00000010U

#define	SYSTIM_ARMSET_CH4_NOEFF 0x00000000U

#define	SYSTIM_ARMSET_CH3 0x00000008U

#define	SYSTIM_ARMSET_CH3_M 0x00000008U

#define	SYSTIM_ARMSET_CH3_S 3U

#define	SYSTIM_ARMSET_CH3_SET 0x00000008U

#define	SYSTIM_ARMSET_CH3_NOEFF 0x00000000U

#define	SYSTIM_ARMSET_CH2 0x00000004U

#define	SYSTIM_ARMSET_CH2_M 0x00000004U

#define	SYSTIM_ARMSET_CH2_S 2U

#define	SYSTIM_ARMSET_CH2_SET 0x00000004U

#define	SYSTIM_ARMSET_CH2_NOEFF 0x00000000U

#define	SYSTIM_ARMSET_CH1 0x00000002U

#define	SYSTIM_ARMSET_CH1_M 0x00000002U

#define	SYSTIM_ARMSET_CH1_S 1U

#define	SYSTIM_ARMSET_CH1_SET 0x00000002U

#define	SYSTIM_ARMSET_CH1_NOEFF 0x00000000U

#define	SYSTIM_ARMSET_CH0 0x00000001U

#define	SYSTIM_ARMSET_CH0_M 0x00000001U

#define	SYSTIM_ARMSET_CH0_S 0U

#define	SYSTIM_ARMSET_CH0_SET 0x00000001U

#define	SYSTIM_ARMSET_CH0_NOEFF 0x00000000U

#define	SYSTIM_ARMCLR_CH4 0x00000010U

#define	SYSTIM_ARMCLR_CH4_M 0x00000010U

#define	SYSTIM_ARMCLR_CH4_S 4U

#define	SYSTIM_ARMCLR_CH4_CLR 0x00000010U

#define	SYSTIM_ARMCLR_CH4_NOEFF 0x00000000U

#define	SYSTIM_ARMCLR_CH3 0x00000008U

#define	SYSTIM_ARMCLR_CH3_M 0x00000008U

#define	SYSTIM_ARMCLR_CH3_S 3U

#define	SYSTIM_ARMCLR_CH3_CLR 0x00000008U

#define	SYSTIM_ARMCLR_CH3_NOEFF 0x00000000U

#define	SYSTIM_ARMCLR_CH2 0x00000004U

#define	SYSTIM_ARMCLR_CH2_M 0x00000004U

#define	SYSTIM_ARMCLR_CH2_S 2U

#define	SYSTIM_ARMCLR_CH2_CLR 0x00000004U

#define	SYSTIM_ARMCLR_CH2_NOEFF 0x00000000U

#define	SYSTIM_ARMCLR_CH1 0x00000002U

#define	SYSTIM_ARMCLR_CH1_M 0x00000002U

#define	SYSTIM_ARMCLR_CH1_S 1U

#define	SYSTIM_ARMCLR_CH1_CLR 0x00000002U

#define	SYSTIM_ARMCLR_CH1_NOEFF 0x00000000U

#define	SYSTIM_ARMCLR_CH0 0x00000001U

#define	SYSTIM_ARMCLR_CH0_M 0x00000001U

#define	SYSTIM_ARMCLR_CH0_S 0U

#define	SYSTIM_ARMCLR_CH0_CLR 0x00000001U

#define	SYSTIM_ARMCLR_CH0_NOEFF 0x00000000U

#define	SYSTIM_CH0CCSR_VAL_W 32U

#define	SYSTIM_CH0CCSR_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH0CCSR_VAL_S 0U

#define	SYSTIM_CH1CCSR_VAL_W 32U

#define	SYSTIM_CH1CCSR_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH1CCSR_VAL_S 0U

#define	SYSTIM_CH2CCSR_VAL_W 32U

#define	SYSTIM_CH2CCSR_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH2CCSR_VAL_S 0U

#define	SYSTIM_CH3CCSR_VAL_W 32U

#define	SYSTIM_CH3CCSR_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH3CCSR_VAL_S 0U

#define	SYSTIM_CH4CCSR_VAL_W 32U

#define	SYSTIM_CH4CCSR_VAL_M 0xFFFFFFFFU

#define	SYSTIM_CH4CCSR_VAL_S 0U

Macro Definition Documentation

§ SYSTIM_O_DESC

#define SYSTIM_O_DESC 0x00000000U

§ SYSTIM_O_IMASK

#define SYSTIM_O_IMASK 0x00000044U

§ SYSTIM_O_RIS

#define SYSTIM_O_RIS 0x00000048U

§ SYSTIM_O_MIS

#define SYSTIM_O_MIS 0x0000004CU

§ SYSTIM_O_ISET

#define SYSTIM_O_ISET 0x00000050U

§ SYSTIM_O_ICLR

#define SYSTIM_O_ICLR 0x00000054U

§ SYSTIM_O_IMSET

#define SYSTIM_O_IMSET 0x00000058U

§ SYSTIM_O_IMCLR

#define SYSTIM_O_IMCLR 0x0000005CU

§ SYSTIM_O_EMU

#define SYSTIM_O_EMU 0x00000060U

§ SYSTIM_O_TIME250N

#define SYSTIM_O_TIME250N 0x00000100U

§ SYSTIM_O_TIME1U

#define SYSTIM_O_TIME1U 0x00000104U

§ SYSTIM_O_OUT

#define SYSTIM_O_OUT 0x00000108U

§ SYSTIM_O_CH0CFG

#define SYSTIM_O_CH0CFG 0x0000010CU

§ SYSTIM_O_CH1CFG

#define SYSTIM_O_CH1CFG 0x00000110U

§ SYSTIM_O_CH2CFG

#define SYSTIM_O_CH2CFG 0x00000114U

§ SYSTIM_O_CH3CFG

#define SYSTIM_O_CH3CFG 0x00000118U

§ SYSTIM_O_CH4CFG

#define SYSTIM_O_CH4CFG 0x0000011CU

§ SYSTIM_O_CH0CC

#define SYSTIM_O_CH0CC 0x00000120U

§ SYSTIM_O_CH1CC

#define SYSTIM_O_CH1CC 0x00000124U

§ SYSTIM_O_CH2CC

#define SYSTIM_O_CH2CC 0x00000128U

§ SYSTIM_O_CH3CC

#define SYSTIM_O_CH3CC 0x0000012CU

§ SYSTIM_O_CH4CC

#define SYSTIM_O_CH4CC 0x00000130U

§ SYSTIM_O_TIMEBIT

#define SYSTIM_O_TIMEBIT 0x00000134U

§ SYSTIM_O_STATUS

#define SYSTIM_O_STATUS 0x00000140U

§ SYSTIM_O_ARMSET

#define SYSTIM_O_ARMSET 0x00000144U

§ SYSTIM_O_ARMCLR

#define SYSTIM_O_ARMCLR 0x00000148U

§ SYSTIM_O_CH0CCSR

#define SYSTIM_O_CH0CCSR 0x0000014CU

§ SYSTIM_O_CH1CCSR

#define SYSTIM_O_CH1CCSR 0x00000150U

§ SYSTIM_O_CH2CCSR

#define SYSTIM_O_CH2CCSR 0x00000154U

§ SYSTIM_O_CH3CCSR

#define SYSTIM_O_CH3CCSR 0x00000158U

§ SYSTIM_O_CH4CCSR

#define SYSTIM_O_CH4CCSR 0x0000015CU

§ SYSTIM_DESC_MODID_W

#define SYSTIM_DESC_MODID_W 16U

§ SYSTIM_DESC_MODID_M

#define SYSTIM_DESC_MODID_M 0xFFFF0000U

§ SYSTIM_DESC_MODID_S

#define SYSTIM_DESC_MODID_S 16U

§ SYSTIM_DESC_STDIPOFF_W

#define SYSTIM_DESC_STDIPOFF_W 4U

§ SYSTIM_DESC_STDIPOFF_M

#define SYSTIM_DESC_STDIPOFF_M 0x0000F000U

§ SYSTIM_DESC_STDIPOFF_S

#define SYSTIM_DESC_STDIPOFF_S 12U

§ SYSTIM_DESC_INSTIDX_W

#define SYSTIM_DESC_INSTIDX_W 4U

§ SYSTIM_DESC_INSTIDX_M

#define SYSTIM_DESC_INSTIDX_M 0x00000F00U

§ SYSTIM_DESC_INSTIDX_S

#define SYSTIM_DESC_INSTIDX_S 8U

§ SYSTIM_DESC_MAJREV_W

#define SYSTIM_DESC_MAJREV_W 4U

§ SYSTIM_DESC_MAJREV_M

#define SYSTIM_DESC_MAJREV_M 0x000000F0U

§ SYSTIM_DESC_MAJREV_S

#define SYSTIM_DESC_MAJREV_S 4U

§ SYSTIM_DESC_MINREV_W

#define SYSTIM_DESC_MINREV_W 4U

§ SYSTIM_DESC_MINREV_M

#define SYSTIM_DESC_MINREV_M 0x0000000FU

§ SYSTIM_DESC_MINREV_S

#define SYSTIM_DESC_MINREV_S 0U

§ SYSTIM_IMASK_OVFL

#define SYSTIM_IMASK_OVFL 0x00000020U

§ SYSTIM_IMASK_OVFL_M

#define SYSTIM_IMASK_OVFL_M 0x00000020U

§ SYSTIM_IMASK_OVFL_S

#define SYSTIM_IMASK_OVFL_S 5U

§ SYSTIM_IMASK_OVFL_EN

#define SYSTIM_IMASK_OVFL_EN 0x00000020U

§ SYSTIM_IMASK_OVFL_DIS

#define SYSTIM_IMASK_OVFL_DIS 0x00000000U

§ SYSTIM_IMASK_EV4

#define SYSTIM_IMASK_EV4 0x00000010U

§ SYSTIM_IMASK_EV4_M

#define SYSTIM_IMASK_EV4_M 0x00000010U

§ SYSTIM_IMASK_EV4_S

#define SYSTIM_IMASK_EV4_S 4U

§ SYSTIM_IMASK_EV4_EN

#define SYSTIM_IMASK_EV4_EN 0x00000010U

§ SYSTIM_IMASK_EV4_DIS

#define SYSTIM_IMASK_EV4_DIS 0x00000000U

§ SYSTIM_IMASK_EV3

#define SYSTIM_IMASK_EV3 0x00000008U

§ SYSTIM_IMASK_EV3_M

#define SYSTIM_IMASK_EV3_M 0x00000008U

§ SYSTIM_IMASK_EV3_S

#define SYSTIM_IMASK_EV3_S 3U

§ SYSTIM_IMASK_EV3_EN

#define SYSTIM_IMASK_EV3_EN 0x00000008U

§ SYSTIM_IMASK_EV3_DIS

#define SYSTIM_IMASK_EV3_DIS 0x00000000U

§ SYSTIM_IMASK_EV2

#define SYSTIM_IMASK_EV2 0x00000004U

§ SYSTIM_IMASK_EV2_M

#define SYSTIM_IMASK_EV2_M 0x00000004U

§ SYSTIM_IMASK_EV2_S

#define SYSTIM_IMASK_EV2_S 2U

§ SYSTIM_IMASK_EV2_EN

#define SYSTIM_IMASK_EV2_EN 0x00000004U

§ SYSTIM_IMASK_EV2_DIS

#define SYSTIM_IMASK_EV2_DIS 0x00000000U

§ SYSTIM_IMASK_EV1

#define SYSTIM_IMASK_EV1 0x00000002U

§ SYSTIM_IMASK_EV1_M

#define SYSTIM_IMASK_EV1_M 0x00000002U

§ SYSTIM_IMASK_EV1_S

#define SYSTIM_IMASK_EV1_S 1U

§ SYSTIM_IMASK_EV1_EN

#define SYSTIM_IMASK_EV1_EN 0x00000002U

§ SYSTIM_IMASK_EV1_DIS

#define SYSTIM_IMASK_EV1_DIS 0x00000000U

§ SYSTIM_IMASK_EV0

#define SYSTIM_IMASK_EV0 0x00000001U

§ SYSTIM_IMASK_EV0_M

#define SYSTIM_IMASK_EV0_M 0x00000001U

§ SYSTIM_IMASK_EV0_S

#define SYSTIM_IMASK_EV0_S 0U

§ SYSTIM_IMASK_EV0_EN

#define SYSTIM_IMASK_EV0_EN 0x00000001U

§ SYSTIM_IMASK_EV0_DIS

#define SYSTIM_IMASK_EV0_DIS 0x00000000U

§ SYSTIM_RIS_OVFL

#define SYSTIM_RIS_OVFL 0x00000020U

§ SYSTIM_RIS_OVFL_M

#define SYSTIM_RIS_OVFL_M 0x00000020U

§ SYSTIM_RIS_OVFL_S

#define SYSTIM_RIS_OVFL_S 5U

§ SYSTIM_RIS_OVFL_SET

#define SYSTIM_RIS_OVFL_SET 0x00000020U

§ SYSTIM_RIS_OVFL_CLR

#define SYSTIM_RIS_OVFL_CLR 0x00000000U

§ SYSTIM_RIS_EV4

#define SYSTIM_RIS_EV4 0x00000010U

§ SYSTIM_RIS_EV4_M

#define SYSTIM_RIS_EV4_M 0x00000010U

§ SYSTIM_RIS_EV4_S

#define SYSTIM_RIS_EV4_S 4U

§ SYSTIM_RIS_EV4_SET

#define SYSTIM_RIS_EV4_SET 0x00000010U

§ SYSTIM_RIS_EV4_CLR

#define SYSTIM_RIS_EV4_CLR 0x00000000U

§ SYSTIM_RIS_EV3

#define SYSTIM_RIS_EV3 0x00000008U

§ SYSTIM_RIS_EV3_M

#define SYSTIM_RIS_EV3_M 0x00000008U

§ SYSTIM_RIS_EV3_S

#define SYSTIM_RIS_EV3_S 3U

§ SYSTIM_RIS_EV3_SET

#define SYSTIM_RIS_EV3_SET 0x00000008U

§ SYSTIM_RIS_EV3_CLR

#define SYSTIM_RIS_EV3_CLR 0x00000000U

§ SYSTIM_RIS_EV2

#define SYSTIM_RIS_EV2 0x00000004U

§ SYSTIM_RIS_EV2_M

#define SYSTIM_RIS_EV2_M 0x00000004U

§ SYSTIM_RIS_EV2_S

#define SYSTIM_RIS_EV2_S 2U

§ SYSTIM_RIS_EV2_SET

#define SYSTIM_RIS_EV2_SET 0x00000004U

§ SYSTIM_RIS_EV2_CLR

#define SYSTIM_RIS_EV2_CLR 0x00000000U

§ SYSTIM_RIS_EV1

#define SYSTIM_RIS_EV1 0x00000002U

§ SYSTIM_RIS_EV1_M

#define SYSTIM_RIS_EV1_M 0x00000002U

§ SYSTIM_RIS_EV1_S

#define SYSTIM_RIS_EV1_S 1U

§ SYSTIM_RIS_EV1_SET

#define SYSTIM_RIS_EV1_SET 0x00000002U

§ SYSTIM_RIS_EV1_CLR

#define SYSTIM_RIS_EV1_CLR 0x00000000U

§ SYSTIM_RIS_EV0

#define SYSTIM_RIS_EV0 0x00000001U

§ SYSTIM_RIS_EV0_M

#define SYSTIM_RIS_EV0_M 0x00000001U

§ SYSTIM_RIS_EV0_S

#define SYSTIM_RIS_EV0_S 0U

§ SYSTIM_RIS_EV0_SET

#define SYSTIM_RIS_EV0_SET 0x00000001U

§ SYSTIM_RIS_EV0_CLR

#define SYSTIM_RIS_EV0_CLR 0x00000000U

§ SYSTIM_MIS_OVFL

#define SYSTIM_MIS_OVFL 0x00000020U

§ SYSTIM_MIS_OVFL_M

#define SYSTIM_MIS_OVFL_M 0x00000020U

§ SYSTIM_MIS_OVFL_S

#define SYSTIM_MIS_OVFL_S 5U

§ SYSTIM_MIS_OVFL_SET

#define SYSTIM_MIS_OVFL_SET 0x00000020U

§ SYSTIM_MIS_OVFL_CLR

#define SYSTIM_MIS_OVFL_CLR 0x00000000U

§ SYSTIM_MIS_EV4

#define SYSTIM_MIS_EV4 0x00000010U

§ SYSTIM_MIS_EV4_M

#define SYSTIM_MIS_EV4_M 0x00000010U

§ SYSTIM_MIS_EV4_S

#define SYSTIM_MIS_EV4_S 4U

§ SYSTIM_MIS_EV4_SET

#define SYSTIM_MIS_EV4_SET 0x00000010U

§ SYSTIM_MIS_EV4_CLR

#define SYSTIM_MIS_EV4_CLR 0x00000000U

§ SYSTIM_MIS_EV3

#define SYSTIM_MIS_EV3 0x00000008U

§ SYSTIM_MIS_EV3_M

#define SYSTIM_MIS_EV3_M 0x00000008U

§ SYSTIM_MIS_EV3_S

#define SYSTIM_MIS_EV3_S 3U

§ SYSTIM_MIS_EV3_SET

#define SYSTIM_MIS_EV3_SET 0x00000008U

§ SYSTIM_MIS_EV3_CLR

#define SYSTIM_MIS_EV3_CLR 0x00000000U

§ SYSTIM_MIS_EV2

#define SYSTIM_MIS_EV2 0x00000004U

§ SYSTIM_MIS_EV2_M

#define SYSTIM_MIS_EV2_M 0x00000004U

§ SYSTIM_MIS_EV2_S

#define SYSTIM_MIS_EV2_S 2U

§ SYSTIM_MIS_EV2_SET

#define SYSTIM_MIS_EV2_SET 0x00000004U

§ SYSTIM_MIS_EV2_CLR

#define SYSTIM_MIS_EV2_CLR 0x00000000U

§ SYSTIM_MIS_EV1

#define SYSTIM_MIS_EV1 0x00000002U

§ SYSTIM_MIS_EV1_M

#define SYSTIM_MIS_EV1_M 0x00000002U

§ SYSTIM_MIS_EV1_S

#define SYSTIM_MIS_EV1_S 1U

§ SYSTIM_MIS_EV1_SET

#define SYSTIM_MIS_EV1_SET 0x00000002U

§ SYSTIM_MIS_EV1_CLR

#define SYSTIM_MIS_EV1_CLR 0x00000000U

§ SYSTIM_MIS_EV0

#define SYSTIM_MIS_EV0 0x00000001U

§ SYSTIM_MIS_EV0_M

#define SYSTIM_MIS_EV0_M 0x00000001U

§ SYSTIM_MIS_EV0_S

#define SYSTIM_MIS_EV0_S 0U

§ SYSTIM_MIS_EV0_SET

#define SYSTIM_MIS_EV0_SET 0x00000001U

§ SYSTIM_MIS_EV0_CLR

#define SYSTIM_MIS_EV0_CLR 0x00000000U

§ SYSTIM_ISET_OVFL

#define SYSTIM_ISET_OVFL 0x00000020U

§ SYSTIM_ISET_OVFL_M

#define SYSTIM_ISET_OVFL_M 0x00000020U

§ SYSTIM_ISET_OVFL_S

#define SYSTIM_ISET_OVFL_S 5U

§ SYSTIM_ISET_OVFL_SET

#define SYSTIM_ISET_OVFL_SET 0x00000020U

§ SYSTIM_ISET_OVFL_NOEFF

#define SYSTIM_ISET_OVFL_NOEFF 0x00000000U

§ SYSTIM_ISET_EV4

#define SYSTIM_ISET_EV4 0x00000010U

§ SYSTIM_ISET_EV4_M

#define SYSTIM_ISET_EV4_M 0x00000010U

§ SYSTIM_ISET_EV4_S

#define SYSTIM_ISET_EV4_S 4U

§ SYSTIM_ISET_EV4_SET

#define SYSTIM_ISET_EV4_SET 0x00000010U

§ SYSTIM_ISET_EV4_NOEFF

#define SYSTIM_ISET_EV4_NOEFF 0x00000000U

§ SYSTIM_ISET_EV3

#define SYSTIM_ISET_EV3 0x00000008U

§ SYSTIM_ISET_EV3_M

#define SYSTIM_ISET_EV3_M 0x00000008U

§ SYSTIM_ISET_EV3_S

#define SYSTIM_ISET_EV3_S 3U

§ SYSTIM_ISET_EV3_SET

#define SYSTIM_ISET_EV3_SET 0x00000008U

§ SYSTIM_ISET_EV3_NOEFF

#define SYSTIM_ISET_EV3_NOEFF 0x00000000U

§ SYSTIM_ISET_EV2

#define SYSTIM_ISET_EV2 0x00000004U

§ SYSTIM_ISET_EV2_M

#define SYSTIM_ISET_EV2_M 0x00000004U

§ SYSTIM_ISET_EV2_S

#define SYSTIM_ISET_EV2_S 2U

§ SYSTIM_ISET_EV2_SET

#define SYSTIM_ISET_EV2_SET 0x00000004U

§ SYSTIM_ISET_EV2_NOEFF

#define SYSTIM_ISET_EV2_NOEFF 0x00000000U

§ SYSTIM_ISET_EV1

#define SYSTIM_ISET_EV1 0x00000002U

§ SYSTIM_ISET_EV1_M

#define SYSTIM_ISET_EV1_M 0x00000002U

§ SYSTIM_ISET_EV1_S

#define SYSTIM_ISET_EV1_S 1U

§ SYSTIM_ISET_EV1_SET

#define SYSTIM_ISET_EV1_SET 0x00000002U

§ SYSTIM_ISET_EV1_NOEFF

#define SYSTIM_ISET_EV1_NOEFF 0x00000000U

§ SYSTIM_ISET_EV0

#define SYSTIM_ISET_EV0 0x00000001U

§ SYSTIM_ISET_EV0_M

#define SYSTIM_ISET_EV0_M 0x00000001U

§ SYSTIM_ISET_EV0_S

#define SYSTIM_ISET_EV0_S 0U

§ SYSTIM_ISET_EV0_SET

#define SYSTIM_ISET_EV0_SET 0x00000001U

§ SYSTIM_ISET_EV0_NOEFF

#define SYSTIM_ISET_EV0_NOEFF 0x00000000U

§ SYSTIM_ICLR_OVFL

#define SYSTIM_ICLR_OVFL 0x00000020U

§ SYSTIM_ICLR_OVFL_M

#define SYSTIM_ICLR_OVFL_M 0x00000020U

§ SYSTIM_ICLR_OVFL_S

#define SYSTIM_ICLR_OVFL_S 5U

§ SYSTIM_ICLR_OVFL_CLR

#define SYSTIM_ICLR_OVFL_CLR 0x00000020U

§ SYSTIM_ICLR_OVFL_NOEFF

#define SYSTIM_ICLR_OVFL_NOEFF 0x00000000U

§ SYSTIM_ICLR_EV4

#define SYSTIM_ICLR_EV4 0x00000010U

§ SYSTIM_ICLR_EV4_M

#define SYSTIM_ICLR_EV4_M 0x00000010U

§ SYSTIM_ICLR_EV4_S

#define SYSTIM_ICLR_EV4_S 4U

§ SYSTIM_ICLR_EV4_CLR

#define SYSTIM_ICLR_EV4_CLR 0x00000010U

§ SYSTIM_ICLR_EV4_NOEFF

#define SYSTIM_ICLR_EV4_NOEFF 0x00000000U

§ SYSTIM_ICLR_EV3

#define SYSTIM_ICLR_EV3 0x00000008U

§ SYSTIM_ICLR_EV3_M

#define SYSTIM_ICLR_EV3_M 0x00000008U

§ SYSTIM_ICLR_EV3_S

#define SYSTIM_ICLR_EV3_S 3U

§ SYSTIM_ICLR_EV3_CLR

#define SYSTIM_ICLR_EV3_CLR 0x00000008U

§ SYSTIM_ICLR_EV3_NOEFF

#define SYSTIM_ICLR_EV3_NOEFF 0x00000000U

§ SYSTIM_ICLR_EV2

#define SYSTIM_ICLR_EV2 0x00000004U

§ SYSTIM_ICLR_EV2_M

#define SYSTIM_ICLR_EV2_M 0x00000004U

§ SYSTIM_ICLR_EV2_S

#define SYSTIM_ICLR_EV2_S 2U

§ SYSTIM_ICLR_EV2_CLR

#define SYSTIM_ICLR_EV2_CLR 0x00000004U

§ SYSTIM_ICLR_EV2_NOEFF

#define SYSTIM_ICLR_EV2_NOEFF 0x00000000U

§ SYSTIM_ICLR_EV1

#define SYSTIM_ICLR_EV1 0x00000002U

§ SYSTIM_ICLR_EV1_M

#define SYSTIM_ICLR_EV1_M 0x00000002U

§ SYSTIM_ICLR_EV1_S

#define SYSTIM_ICLR_EV1_S 1U

§ SYSTIM_ICLR_EV1_CLR

#define SYSTIM_ICLR_EV1_CLR 0x00000002U

§ SYSTIM_ICLR_EV1_NOEFF

#define SYSTIM_ICLR_EV1_NOEFF 0x00000000U

§ SYSTIM_ICLR_EV0

#define SYSTIM_ICLR_EV0 0x00000001U

§ SYSTIM_ICLR_EV0_M

#define SYSTIM_ICLR_EV0_M 0x00000001U

§ SYSTIM_ICLR_EV0_S

#define SYSTIM_ICLR_EV0_S 0U

§ SYSTIM_ICLR_EV0_CLR

#define SYSTIM_ICLR_EV0_CLR 0x00000001U

§ SYSTIM_ICLR_EV0_NOEFF

#define SYSTIM_ICLR_EV0_NOEFF 0x00000000U

§ SYSTIM_IMSET_OVFL

#define SYSTIM_IMSET_OVFL 0x00000020U

§ SYSTIM_IMSET_OVFL_M

#define SYSTIM_IMSET_OVFL_M 0x00000020U

§ SYSTIM_IMSET_OVFL_S

#define SYSTIM_IMSET_OVFL_S 5U

§ SYSTIM_IMSET_OVFL_SET

#define SYSTIM_IMSET_OVFL_SET 0x00000020U

§ SYSTIM_IMSET_OVFL_NOEFF

#define SYSTIM_IMSET_OVFL_NOEFF 0x00000000U

§ SYSTIM_IMSET_EV4

#define SYSTIM_IMSET_EV4 0x00000010U

§ SYSTIM_IMSET_EV4_M

#define SYSTIM_IMSET_EV4_M 0x00000010U

§ SYSTIM_IMSET_EV4_S

#define SYSTIM_IMSET_EV4_S 4U

§ SYSTIM_IMSET_EV4_SET

#define SYSTIM_IMSET_EV4_SET 0x00000010U

§ SYSTIM_IMSET_EV4_NOEFF

#define SYSTIM_IMSET_EV4_NOEFF 0x00000000U

§ SYSTIM_IMSET_EV3

#define SYSTIM_IMSET_EV3 0x00000008U

§ SYSTIM_IMSET_EV3_M

#define SYSTIM_IMSET_EV3_M 0x00000008U

§ SYSTIM_IMSET_EV3_S

#define SYSTIM_IMSET_EV3_S 3U

§ SYSTIM_IMSET_EV3_SET

#define SYSTIM_IMSET_EV3_SET 0x00000008U

§ SYSTIM_IMSET_EV3_NOEFF

#define SYSTIM_IMSET_EV3_NOEFF 0x00000000U

§ SYSTIM_IMSET_EV2

#define SYSTIM_IMSET_EV2 0x00000004U

§ SYSTIM_IMSET_EV2_M

#define SYSTIM_IMSET_EV2_M 0x00000004U

§ SYSTIM_IMSET_EV2_S

#define SYSTIM_IMSET_EV2_S 2U

§ SYSTIM_IMSET_EV2_SET

#define SYSTIM_IMSET_EV2_SET 0x00000004U

§ SYSTIM_IMSET_EV2_NOEFF

#define SYSTIM_IMSET_EV2_NOEFF 0x00000000U

§ SYSTIM_IMSET_EV1

#define SYSTIM_IMSET_EV1 0x00000002U

§ SYSTIM_IMSET_EV1_M

#define SYSTIM_IMSET_EV1_M 0x00000002U

§ SYSTIM_IMSET_EV1_S

#define SYSTIM_IMSET_EV1_S 1U

§ SYSTIM_IMSET_EV1_SET

#define SYSTIM_IMSET_EV1_SET 0x00000002U

§ SYSTIM_IMSET_EV1_NOEFF

#define SYSTIM_IMSET_EV1_NOEFF 0x00000000U

§ SYSTIM_IMSET_EV0

#define SYSTIM_IMSET_EV0 0x00000001U

§ SYSTIM_IMSET_EV0_M

#define SYSTIM_IMSET_EV0_M 0x00000001U

§ SYSTIM_IMSET_EV0_S

#define SYSTIM_IMSET_EV0_S 0U

§ SYSTIM_IMSET_EV0_SET

#define SYSTIM_IMSET_EV0_SET 0x00000001U

§ SYSTIM_IMSET_EV0_NOEFF

#define SYSTIM_IMSET_EV0_NOEFF 0x00000000U

§ SYSTIM_IMCLR_OVFL

#define SYSTIM_IMCLR_OVFL 0x00000020U

§ SYSTIM_IMCLR_OVFL_M

#define SYSTIM_IMCLR_OVFL_M 0x00000020U

§ SYSTIM_IMCLR_OVFL_S

#define SYSTIM_IMCLR_OVFL_S 5U

§ SYSTIM_IMCLR_OVFL_CLR

#define SYSTIM_IMCLR_OVFL_CLR 0x00000020U

§ SYSTIM_IMCLR_OVFL_NOEFF

#define SYSTIM_IMCLR_OVFL_NOEFF 0x00000000U

§ SYSTIM_IMCLR_EV4

#define SYSTIM_IMCLR_EV4 0x00000010U

§ SYSTIM_IMCLR_EV4_M

#define SYSTIM_IMCLR_EV4_M 0x00000010U

§ SYSTIM_IMCLR_EV4_S

#define SYSTIM_IMCLR_EV4_S 4U

§ SYSTIM_IMCLR_EV4_CLR

#define SYSTIM_IMCLR_EV4_CLR 0x00000010U

§ SYSTIM_IMCLR_EV4_NOEFF

#define SYSTIM_IMCLR_EV4_NOEFF 0x00000000U

§ SYSTIM_IMCLR_EV3

#define SYSTIM_IMCLR_EV3 0x00000008U

§ SYSTIM_IMCLR_EV3_M

#define SYSTIM_IMCLR_EV3_M 0x00000008U

§ SYSTIM_IMCLR_EV3_S

#define SYSTIM_IMCLR_EV3_S 3U

§ SYSTIM_IMCLR_EV3_CLR

#define SYSTIM_IMCLR_EV3_CLR 0x00000008U

§ SYSTIM_IMCLR_EV3_NOEFF

#define SYSTIM_IMCLR_EV3_NOEFF 0x00000000U

§ SYSTIM_IMCLR_EV2

#define SYSTIM_IMCLR_EV2 0x00000004U

§ SYSTIM_IMCLR_EV2_M

#define SYSTIM_IMCLR_EV2_M 0x00000004U

§ SYSTIM_IMCLR_EV2_S

#define SYSTIM_IMCLR_EV2_S 2U

§ SYSTIM_IMCLR_EV2_CLR

#define SYSTIM_IMCLR_EV2_CLR 0x00000004U

§ SYSTIM_IMCLR_EV2_NOEFF

#define SYSTIM_IMCLR_EV2_NOEFF 0x00000000U

§ SYSTIM_IMCLR_EV1

#define SYSTIM_IMCLR_EV1 0x00000002U

§ SYSTIM_IMCLR_EV1_M

#define SYSTIM_IMCLR_EV1_M 0x00000002U

§ SYSTIM_IMCLR_EV1_S

#define SYSTIM_IMCLR_EV1_S 1U

§ SYSTIM_IMCLR_EV1_CLR

#define SYSTIM_IMCLR_EV1_CLR 0x00000002U

§ SYSTIM_IMCLR_EV1_NOEFF

#define SYSTIM_IMCLR_EV1_NOEFF 0x00000000U

§ SYSTIM_IMCLR_EV0

#define SYSTIM_IMCLR_EV0 0x00000001U

§ SYSTIM_IMCLR_EV0_M

#define SYSTIM_IMCLR_EV0_M 0x00000001U

§ SYSTIM_IMCLR_EV0_S

#define SYSTIM_IMCLR_EV0_S 0U

§ SYSTIM_IMCLR_EV0_CLR

#define SYSTIM_IMCLR_EV0_CLR 0x00000001U

§ SYSTIM_IMCLR_EV0_NOEFF

#define SYSTIM_IMCLR_EV0_NOEFF 0x00000000U

§ SYSTIM_EMU_HALT

#define SYSTIM_EMU_HALT 0x00000001U

§ SYSTIM_EMU_HALT_M

#define SYSTIM_EMU_HALT_M 0x00000001U

§ SYSTIM_EMU_HALT_S

#define SYSTIM_EMU_HALT_S 0U

§ SYSTIM_EMU_HALT_STOP

#define SYSTIM_EMU_HALT_STOP 0x00000001U

§ SYSTIM_EMU_HALT_RUN

#define SYSTIM_EMU_HALT_RUN 0x00000000U

§ SYSTIM_TIME250N_VAL_W

#define SYSTIM_TIME250N_VAL_W 32U

§ SYSTIM_TIME250N_VAL_M

#define SYSTIM_TIME250N_VAL_M 0xFFFFFFFFU

§ SYSTIM_TIME250N_VAL_S

#define SYSTIM_TIME250N_VAL_S 0U

§ SYSTIM_TIME1U_VAL_W

#define SYSTIM_TIME1U_VAL_W 32U

§ SYSTIM_TIME1U_VAL_M

#define SYSTIM_TIME1U_VAL_M 0xFFFFFFFFU

§ SYSTIM_TIME1U_VAL_S

#define SYSTIM_TIME1U_VAL_S 0U

§ SYSTIM_OUT_OUT4

#define SYSTIM_OUT_OUT4 0x00000010U

§ SYSTIM_OUT_OUT4_M

#define SYSTIM_OUT_OUT4_M 0x00000010U

§ SYSTIM_OUT_OUT4_S

#define SYSTIM_OUT_OUT4_S 4U

§ SYSTIM_OUT_OUT4_SET

#define SYSTIM_OUT_OUT4_SET 0x00000010U

§ SYSTIM_OUT_OUT4_CLR

#define SYSTIM_OUT_OUT4_CLR 0x00000000U

§ SYSTIM_OUT_OUT3

#define SYSTIM_OUT_OUT3 0x00000008U

§ SYSTIM_OUT_OUT3_M

#define SYSTIM_OUT_OUT3_M 0x00000008U

§ SYSTIM_OUT_OUT3_S

#define SYSTIM_OUT_OUT3_S 3U

§ SYSTIM_OUT_OUT3_SET

#define SYSTIM_OUT_OUT3_SET 0x00000008U

§ SYSTIM_OUT_OUT3_CLR

#define SYSTIM_OUT_OUT3_CLR 0x00000000U

§ SYSTIM_OUT_OUT2

#define SYSTIM_OUT_OUT2 0x00000004U

§ SYSTIM_OUT_OUT2_M

#define SYSTIM_OUT_OUT2_M 0x00000004U

§ SYSTIM_OUT_OUT2_S

#define SYSTIM_OUT_OUT2_S 2U

§ SYSTIM_OUT_OUT2_SET

#define SYSTIM_OUT_OUT2_SET 0x00000004U

§ SYSTIM_OUT_OUT2_CLR

#define SYSTIM_OUT_OUT2_CLR 0x00000000U

§ SYSTIM_OUT_OUT1

#define SYSTIM_OUT_OUT1 0x00000002U

§ SYSTIM_OUT_OUT1_M

#define SYSTIM_OUT_OUT1_M 0x00000002U

§ SYSTIM_OUT_OUT1_S

#define SYSTIM_OUT_OUT1_S 1U

§ SYSTIM_OUT_OUT1_SET

#define SYSTIM_OUT_OUT1_SET 0x00000002U

§ SYSTIM_OUT_OUT1_CLR

#define SYSTIM_OUT_OUT1_CLR 0x00000000U

§ SYSTIM_OUT_OUT0

#define SYSTIM_OUT_OUT0 0x00000001U

§ SYSTIM_OUT_OUT0_M

#define SYSTIM_OUT_OUT0_M 0x00000001U

§ SYSTIM_OUT_OUT0_S

#define SYSTIM_OUT_OUT0_S 0U

§ SYSTIM_OUT_OUT0_SET

#define SYSTIM_OUT_OUT0_SET 0x00000001U

§ SYSTIM_OUT_OUT0_CLR

#define SYSTIM_OUT_OUT0_CLR 0x00000000U

§ SYSTIM_CH0CFG_RES

#define SYSTIM_CH0CFG_RES 0x00000010U

§ SYSTIM_CH0CFG_RES_M

#define SYSTIM_CH0CFG_RES_M 0x00000010U

§ SYSTIM_CH0CFG_RES_S

#define SYSTIM_CH0CFG_RES_S 4U

§ SYSTIM_CH0CFG_RES_NS

#define SYSTIM_CH0CFG_RES_NS 0x00000010U

§ SYSTIM_CH0CFG_RES_US

#define SYSTIM_CH0CFG_RES_US 0x00000000U

§ SYSTIM_CH0CFG_REARM

#define SYSTIM_CH0CFG_REARM 0x00000008U

§ SYSTIM_CH0CFG_REARM_M

#define SYSTIM_CH0CFG_REARM_M 0x00000008U

§ SYSTIM_CH0CFG_REARM_S

#define SYSTIM_CH0CFG_REARM_S 3U

§ SYSTIM_CH0CFG_REARM_EN

#define SYSTIM_CH0CFG_REARM_EN 0x00000008U

§ SYSTIM_CH0CFG_REARM_DIS

#define SYSTIM_CH0CFG_REARM_DIS 0x00000000U

§ SYSTIM_CH0CFG_INP_W

#define SYSTIM_CH0CFG_INP_W 2U

§ SYSTIM_CH0CFG_INP_M

#define SYSTIM_CH0CFG_INP_M 0x00000006U

§ SYSTIM_CH0CFG_INP_S

#define SYSTIM_CH0CFG_INP_S 1U

§ SYSTIM_CH0CFG_INP_BOTH

#define SYSTIM_CH0CFG_INP_BOTH 0x00000004U

§ SYSTIM_CH0CFG_INP_FALL

#define SYSTIM_CH0CFG_INP_FALL 0x00000002U

§ SYSTIM_CH0CFG_INP_RISE

#define SYSTIM_CH0CFG_INP_RISE 0x00000000U

§ SYSTIM_CH0CFG_MODE

#define SYSTIM_CH0CFG_MODE 0x00000001U

§ SYSTIM_CH0CFG_MODE_M

#define SYSTIM_CH0CFG_MODE_M 0x00000001U

§ SYSTIM_CH0CFG_MODE_S

#define SYSTIM_CH0CFG_MODE_S 0U

§ SYSTIM_CH0CFG_MODE_CAPT

#define SYSTIM_CH0CFG_MODE_CAPT 0x00000001U

§ SYSTIM_CH0CFG_MODE_DIS

#define SYSTIM_CH0CFG_MODE_DIS 0x00000000U

§ SYSTIM_CH1CFG_REARM

#define SYSTIM_CH1CFG_REARM 0x00000008U

§ SYSTIM_CH1CFG_REARM_M

#define SYSTIM_CH1CFG_REARM_M 0x00000008U

§ SYSTIM_CH1CFG_REARM_S

#define SYSTIM_CH1CFG_REARM_S 3U

§ SYSTIM_CH1CFG_REARM_EN

#define SYSTIM_CH1CFG_REARM_EN 0x00000008U

§ SYSTIM_CH1CFG_REARM_DIS

#define SYSTIM_CH1CFG_REARM_DIS 0x00000000U

§ SYSTIM_CH1CFG_INP_W

#define SYSTIM_CH1CFG_INP_W 2U

§ SYSTIM_CH1CFG_INP_M

#define SYSTIM_CH1CFG_INP_M 0x00000006U

§ SYSTIM_CH1CFG_INP_S

#define SYSTIM_CH1CFG_INP_S 1U

§ SYSTIM_CH1CFG_INP_BOTH

#define SYSTIM_CH1CFG_INP_BOTH 0x00000004U

§ SYSTIM_CH1CFG_INP_FALL

#define SYSTIM_CH1CFG_INP_FALL 0x00000002U

§ SYSTIM_CH1CFG_INP_RISE

#define SYSTIM_CH1CFG_INP_RISE 0x00000000U

§ SYSTIM_CH1CFG_MODE

#define SYSTIM_CH1CFG_MODE 0x00000001U

§ SYSTIM_CH1CFG_MODE_M

#define SYSTIM_CH1CFG_MODE_M 0x00000001U

§ SYSTIM_CH1CFG_MODE_S

#define SYSTIM_CH1CFG_MODE_S 0U

§ SYSTIM_CH1CFG_MODE_CAPT

#define SYSTIM_CH1CFG_MODE_CAPT 0x00000001U

§ SYSTIM_CH1CFG_MODE_DIS

#define SYSTIM_CH1CFG_MODE_DIS 0x00000000U

§ SYSTIM_CH2CFG_REARM

#define SYSTIM_CH2CFG_REARM 0x00000008U

§ SYSTIM_CH2CFG_REARM_M

#define SYSTIM_CH2CFG_REARM_M 0x00000008U

§ SYSTIM_CH2CFG_REARM_S

#define SYSTIM_CH2CFG_REARM_S 3U

§ SYSTIM_CH2CFG_REARM_EN

#define SYSTIM_CH2CFG_REARM_EN 0x00000008U

§ SYSTIM_CH2CFG_REARM_DIS

#define SYSTIM_CH2CFG_REARM_DIS 0x00000000U

§ SYSTIM_CH2CFG_INP_W

#define SYSTIM_CH2CFG_INP_W 2U

§ SYSTIM_CH2CFG_INP_M

#define SYSTIM_CH2CFG_INP_M 0x00000006U

§ SYSTIM_CH2CFG_INP_S

#define SYSTIM_CH2CFG_INP_S 1U

§ SYSTIM_CH2CFG_INP_BOTH

#define SYSTIM_CH2CFG_INP_BOTH 0x00000004U

§ SYSTIM_CH2CFG_INP_FALL

#define SYSTIM_CH2CFG_INP_FALL 0x00000002U

§ SYSTIM_CH2CFG_INP_RISE

#define SYSTIM_CH2CFG_INP_RISE 0x00000000U

§ SYSTIM_CH2CFG_MODE

#define SYSTIM_CH2CFG_MODE 0x00000001U

§ SYSTIM_CH2CFG_MODE_M

#define SYSTIM_CH2CFG_MODE_M 0x00000001U

§ SYSTIM_CH2CFG_MODE_S

#define SYSTIM_CH2CFG_MODE_S 0U

§ SYSTIM_CH2CFG_MODE_CAPT

#define SYSTIM_CH2CFG_MODE_CAPT 0x00000001U

§ SYSTIM_CH2CFG_MODE_DIS

#define SYSTIM_CH2CFG_MODE_DIS 0x00000000U

§ SYSTIM_CH3CFG_REARM

#define SYSTIM_CH3CFG_REARM 0x00000008U

§ SYSTIM_CH3CFG_REARM_M

#define SYSTIM_CH3CFG_REARM_M 0x00000008U

§ SYSTIM_CH3CFG_REARM_S

#define SYSTIM_CH3CFG_REARM_S 3U

§ SYSTIM_CH3CFG_REARM_EN

#define SYSTIM_CH3CFG_REARM_EN 0x00000008U

§ SYSTIM_CH3CFG_REARM_DIS

#define SYSTIM_CH3CFG_REARM_DIS 0x00000000U

§ SYSTIM_CH3CFG_INP_W

#define SYSTIM_CH3CFG_INP_W 2U

§ SYSTIM_CH3CFG_INP_M

#define SYSTIM_CH3CFG_INP_M 0x00000006U

§ SYSTIM_CH3CFG_INP_S

#define SYSTIM_CH3CFG_INP_S 1U

§ SYSTIM_CH3CFG_INP_BOTH

#define SYSTIM_CH3CFG_INP_BOTH 0x00000004U

§ SYSTIM_CH3CFG_INP_FALL

#define SYSTIM_CH3CFG_INP_FALL 0x00000002U

§ SYSTIM_CH3CFG_INP_RISE

#define SYSTIM_CH3CFG_INP_RISE 0x00000000U

§ SYSTIM_CH3CFG_MODE

#define SYSTIM_CH3CFG_MODE 0x00000001U

§ SYSTIM_CH3CFG_MODE_M

#define SYSTIM_CH3CFG_MODE_M 0x00000001U

§ SYSTIM_CH3CFG_MODE_S

#define SYSTIM_CH3CFG_MODE_S 0U

§ SYSTIM_CH3CFG_MODE_CAPT

#define SYSTIM_CH3CFG_MODE_CAPT 0x00000001U

§ SYSTIM_CH3CFG_MODE_DIS

#define SYSTIM_CH3CFG_MODE_DIS 0x00000000U

§ SYSTIM_CH4CFG_REARM

#define SYSTIM_CH4CFG_REARM 0x00000008U

§ SYSTIM_CH4CFG_REARM_M

#define SYSTIM_CH4CFG_REARM_M 0x00000008U

§ SYSTIM_CH4CFG_REARM_S

#define SYSTIM_CH4CFG_REARM_S 3U

§ SYSTIM_CH4CFG_REARM_EN

#define SYSTIM_CH4CFG_REARM_EN 0x00000008U

§ SYSTIM_CH4CFG_REARM_DIS

#define SYSTIM_CH4CFG_REARM_DIS 0x00000000U

§ SYSTIM_CH4CFG_INP_W

#define SYSTIM_CH4CFG_INP_W 2U

§ SYSTIM_CH4CFG_INP_M

#define SYSTIM_CH4CFG_INP_M 0x00000006U

§ SYSTIM_CH4CFG_INP_S

#define SYSTIM_CH4CFG_INP_S 1U

§ SYSTIM_CH4CFG_INP_BOTH

#define SYSTIM_CH4CFG_INP_BOTH 0x00000004U

§ SYSTIM_CH4CFG_INP_FALL

#define SYSTIM_CH4CFG_INP_FALL 0x00000002U

§ SYSTIM_CH4CFG_INP_RISE

#define SYSTIM_CH4CFG_INP_RISE 0x00000000U

§ SYSTIM_CH4CFG_MODE

#define SYSTIM_CH4CFG_MODE 0x00000001U

§ SYSTIM_CH4CFG_MODE_M

#define SYSTIM_CH4CFG_MODE_M 0x00000001U

§ SYSTIM_CH4CFG_MODE_S

#define SYSTIM_CH4CFG_MODE_S 0U

§ SYSTIM_CH4CFG_MODE_CAPT

#define SYSTIM_CH4CFG_MODE_CAPT 0x00000001U

§ SYSTIM_CH4CFG_MODE_DIS

#define SYSTIM_CH4CFG_MODE_DIS 0x00000000U

§ SYSTIM_CH0CC_VAL_W

#define SYSTIM_CH0CC_VAL_W 32U

§ SYSTIM_CH0CC_VAL_M

#define SYSTIM_CH0CC_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH0CC_VAL_S

#define SYSTIM_CH0CC_VAL_S 0U

§ SYSTIM_CH1CC_VAL_W

#define SYSTIM_CH1CC_VAL_W 32U

§ SYSTIM_CH1CC_VAL_M

#define SYSTIM_CH1CC_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH1CC_VAL_S

#define SYSTIM_CH1CC_VAL_S 0U

§ SYSTIM_CH2CC_VAL_W

#define SYSTIM_CH2CC_VAL_W 32U

§ SYSTIM_CH2CC_VAL_M

#define SYSTIM_CH2CC_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH2CC_VAL_S

#define SYSTIM_CH2CC_VAL_S 0U

§ SYSTIM_CH3CC_VAL_W

#define SYSTIM_CH3CC_VAL_W 32U

§ SYSTIM_CH3CC_VAL_M

#define SYSTIM_CH3CC_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH3CC_VAL_S

#define SYSTIM_CH3CC_VAL_S 0U

§ SYSTIM_CH4CC_VAL_W

#define SYSTIM_CH4CC_VAL_W 32U

§ SYSTIM_CH4CC_VAL_M

#define SYSTIM_CH4CC_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH4CC_VAL_S

#define SYSTIM_CH4CC_VAL_S 0U

§ SYSTIM_TIMEBIT_VAL_W

#define SYSTIM_TIMEBIT_VAL_W 16U

§ SYSTIM_TIMEBIT_VAL_M

#define SYSTIM_TIMEBIT_VAL_M 0x0000FFFFU

§ SYSTIM_TIMEBIT_VAL_S

#define SYSTIM_TIMEBIT_VAL_S 0U

§ SYSTIM_TIMEBIT_VAL_BIT17

#define SYSTIM_TIMEBIT_VAL_BIT17 0x00008000U

§ SYSTIM_TIMEBIT_VAL_BIT16

#define SYSTIM_TIMEBIT_VAL_BIT16 0x00004000U

§ SYSTIM_TIMEBIT_VAL_BIT15

#define SYSTIM_TIMEBIT_VAL_BIT15 0x00002000U

§ SYSTIM_TIMEBIT_VAL_BIT14

#define SYSTIM_TIMEBIT_VAL_BIT14 0x00001000U

§ SYSTIM_TIMEBIT_VAL_BIT13

#define SYSTIM_TIMEBIT_VAL_BIT13 0x00000800U

§ SYSTIM_TIMEBIT_VAL_BIT12

#define SYSTIM_TIMEBIT_VAL_BIT12 0x00000400U

§ SYSTIM_TIMEBIT_VAL_BIT11

#define SYSTIM_TIMEBIT_VAL_BIT11 0x00000200U

§ SYSTIM_TIMEBIT_VAL_BIT10

#define SYSTIM_TIMEBIT_VAL_BIT10 0x00000100U

§ SYSTIM_TIMEBIT_VAL_BIT9

#define SYSTIM_TIMEBIT_VAL_BIT9 0x00000080U

§ SYSTIM_TIMEBIT_VAL_BIT8

#define SYSTIM_TIMEBIT_VAL_BIT8 0x00000040U

§ SYSTIM_TIMEBIT_VAL_BIT7

#define SYSTIM_TIMEBIT_VAL_BIT7 0x00000020U

§ SYSTIM_TIMEBIT_VAL_BIT6

#define SYSTIM_TIMEBIT_VAL_BIT6 0x00000010U

§ SYSTIM_TIMEBIT_VAL_BIT5

#define SYSTIM_TIMEBIT_VAL_BIT5 0x00000008U

§ SYSTIM_TIMEBIT_VAL_BIT4

#define SYSTIM_TIMEBIT_VAL_BIT4 0x00000004U

§ SYSTIM_TIMEBIT_VAL_BIT3

#define SYSTIM_TIMEBIT_VAL_BIT3 0x00000002U

§ SYSTIM_TIMEBIT_VAL_BIT2

#define SYSTIM_TIMEBIT_VAL_BIT2 0x00000001U

§ SYSTIM_TIMEBIT_VAL_NOBIT

#define SYSTIM_TIMEBIT_VAL_NOBIT 0x00000000U

§ SYSTIM_STATUS_SYNCUP

#define SYSTIM_STATUS_SYNCUP 0x00000010U

§ SYSTIM_STATUS_SYNCUP_M

#define SYSTIM_STATUS_SYNCUP_M 0x00000010U

§ SYSTIM_STATUS_SYNCUP_S

#define SYSTIM_STATUS_SYNCUP_S 4U

§ SYSTIM_STATUS_VAL

#define SYSTIM_STATUS_VAL 0x00000001U

§ SYSTIM_STATUS_VAL_M

#define SYSTIM_STATUS_VAL_M 0x00000001U

§ SYSTIM_STATUS_VAL_S

#define SYSTIM_STATUS_VAL_S 0U

§ SYSTIM_STATUS_VAL_RUN

#define SYSTIM_STATUS_VAL_RUN 0x00000001U

§ SYSTIM_STATUS_VAL_STOP

#define SYSTIM_STATUS_VAL_STOP 0x00000000U

§ SYSTIM_ARMSET_CH4

#define SYSTIM_ARMSET_CH4 0x00000010U

§ SYSTIM_ARMSET_CH4_M

#define SYSTIM_ARMSET_CH4_M 0x00000010U

§ SYSTIM_ARMSET_CH4_S

#define SYSTIM_ARMSET_CH4_S 4U

§ SYSTIM_ARMSET_CH4_SET

#define SYSTIM_ARMSET_CH4_SET 0x00000010U

§ SYSTIM_ARMSET_CH4_NOEFF

#define SYSTIM_ARMSET_CH4_NOEFF 0x00000000U

§ SYSTIM_ARMSET_CH3

#define SYSTIM_ARMSET_CH3 0x00000008U

§ SYSTIM_ARMSET_CH3_M

#define SYSTIM_ARMSET_CH3_M 0x00000008U

§ SYSTIM_ARMSET_CH3_S

#define SYSTIM_ARMSET_CH3_S 3U

§ SYSTIM_ARMSET_CH3_SET

#define SYSTIM_ARMSET_CH3_SET 0x00000008U

§ SYSTIM_ARMSET_CH3_NOEFF

#define SYSTIM_ARMSET_CH3_NOEFF 0x00000000U

§ SYSTIM_ARMSET_CH2

#define SYSTIM_ARMSET_CH2 0x00000004U

§ SYSTIM_ARMSET_CH2_M

#define SYSTIM_ARMSET_CH2_M 0x00000004U

§ SYSTIM_ARMSET_CH2_S

#define SYSTIM_ARMSET_CH2_S 2U

§ SYSTIM_ARMSET_CH2_SET

#define SYSTIM_ARMSET_CH2_SET 0x00000004U

§ SYSTIM_ARMSET_CH2_NOEFF

#define SYSTIM_ARMSET_CH2_NOEFF 0x00000000U

§ SYSTIM_ARMSET_CH1

#define SYSTIM_ARMSET_CH1 0x00000002U

§ SYSTIM_ARMSET_CH1_M

#define SYSTIM_ARMSET_CH1_M 0x00000002U

§ SYSTIM_ARMSET_CH1_S

#define SYSTIM_ARMSET_CH1_S 1U

§ SYSTIM_ARMSET_CH1_SET

#define SYSTIM_ARMSET_CH1_SET 0x00000002U

§ SYSTIM_ARMSET_CH1_NOEFF

#define SYSTIM_ARMSET_CH1_NOEFF 0x00000000U

§ SYSTIM_ARMSET_CH0

#define SYSTIM_ARMSET_CH0 0x00000001U

§ SYSTIM_ARMSET_CH0_M

#define SYSTIM_ARMSET_CH0_M 0x00000001U

§ SYSTIM_ARMSET_CH0_S

#define SYSTIM_ARMSET_CH0_S 0U

§ SYSTIM_ARMSET_CH0_SET

#define SYSTIM_ARMSET_CH0_SET 0x00000001U

§ SYSTIM_ARMSET_CH0_NOEFF

#define SYSTIM_ARMSET_CH0_NOEFF 0x00000000U

§ SYSTIM_ARMCLR_CH4

#define SYSTIM_ARMCLR_CH4 0x00000010U

§ SYSTIM_ARMCLR_CH4_M

#define SYSTIM_ARMCLR_CH4_M 0x00000010U

§ SYSTIM_ARMCLR_CH4_S

#define SYSTIM_ARMCLR_CH4_S 4U

§ SYSTIM_ARMCLR_CH4_CLR

#define SYSTIM_ARMCLR_CH4_CLR 0x00000010U

§ SYSTIM_ARMCLR_CH4_NOEFF

#define SYSTIM_ARMCLR_CH4_NOEFF 0x00000000U

§ SYSTIM_ARMCLR_CH3

#define SYSTIM_ARMCLR_CH3 0x00000008U

§ SYSTIM_ARMCLR_CH3_M

#define SYSTIM_ARMCLR_CH3_M 0x00000008U

§ SYSTIM_ARMCLR_CH3_S

#define SYSTIM_ARMCLR_CH3_S 3U

§ SYSTIM_ARMCLR_CH3_CLR

#define SYSTIM_ARMCLR_CH3_CLR 0x00000008U

§ SYSTIM_ARMCLR_CH3_NOEFF

#define SYSTIM_ARMCLR_CH3_NOEFF 0x00000000U

§ SYSTIM_ARMCLR_CH2

#define SYSTIM_ARMCLR_CH2 0x00000004U

§ SYSTIM_ARMCLR_CH2_M

#define SYSTIM_ARMCLR_CH2_M 0x00000004U

§ SYSTIM_ARMCLR_CH2_S

#define SYSTIM_ARMCLR_CH2_S 2U

§ SYSTIM_ARMCLR_CH2_CLR

#define SYSTIM_ARMCLR_CH2_CLR 0x00000004U

§ SYSTIM_ARMCLR_CH2_NOEFF

#define SYSTIM_ARMCLR_CH2_NOEFF 0x00000000U

§ SYSTIM_ARMCLR_CH1

#define SYSTIM_ARMCLR_CH1 0x00000002U

§ SYSTIM_ARMCLR_CH1_M

#define SYSTIM_ARMCLR_CH1_M 0x00000002U

§ SYSTIM_ARMCLR_CH1_S

#define SYSTIM_ARMCLR_CH1_S 1U

§ SYSTIM_ARMCLR_CH1_CLR

#define SYSTIM_ARMCLR_CH1_CLR 0x00000002U

§ SYSTIM_ARMCLR_CH1_NOEFF

#define SYSTIM_ARMCLR_CH1_NOEFF 0x00000000U

§ SYSTIM_ARMCLR_CH0

#define SYSTIM_ARMCLR_CH0 0x00000001U

§ SYSTIM_ARMCLR_CH0_M

#define SYSTIM_ARMCLR_CH0_M 0x00000001U

§ SYSTIM_ARMCLR_CH0_S

#define SYSTIM_ARMCLR_CH0_S 0U

§ SYSTIM_ARMCLR_CH0_CLR

#define SYSTIM_ARMCLR_CH0_CLR 0x00000001U

§ SYSTIM_ARMCLR_CH0_NOEFF

#define SYSTIM_ARMCLR_CH0_NOEFF 0x00000000U

§ SYSTIM_CH0CCSR_VAL_W

#define SYSTIM_CH0CCSR_VAL_W 32U

§ SYSTIM_CH0CCSR_VAL_M

#define SYSTIM_CH0CCSR_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH0CCSR_VAL_S

#define SYSTIM_CH0CCSR_VAL_S 0U

§ SYSTIM_CH1CCSR_VAL_W

#define SYSTIM_CH1CCSR_VAL_W 32U

§ SYSTIM_CH1CCSR_VAL_M

#define SYSTIM_CH1CCSR_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH1CCSR_VAL_S

#define SYSTIM_CH1CCSR_VAL_S 0U

§ SYSTIM_CH2CCSR_VAL_W

#define SYSTIM_CH2CCSR_VAL_W 32U

§ SYSTIM_CH2CCSR_VAL_M

#define SYSTIM_CH2CCSR_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH2CCSR_VAL_S

#define SYSTIM_CH2CCSR_VAL_S 0U

§ SYSTIM_CH3CCSR_VAL_W

#define SYSTIM_CH3CCSR_VAL_W 32U

§ SYSTIM_CH3CCSR_VAL_M

#define SYSTIM_CH3CCSR_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH3CCSR_VAL_S

#define SYSTIM_CH3CCSR_VAL_S 0U

§ SYSTIM_CH4CCSR_VAL_W

#define SYSTIM_CH4CCSR_VAL_W 32U

§ SYSTIM_CH4CCSR_VAL_M

#define SYSTIM_CH4CCSR_VAL_M 0xFFFFFFFFU

§ SYSTIM_CH4CCSR_VAL_S

#define SYSTIM_CH4CCSR_VAL_S 0U

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