CC23x0R5DriverLibrary
Macros
hw_sys0.h File Reference
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Macros

#define SYS0_O_DESC   0x00000000U
 
#define SYS0_O_MUNLOCK   0x0000000CU
 
#define SYS0_O_ATESTCFG   0x00000100U
 
#define SYS0_O_TSENSCFG   0x00000108U
 
#define SYS0_O_LPCMPCFG   0x0000010CU
 
#define SYS0_O_DEVICEID   0x000003FCU
 
#define SYS0_O_PARTID   0x000007F8U
 
#define SYS0_O_TMUTE0   0x00000800U
 
#define SYS0_O_TMUTE1   0x00000804U
 
#define SYS0_O_TMUTE2   0x00000808U
 
#define SYS0_O_TMUTE3   0x0000080CU
 
#define SYS0_O_TMUTE4   0x00000810U
 
#define SYS0_O_TMUTE5   0x00000814U
 
#define SYS0_DESC_MODID_W   16U
 
#define SYS0_DESC_MODID_M   0xFFFF0000U
 
#define SYS0_DESC_MODID_S   16U
 
#define SYS0_DESC_STDIPOFF_W   4U
 
#define SYS0_DESC_STDIPOFF_M   0x0000F000U
 
#define SYS0_DESC_STDIPOFF_S   12U
 
#define SYS0_DESC_INSTIDX_W   4U
 
#define SYS0_DESC_INSTIDX_M   0x00000F00U
 
#define SYS0_DESC_INSTIDX_S   8U
 
#define SYS0_DESC_MAJREV_W   4U
 
#define SYS0_DESC_MAJREV_M   0x000000F0U
 
#define SYS0_DESC_MAJREV_S   4U
 
#define SYS0_DESC_MINREV_W   4U
 
#define SYS0_DESC_MINREV_M   0x0000000FU
 
#define SYS0_DESC_MINREV_S   0U
 
#define SYS0_MUNLOCK_KEY_W   32U
 
#define SYS0_MUNLOCK_KEY_M   0xFFFFFFFFU
 
#define SYS0_MUNLOCK_KEY_S   0U
 
#define SYS0_MUNLOCK_KEY_UNLOCK   0xC5AF6927U
 
#define SYS0_MUNLOCK_KEY_LOCK   0x00000000U
 
#define SYS0_ATESTCFG_KEY_W   8U
 
#define SYS0_ATESTCFG_KEY_M   0xFF000000U
 
#define SYS0_ATESTCFG_KEY_S   24U
 
#define SYS0_ATESTCFG_VSEL   0x00000100U
 
#define SYS0_ATESTCFG_VSEL_M   0x00000100U
 
#define SYS0_ATESTCFG_VSEL_S   8U
 
#define SYS0_ATESTCFG_VSEL_VDDA   0x00000100U
 
#define SYS0_ATESTCFG_VSEL_VDDBST   0x00000000U
 
#define SYS0_ATESTCFG_VA2VA1   0x00000080U
 
#define SYS0_ATESTCFG_VA2VA1_M   0x00000080U
 
#define SYS0_ATESTCFG_VA2VA1_S   7U
 
#define SYS0_ATESTCFG_VA2VA1_CLOSE   0x00000080U
 
#define SYS0_ATESTCFG_VA2VA1_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_VA2VA0   0x00000040U
 
#define SYS0_ATESTCFG_VA2VA0_M   0x00000040U
 
#define SYS0_ATESTCFG_VA2VA0_S   6U
 
#define SYS0_ATESTCFG_VA2VA0_CLOSE   0x00000040U
 
#define SYS0_ATESTCFG_VA2VA0_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_VR2VA1   0x00000020U
 
#define SYS0_ATESTCFG_VR2VA1_M   0x00000020U
 
#define SYS0_ATESTCFG_VR2VA1_S   5U
 
#define SYS0_ATESTCFG_VR2VA1_CLOSE   0x00000020U
 
#define SYS0_ATESTCFG_VR2VA1_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_VR2VA0   0x00000010U
 
#define SYS0_ATESTCFG_VR2VA0_M   0x00000010U
 
#define SYS0_ATESTCFG_VR2VA0_S   4U
 
#define SYS0_ATESTCFG_VR2VA0_CLOSE   0x00000010U
 
#define SYS0_ATESTCFG_VR2VA0_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_SHTVA1   0x00000008U
 
#define SYS0_ATESTCFG_SHTVA1_M   0x00000008U
 
#define SYS0_ATESTCFG_SHTVA1_S   3U
 
#define SYS0_ATESTCFG_SHTVA1_CLOSE   0x00000008U
 
#define SYS0_ATESTCFG_SHTVA1_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_SHTVA0   0x00000004U
 
#define SYS0_ATESTCFG_SHTVA0_M   0x00000004U
 
#define SYS0_ATESTCFG_SHTVA0_S   2U
 
#define SYS0_ATESTCFG_SHTVA0_CLOSE   0x00000004U
 
#define SYS0_ATESTCFG_SHTVA0_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_SHTVR1   0x00000002U
 
#define SYS0_ATESTCFG_SHTVR1_M   0x00000002U
 
#define SYS0_ATESTCFG_SHTVR1_S   1U
 
#define SYS0_ATESTCFG_SHTVR1_CLOSE   0x00000002U
 
#define SYS0_ATESTCFG_SHTVR1_OPEN   0x00000000U
 
#define SYS0_ATESTCFG_SHTVR0   0x00000001U
 
#define SYS0_ATESTCFG_SHTVR0_M   0x00000001U
 
#define SYS0_ATESTCFG_SHTVR0_S   0U
 
#define SYS0_ATESTCFG_SHTVR0_CLOSE   0x00000001U
 
#define SYS0_ATESTCFG_SHTVR0_OPEN   0x00000000U
 
#define SYS0_TSENSCFG_SPARE_W   4U
 
#define SYS0_TSENSCFG_SPARE_M   0x00000F00U
 
#define SYS0_TSENSCFG_SPARE_S   8U
 
#define SYS0_TSENSCFG_SEL_W   2U
 
#define SYS0_TSENSCFG_SEL_M   0x00000003U
 
#define SYS0_TSENSCFG_SEL_S   0U
 
#define SYS0_TSENSCFG_SEL_GND   0x00000002U
 
#define SYS0_TSENSCFG_SEL_VALUE   0x00000001U
 
#define SYS0_TSENSCFG_SEL_DISABLE   0x00000000U
 
#define SYS0_LPCMPCFG_HYSPOL   0x40000000U
 
#define SYS0_LPCMPCFG_HYSPOL_M   0x40000000U
 
#define SYS0_LPCMPCFG_HYSPOL_S   30U
 
#define SYS0_LPCMPCFG_ATESTMUX_W   2U
 
#define SYS0_LPCMPCFG_ATESTMUX_M   0x30000000U
 
#define SYS0_LPCMPCFG_ATESTMUX_S   28U
 
#define SYS0_LPCMPCFG_ATESTMUX_IBIASOUT   0x30000000U
 
#define SYS0_LPCMPCFG_ATESTMUX_COMP_VIN_NEG   0x20000000U
 
#define SYS0_LPCMPCFG_ATESTMUX_COMPOUT   0x10000000U
 
#define SYS0_LPCMPCFG_ATESTMUX_OFF   0x00000000U
 
#define SYS0_LPCMPCFG_EVTIFG   0x01000000U
 
#define SYS0_LPCMPCFG_EVTIFG_M   0x01000000U
 
#define SYS0_LPCMPCFG_EVTIFG_S   24U
 
#define SYS0_LPCMPCFG_EVTIFG_SET   0x01000000U
 
#define SYS0_LPCMPCFG_EVTIFG_CLR   0x00000000U
 
#define SYS0_LPCMPCFG_COUTEN   0x00200000U
 
#define SYS0_LPCMPCFG_COUTEN_M   0x00200000U
 
#define SYS0_LPCMPCFG_COUTEN_S   21U
 
#define SYS0_LPCMPCFG_COUTEN_EN   0x00200000U
 
#define SYS0_LPCMPCFG_COUTEN_DIS   0x00000000U
 
#define SYS0_LPCMPCFG_COUT   0x00100000U
 
#define SYS0_LPCMPCFG_COUT_M   0x00100000U
 
#define SYS0_LPCMPCFG_COUT_S   20U
 
#define SYS0_LPCMPCFG_COUT_HIGH   0x00100000U
 
#define SYS0_LPCMPCFG_COUT_LOW   0x00000000U
 
#define SYS0_LPCMPCFG_WUENSB   0x00040000U
 
#define SYS0_LPCMPCFG_WUENSB_M   0x00040000U
 
#define SYS0_LPCMPCFG_WUENSB_S   18U
 
#define SYS0_LPCMPCFG_WUENSB_EN   0x00040000U
 
#define SYS0_LPCMPCFG_WUENSB_DIS   0x00000000U
 
#define SYS0_LPCMPCFG_EVTEN   0x00020000U
 
#define SYS0_LPCMPCFG_EVTEN_M   0x00020000U
 
#define SYS0_LPCMPCFG_EVTEN_S   17U
 
#define SYS0_LPCMPCFG_EVTEN_EN   0x00020000U
 
#define SYS0_LPCMPCFG_EVTEN_DIS   0x00000000U
 
#define SYS0_LPCMPCFG_EDGCFG   0x00010000U
 
#define SYS0_LPCMPCFG_EDGCFG_M   0x00010000U
 
#define SYS0_LPCMPCFG_EDGCFG_S   16U
 
#define SYS0_LPCMPCFG_EDGCFG_FALL   0x00010000U
 
#define SYS0_LPCMPCFG_EDGCFG_RISE   0x00000000U
 
#define SYS0_LPCMPCFG_NSEL_W   3U
 
#define SYS0_LPCMPCFG_NSEL_M   0x00007000U
 
#define SYS0_LPCMPCFG_NSEL_S   12U
 
#define SYS0_LPCMPCFG_NSEL_VDDD   0x00004000U
 
#define SYS0_LPCMPCFG_NSEL_VDDA   0x00003000U
 
#define SYS0_LPCMPCFG_NSEL_VA_PAD_A3   0x00002000U
 
#define SYS0_LPCMPCFG_NSEL_VA_PAD_A2   0x00001000U
 
#define SYS0_LPCMPCFG_NSEL_OPEN   0x00000000U
 
#define SYS0_LPCMPCFG_PSEL_W   4U
 
#define SYS0_LPCMPCFG_PSEL_M   0x00000F00U
 
#define SYS0_LPCMPCFG_PSEL_S   8U
 
#define SYS0_LPCMPCFG_PSEL_VDDA   0x00000800U
 
#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A1   0x00000700U
 
#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A0   0x00000600U
 
#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A1   0x00000500U
 
#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A0   0x00000400U
 
#define SYS0_LPCMPCFG_PSEL_VA_PAD_A3   0x00000300U
 
#define SYS0_LPCMPCFG_PSEL_VA_PAD_A2   0x00000200U
 
#define SYS0_LPCMPCFG_PSEL_VA_PAD_A1   0x00000100U
 
#define SYS0_LPCMPCFG_PSEL_OPEN   0x00000000U
 
#define SYS0_LPCMPCFG_HYSSEL_W   3U
 
#define SYS0_LPCMPCFG_HYSSEL_M   0x000000E0U
 
#define SYS0_LPCMPCFG_HYSSEL_S   5U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL7   0x000000E0U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL6   0x000000C0U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL5   0x000000A0U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL4   0x00000080U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL3   0x00000060U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL2   0x00000040U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL1   0x00000020U
 
#define SYS0_LPCMPCFG_HYSSEL_VAL0   0x00000000U
 
#define SYS0_LPCMPCFG_DIVPATH   0x00000010U
 
#define SYS0_LPCMPCFG_DIVPATH_M   0x00000010U
 
#define SYS0_LPCMPCFG_DIVPATH_S   4U
 
#define SYS0_LPCMPCFG_DIVPATH_PSIDE   0x00000010U
 
#define SYS0_LPCMPCFG_DIVPATH_NSIDE   0x00000000U
 
#define SYS0_LPCMPCFG_DIV_W   3U
 
#define SYS0_LPCMPCFG_DIV_M   0x0000000EU
 
#define SYS0_LPCMPCFG_DIV_S   1U
 
#define SYS0_LPCMPCFG_DIV_VAL4   0x00000008U
 
#define SYS0_LPCMPCFG_DIV_VAL3   0x00000006U
 
#define SYS0_LPCMPCFG_DIV_VAL2   0x00000004U
 
#define SYS0_LPCMPCFG_DIV_VAL1   0x00000002U
 
#define SYS0_LPCMPCFG_DIV_VAL0   0x00000000U
 
#define SYS0_LPCMPCFG_EN   0x00000001U
 
#define SYS0_LPCMPCFG_EN_M   0x00000001U
 
#define SYS0_LPCMPCFG_EN_S   0U
 
#define SYS0_LPCMPCFG_EN_EN   0x00000001U
 
#define SYS0_LPCMPCFG_EN_DIS   0x00000000U
 
#define SYS0_DEVICEID_VERSION_W   4U
 
#define SYS0_DEVICEID_VERSION_M   0xF0000000U
 
#define SYS0_DEVICEID_VERSION_S   28U
 
#define SYS0_DEVICEID_DEVICE_W   16U
 
#define SYS0_DEVICEID_DEVICE_M   0x0FFFF000U
 
#define SYS0_DEVICEID_DEVICE_S   12U
 
#define SYS0_DEVICEID_MANFACTURER_W   11U
 
#define SYS0_DEVICEID_MANFACTURER_M   0x00000FFEU
 
#define SYS0_DEVICEID_MANFACTURER_S   1U
 
#define SYS0_DEVICEID_ALWAYSONE   0x00000001U
 
#define SYS0_DEVICEID_ALWAYSONE_M   0x00000001U
 
#define SYS0_DEVICEID_ALWAYSONE_S   0U
 
#define SYS0_PARTID_START   0x80000000U
 
#define SYS0_PARTID_START_M   0x80000000U
 
#define SYS0_PARTID_START_S   31U
 
#define SYS0_PARTID_START_SET   0x80000000U
 
#define SYS0_PARTID_START_CLR   0x00000000U
 
#define SYS0_PARTID_MAJORREV_W   3U
 
#define SYS0_PARTID_MAJORREV_M   0x70000000U
 
#define SYS0_PARTID_MAJORREV_S   28U
 
#define SYS0_PARTID_MINORREV_W   4U
 
#define SYS0_PARTID_MINORREV_M   0x0F000000U
 
#define SYS0_PARTID_MINORREV_S   24U
 
#define SYS0_PARTID_VARIANT_W   8U
 
#define SYS0_PARTID_VARIANT_M   0x00FF0000U
 
#define SYS0_PARTID_VARIANT_S   16U
 
#define SYS0_PARTID_PART_W   16U
 
#define SYS0_PARTID_PART_M   0x0000FFFFU
 
#define SYS0_PARTID_PART_S   0U
 
#define SYS0_TMUTE0_CDACL_W   32U
 
#define SYS0_TMUTE0_CDACL_M   0xFFFFFFFFU
 
#define SYS0_TMUTE0_CDACL_S   0U
 
#define SYS0_TMUTE1_CDACM_W   32U
 
#define SYS0_TMUTE1_CDACM_M   0xFFFFFFFFU
 
#define SYS0_TMUTE1_CDACM_S   0U
 
#define SYS0_TMUTE2_IBTRIM_W   5U
 
#define SYS0_TMUTE2_IBTRIM_M   0x7C000000U
 
#define SYS0_TMUTE2_IBTRIM_S   26U
 
#define SYS0_TMUTE2_TRIM_W   3U
 
#define SYS0_TMUTE2_TRIM_M   0x03800000U
 
#define SYS0_TMUTE2_TRIM_S   23U
 
#define SYS0_TMUTE2_LATCH_W   7U
 
#define SYS0_TMUTE2_LATCH_M   0x007F0000U
 
#define SYS0_TMUTE2_LATCH_S   16U
 
#define SYS0_TMUTE2_OFFSET_W   12U
 
#define SYS0_TMUTE2_OFFSET_M   0x0000FFF0U
 
#define SYS0_TMUTE2_OFFSET_S   4U
 
#define SYS0_TMUTE2_RES_W   2U
 
#define SYS0_TMUTE2_RES_M   0x0000000CU
 
#define SYS0_TMUTE2_RES_S   2U
 
#define SYS0_TMUTE2_CDACU_W   2U
 
#define SYS0_TMUTE2_CDACU_M   0x00000003U
 
#define SYS0_TMUTE2_CDACU_S   0U
 
#define SYS0_TMUTE3_BATC1_W   6U
 
#define SYS0_TMUTE3_BATC1_M   0xFC000000U
 
#define SYS0_TMUTE3_BATC1_S   26U
 
#define SYS0_TMUTE3_BATC0_W   7U
 
#define SYS0_TMUTE3_BATC0_M   0x03F80000U
 
#define SYS0_TMUTE3_BATC0_S   19U
 
#define SYS0_TMUTE3_TEMPC2_W   5U
 
#define SYS0_TMUTE3_TEMPC2_M   0x0007C000U
 
#define SYS0_TMUTE3_TEMPC2_S   14U
 
#define SYS0_TMUTE3_TEMPC1_W   6U
 
#define SYS0_TMUTE3_TEMPC1_M   0x00003F00U
 
#define SYS0_TMUTE3_TEMPC1_S   8U
 
#define SYS0_TMUTE3_TEMPC0_W   8U
 
#define SYS0_TMUTE3_TEMPC0_M   0x000000FFU
 
#define SYS0_TMUTE3_TEMPC0_S   0U
 
#define SYS0_TMUTE4_RECHCOMPREFLVL_W   4U
 
#define SYS0_TMUTE4_RECHCOMPREFLVL_M   0xF0000000U
 
#define SYS0_TMUTE4_RECHCOMPREFLVL_S   28U
 
#define SYS0_TMUTE4_IOSTRCFG2_W   2U
 
#define SYS0_TMUTE4_IOSTRCFG2_M   0x0C000000U
 
#define SYS0_TMUTE4_IOSTRCFG2_S   26U
 
#define SYS0_TMUTE4_IOSTRCFG1_W   4U
 
#define SYS0_TMUTE4_IOSTRCFG1_M   0x03C00000U
 
#define SYS0_TMUTE4_IOSTRCFG1_S   22U
 
#define SYS0_TMUTE4_MAX_W   3U
 
#define SYS0_TMUTE4_MAX_M   0x00380000U
 
#define SYS0_TMUTE4_MAX_S   19U
 
#define SYS0_TMUTE4_MED_W   3U
 
#define SYS0_TMUTE4_MED_M   0x00070000U
 
#define SYS0_TMUTE4_MED_S   16U
 
#define SYS0_TMUTE4_MIN_W   3U
 
#define SYS0_TMUTE4_MIN_M   0x0000E000U
 
#define SYS0_TMUTE4_MIN_S   13U
 
#define SYS0_TMUTE4_DCDCLOAD_W   2U
 
#define SYS0_TMUTE4_DCDCLOAD_M   0x00001800U
 
#define SYS0_TMUTE4_DCDCLOAD_S   11U
 
#define SYS0_TMUTE4_IPEAK_W   3U
 
#define SYS0_TMUTE4_IPEAK_M   0x00000700U
 
#define SYS0_TMUTE4_IPEAK_S   8U
 
#define SYS0_TMUTE4_DTIME_W   2U
 
#define SYS0_TMUTE4_DTIME_M   0x000000C0U
 
#define SYS0_TMUTE4_DTIME_S   6U
 
#define SYS0_TMUTE4_LENSEL_W   3U
 
#define SYS0_TMUTE4_LENSEL_M   0x00000038U
 
#define SYS0_TMUTE4_LENSEL_S   3U
 
#define SYS0_TMUTE4_HENSEL_W   3U
 
#define SYS0_TMUTE4_HENSEL_M   0x00000007U
 
#define SYS0_TMUTE4_HENSEL_S   0U
 
#define SYS0_TMUTE5_DCDCDRVDS_W   3U
 
#define SYS0_TMUTE5_DCDCDRVDS_M   0x00001C00U
 
#define SYS0_TMUTE5_DCDCDRVDS_S   10U
 
#define SYS0_TMUTE5_GLDOISCLR_W   5U
 
#define SYS0_TMUTE5_GLDOISCLR_M   0x000003E0U
 
#define SYS0_TMUTE5_GLDOISCLR_S   5U
 
#define SYS0_TMUTE5_GLDOISSET_W   5U
 
#define SYS0_TMUTE5_GLDOISSET_M   0x0000001FU
 
#define SYS0_TMUTE5_GLDOISSET_S   0U
 

Macro Definition Documentation

§ SYS0_O_DESC

#define SYS0_O_DESC   0x00000000U

§ SYS0_O_MUNLOCK

#define SYS0_O_MUNLOCK   0x0000000CU

Referenced by ADCSetAdjustmentOffset().

§ SYS0_O_ATESTCFG

#define SYS0_O_ATESTCFG   0x00000100U

Referenced by TempDiodeGetTemp().

§ SYS0_O_TSENSCFG

#define SYS0_O_TSENSCFG   0x00000108U

Referenced by TempDiodeGetTemp().

§ SYS0_O_LPCMPCFG

#define SYS0_O_LPCMPCFG   0x0000010CU

Referenced by LPCMPClearEvent(), LPCMPDisable(), LPCMPDisableEvent(), LPCMPDisableWakeup(), LPCMPEnable(), LPCMPEnableEvent(), LPCMPEnableWakeup(), LPCMPIsOutputHigh(), LPCMPSelectNegativeInput(), LPCMPSelectPositiveInput(), LPCMPSetDividerPath(), LPCMPSetDividerRatio(), and LPCMPSetPolarity().

§ SYS0_O_DEVICEID

#define SYS0_O_DEVICEID   0x000003FCU

Referenced by ChipInfoGetVersion().

§ SYS0_O_PARTID

#define SYS0_O_PARTID   0x000007F8U

§ SYS0_O_TMUTE0

#define SYS0_O_TMUTE0   0x00000800U

§ SYS0_O_TMUTE1

#define SYS0_O_TMUTE1   0x00000804U

§ SYS0_O_TMUTE2

#define SYS0_O_TMUTE2   0x00000808U

Referenced by ADCSetAdjustmentOffset().

§ SYS0_O_TMUTE3

#define SYS0_O_TMUTE3   0x0000080CU

§ SYS0_O_TMUTE4

#define SYS0_O_TMUTE4   0x00000810U

§ SYS0_O_TMUTE5

#define SYS0_O_TMUTE5   0x00000814U

§ SYS0_DESC_MODID_W

#define SYS0_DESC_MODID_W   16U

§ SYS0_DESC_MODID_M

#define SYS0_DESC_MODID_M   0xFFFF0000U

§ SYS0_DESC_MODID_S

#define SYS0_DESC_MODID_S   16U

§ SYS0_DESC_STDIPOFF_W

#define SYS0_DESC_STDIPOFF_W   4U

§ SYS0_DESC_STDIPOFF_M

#define SYS0_DESC_STDIPOFF_M   0x0000F000U

§ SYS0_DESC_STDIPOFF_S

#define SYS0_DESC_STDIPOFF_S   12U

§ SYS0_DESC_INSTIDX_W

#define SYS0_DESC_INSTIDX_W   4U

§ SYS0_DESC_INSTIDX_M

#define SYS0_DESC_INSTIDX_M   0x00000F00U

§ SYS0_DESC_INSTIDX_S

#define SYS0_DESC_INSTIDX_S   8U

§ SYS0_DESC_MAJREV_W

#define SYS0_DESC_MAJREV_W   4U

§ SYS0_DESC_MAJREV_M

#define SYS0_DESC_MAJREV_M   0x000000F0U

§ SYS0_DESC_MAJREV_S

#define SYS0_DESC_MAJREV_S   4U

§ SYS0_DESC_MINREV_W

#define SYS0_DESC_MINREV_W   4U

§ SYS0_DESC_MINREV_M

#define SYS0_DESC_MINREV_M   0x0000000FU

§ SYS0_DESC_MINREV_S

#define SYS0_DESC_MINREV_S   0U

§ SYS0_MUNLOCK_KEY_W

#define SYS0_MUNLOCK_KEY_W   32U

§ SYS0_MUNLOCK_KEY_M

#define SYS0_MUNLOCK_KEY_M   0xFFFFFFFFU

§ SYS0_MUNLOCK_KEY_S

#define SYS0_MUNLOCK_KEY_S   0U

§ SYS0_MUNLOCK_KEY_UNLOCK

#define SYS0_MUNLOCK_KEY_UNLOCK   0xC5AF6927U

§ SYS0_MUNLOCK_KEY_LOCK

#define SYS0_MUNLOCK_KEY_LOCK   0x00000000U

§ SYS0_ATESTCFG_KEY_W

#define SYS0_ATESTCFG_KEY_W   8U

§ SYS0_ATESTCFG_KEY_M

#define SYS0_ATESTCFG_KEY_M   0xFF000000U

§ SYS0_ATESTCFG_KEY_S

#define SYS0_ATESTCFG_KEY_S   24U

§ SYS0_ATESTCFG_VSEL

#define SYS0_ATESTCFG_VSEL   0x00000100U

§ SYS0_ATESTCFG_VSEL_M

#define SYS0_ATESTCFG_VSEL_M   0x00000100U

§ SYS0_ATESTCFG_VSEL_S

#define SYS0_ATESTCFG_VSEL_S   8U

§ SYS0_ATESTCFG_VSEL_VDDA

#define SYS0_ATESTCFG_VSEL_VDDA   0x00000100U

§ SYS0_ATESTCFG_VSEL_VDDBST

#define SYS0_ATESTCFG_VSEL_VDDBST   0x00000000U

§ SYS0_ATESTCFG_VA2VA1

#define SYS0_ATESTCFG_VA2VA1   0x00000080U

§ SYS0_ATESTCFG_VA2VA1_M

#define SYS0_ATESTCFG_VA2VA1_M   0x00000080U

§ SYS0_ATESTCFG_VA2VA1_S

#define SYS0_ATESTCFG_VA2VA1_S   7U

§ SYS0_ATESTCFG_VA2VA1_CLOSE

#define SYS0_ATESTCFG_VA2VA1_CLOSE   0x00000080U

§ SYS0_ATESTCFG_VA2VA1_OPEN

#define SYS0_ATESTCFG_VA2VA1_OPEN   0x00000000U

§ SYS0_ATESTCFG_VA2VA0

#define SYS0_ATESTCFG_VA2VA0   0x00000040U

§ SYS0_ATESTCFG_VA2VA0_M

#define SYS0_ATESTCFG_VA2VA0_M   0x00000040U

§ SYS0_ATESTCFG_VA2VA0_S

#define SYS0_ATESTCFG_VA2VA0_S   6U

§ SYS0_ATESTCFG_VA2VA0_CLOSE

#define SYS0_ATESTCFG_VA2VA0_CLOSE   0x00000040U

§ SYS0_ATESTCFG_VA2VA0_OPEN

#define SYS0_ATESTCFG_VA2VA0_OPEN   0x00000000U

§ SYS0_ATESTCFG_VR2VA1

#define SYS0_ATESTCFG_VR2VA1   0x00000020U

Referenced by TempDiodeGetTemp().

§ SYS0_ATESTCFG_VR2VA1_M

#define SYS0_ATESTCFG_VR2VA1_M   0x00000020U

§ SYS0_ATESTCFG_VR2VA1_S

#define SYS0_ATESTCFG_VR2VA1_S   5U

§ SYS0_ATESTCFG_VR2VA1_CLOSE

#define SYS0_ATESTCFG_VR2VA1_CLOSE   0x00000020U

§ SYS0_ATESTCFG_VR2VA1_OPEN

#define SYS0_ATESTCFG_VR2VA1_OPEN   0x00000000U

§ SYS0_ATESTCFG_VR2VA0

#define SYS0_ATESTCFG_VR2VA0   0x00000010U

Referenced by TempDiodeGetTemp().

§ SYS0_ATESTCFG_VR2VA0_M

#define SYS0_ATESTCFG_VR2VA0_M   0x00000010U

§ SYS0_ATESTCFG_VR2VA0_S

#define SYS0_ATESTCFG_VR2VA0_S   4U

§ SYS0_ATESTCFG_VR2VA0_CLOSE

#define SYS0_ATESTCFG_VR2VA0_CLOSE   0x00000010U

§ SYS0_ATESTCFG_VR2VA0_OPEN

#define SYS0_ATESTCFG_VR2VA0_OPEN   0x00000000U

§ SYS0_ATESTCFG_SHTVA1

#define SYS0_ATESTCFG_SHTVA1   0x00000008U

§ SYS0_ATESTCFG_SHTVA1_M

#define SYS0_ATESTCFG_SHTVA1_M   0x00000008U

§ SYS0_ATESTCFG_SHTVA1_S

#define SYS0_ATESTCFG_SHTVA1_S   3U

§ SYS0_ATESTCFG_SHTVA1_CLOSE

#define SYS0_ATESTCFG_SHTVA1_CLOSE   0x00000008U

§ SYS0_ATESTCFG_SHTVA1_OPEN

#define SYS0_ATESTCFG_SHTVA1_OPEN   0x00000000U

§ SYS0_ATESTCFG_SHTVA0

#define SYS0_ATESTCFG_SHTVA0   0x00000004U

§ SYS0_ATESTCFG_SHTVA0_M

#define SYS0_ATESTCFG_SHTVA0_M   0x00000004U

§ SYS0_ATESTCFG_SHTVA0_S

#define SYS0_ATESTCFG_SHTVA0_S   2U

§ SYS0_ATESTCFG_SHTVA0_CLOSE

#define SYS0_ATESTCFG_SHTVA0_CLOSE   0x00000004U

§ SYS0_ATESTCFG_SHTVA0_OPEN

#define SYS0_ATESTCFG_SHTVA0_OPEN   0x00000000U

§ SYS0_ATESTCFG_SHTVR1

#define SYS0_ATESTCFG_SHTVR1   0x00000002U

§ SYS0_ATESTCFG_SHTVR1_M

#define SYS0_ATESTCFG_SHTVR1_M   0x00000002U

§ SYS0_ATESTCFG_SHTVR1_S

#define SYS0_ATESTCFG_SHTVR1_S   1U

§ SYS0_ATESTCFG_SHTVR1_CLOSE

#define SYS0_ATESTCFG_SHTVR1_CLOSE   0x00000002U

§ SYS0_ATESTCFG_SHTVR1_OPEN

#define SYS0_ATESTCFG_SHTVR1_OPEN   0x00000000U

§ SYS0_ATESTCFG_SHTVR0

#define SYS0_ATESTCFG_SHTVR0   0x00000001U

§ SYS0_ATESTCFG_SHTVR0_M

#define SYS0_ATESTCFG_SHTVR0_M   0x00000001U

§ SYS0_ATESTCFG_SHTVR0_S

#define SYS0_ATESTCFG_SHTVR0_S   0U

§ SYS0_ATESTCFG_SHTVR0_CLOSE

#define SYS0_ATESTCFG_SHTVR0_CLOSE   0x00000001U

§ SYS0_ATESTCFG_SHTVR0_OPEN

#define SYS0_ATESTCFG_SHTVR0_OPEN   0x00000000U

§ SYS0_TSENSCFG_SPARE_W

#define SYS0_TSENSCFG_SPARE_W   4U

§ SYS0_TSENSCFG_SPARE_M

#define SYS0_TSENSCFG_SPARE_M   0x00000F00U

§ SYS0_TSENSCFG_SPARE_S

#define SYS0_TSENSCFG_SPARE_S   8U

§ SYS0_TSENSCFG_SEL_W

#define SYS0_TSENSCFG_SEL_W   2U

§ SYS0_TSENSCFG_SEL_M

#define SYS0_TSENSCFG_SEL_M   0x00000003U

Referenced by TempDiodeGetTemp().

§ SYS0_TSENSCFG_SEL_S

#define SYS0_TSENSCFG_SEL_S   0U

§ SYS0_TSENSCFG_SEL_GND

#define SYS0_TSENSCFG_SEL_GND   0x00000002U

Referenced by TempDiodeGetTemp().

§ SYS0_TSENSCFG_SEL_VALUE

#define SYS0_TSENSCFG_SEL_VALUE   0x00000001U

Referenced by TempDiodeGetTemp().

§ SYS0_TSENSCFG_SEL_DISABLE

#define SYS0_TSENSCFG_SEL_DISABLE   0x00000000U

§ SYS0_LPCMPCFG_HYSPOL

#define SYS0_LPCMPCFG_HYSPOL   0x40000000U

§ SYS0_LPCMPCFG_HYSPOL_M

#define SYS0_LPCMPCFG_HYSPOL_M   0x40000000U

§ SYS0_LPCMPCFG_HYSPOL_S

#define SYS0_LPCMPCFG_HYSPOL_S   30U

§ SYS0_LPCMPCFG_ATESTMUX_W

#define SYS0_LPCMPCFG_ATESTMUX_W   2U

§ SYS0_LPCMPCFG_ATESTMUX_M

#define SYS0_LPCMPCFG_ATESTMUX_M   0x30000000U

§ SYS0_LPCMPCFG_ATESTMUX_S

#define SYS0_LPCMPCFG_ATESTMUX_S   28U

§ SYS0_LPCMPCFG_ATESTMUX_IBIASOUT

#define SYS0_LPCMPCFG_ATESTMUX_IBIASOUT   0x30000000U

§ SYS0_LPCMPCFG_ATESTMUX_COMP_VIN_NEG

#define SYS0_LPCMPCFG_ATESTMUX_COMP_VIN_NEG   0x20000000U

§ SYS0_LPCMPCFG_ATESTMUX_COMPOUT

#define SYS0_LPCMPCFG_ATESTMUX_COMPOUT   0x10000000U

§ SYS0_LPCMPCFG_ATESTMUX_OFF

#define SYS0_LPCMPCFG_ATESTMUX_OFF   0x00000000U

§ SYS0_LPCMPCFG_EVTIFG

#define SYS0_LPCMPCFG_EVTIFG   0x01000000U

Referenced by LPCMPClearEvent().

§ SYS0_LPCMPCFG_EVTIFG_M

#define SYS0_LPCMPCFG_EVTIFG_M   0x01000000U

§ SYS0_LPCMPCFG_EVTIFG_S

#define SYS0_LPCMPCFG_EVTIFG_S   24U

§ SYS0_LPCMPCFG_EVTIFG_SET

#define SYS0_LPCMPCFG_EVTIFG_SET   0x01000000U

§ SYS0_LPCMPCFG_EVTIFG_CLR

#define SYS0_LPCMPCFG_EVTIFG_CLR   0x00000000U

§ SYS0_LPCMPCFG_COUTEN

#define SYS0_LPCMPCFG_COUTEN   0x00200000U

§ SYS0_LPCMPCFG_COUTEN_M

#define SYS0_LPCMPCFG_COUTEN_M   0x00200000U

§ SYS0_LPCMPCFG_COUTEN_S

#define SYS0_LPCMPCFG_COUTEN_S   21U

§ SYS0_LPCMPCFG_COUTEN_EN

#define SYS0_LPCMPCFG_COUTEN_EN   0x00200000U

§ SYS0_LPCMPCFG_COUTEN_DIS

#define SYS0_LPCMPCFG_COUTEN_DIS   0x00000000U

§ SYS0_LPCMPCFG_COUT

#define SYS0_LPCMPCFG_COUT   0x00100000U

§ SYS0_LPCMPCFG_COUT_M

#define SYS0_LPCMPCFG_COUT_M   0x00100000U

§ SYS0_LPCMPCFG_COUT_S

#define SYS0_LPCMPCFG_COUT_S   20U

§ SYS0_LPCMPCFG_COUT_HIGH

#define SYS0_LPCMPCFG_COUT_HIGH   0x00100000U

Referenced by LPCMPIsOutputHigh().

§ SYS0_LPCMPCFG_COUT_LOW

#define SYS0_LPCMPCFG_COUT_LOW   0x00000000U

§ SYS0_LPCMPCFG_WUENSB

#define SYS0_LPCMPCFG_WUENSB   0x00040000U

Referenced by LPCMPDisableWakeup(), and LPCMPEnableWakeup().

§ SYS0_LPCMPCFG_WUENSB_M

#define SYS0_LPCMPCFG_WUENSB_M   0x00040000U

§ SYS0_LPCMPCFG_WUENSB_S

#define SYS0_LPCMPCFG_WUENSB_S   18U

§ SYS0_LPCMPCFG_WUENSB_EN

#define SYS0_LPCMPCFG_WUENSB_EN   0x00040000U

§ SYS0_LPCMPCFG_WUENSB_DIS

#define SYS0_LPCMPCFG_WUENSB_DIS   0x00000000U

§ SYS0_LPCMPCFG_EVTEN

#define SYS0_LPCMPCFG_EVTEN   0x00020000U

Referenced by LPCMPDisableEvent(), and LPCMPEnableEvent().

§ SYS0_LPCMPCFG_EVTEN_M

#define SYS0_LPCMPCFG_EVTEN_M   0x00020000U

§ SYS0_LPCMPCFG_EVTEN_S

#define SYS0_LPCMPCFG_EVTEN_S   17U

§ SYS0_LPCMPCFG_EVTEN_EN

#define SYS0_LPCMPCFG_EVTEN_EN   0x00020000U

§ SYS0_LPCMPCFG_EVTEN_DIS

#define SYS0_LPCMPCFG_EVTEN_DIS   0x00000000U

§ SYS0_LPCMPCFG_EDGCFG

#define SYS0_LPCMPCFG_EDGCFG   0x00010000U

Referenced by LPCMPSetPolarity().

§ SYS0_LPCMPCFG_EDGCFG_M

#define SYS0_LPCMPCFG_EDGCFG_M   0x00010000U

§ SYS0_LPCMPCFG_EDGCFG_S

#define SYS0_LPCMPCFG_EDGCFG_S   16U

§ SYS0_LPCMPCFG_EDGCFG_FALL

#define SYS0_LPCMPCFG_EDGCFG_FALL   0x00010000U

§ SYS0_LPCMPCFG_EDGCFG_RISE

#define SYS0_LPCMPCFG_EDGCFG_RISE   0x00000000U

§ SYS0_LPCMPCFG_NSEL_W

#define SYS0_LPCMPCFG_NSEL_W   3U

§ SYS0_LPCMPCFG_NSEL_M

#define SYS0_LPCMPCFG_NSEL_M   0x00007000U

Referenced by LPCMPSelectNegativeInput().

§ SYS0_LPCMPCFG_NSEL_S

#define SYS0_LPCMPCFG_NSEL_S   12U

§ SYS0_LPCMPCFG_NSEL_VDDD

#define SYS0_LPCMPCFG_NSEL_VDDD   0x00004000U

§ SYS0_LPCMPCFG_NSEL_VDDA

#define SYS0_LPCMPCFG_NSEL_VDDA   0x00003000U

§ SYS0_LPCMPCFG_NSEL_VA_PAD_A3

#define SYS0_LPCMPCFG_NSEL_VA_PAD_A3   0x00002000U

§ SYS0_LPCMPCFG_NSEL_VA_PAD_A2

#define SYS0_LPCMPCFG_NSEL_VA_PAD_A2   0x00001000U

§ SYS0_LPCMPCFG_NSEL_OPEN

#define SYS0_LPCMPCFG_NSEL_OPEN   0x00000000U

§ SYS0_LPCMPCFG_PSEL_W

#define SYS0_LPCMPCFG_PSEL_W   4U

§ SYS0_LPCMPCFG_PSEL_M

#define SYS0_LPCMPCFG_PSEL_M   0x00000F00U

Referenced by LPCMPSelectPositiveInput().

§ SYS0_LPCMPCFG_PSEL_S

#define SYS0_LPCMPCFG_PSEL_S   8U

§ SYS0_LPCMPCFG_PSEL_VDDA

#define SYS0_LPCMPCFG_PSEL_VDDA   0x00000800U

§ SYS0_LPCMPCFG_PSEL_VA_ATEST_A1

#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A1   0x00000700U

§ SYS0_LPCMPCFG_PSEL_VA_ATEST_A0

#define SYS0_LPCMPCFG_PSEL_VA_ATEST_A0   0x00000600U

§ SYS0_LPCMPCFG_PSEL_VR_ATEST_A1

#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A1   0x00000500U

§ SYS0_LPCMPCFG_PSEL_VR_ATEST_A0

#define SYS0_LPCMPCFG_PSEL_VR_ATEST_A0   0x00000400U

§ SYS0_LPCMPCFG_PSEL_VA_PAD_A3

#define SYS0_LPCMPCFG_PSEL_VA_PAD_A3   0x00000300U

§ SYS0_LPCMPCFG_PSEL_VA_PAD_A2

#define SYS0_LPCMPCFG_PSEL_VA_PAD_A2   0x00000200U

§ SYS0_LPCMPCFG_PSEL_VA_PAD_A1

#define SYS0_LPCMPCFG_PSEL_VA_PAD_A1   0x00000100U

§ SYS0_LPCMPCFG_PSEL_OPEN

#define SYS0_LPCMPCFG_PSEL_OPEN   0x00000000U

§ SYS0_LPCMPCFG_HYSSEL_W

#define SYS0_LPCMPCFG_HYSSEL_W   3U

§ SYS0_LPCMPCFG_HYSSEL_M

#define SYS0_LPCMPCFG_HYSSEL_M   0x000000E0U

§ SYS0_LPCMPCFG_HYSSEL_S

#define SYS0_LPCMPCFG_HYSSEL_S   5U

§ SYS0_LPCMPCFG_HYSSEL_VAL7

#define SYS0_LPCMPCFG_HYSSEL_VAL7   0x000000E0U

§ SYS0_LPCMPCFG_HYSSEL_VAL6

#define SYS0_LPCMPCFG_HYSSEL_VAL6   0x000000C0U

§ SYS0_LPCMPCFG_HYSSEL_VAL5

#define SYS0_LPCMPCFG_HYSSEL_VAL5   0x000000A0U

§ SYS0_LPCMPCFG_HYSSEL_VAL4

#define SYS0_LPCMPCFG_HYSSEL_VAL4   0x00000080U

§ SYS0_LPCMPCFG_HYSSEL_VAL3

#define SYS0_LPCMPCFG_HYSSEL_VAL3   0x00000060U

§ SYS0_LPCMPCFG_HYSSEL_VAL2

#define SYS0_LPCMPCFG_HYSSEL_VAL2   0x00000040U

§ SYS0_LPCMPCFG_HYSSEL_VAL1

#define SYS0_LPCMPCFG_HYSSEL_VAL1   0x00000020U

§ SYS0_LPCMPCFG_HYSSEL_VAL0

#define SYS0_LPCMPCFG_HYSSEL_VAL0   0x00000000U

§ SYS0_LPCMPCFG_DIVPATH

#define SYS0_LPCMPCFG_DIVPATH   0x00000010U

Referenced by LPCMPSetDividerPath().

§ SYS0_LPCMPCFG_DIVPATH_M

#define SYS0_LPCMPCFG_DIVPATH_M   0x00000010U

§ SYS0_LPCMPCFG_DIVPATH_S

#define SYS0_LPCMPCFG_DIVPATH_S   4U

§ SYS0_LPCMPCFG_DIVPATH_PSIDE

#define SYS0_LPCMPCFG_DIVPATH_PSIDE   0x00000010U

§ SYS0_LPCMPCFG_DIVPATH_NSIDE

#define SYS0_LPCMPCFG_DIVPATH_NSIDE   0x00000000U

§ SYS0_LPCMPCFG_DIV_W

#define SYS0_LPCMPCFG_DIV_W   3U

§ SYS0_LPCMPCFG_DIV_M

#define SYS0_LPCMPCFG_DIV_M   0x0000000EU

Referenced by LPCMPSetDividerRatio().

§ SYS0_LPCMPCFG_DIV_S

#define SYS0_LPCMPCFG_DIV_S   1U

§ SYS0_LPCMPCFG_DIV_VAL4

#define SYS0_LPCMPCFG_DIV_VAL4   0x00000008U

§ SYS0_LPCMPCFG_DIV_VAL3

#define SYS0_LPCMPCFG_DIV_VAL3   0x00000006U

§ SYS0_LPCMPCFG_DIV_VAL2

#define SYS0_LPCMPCFG_DIV_VAL2   0x00000004U

§ SYS0_LPCMPCFG_DIV_VAL1

#define SYS0_LPCMPCFG_DIV_VAL1   0x00000002U

§ SYS0_LPCMPCFG_DIV_VAL0

#define SYS0_LPCMPCFG_DIV_VAL0   0x00000000U

§ SYS0_LPCMPCFG_EN

#define SYS0_LPCMPCFG_EN   0x00000001U

Referenced by LPCMPDisable(), and LPCMPEnable().

§ SYS0_LPCMPCFG_EN_M

#define SYS0_LPCMPCFG_EN_M   0x00000001U

§ SYS0_LPCMPCFG_EN_S

#define SYS0_LPCMPCFG_EN_S   0U

§ SYS0_LPCMPCFG_EN_EN

#define SYS0_LPCMPCFG_EN_EN   0x00000001U

§ SYS0_LPCMPCFG_EN_DIS

#define SYS0_LPCMPCFG_EN_DIS   0x00000000U

§ SYS0_DEVICEID_VERSION_W

#define SYS0_DEVICEID_VERSION_W   4U

§ SYS0_DEVICEID_VERSION_M

#define SYS0_DEVICEID_VERSION_M   0xF0000000U

Referenced by ChipInfoGetVersion().

§ SYS0_DEVICEID_VERSION_S

#define SYS0_DEVICEID_VERSION_S   28U

Referenced by ChipInfoGetVersion().

§ SYS0_DEVICEID_DEVICE_W

#define SYS0_DEVICEID_DEVICE_W   16U

§ SYS0_DEVICEID_DEVICE_M

#define SYS0_DEVICEID_DEVICE_M   0x0FFFF000U

§ SYS0_DEVICEID_DEVICE_S

#define SYS0_DEVICEID_DEVICE_S   12U

§ SYS0_DEVICEID_MANFACTURER_W

#define SYS0_DEVICEID_MANFACTURER_W   11U

§ SYS0_DEVICEID_MANFACTURER_M

#define SYS0_DEVICEID_MANFACTURER_M   0x00000FFEU

§ SYS0_DEVICEID_MANFACTURER_S

#define SYS0_DEVICEID_MANFACTURER_S   1U

§ SYS0_DEVICEID_ALWAYSONE

#define SYS0_DEVICEID_ALWAYSONE   0x00000001U

§ SYS0_DEVICEID_ALWAYSONE_M

#define SYS0_DEVICEID_ALWAYSONE_M   0x00000001U

§ SYS0_DEVICEID_ALWAYSONE_S

#define SYS0_DEVICEID_ALWAYSONE_S   0U

§ SYS0_PARTID_START

#define SYS0_PARTID_START   0x80000000U

§ SYS0_PARTID_START_M

#define SYS0_PARTID_START_M   0x80000000U

§ SYS0_PARTID_START_S

#define SYS0_PARTID_START_S   31U

§ SYS0_PARTID_START_SET

#define SYS0_PARTID_START_SET   0x80000000U

§ SYS0_PARTID_START_CLR

#define SYS0_PARTID_START_CLR   0x00000000U

§ SYS0_PARTID_MAJORREV_W

#define SYS0_PARTID_MAJORREV_W   3U

§ SYS0_PARTID_MAJORREV_M

#define SYS0_PARTID_MAJORREV_M   0x70000000U

§ SYS0_PARTID_MAJORREV_S

#define SYS0_PARTID_MAJORREV_S   28U

§ SYS0_PARTID_MINORREV_W

#define SYS0_PARTID_MINORREV_W   4U

§ SYS0_PARTID_MINORREV_M

#define SYS0_PARTID_MINORREV_M   0x0F000000U

§ SYS0_PARTID_MINORREV_S

#define SYS0_PARTID_MINORREV_S   24U

§ SYS0_PARTID_VARIANT_W

#define SYS0_PARTID_VARIANT_W   8U

§ SYS0_PARTID_VARIANT_M

#define SYS0_PARTID_VARIANT_M   0x00FF0000U

§ SYS0_PARTID_VARIANT_S

#define SYS0_PARTID_VARIANT_S   16U

§ SYS0_PARTID_PART_W

#define SYS0_PARTID_PART_W   16U

§ SYS0_PARTID_PART_M

#define SYS0_PARTID_PART_M   0x0000FFFFU

§ SYS0_PARTID_PART_S

#define SYS0_PARTID_PART_S   0U

§ SYS0_TMUTE0_CDACL_W

#define SYS0_TMUTE0_CDACL_W   32U

§ SYS0_TMUTE0_CDACL_M

#define SYS0_TMUTE0_CDACL_M   0xFFFFFFFFU

§ SYS0_TMUTE0_CDACL_S

#define SYS0_TMUTE0_CDACL_S   0U

§ SYS0_TMUTE1_CDACM_W

#define SYS0_TMUTE1_CDACM_W   32U

§ SYS0_TMUTE1_CDACM_M

#define SYS0_TMUTE1_CDACM_M   0xFFFFFFFFU

§ SYS0_TMUTE1_CDACM_S

#define SYS0_TMUTE1_CDACM_S   0U

§ SYS0_TMUTE2_IBTRIM_W

#define SYS0_TMUTE2_IBTRIM_W   5U

§ SYS0_TMUTE2_IBTRIM_M

#define SYS0_TMUTE2_IBTRIM_M   0x7C000000U

§ SYS0_TMUTE2_IBTRIM_S

#define SYS0_TMUTE2_IBTRIM_S   26U

§ SYS0_TMUTE2_TRIM_W

#define SYS0_TMUTE2_TRIM_W   3U

§ SYS0_TMUTE2_TRIM_M

#define SYS0_TMUTE2_TRIM_M   0x03800000U

§ SYS0_TMUTE2_TRIM_S

#define SYS0_TMUTE2_TRIM_S   23U

§ SYS0_TMUTE2_LATCH_W

#define SYS0_TMUTE2_LATCH_W   7U

§ SYS0_TMUTE2_LATCH_M

#define SYS0_TMUTE2_LATCH_M   0x007F0000U

§ SYS0_TMUTE2_LATCH_S

#define SYS0_TMUTE2_LATCH_S   16U

§ SYS0_TMUTE2_OFFSET_W

#define SYS0_TMUTE2_OFFSET_W   12U

§ SYS0_TMUTE2_OFFSET_M

#define SYS0_TMUTE2_OFFSET_M   0x0000FFF0U

Referenced by ADCSetAdjustmentOffset().

§ SYS0_TMUTE2_OFFSET_S

#define SYS0_TMUTE2_OFFSET_S   4U

Referenced by ADCSetAdjustmentOffset().

§ SYS0_TMUTE2_RES_W

#define SYS0_TMUTE2_RES_W   2U

§ SYS0_TMUTE2_RES_M

#define SYS0_TMUTE2_RES_M   0x0000000CU

§ SYS0_TMUTE2_RES_S

#define SYS0_TMUTE2_RES_S   2U

§ SYS0_TMUTE2_CDACU_W

#define SYS0_TMUTE2_CDACU_W   2U

§ SYS0_TMUTE2_CDACU_M

#define SYS0_TMUTE2_CDACU_M   0x00000003U

§ SYS0_TMUTE2_CDACU_S

#define SYS0_TMUTE2_CDACU_S   0U

§ SYS0_TMUTE3_BATC1_W

#define SYS0_TMUTE3_BATC1_W   6U

§ SYS0_TMUTE3_BATC1_M

#define SYS0_TMUTE3_BATC1_M   0xFC000000U

§ SYS0_TMUTE3_BATC1_S

#define SYS0_TMUTE3_BATC1_S   26U

§ SYS0_TMUTE3_BATC0_W

#define SYS0_TMUTE3_BATC0_W   7U

§ SYS0_TMUTE3_BATC0_M

#define SYS0_TMUTE3_BATC0_M   0x03F80000U

§ SYS0_TMUTE3_BATC0_S

#define SYS0_TMUTE3_BATC0_S   19U

§ SYS0_TMUTE3_TEMPC2_W

#define SYS0_TMUTE3_TEMPC2_W   5U

§ SYS0_TMUTE3_TEMPC2_M

#define SYS0_TMUTE3_TEMPC2_M   0x0007C000U

§ SYS0_TMUTE3_TEMPC2_S

#define SYS0_TMUTE3_TEMPC2_S   14U

§ SYS0_TMUTE3_TEMPC1_W

#define SYS0_TMUTE3_TEMPC1_W   6U

§ SYS0_TMUTE3_TEMPC1_M

#define SYS0_TMUTE3_TEMPC1_M   0x00003F00U

§ SYS0_TMUTE3_TEMPC1_S

#define SYS0_TMUTE3_TEMPC1_S   8U

§ SYS0_TMUTE3_TEMPC0_W

#define SYS0_TMUTE3_TEMPC0_W   8U

§ SYS0_TMUTE3_TEMPC0_M

#define SYS0_TMUTE3_TEMPC0_M   0x000000FFU

§ SYS0_TMUTE3_TEMPC0_S

#define SYS0_TMUTE3_TEMPC0_S   0U

§ SYS0_TMUTE4_RECHCOMPREFLVL_W

#define SYS0_TMUTE4_RECHCOMPREFLVL_W   4U

§ SYS0_TMUTE4_RECHCOMPREFLVL_M

#define SYS0_TMUTE4_RECHCOMPREFLVL_M   0xF0000000U

§ SYS0_TMUTE4_RECHCOMPREFLVL_S

#define SYS0_TMUTE4_RECHCOMPREFLVL_S   28U

§ SYS0_TMUTE4_IOSTRCFG2_W

#define SYS0_TMUTE4_IOSTRCFG2_W   2U

§ SYS0_TMUTE4_IOSTRCFG2_M

#define SYS0_TMUTE4_IOSTRCFG2_M   0x0C000000U

§ SYS0_TMUTE4_IOSTRCFG2_S

#define SYS0_TMUTE4_IOSTRCFG2_S   26U

§ SYS0_TMUTE4_IOSTRCFG1_W

#define SYS0_TMUTE4_IOSTRCFG1_W   4U

§ SYS0_TMUTE4_IOSTRCFG1_M

#define SYS0_TMUTE4_IOSTRCFG1_M   0x03C00000U

§ SYS0_TMUTE4_IOSTRCFG1_S

#define SYS0_TMUTE4_IOSTRCFG1_S   22U

§ SYS0_TMUTE4_MAX_W

#define SYS0_TMUTE4_MAX_W   3U

§ SYS0_TMUTE4_MAX_M

#define SYS0_TMUTE4_MAX_M   0x00380000U

§ SYS0_TMUTE4_MAX_S

#define SYS0_TMUTE4_MAX_S   19U

§ SYS0_TMUTE4_MED_W

#define SYS0_TMUTE4_MED_W   3U

§ SYS0_TMUTE4_MED_M

#define SYS0_TMUTE4_MED_M   0x00070000U

§ SYS0_TMUTE4_MED_S

#define SYS0_TMUTE4_MED_S   16U

§ SYS0_TMUTE4_MIN_W

#define SYS0_TMUTE4_MIN_W   3U

§ SYS0_TMUTE4_MIN_M

#define SYS0_TMUTE4_MIN_M   0x0000E000U

§ SYS0_TMUTE4_MIN_S

#define SYS0_TMUTE4_MIN_S   13U

§ SYS0_TMUTE4_DCDCLOAD_W

#define SYS0_TMUTE4_DCDCLOAD_W   2U

§ SYS0_TMUTE4_DCDCLOAD_M

#define SYS0_TMUTE4_DCDCLOAD_M   0x00001800U

§ SYS0_TMUTE4_DCDCLOAD_S

#define SYS0_TMUTE4_DCDCLOAD_S   11U

§ SYS0_TMUTE4_IPEAK_W

#define SYS0_TMUTE4_IPEAK_W   3U

§ SYS0_TMUTE4_IPEAK_M

#define SYS0_TMUTE4_IPEAK_M   0x00000700U

§ SYS0_TMUTE4_IPEAK_S

#define SYS0_TMUTE4_IPEAK_S   8U

§ SYS0_TMUTE4_DTIME_W

#define SYS0_TMUTE4_DTIME_W   2U

§ SYS0_TMUTE4_DTIME_M

#define SYS0_TMUTE4_DTIME_M   0x000000C0U

§ SYS0_TMUTE4_DTIME_S

#define SYS0_TMUTE4_DTIME_S   6U

§ SYS0_TMUTE4_LENSEL_W

#define SYS0_TMUTE4_LENSEL_W   3U

§ SYS0_TMUTE4_LENSEL_M

#define SYS0_TMUTE4_LENSEL_M   0x00000038U

§ SYS0_TMUTE4_LENSEL_S

#define SYS0_TMUTE4_LENSEL_S   3U

§ SYS0_TMUTE4_HENSEL_W

#define SYS0_TMUTE4_HENSEL_W   3U

§ SYS0_TMUTE4_HENSEL_M

#define SYS0_TMUTE4_HENSEL_M   0x00000007U

§ SYS0_TMUTE4_HENSEL_S

#define SYS0_TMUTE4_HENSEL_S   0U

§ SYS0_TMUTE5_DCDCDRVDS_W

#define SYS0_TMUTE5_DCDCDRVDS_W   3U

§ SYS0_TMUTE5_DCDCDRVDS_M

#define SYS0_TMUTE5_DCDCDRVDS_M   0x00001C00U

§ SYS0_TMUTE5_DCDCDRVDS_S

#define SYS0_TMUTE5_DCDCDRVDS_S   10U

§ SYS0_TMUTE5_GLDOISCLR_W

#define SYS0_TMUTE5_GLDOISCLR_W   5U

§ SYS0_TMUTE5_GLDOISCLR_M

#define SYS0_TMUTE5_GLDOISCLR_M   0x000003E0U

§ SYS0_TMUTE5_GLDOISCLR_S

#define SYS0_TMUTE5_GLDOISCLR_S   5U

§ SYS0_TMUTE5_GLDOISSET_W

#define SYS0_TMUTE5_GLDOISSET_W   5U

§ SYS0_TMUTE5_GLDOISSET_M

#define SYS0_TMUTE5_GLDOISSET_M   0x0000001FU

§ SYS0_TMUTE5_GLDOISSET_S

#define SYS0_TMUTE5_GLDOISSET_S   0U