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CC23x0R5DriverLibrary
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Go to the source code of this file.
| #define SCB_O_CPUID 0x00000000U |
| #define SCB_O_ICSR 0x00000004U |
| #define SCB_O_VTOR 0x00000008U |
| #define SCB_O_AIRCR 0x0000000CU |
| #define SCB_O_SCR 0x00000010U |
| #define SCB_O_CCR 0x00000014U |
| #define SCB_O_SHPR2 0x0000001CU |
| #define SCB_O_SHPR3 0x00000020U |
| #define SCB_O_SHCSR 0x00000024U |
| #define SCB_CPUID_IMPLEMENTER_W 8U |
| #define SCB_CPUID_IMPLEMENTER_M 0xFF000000U |
| #define SCB_CPUID_IMPLEMENTER_S 24U |
| #define SCB_CPUID_VARIANT_W 4U |
| #define SCB_CPUID_VARIANT_M 0x00F00000U |
| #define SCB_CPUID_VARIANT_S 20U |
| #define SCB_CPUID_CONSTANT_W 4U |
| #define SCB_CPUID_CONSTANT_M 0x000F0000U |
| #define SCB_CPUID_CONSTANT_S 16U |
| #define SCB_CPUID_PARTNO_W 12U |
| #define SCB_CPUID_PARTNO_M 0x0000FFF0U |
| #define SCB_CPUID_PARTNO_S 4U |
| #define SCB_CPUID_REVISION_W 4U |
| #define SCB_CPUID_REVISION_M 0x0000000FU |
| #define SCB_CPUID_REVISION_S 0U |
| #define SCB_ICSR_NMIPENDSET 0x80000000U |
| #define SCB_ICSR_NMIPENDSET_M 0x80000000U |
| #define SCB_ICSR_NMIPENDSET_S 31U |
| #define SCB_ICSR_PENDSVSET 0x10000000U |
| #define SCB_ICSR_PENDSVSET_M 0x10000000U |
| #define SCB_ICSR_PENDSVSET_S 28U |
| #define SCB_ICSR_PENDSVCLR 0x08000000U |
| #define SCB_ICSR_PENDSVCLR_M 0x08000000U |
| #define SCB_ICSR_PENDSVCLR_S 27U |
| #define SCB_ICSR_PENDSTSET 0x04000000U |
| #define SCB_ICSR_PENDSTSET_M 0x04000000U |
| #define SCB_ICSR_PENDSTSET_S 26U |
| #define SCB_ICSR_PENDSTCLR 0x02000000U |
| #define SCB_ICSR_PENDSTCLR_M 0x02000000U |
| #define SCB_ICSR_PENDSTCLR_S 25U |
| #define SCB_ICSR_ISRPREEMPT 0x00800000U |
| #define SCB_ICSR_ISRPREEMPT_M 0x00800000U |
| #define SCB_ICSR_ISRPREEMPT_S 23U |
| #define SCB_ICSR_ISRPENDING 0x00400000U |
| #define SCB_ICSR_ISRPENDING_M 0x00400000U |
| #define SCB_ICSR_ISRPENDING_S 22U |
| #define SCB_ICSR_VECTPENDING_W 9U |
| #define SCB_ICSR_VECTPENDING_M 0x001FF000U |
| #define SCB_ICSR_VECTPENDING_S 12U |
| #define SCB_ICSR_VECTACTIVE_W 9U |
| #define SCB_ICSR_VECTACTIVE_M 0x000001FFU |
| #define SCB_ICSR_VECTACTIVE_S 0U |
| #define SCB_VTOR_TBLOFF_W 24U |
| #define SCB_VTOR_TBLOFF_M 0xFFFFFF00U |
| #define SCB_VTOR_TBLOFF_S 8U |
| #define SCB_AIRCR_VECTKEY_W 16U |
| #define SCB_AIRCR_VECTKEY_M 0xFFFF0000U |
| #define SCB_AIRCR_VECTKEY_S 16U |
| #define SCB_AIRCR_ENDIANESS 0x00008000U |
| #define SCB_AIRCR_ENDIANESS_M 0x00008000U |
| #define SCB_AIRCR_ENDIANESS_S 15U |
| #define SCB_AIRCR_SYSRESETREQ 0x00000004U |
| #define SCB_AIRCR_SYSRESETREQ_M 0x00000004U |
| #define SCB_AIRCR_SYSRESETREQ_S 2U |
| #define SCB_AIRCR_VECTCLRACTIVE 0x00000002U |
| #define SCB_AIRCR_VECTCLRACTIVE_M 0x00000002U |
| #define SCB_AIRCR_VECTCLRACTIVE_S 1U |
| #define SCB_SCR_SEVONPEND 0x00000010U |
| #define SCB_SCR_SEVONPEND_M 0x00000010U |
| #define SCB_SCR_SEVONPEND_S 4U |
| #define SCB_SCR_SLEEPDEEP 0x00000004U |
| #define SCB_SCR_SLEEPDEEP_M 0x00000004U |
| #define SCB_SCR_SLEEPDEEP_S 2U |
| #define SCB_SCR_SLEEPDEEP_DSLP_EN 0x00000004U |
| #define SCB_SCR_SLEEPDEEP_DSLP_DIS 0x00000000U |
| #define SCB_SCR_SLEEPONEXIT 0x00000002U |
| #define SCB_SCR_SLEEPONEXIT_M 0x00000002U |
| #define SCB_SCR_SLEEPONEXIT_S 1U |
| #define SCB_SCR_SLEEPONEXIT_SLP_EN 0x00000002U |
| #define SCB_SCR_SLEEPONEXIT_SLP_DIS 0x00000000U |
| #define SCB_CCR_STKALIGN 0x00000200U |
| #define SCB_CCR_STKALIGN_M 0x00000200U |
| #define SCB_CCR_STKALIGN_S 9U |
| #define SCB_CCR_UNALIGN_TRP 0x00000008U |
| #define SCB_CCR_UNALIGN_TRP_M 0x00000008U |
| #define SCB_CCR_UNALIGN_TRP_S 3U |
| #define SCB_SHPR2_PRI_11_W 2U |
| #define SCB_SHPR2_PRI_11_M 0xC0000000U |
| #define SCB_SHPR2_PRI_11_S 30U |
| #define SCB_SHPR3_PRI_15_W 2U |
| #define SCB_SHPR3_PRI_15_M 0xC0000000U |
| #define SCB_SHPR3_PRI_15_S 30U |
| #define SCB_SHPR3_PRI_14_W 2U |
| #define SCB_SHPR3_PRI_14_M 0x00C00000U |
| #define SCB_SHPR3_PRI_14_S 22U |
| #define SCB_SHCSR_SVCALLPENDED 0x00008000U |
| #define SCB_SHCSR_SVCALLPENDED_M 0x00008000U |
| #define SCB_SHCSR_SVCALLPENDED_S 15U |