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Go to the documentation of this file. 43 #define PMUD_O_CTL 0x00000000U 46 #define PMUD_O_MEASCFG 0x00000004U 49 #define PMUD_O_BAT 0x00000028U 52 #define PMUD_O_BATUPD 0x0000002CU 55 #define PMUD_O_TEMP 0x00000030U 58 #define PMUD_O_TEMPUPD 0x00000034U 61 #define PMUD_O_EVENTMASK 0x00000048U 64 #define PMUD_O_EVENT 0x0000004CU 67 #define PMUD_O_BATTUL 0x00000050U 70 #define PMUD_O_BATTLL 0x00000054U 73 #define PMUD_O_TEMPUL 0x00000058U 76 #define PMUD_O_TEMPLL 0x0000005CU 79 #define PMUD_O_PREG0 0x00000090U 82 #define PMUD_O_PREG1 0x00000094U 85 #define PMUD_O_PREG2 0x00000098U 88 #define PMUD_O_DCDCCFG 0x0000009CU 91 #define PMUD_O_DCDCSTAT 0x000000A0U 104 #define PMUD_CTL_HYST_EN 0x00000004U 105 #define PMUD_CTL_HYST_EN_M 0x00000004U 106 #define PMUD_CTL_HYST_EN_S 2U 107 #define PMUD_CTL_HYST_EN_EN 0x00000004U 108 #define PMUD_CTL_HYST_EN_DIS 0x00000000U 117 #define PMUD_CTL_CALC_EN 0x00000002U 118 #define PMUD_CTL_CALC_EN_M 0x00000002U 119 #define PMUD_CTL_CALC_EN_S 1U 120 #define PMUD_CTL_CALC_EN_EN 0x00000002U 121 #define PMUD_CTL_CALC_EN_DIS 0x00000000U 131 #define PMUD_CTL_MEAS_EN 0x00000001U 132 #define PMUD_CTL_MEAS_EN_M 0x00000001U 133 #define PMUD_CTL_MEAS_EN_S 0U 134 #define PMUD_CTL_MEAS_EN_EN 0x00000001U 135 #define PMUD_CTL_MEAS_EN_DIS 0x00000000U 150 #define PMUD_MEASCFG_PER_W 2U 151 #define PMUD_MEASCFG_PER_M 0x00000003U 152 #define PMUD_MEASCFG_PER_S 0U 153 #define PMUD_MEASCFG_PER__32CYC 0x00000003U 154 #define PMUD_MEASCFG_PER__16CYC 0x00000002U 155 #define PMUD_MEASCFG_PER__8CYC 0x00000001U 156 #define PMUD_MEASCFG_PER_CONT 0x00000000U 171 #define PMUD_BAT_INT_W 3U 172 #define PMUD_BAT_INT_M 0x00000700U 173 #define PMUD_BAT_INT_S 8U 188 #define PMUD_BAT_FRAC_W 8U 189 #define PMUD_BAT_FRAC_M 0x000000FFU 190 #define PMUD_BAT_FRAC_S 0U 203 #define PMUD_BATUPD_STA 0x00000001U 204 #define PMUD_BATUPD_STA_M 0x00000001U 205 #define PMUD_BATUPD_STA_S 0U 206 #define PMUD_BATUPD_STA_UPD 0x00000001U 207 #define PMUD_BATUPD_STA_NOUPD 0x00000000U 227 #define PMUD_TEMP_INT_W 9U 228 #define PMUD_TEMP_INT_M 0x0001FF00U 229 #define PMUD_TEMP_INT_S 8U 253 #define PMUD_TEMP_FRAC_W 2U 254 #define PMUD_TEMP_FRAC_M 0x000000C0U 255 #define PMUD_TEMP_FRAC_S 6U 268 #define PMUD_TEMPUPD_STA 0x00000001U 269 #define PMUD_TEMPUPD_STA_M 0x00000001U 270 #define PMUD_TEMPUPD_STA_S 0U 271 #define PMUD_TEMPUPD_STA_UPD 0x00000001U 272 #define PMUD_TEMPUPD_STA_NOUPD 0x00000000U 283 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK 0x00000020U 284 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020U 285 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_S 5U 291 #define PMUD_EVENTMASK_BATT_UPDATE_MASK 0x00000010U 292 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010U 293 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_S 4U 299 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008U 300 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008U 301 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_S 3U 307 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004U 308 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004U 309 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_S 2U 315 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002U 316 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002U 317 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_S 1U 323 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK 0x00000001U 324 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001U 325 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_S 0U 335 #define PMUD_EVENT_TEMP_UPDATE 0x00000020U 336 #define PMUD_EVENT_TEMP_UPDATE_M 0x00000020U 337 #define PMUD_EVENT_TEMP_UPDATE_S 5U 342 #define PMUD_EVENT_BATT_UPDATE 0x00000010U 343 #define PMUD_EVENT_BATT_UPDATE_M 0x00000010U 344 #define PMUD_EVENT_BATT_UPDATE_S 4U 354 #define PMUD_EVENT_TEMP_BELOW_LL 0x00000008U 355 #define PMUD_EVENT_TEMP_BELOW_LL_M 0x00000008U 356 #define PMUD_EVENT_TEMP_BELOW_LL_S 3U 366 #define PMUD_EVENT_TEMP_OVER_UL 0x00000004U 367 #define PMUD_EVENT_TEMP_OVER_UL_M 0x00000004U 368 #define PMUD_EVENT_TEMP_OVER_UL_S 2U 378 #define PMUD_EVENT_BATT_BELOW_LL 0x00000002U 379 #define PMUD_EVENT_BATT_BELOW_LL_M 0x00000002U 380 #define PMUD_EVENT_BATT_BELOW_LL_S 1U 390 #define PMUD_EVENT_BATT_OVER_UL 0x00000001U 391 #define PMUD_EVENT_BATT_OVER_UL_M 0x00000001U 392 #define PMUD_EVENT_BATT_OVER_UL_S 0U 408 #define PMUD_BATTUL_INT_W 3U 409 #define PMUD_BATTUL_INT_M 0x00000700U 410 #define PMUD_BATTUL_INT_S 8U 425 #define PMUD_BATTUL_FRAC_W 8U 426 #define PMUD_BATTUL_FRAC_M 0x000000FFU 427 #define PMUD_BATTUL_FRAC_S 0U 443 #define PMUD_BATTLL_INT_W 3U 444 #define PMUD_BATTLL_INT_M 0x00000700U 445 #define PMUD_BATTLL_INT_S 8U 460 #define PMUD_BATTLL_FRAC_W 8U 461 #define PMUD_BATTLL_FRAC_M 0x000000FFU 462 #define PMUD_BATTLL_FRAC_S 0U 482 #define PMUD_TEMPUL_INT_W 9U 483 #define PMUD_TEMPUL_INT_M 0x0001FF00U 484 #define PMUD_TEMPUL_INT_S 8U 508 #define PMUD_TEMPUL_FRAC_W 2U 509 #define PMUD_TEMPUL_FRAC_M 0x000000C0U 510 #define PMUD_TEMPUL_FRAC_S 6U 530 #define PMUD_TEMPLL_INT_W 9U 531 #define PMUD_TEMPLL_INT_M 0x0001FF00U 532 #define PMUD_TEMPLL_INT_S 8U 556 #define PMUD_TEMPLL_FRAC_W 2U 557 #define PMUD_TEMPLL_FRAC_M 0x000000C0U 558 #define PMUD_TEMPLL_FRAC_S 6U 571 #define PMUD_PREG0_LOW_IPEAK_DIS 0x00000800U 572 #define PMUD_PREG0_LOW_IPEAK_DIS_M 0x00000800U 573 #define PMUD_PREG0_LOW_IPEAK_DIS_S 11U 574 #define PMUD_PREG0_LOW_IPEAK_DIS_SET 0x00000800U 575 #define PMUD_PREG0_LOW_IPEAK_DIS_CLR 0x00000000U 583 #define PMUD_PREG0_SOCLDO_ITESTEN 0x00000400U 584 #define PMUD_PREG0_SOCLDO_ITESTEN_M 0x00000400U 585 #define PMUD_PREG0_SOCLDO_ITESTEN_S 10U 586 #define PMUD_PREG0_SOCLDO_ITESTEN_EN 0x00000400U 587 #define PMUD_PREG0_SOCLDO_ITESTEN_DIS 0x00000000U 597 #define PMUD_PREG0_SOCLDO_ATBSEL_W 3U 598 #define PMUD_PREG0_SOCLDO_ATBSEL_M 0x00000380U 599 #define PMUD_PREG0_SOCLDO_ATBSEL_S 7U 600 #define PMUD_PREG0_SOCLDO_ATBSEL_VDD_AON 0x00000200U 601 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_VREF_AMP_OUT 0x00000100U 602 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_ITEST 0x00000080U 603 #define PMUD_PREG0_SOCLDO_ATBSEL_NC 0x00000000U 613 #define PMUD_PREG0_UDIGLDO_ATBSEL_W 2U 614 #define PMUD_PREG0_UDIGLDO_ATBSEL_M 0x00000060U 615 #define PMUD_PREG0_UDIGLDO_ATBSEL_S 5U 616 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL3 0x00000060U 617 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL2 0x00000040U 618 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL1 0x00000020U 619 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL0 0x00000000U 629 #define PMUD_PREG0_DIGLDO_ATBSEL_W 3U 630 #define PMUD_PREG0_DIGLDO_ATBSEL_M 0x0000001CU 631 #define PMUD_PREG0_DIGLDO_ATBSEL_S 2U 632 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL4 0x00000010U 633 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL2 0x00000008U 634 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL1 0x00000004U 635 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL0 0x00000000U 640 #define PMUD_PREG0_SPARE 0x00000002U 641 #define PMUD_PREG0_SPARE_M 0x00000002U 642 #define PMUD_PREG0_SPARE_S 1U 650 #define PMUD_PREG0_UDIGLDO_EN 0x00000001U 651 #define PMUD_PREG0_UDIGLDO_EN_M 0x00000001U 652 #define PMUD_PREG0_UDIGLDO_EN_S 0U 653 #define PMUD_PREG0_UDIGLDO_EN_EN 0x00000001U 654 #define PMUD_PREG0_UDIGLDO_EN_DIS 0x00000000U 667 #define PMUD_PREG1_TEST_DCDC_NMOS 0x00080000U 668 #define PMUD_PREG1_TEST_DCDC_NMOS_M 0x00080000U 669 #define PMUD_PREG1_TEST_DCDC_NMOS_S 19U 670 #define PMUD_PREG1_TEST_DCDC_NMOS_EN 0x00080000U 671 #define PMUD_PREG1_TEST_DCDC_NMOS_DIS 0x00000000U 679 #define PMUD_PREG1_TEST_DCDC_PMOS 0x00040000U 680 #define PMUD_PREG1_TEST_DCDC_PMOS_M 0x00040000U 681 #define PMUD_PREG1_TEST_DCDC_PMOS_S 18U 682 #define PMUD_PREG1_TEST_DCDC_PMOS_EN 0x00040000U 683 #define PMUD_PREG1_TEST_DCDC_PMOS_DIS 0x00000000U 691 #define PMUD_PREG1_DITHER_EN 0x00020000U 692 #define PMUD_PREG1_DITHER_EN_M 0x00020000U 693 #define PMUD_PREG1_DITHER_EN_S 17U 694 #define PMUD_PREG1_DITHER_EN_EN 0x00020000U 695 #define PMUD_PREG1_DITHER_EN_DIS 0x00000000U 703 #define PMUD_PREG1_GLDO_AON 0x00010000U 704 #define PMUD_PREG1_GLDO_AON_M 0x00010000U 705 #define PMUD_PREG1_GLDO_AON_S 16U 706 #define PMUD_PREG1_GLDO_AON_EN 0x00010000U 707 #define PMUD_PREG1_GLDO_AON_DIS 0x00000000U 715 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN 0x00008000U 716 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_M 0x00008000U 717 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_S 15U 718 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_EN 0x00008000U 719 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_DIS 0x00000000U 727 #define PMUD_PREG1_RCHG_BLK_ATEST_EN 0x00004000U 728 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_M 0x00004000U 729 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_S 14U 730 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_EN 0x00004000U 731 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_DIS 0x00000000U 739 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF 0x00002000U 740 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_M 0x00002000U 741 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_S 13U 742 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_EN 0x00002000U 743 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_DIS 0x00000000U 751 #define PMUD_PREG1_RCHG_COMP_CLK_DIS 0x00001000U 752 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_M 0x00001000U 753 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_S 12U 754 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_DIS 0x00001000U 755 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_EN 0x00000000U 760 #define PMUD_PREG1_SPARE 0x00000080U 761 #define PMUD_PREG1_SPARE_M 0x00000080U 762 #define PMUD_PREG1_SPARE_S 7U 770 #define PMUD_PREG1_VDDR_ATBSEL 0x00000040U 771 #define PMUD_PREG1_VDDR_ATBSEL_M 0x00000040U 772 #define PMUD_PREG1_VDDR_ATBSEL_S 6U 773 #define PMUD_PREG1_VDDR_ATBSEL_EN 0x00000040U 774 #define PMUD_PREG1_VDDR_ATBSEL_DIS 0x00000000U 782 #define PMUD_PREG1_GLDO_EA_BIAS_DIS 0x00000020U 783 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_M 0x00000020U 784 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_S 5U 785 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_OFF 0x00000020U 786 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_ON 0x00000000U 797 #define PMUD_PREG1_GLDO_ATBSEL_W 4U 798 #define PMUD_PREG1_GLDO_ATBSEL_M 0x0000001EU 799 #define PMUD_PREG1_GLDO_ATBSEL_S 1U 800 #define PMUD_PREG1_GLDO_ATBSEL_VDDROK 0x00000010U 801 #define PMUD_PREG1_GLDO_ATBSEL_IB1U 0x00000008U 802 #define PMUD_PREG1_GLDO_ATBSEL_PASSGATE 0x00000004U 803 #define PMUD_PREG1_GLDO_ATBSEL_ERRAMP_OUT 0x00000002U 804 #define PMUD_PREG1_GLDO_ATBSEL_NC 0x00000000U 817 #define PMUD_PREG2_RSTNMASK 0x00000020U 818 #define PMUD_PREG2_RSTNMASK_M 0x00000020U 819 #define PMUD_PREG2_RSTNMASK_S 5U 820 #define PMUD_PREG2_RSTNMASK_BM 0x00000020U 821 #define PMUD_PREG2_RSTNMASK_BNM 0x00000000U 829 #define PMUD_PREG2_DCDC_RCHG_ATBSEL 0x00000010U 830 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_M 0x00000010U 831 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_S 4U 832 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_RCHG_BLK 0x00000010U 833 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_DCDC_GLDO 0x00000000U 844 #define PMUD_PREG2_PMUREG_ATBSEL_W 4U 845 #define PMUD_PREG2_PMUREG_ATBSEL_M 0x0000000FU 846 #define PMUD_PREG2_PMUREG_ATBSEL_S 0U 847 #define PMUD_PREG2_PMUREG_ATBSEL_DCDC_ATEST0_RCHG_ATEST1 0x00000008U 848 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOI_A0 0x00000004U 849 #define PMUD_PREG2_PMUREG_ATBSEL_RESERVED 0x00000002U 850 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOV_A1 0x00000001U 851 #define PMUD_PREG2_PMUREG_ATBSEL_NC 0x00000000U 863 #define PMUD_DCDCCFG_LM_HIGHTH_W 7U 864 #define PMUD_DCDCCFG_LM_HIGHTH_M 0x007F0000U 865 #define PMUD_DCDCCFG_LM_HIGHTH_S 16U 872 #define PMUD_DCDCCFG_LM_LOWTH_W 7U 873 #define PMUD_DCDCCFG_LM_LOWTH_M 0x00007F00U 874 #define PMUD_DCDCCFG_LM_LOWTH_S 8U 885 #define PMUD_DCDCCFG_ADP_IPEAK_EN 0x00000010U 886 #define PMUD_DCDCCFG_ADP_IPEAK_EN_M 0x00000010U 887 #define PMUD_DCDCCFG_ADP_IPEAK_EN_S 4U 888 #define PMUD_DCDCCFG_ADP_IPEAK_EN_EN 0x00000010U 889 #define PMUD_DCDCCFG_ADP_IPEAK_EN_DIS 0x00000000U 899 #define PMUD_DCDCCFG_LMEN 0x00000001U 900 #define PMUD_DCDCCFG_LMEN_M 0x00000001U 901 #define PMUD_DCDCCFG_LMEN_S 0U 902 #define PMUD_DCDCCFG_LMEN_EN 0x00000001U 903 #define PMUD_DCDCCFG_LMEN_DIS 0x00000000U 917 #define PMUD_DCDCSTAT_IPEAK_W 3U 918 #define PMUD_DCDCSTAT_IPEAK_M 0x00000700U 919 #define PMUD_DCDCSTAT_IPEAK_S 8U 925 #define PMUD_DCDCSTAT_LOAD_W 7U 926 #define PMUD_DCDCSTAT_LOAD_M 0x0000007FU 927 #define PMUD_DCDCSTAT_LOAD_S 0U