CC23x0R5DriverLibrary
hw_pmud.h
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32 
33 #ifndef __HW_PMUD_H__
34 #define __HW_PMUD_H__
35 
36 //*****************************************************************************
37 //
38 // This section defines the register offsets of
39 // PMUD component
40 //
41 //*****************************************************************************
42 // Control
43 #define PMUD_O_CTL 0x00000000U
44 
45 // Internal. Only to be used through TI provided API.
46 #define PMUD_O_MEASCFG 0x00000004U
47 
48 // Last Measured Battery Voltage
49 #define PMUD_O_BAT 0x00000028U
50 
51 // Battery Update
52 #define PMUD_O_BATUPD 0x0000002CU
53 
54 // Last measured Temperature in Degree Celsius
55 #define PMUD_O_TEMP 0x00000030U
56 
57 // Temperature Update
58 #define PMUD_O_TEMPUPD 0x00000034U
59 
60 // Event Mask
61 #define PMUD_O_EVENTMASK 0x00000048U
62 
63 // Event
64 #define PMUD_O_EVENT 0x0000004CU
65 
66 // Battery Upper Limit
67 #define PMUD_O_BATTUL 0x00000050U
68 
69 // Battery Lower Limit
70 #define PMUD_O_BATTLL 0x00000054U
71 
72 // Temperature Upper Limit
73 #define PMUD_O_TEMPUL 0x00000058U
74 
75 // Temperature Lower Limit
76 #define PMUD_O_TEMPLL 0x0000005CU
77 
78 // Internal. Only to be used through TI provided API.
79 #define PMUD_O_PREG0 0x00000090U
80 
81 // Internal. Only to be used through TI provided API.
82 #define PMUD_O_PREG1 0x00000094U
83 
84 // Internal. Only to be used through TI provided API.
85 #define PMUD_O_PREG2 0x00000098U
86 
87 // DCDC configuration
88 #define PMUD_O_DCDCCFG 0x0000009CU
89 
90 // DCDC status
91 #define PMUD_O_DCDCSTAT 0x000000A0U
92 
93 //*****************************************************************************
94 //
95 // Register: PMUD_O_CTL
96 //
97 //*****************************************************************************
98 // Field: [2] HYST_EN
99 //
100 // Enables hysteresis on both battery and temperature measurements.
101 // ENUMs:
102 // EN Enable
103 // DIS Disable
104 #define PMUD_CTL_HYST_EN 0x00000004U
105 #define PMUD_CTL_HYST_EN_M 0x00000004U
106 #define PMUD_CTL_HYST_EN_S 2U
107 #define PMUD_CTL_HYST_EN_EN 0x00000004U
108 #define PMUD_CTL_HYST_EN_DIS 0x00000000U
109 
110 // Field: [1] CALC_EN
111 //
112 // Configuration of the calculation block that converts the digital
113 // battery/temperature level to a Volt/Celsius value.
114 // ENUMs:
115 // EN Calculation enabled
116 // DIS Calculation disabled
117 #define PMUD_CTL_CALC_EN 0x00000002U
118 #define PMUD_CTL_CALC_EN_M 0x00000002U
119 #define PMUD_CTL_CALC_EN_S 1U
120 #define PMUD_CTL_CALC_EN_EN 0x00000002U
121 #define PMUD_CTL_CALC_EN_DIS 0x00000000U
122 
123 // Field: [0] MEAS_EN
124 //
125 // Configuration of the measurement block that interfaces with the analog
126 // domain.
127 // ENUMs:
128 // EN Measurements enabled (battery voltage and
129 // temperature)
130 // DIS Measurements disabled
131 #define PMUD_CTL_MEAS_EN 0x00000001U
132 #define PMUD_CTL_MEAS_EN_M 0x00000001U
133 #define PMUD_CTL_MEAS_EN_S 0U
134 #define PMUD_CTL_MEAS_EN_EN 0x00000001U
135 #define PMUD_CTL_MEAS_EN_DIS 0x00000000U
136 
137 //*****************************************************************************
138 //
139 // Register: PMUD_O_MEASCFG
140 //
141 //*****************************************************************************
142 // Field: [1:0] PER
143 //
144 // Internal. Only to be used through TI provided API.
145 // ENUMs:
146 // _32CYC Internal. Only to be used through TI provided API.
147 // _16CYC Internal. Only to be used through TI provided API.
148 // _8CYC Internal. Only to be used through TI provided API.
149 // CONT Internal. Only to be used through TI provided API.
150 #define PMUD_MEASCFG_PER_W 2U
151 #define PMUD_MEASCFG_PER_M 0x00000003U
152 #define PMUD_MEASCFG_PER_S 0U
153 #define PMUD_MEASCFG_PER__32CYC 0x00000003U
154 #define PMUD_MEASCFG_PER__16CYC 0x00000002U
155 #define PMUD_MEASCFG_PER__8CYC 0x00000001U
156 #define PMUD_MEASCFG_PER_CONT 0x00000000U
157 
158 //*****************************************************************************
159 //
160 // Register: PMUD_O_BAT
161 //
162 //*****************************************************************************
163 // Field: [10:8] INT
164 //
165 // Integer part:
166 //
167 // 0x0: Battery voltage = 0V + fractional part
168 // ...
169 // 0x3: Battery voltage = 3V + fractional part
170 // 0x4: Battery voltage = 4V + fractional part
171 #define PMUD_BAT_INT_W 3U
172 #define PMUD_BAT_INT_M 0x00000700U
173 #define PMUD_BAT_INT_S 8U
174 
175 // Field: [7:0] FRAC
176 //
177 // Fractional part, standard binary fractional encoding.
178 //
179 // 0x00: .0V
180 // ...
181 // 0x20: 1/8 = .125V
182 // 0x40: 1/4 = .25V
183 // 0x80: 1/2 = .5V
184 // ...
185 // 0xA0: 1/2 + 1/8 = .625V
186 // ...
187 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V
188 #define PMUD_BAT_FRAC_W 8U
189 #define PMUD_BAT_FRAC_M 0x000000FFU
190 #define PMUD_BAT_FRAC_S 0U
191 
192 //*****************************************************************************
193 //
194 // Register: PMUD_O_BATUPD
195 //
196 //*****************************************************************************
197 // Field: [0] STA
198 //
199 // Battery update status. Write 1 to clear the status.
200 // ENUMs:
201 // UPD New battery voltage present
202 // NOUPD No update since last clear
203 #define PMUD_BATUPD_STA 0x00000001U
204 #define PMUD_BATUPD_STA_M 0x00000001U
205 #define PMUD_BATUPD_STA_S 0U
206 #define PMUD_BATUPD_STA_UPD 0x00000001U
207 #define PMUD_BATUPD_STA_NOUPD 0x00000000U
208 
209 //*****************************************************************************
210 //
211 // Register: PMUD_O_TEMP
212 //
213 //*****************************************************************************
214 // Field: [16:8] INT
215 //
216 // Integer part of temperature value (signed)
217 // Total value = INT + FRAC
218 // 2's complement encoding
219 //
220 // 0x100: Min value (-256°C)
221 // 0x1D8: -40°C
222 // 0x1FF: -1°C
223 // 0x00: 0°C
224 // 0x1B: 27°C
225 // 0x55: 85°C
226 // 0xFF: Max value (255°C)
227 #define PMUD_TEMP_INT_W 9U
228 #define PMUD_TEMP_INT_M 0x0001FF00U
229 #define PMUD_TEMP_INT_S 8U
230 
231 // Field: [7:6] FRAC
232 //
233 // Fractional part of temperature value.
234 // Total value = INT + FRAC
235 // The encoding is an extension of the 2's complement encoding.
236 //
237 // 00: 0.0°C
238 // 01: 0.25°C
239 // 10: 0.5°C
240 // 11: 0.75°C
241 //
242 // For example:
243 // 000000001,00 = ( 1+0,00) = 1,00
244 // 000000000,11 = ( 0+0,75) = 0,75
245 // 000000000,10 = ( 0+0,50) = 0,50
246 // 000000000,01 = ( 0+0,25) = 0,25
247 // 000000000,00 = ( 0+0,00) = 0,00
248 // 111111111,11 = (-1+0,75) = -0,25
249 // 111111111,10 = (-1+0,50) = -0,50
250 // 111111111,01 = (-1+0,25) = -0,75
251 // 111111111,00 = (-1+0,00) = -1,00
252 // 111111110,11 = (-2+0,75) = -1,25
253 #define PMUD_TEMP_FRAC_W 2U
254 #define PMUD_TEMP_FRAC_M 0x000000C0U
255 #define PMUD_TEMP_FRAC_S 6U
256 
257 //*****************************************************************************
258 //
259 // Register: PMUD_O_TEMPUPD
260 //
261 //*****************************************************************************
262 // Field: [0] STA
263 //
264 // Temperature update status. Write 1 to clear the status.
265 // ENUMs:
266 // UPD New temperature value present
267 // NOUPD No temperature update since last clear
268 #define PMUD_TEMPUPD_STA 0x00000001U
269 #define PMUD_TEMPUPD_STA_M 0x00000001U
270 #define PMUD_TEMPUPD_STA_S 0U
271 #define PMUD_TEMPUPD_STA_UPD 0x00000001U
272 #define PMUD_TEMPUPD_STA_NOUPD 0x00000000U
273 
274 //*****************************************************************************
275 //
276 // Register: PMUD_O_EVENTMASK
277 //
278 //*****************************************************************************
279 // Field: [5] TEMP_UPDATE_MASK
280 //
281 // 1: EVENT.TEMP_UPDATE contributes to combined event from BATMON
282 // 0: EVENT.TEMP_UPDATE does not contribute to combined event from BATMON
283 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK 0x00000020U
284 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_M 0x00000020U
285 #define PMUD_EVENTMASK_TEMP_UPDATE_MASK_S 5U
286 
287 // Field: [4] BATT_UPDATE_MASK
288 //
289 // 1: EVENT.BATT_UPDATE contributes to combined event from BATMON
290 // 0: EVENT.BATT_UPDATE does not contribute to combined event from BATMON
291 #define PMUD_EVENTMASK_BATT_UPDATE_MASK 0x00000010U
292 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_M 0x00000010U
293 #define PMUD_EVENTMASK_BATT_UPDATE_MASK_S 4U
294 
295 // Field: [3] TEMP_BELOW_LL_MASK
296 //
297 // 1: EVENT.TEMP_BELOW_LL contributes to combined event from BATMON
298 // 0: EVENT.TEMP_BELOW_LL does not contribute to combined event from BATMON
299 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK 0x00000008U
300 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_M 0x00000008U
301 #define PMUD_EVENTMASK_TEMP_BELOW_LL_MASK_S 3U
302 
303 // Field: [2] TEMP_OVER_UL_MASK
304 //
305 // 1: EVENT.TEMP_OVER_UL contributes to combined event from BATMON
306 // 0: EVENT.TEMP_OVER_UL does not contribute to combined event from BATMON
307 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK 0x00000004U
308 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_M 0x00000004U
309 #define PMUD_EVENTMASK_TEMP_OVER_UL_MASK_S 2U
310 
311 // Field: [1] BATT_BELOW_LL_MASK
312 //
313 // 1: EVENT.BATT_BELOW_LL contributes to combined event from BATMON
314 // 0: EVENT.BATT_BELOW_LL does not contribute to combined event from BATMON
315 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK 0x00000002U
316 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_M 0x00000002U
317 #define PMUD_EVENTMASK_BATT_BELOW_LL_MASK_S 1U
318 
319 // Field: [0] BATT_OVER_UL_MASK
320 //
321 // 1: EVENT.BATT_OVER_UL contributes to combined event from BATMON
322 // 0: EVENT.BATT_OVER_UL does not contribute to combined event from BATMON
323 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK 0x00000001U
324 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_M 0x00000001U
325 #define PMUD_EVENTMASK_BATT_OVER_UL_MASK_S 0U
326 
327 //*****************************************************************************
328 //
329 // Register: PMUD_O_EVENT
330 //
331 //*****************************************************************************
332 // Field: [5] TEMP_UPDATE
333 //
334 // Alias to TEMPUPD.STA
335 #define PMUD_EVENT_TEMP_UPDATE 0x00000020U
336 #define PMUD_EVENT_TEMP_UPDATE_M 0x00000020U
337 #define PMUD_EVENT_TEMP_UPDATE_S 5U
338 
339 // Field: [4] BATT_UPDATE
340 //
341 // Alias to BATUPD.STA
342 #define PMUD_EVENT_BATT_UPDATE 0x00000010U
343 #define PMUD_EVENT_BATT_UPDATE_M 0x00000010U
344 #define PMUD_EVENT_BATT_UPDATE_S 4U
345 
346 // Field: [3] TEMP_BELOW_LL
347 //
348 // Read:
349 // 1: Temperature level is below the lower limit set by TEMPLL.
350 // 0: Temperature level is not below the lower limit set by TEMPLL.
351 // Write:
352 // 1: Clears the flag
353 // 0: No change in the flag
354 #define PMUD_EVENT_TEMP_BELOW_LL 0x00000008U
355 #define PMUD_EVENT_TEMP_BELOW_LL_M 0x00000008U
356 #define PMUD_EVENT_TEMP_BELOW_LL_S 3U
357 
358 // Field: [2] TEMP_OVER_UL
359 //
360 // Read:
361 // 1: Temperature level is above the upper limit set by TEMPUL.
362 // 0: Temperature level is not above the upper limit set by TEMPUL.
363 // Write:
364 // 1: Clears the flag
365 // 0: No change in the flag
366 #define PMUD_EVENT_TEMP_OVER_UL 0x00000004U
367 #define PMUD_EVENT_TEMP_OVER_UL_M 0x00000004U
368 #define PMUD_EVENT_TEMP_OVER_UL_S 2U
369 
370 // Field: [1] BATT_BELOW_LL
371 //
372 // Read:
373 // 1: Battery level is below the lower limit set by BATTLL.
374 // 0: Battery level is not below the lower limit set by BATTLL.
375 // Write:
376 // 1: Clears the flag
377 // 0: No change in the flag
378 #define PMUD_EVENT_BATT_BELOW_LL 0x00000002U
379 #define PMUD_EVENT_BATT_BELOW_LL_M 0x00000002U
380 #define PMUD_EVENT_BATT_BELOW_LL_S 1U
381 
382 // Field: [0] BATT_OVER_UL
383 //
384 // Read:
385 // 1: Battery level is above the upper limit set by BATTUL.
386 // 0: Battery level is not above the upper limit set by BATTUL.
387 // Write:
388 // 1: Clears the flag
389 // 0: No change in the flag
390 #define PMUD_EVENT_BATT_OVER_UL 0x00000001U
391 #define PMUD_EVENT_BATT_OVER_UL_M 0x00000001U
392 #define PMUD_EVENT_BATT_OVER_UL_S 0U
393 
394 //*****************************************************************************
395 //
396 // Register: PMUD_O_BATTUL
397 //
398 //*****************************************************************************
399 // Field: [10:8] INT
400 //
401 // Integer part:
402 // Total battery voltage = INT + FRAC (integer and fractional part)
403 //
404 // 0x0: Battery voltage = 0V + fractional part
405 // ...
406 // 0x3: Battery voltage = 3V + fractional part
407 // 0x4: Battery voltage = 4V + fractional part
408 #define PMUD_BATTUL_INT_W 3U
409 #define PMUD_BATTUL_INT_M 0x00000700U
410 #define PMUD_BATTUL_INT_S 8U
411 
412 // Field: [7:0] FRAC
413 //
414 // Fractional part, standard binary fractional encoding.
415 //
416 // 0x00: .0V
417 // ...
418 // 0x20: 1/8 = .125V
419 // 0x40: 1/4 = .25V
420 // 0x80: 1/2 = .5V
421 // ...
422 // 0xA0: 1/2 + 1/8 = .625V
423 // ...
424 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V
425 #define PMUD_BATTUL_FRAC_W 8U
426 #define PMUD_BATTUL_FRAC_M 0x000000FFU
427 #define PMUD_BATTUL_FRAC_S 0U
428 
429 //*****************************************************************************
430 //
431 // Register: PMUD_O_BATTLL
432 //
433 //*****************************************************************************
434 // Field: [10:8] INT
435 //
436 // Integer part:
437 // Total battery voltage = INT + FRAC (integer and fractional part)
438 //
439 // 0x0: Battery voltage = 0V + fractional part
440 // ...
441 // 0x3: Battery voltage = 3V + fractional part
442 // 0x4: Battery voltage = 4V + fractional part
443 #define PMUD_BATTLL_INT_W 3U
444 #define PMUD_BATTLL_INT_M 0x00000700U
445 #define PMUD_BATTLL_INT_S 8U
446 
447 // Field: [7:0] FRAC
448 //
449 // Fractional part, standard binary fractional encoding.
450 //
451 // 0x00: .0V
452 // ...
453 // 0x20: 1/8 = .125V
454 // 0x40: 1/4 = .25V
455 // 0x80: 1/2 = .5V
456 // ...
457 // 0xA0: 1/2 + 1/8 = .625V
458 // ...
459 // 0xFF: 1/2 + 1/4 + 1/8 + ... + 1/256 = 0.99V
460 #define PMUD_BATTLL_FRAC_W 8U
461 #define PMUD_BATTLL_FRAC_M 0x000000FFU
462 #define PMUD_BATTLL_FRAC_S 0U
463 
464 //*****************************************************************************
465 //
466 // Register: PMUD_O_TEMPUL
467 //
468 //*****************************************************************************
469 // Field: [16:8] INT
470 //
471 // Integer part (signed) of temperature upper limit.
472 // Total value = INT + FRAC
473 // 2's complement encoding
474 //
475 // 0x100: Min value (-256°C)
476 // 0x1D8: -40°C
477 // 0x1FF: -1°C
478 // 0x00: 0°C
479 // 0x1B: 27°C
480 // 0x55: 85°C
481 // 0xFF: Max value (255°C)
482 #define PMUD_TEMPUL_INT_W 9U
483 #define PMUD_TEMPUL_INT_M 0x0001FF00U
484 #define PMUD_TEMPUL_INT_S 8U
485 
486 // Field: [7:6] FRAC
487 //
488 // Fractional part of temperature upper limit.
489 // Total value = INT + FRAC
490 // The encoding is an extension of the 2's complement encoding.
491 //
492 // 00: 0.0°C
493 // 01: 0.25°C
494 // 10: 0.5°C
495 // 11: 0.75°C
496 //
497 // For example:
498 // 000000001,00 = ( 1+0,00) = 1,00
499 // 000000000,11 = ( 0+0,75) = 0,75
500 // 000000000,10 = ( 0+0,50) = 0,50
501 // 000000000,01 = ( 0+0,25) = 0,25
502 // 000000000,00 = ( 0+0,00) = 0,00
503 // 111111111,11 = (-1+0,75) = -0,25
504 // 111111111,10 = (-1+0,50) = -0,50
505 // 111111111,01 = (-1+0,25) = -0,75
506 // 111111111,00 = (-1+0,00) = -1,00
507 // 111111110,11 = (-2+0,75) = -1,25
508 #define PMUD_TEMPUL_FRAC_W 2U
509 #define PMUD_TEMPUL_FRAC_M 0x000000C0U
510 #define PMUD_TEMPUL_FRAC_S 6U
511 
512 //*****************************************************************************
513 //
514 // Register: PMUD_O_TEMPLL
515 //
516 //*****************************************************************************
517 // Field: [16:8] INT
518 //
519 // Integer part (signed) of temperature lower limit.
520 // Total value = INT + FRAC
521 // 2's complement encoding
522 //
523 // 0x100: Min value (-256°C)
524 // 0x1D8: -40°C
525 // 0x1FF: -1°C
526 // 0x00: 0°C
527 // 0x1B: 27°C
528 // 0x55: 85°C
529 // 0xFF: Max value (255°C)
530 #define PMUD_TEMPLL_INT_W 9U
531 #define PMUD_TEMPLL_INT_M 0x0001FF00U
532 #define PMUD_TEMPLL_INT_S 8U
533 
534 // Field: [7:6] FRAC
535 //
536 // Fractional part of temperature lower limit.
537 // Total value = INT + FRAC
538 // The encoding is an extension of the 2's complement encoding.
539 //
540 // 00: 0.0°C
541 // 01: 0.25°C
542 // 10: 0.5°C
543 // 11: 0.75°C
544 //
545 // For example:
546 // 000000001,00 = ( 1+0,00) = 1,00
547 // 000000000,11 = ( 0+0,75) = 0,75
548 // 000000000,10 = ( 0+0,50) = 0,50
549 // 000000000,01 = ( 0+0,25) = 0,25
550 // 000000000,00 = ( 0+0,00) = 0,00
551 // 111111111,11 = (-1+0,75) = -0,25
552 // 111111111,10 = (-1+0,50) = -0,50
553 // 111111111,01 = (-1+0,25) = -0,75
554 // 111111111,00 = (-1+0,00) = -1,00
555 // 111111110,11 = (-2+0,75) = -1,25
556 #define PMUD_TEMPLL_FRAC_W 2U
557 #define PMUD_TEMPLL_FRAC_M 0x000000C0U
558 #define PMUD_TEMPLL_FRAC_S 6U
559 
560 //*****************************************************************************
561 //
562 // Register: PMUD_O_PREG0
563 //
564 //*****************************************************************************
565 // Field: [11] LOW_IPEAK_DIS
566 //
567 // Internal. Only to be used through TI provided API.
568 // ENUMs:
569 // SET Internal. Only to be used through TI provided API.
570 // CLR Internal. Only to be used through TI provided API.
571 #define PMUD_PREG0_LOW_IPEAK_DIS 0x00000800U
572 #define PMUD_PREG0_LOW_IPEAK_DIS_M 0x00000800U
573 #define PMUD_PREG0_LOW_IPEAK_DIS_S 11U
574 #define PMUD_PREG0_LOW_IPEAK_DIS_SET 0x00000800U
575 #define PMUD_PREG0_LOW_IPEAK_DIS_CLR 0x00000000U
576 
577 // Field: [10] SOCLDO_ITESTEN
578 //
579 // Internal. Only to be used through TI provided API.
580 // ENUMs:
581 // EN Internal. Only to be used through TI provided API.
582 // DIS Internal. Only to be used through TI provided API.
583 #define PMUD_PREG0_SOCLDO_ITESTEN 0x00000400U
584 #define PMUD_PREG0_SOCLDO_ITESTEN_M 0x00000400U
585 #define PMUD_PREG0_SOCLDO_ITESTEN_S 10U
586 #define PMUD_PREG0_SOCLDO_ITESTEN_EN 0x00000400U
587 #define PMUD_PREG0_SOCLDO_ITESTEN_DIS 0x00000000U
588 
589 // Field: [9:7] SOCLDO_ATBSEL
590 //
591 // Internal. Only to be used through TI provided API.
592 // ENUMs:
593 // VDD_AON Internal. Only to be used through TI provided API.
594 // SOCLDO_VREF_AMP_OUT Internal. Only to be used through TI provided API.
595 // SOCLDO_ITEST Internal. Only to be used through TI provided API.
596 // NC Internal. Only to be used through TI provided API.
597 #define PMUD_PREG0_SOCLDO_ATBSEL_W 3U
598 #define PMUD_PREG0_SOCLDO_ATBSEL_M 0x00000380U
599 #define PMUD_PREG0_SOCLDO_ATBSEL_S 7U
600 #define PMUD_PREG0_SOCLDO_ATBSEL_VDD_AON 0x00000200U
601 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_VREF_AMP_OUT 0x00000100U
602 #define PMUD_PREG0_SOCLDO_ATBSEL_SOCLDO_ITEST 0x00000080U
603 #define PMUD_PREG0_SOCLDO_ATBSEL_NC 0x00000000U
604 
605 // Field: [6:5] UDIGLDO_ATBSEL
606 //
607 // Internal. Only to be used through TI provided API.
608 // ENUMs:
609 // VAL3 Internal. Only to be used through TI provided API.
610 // VAL2 Internal. Only to be used through TI provided API.
611 // VAL1 Internal. Only to be used through TI provided API.
612 // VAL0 Internal. Only to be used through TI provided API.
613 #define PMUD_PREG0_UDIGLDO_ATBSEL_W 2U
614 #define PMUD_PREG0_UDIGLDO_ATBSEL_M 0x00000060U
615 #define PMUD_PREG0_UDIGLDO_ATBSEL_S 5U
616 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL3 0x00000060U
617 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL2 0x00000040U
618 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL1 0x00000020U
619 #define PMUD_PREG0_UDIGLDO_ATBSEL_VAL0 0x00000000U
620 
621 // Field: [4:2] DIGLDO_ATBSEL
622 //
623 // Internal. Only to be used through TI provided API.
624 // ENUMs:
625 // VAL4 Internal. Only to be used through TI provided API.
626 // VAL2 Internal. Only to be used through TI provided API.
627 // VAL1 Internal. Only to be used through TI provided API.
628 // VAL0 Internal. Only to be used through TI provided API.
629 #define PMUD_PREG0_DIGLDO_ATBSEL_W 3U
630 #define PMUD_PREG0_DIGLDO_ATBSEL_M 0x0000001CU
631 #define PMUD_PREG0_DIGLDO_ATBSEL_S 2U
632 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL4 0x00000010U
633 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL2 0x00000008U
634 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL1 0x00000004U
635 #define PMUD_PREG0_DIGLDO_ATBSEL_VAL0 0x00000000U
636 
637 // Field: [1] SPARE
638 //
639 // Internal. Only to be used through TI provided API.
640 #define PMUD_PREG0_SPARE 0x00000002U
641 #define PMUD_PREG0_SPARE_M 0x00000002U
642 #define PMUD_PREG0_SPARE_S 1U
643 
644 // Field: [0] UDIGLDO_EN
645 //
646 // Internal. Only to be used through TI provided API.
647 // ENUMs:
648 // EN Internal. Only to be used through TI provided API.
649 // DIS Internal. Only to be used through TI provided API.
650 #define PMUD_PREG0_UDIGLDO_EN 0x00000001U
651 #define PMUD_PREG0_UDIGLDO_EN_M 0x00000001U
652 #define PMUD_PREG0_UDIGLDO_EN_S 0U
653 #define PMUD_PREG0_UDIGLDO_EN_EN 0x00000001U
654 #define PMUD_PREG0_UDIGLDO_EN_DIS 0x00000000U
655 
656 //*****************************************************************************
657 //
658 // Register: PMUD_O_PREG1
659 //
660 //*****************************************************************************
661 // Field: [19] TEST_DCDC_NMOS
662 //
663 // Internal. Only to be used through TI provided API.
664 // ENUMs:
665 // EN Internal. Only to be used through TI provided API.
666 // DIS Internal. Only to be used through TI provided API.
667 #define PMUD_PREG1_TEST_DCDC_NMOS 0x00080000U
668 #define PMUD_PREG1_TEST_DCDC_NMOS_M 0x00080000U
669 #define PMUD_PREG1_TEST_DCDC_NMOS_S 19U
670 #define PMUD_PREG1_TEST_DCDC_NMOS_EN 0x00080000U
671 #define PMUD_PREG1_TEST_DCDC_NMOS_DIS 0x00000000U
672 
673 // Field: [18] TEST_DCDC_PMOS
674 //
675 // Internal. Only to be used through TI provided API.
676 // ENUMs:
677 // EN Internal. Only to be used through TI provided API.
678 // DIS Internal. Only to be used through TI provided API.
679 #define PMUD_PREG1_TEST_DCDC_PMOS 0x00040000U
680 #define PMUD_PREG1_TEST_DCDC_PMOS_M 0x00040000U
681 #define PMUD_PREG1_TEST_DCDC_PMOS_S 18U
682 #define PMUD_PREG1_TEST_DCDC_PMOS_EN 0x00040000U
683 #define PMUD_PREG1_TEST_DCDC_PMOS_DIS 0x00000000U
684 
685 // Field: [17] DITHER_EN
686 //
687 // Internal. Only to be used through TI provided API.
688 // ENUMs:
689 // EN Internal. Only to be used through TI provided API.
690 // DIS Internal. Only to be used through TI provided API.
691 #define PMUD_PREG1_DITHER_EN 0x00020000U
692 #define PMUD_PREG1_DITHER_EN_M 0x00020000U
693 #define PMUD_PREG1_DITHER_EN_S 17U
694 #define PMUD_PREG1_DITHER_EN_EN 0x00020000U
695 #define PMUD_PREG1_DITHER_EN_DIS 0x00000000U
696 
697 // Field: [16] GLDO_AON
698 //
699 // Internal. Only to be used through TI provided API.
700 // ENUMs:
701 // EN Internal. Only to be used through TI provided API.
702 // DIS Internal. Only to be used through TI provided API.
703 #define PMUD_PREG1_GLDO_AON 0x00010000U
704 #define PMUD_PREG1_GLDO_AON_M 0x00010000U
705 #define PMUD_PREG1_GLDO_AON_S 16U
706 #define PMUD_PREG1_GLDO_AON_EN 0x00010000U
707 #define PMUD_PREG1_GLDO_AON_DIS 0x00000000U
708 
709 // Field: [15] RCHG_BLK_VTRIG_EN
710 //
711 // Internal. Only to be used through TI provided API.
712 // ENUMs:
713 // EN Internal. Only to be used through TI provided API.
714 // DIS Internal. Only to be used through TI provided API.
715 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN 0x00008000U
716 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_M 0x00008000U
717 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_S 15U
718 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_EN 0x00008000U
719 #define PMUD_PREG1_RCHG_BLK_VTRIG_EN_DIS 0x00000000U
720 
721 // Field: [14] RCHG_BLK_ATEST_EN
722 //
723 // Internal. Only to be used through TI provided API.
724 // ENUMs:
725 // EN Internal. Only to be used through TI provided API.
726 // DIS Internal. Only to be used through TI provided API.
727 #define PMUD_PREG1_RCHG_BLK_ATEST_EN 0x00004000U
728 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_M 0x00004000U
729 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_S 14U
730 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_EN 0x00004000U
731 #define PMUD_PREG1_RCHG_BLK_ATEST_EN_DIS 0x00000000U
732 
733 // Field: [13] RCHG_FORCE_SAMP_VREF
734 //
735 // Internal. Only to be used through TI provided API.
736 // ENUMs:
737 // EN Internal. Only to be used through TI provided API.
738 // DIS Internal. Only to be used through TI provided API.
739 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF 0x00002000U
740 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_M 0x00002000U
741 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_S 13U
742 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_EN 0x00002000U
743 #define PMUD_PREG1_RCHG_FORCE_SAMP_VREF_DIS 0x00000000U
744 
745 // Field: [12] RCHG_COMP_CLK_DIS
746 //
747 // Internal. Only to be used through TI provided API.
748 // ENUMs:
749 // DIS Internal. Only to be used through TI provided API.
750 // EN Internal. Only to be used through TI provided API.
751 #define PMUD_PREG1_RCHG_COMP_CLK_DIS 0x00001000U
752 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_M 0x00001000U
753 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_S 12U
754 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_DIS 0x00001000U
755 #define PMUD_PREG1_RCHG_COMP_CLK_DIS_EN 0x00000000U
756 
757 // Field: [7] SPARE
758 //
759 // Internal. Only to be used through TI provided API.
760 #define PMUD_PREG1_SPARE 0x00000080U
761 #define PMUD_PREG1_SPARE_M 0x00000080U
762 #define PMUD_PREG1_SPARE_S 7U
763 
764 // Field: [6] VDDR_ATBSEL
765 //
766 // Internal. Only to be used through TI provided API.
767 // ENUMs:
768 // EN Internal. Only to be used through TI provided API.
769 // DIS Internal. Only to be used through TI provided API.
770 #define PMUD_PREG1_VDDR_ATBSEL 0x00000040U
771 #define PMUD_PREG1_VDDR_ATBSEL_M 0x00000040U
772 #define PMUD_PREG1_VDDR_ATBSEL_S 6U
773 #define PMUD_PREG1_VDDR_ATBSEL_EN 0x00000040U
774 #define PMUD_PREG1_VDDR_ATBSEL_DIS 0x00000000U
775 
776 // Field: [5] GLDO_EA_BIAS_DIS
777 //
778 // Internal. Only to be used through TI provided API.
779 // ENUMs:
780 // OFF Internal. Only to be used through TI provided API.
781 // ON Internal. Only to be used through TI provided API.
782 #define PMUD_PREG1_GLDO_EA_BIAS_DIS 0x00000020U
783 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_M 0x00000020U
784 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_S 5U
785 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_OFF 0x00000020U
786 #define PMUD_PREG1_GLDO_EA_BIAS_DIS_ON 0x00000000U
787 
788 // Field: [4:1] GLDO_ATBSEL
789 //
790 // Internal. Only to be used through TI provided API.
791 // ENUMs:
792 // VDDROK Internal. Only to be used through TI provided API.
793 // IB1U Internal. Only to be used through TI provided API.
794 // PASSGATE Internal. Only to be used through TI provided API.
795 // ERRAMP_OUT Internal. Only to be used through TI provided API.
796 // NC Internal. Only to be used through TI provided API.
797 #define PMUD_PREG1_GLDO_ATBSEL_W 4U
798 #define PMUD_PREG1_GLDO_ATBSEL_M 0x0000001EU
799 #define PMUD_PREG1_GLDO_ATBSEL_S 1U
800 #define PMUD_PREG1_GLDO_ATBSEL_VDDROK 0x00000010U
801 #define PMUD_PREG1_GLDO_ATBSEL_IB1U 0x00000008U
802 #define PMUD_PREG1_GLDO_ATBSEL_PASSGATE 0x00000004U
803 #define PMUD_PREG1_GLDO_ATBSEL_ERRAMP_OUT 0x00000002U
804 #define PMUD_PREG1_GLDO_ATBSEL_NC 0x00000000U
805 
806 //*****************************************************************************
807 //
808 // Register: PMUD_O_PREG2
809 //
810 //*****************************************************************************
811 // Field: [5] RSTNMASK
812 //
813 // Internal. Only to be used through TI provided API.
814 // ENUMs:
815 // BM Internal. Only to be used through TI provided API.
816 // BNM Internal. Only to be used through TI provided API.
817 #define PMUD_PREG2_RSTNMASK 0x00000020U
818 #define PMUD_PREG2_RSTNMASK_M 0x00000020U
819 #define PMUD_PREG2_RSTNMASK_S 5U
820 #define PMUD_PREG2_RSTNMASK_BM 0x00000020U
821 #define PMUD_PREG2_RSTNMASK_BNM 0x00000000U
822 
823 // Field: [4] DCDC_RCHG_ATBSEL
824 //
825 // Internal. Only to be used through TI provided API.
826 // ENUMs:
827 // RCHG_BLK Internal. Only to be used through TI provided API.
828 // DCDC_GLDO Internal. Only to be used through TI provided API.
829 #define PMUD_PREG2_DCDC_RCHG_ATBSEL 0x00000010U
830 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_M 0x00000010U
831 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_S 4U
832 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_RCHG_BLK 0x00000010U
833 #define PMUD_PREG2_DCDC_RCHG_ATBSEL_DCDC_GLDO 0x00000000U
834 
835 // Field: [3:0] PMUREG_ATBSEL
836 //
837 // Internal. Only to be used through TI provided API.
838 // ENUMs:
839 // DCDC_ATEST0_RCHG_ATEST1 Internal. Only to be used through TI provided API.
840 // SOCLDOI_A0 Internal. Only to be used through TI provided API.
841 // RESERVED Internal. Only to be used through TI provided API.
842 // SOCLDOV_A1 Internal. Only to be used through TI provided API.
843 // NC Internal. Only to be used through TI provided API.
844 #define PMUD_PREG2_PMUREG_ATBSEL_W 4U
845 #define PMUD_PREG2_PMUREG_ATBSEL_M 0x0000000FU
846 #define PMUD_PREG2_PMUREG_ATBSEL_S 0U
847 #define PMUD_PREG2_PMUREG_ATBSEL_DCDC_ATEST0_RCHG_ATEST1 0x00000008U
848 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOI_A0 0x00000004U
849 #define PMUD_PREG2_PMUREG_ATBSEL_RESERVED 0x00000002U
850 #define PMUD_PREG2_PMUREG_ATBSEL_SOCLDOV_A1 0x00000001U
851 #define PMUD_PREG2_PMUREG_ATBSEL_NC 0x00000000U
852 
853 //*****************************************************************************
854 //
855 // Register: PMUD_O_DCDCCFG
856 //
857 //*****************************************************************************
858 // Field: [22:16] LM_HIGHTH
859 //
860 // DCDC load meter high threshold value for adaptive IPEAK adjustment. DCDC
861 // load meter output is in percentage scale so the applicable values are 'd1 to
862 // 'd100. Values from 'd101 to 'd127 are invalid and not to be used.
863 #define PMUD_DCDCCFG_LM_HIGHTH_W 7U
864 #define PMUD_DCDCCFG_LM_HIGHTH_M 0x007F0000U
865 #define PMUD_DCDCCFG_LM_HIGHTH_S 16U
866 
867 // Field: [14:8] LM_LOWTH
868 //
869 // DCDC load meter low threshold value for adaptive IPEAK adjustment. DCDC load
870 // meter output is in percentage scale so the applicable values are 'd1 to
871 // 'd100. Values from 'd101 to 'd127 are invalid and not to be used.
872 #define PMUD_DCDCCFG_LM_LOWTH_W 7U
873 #define PMUD_DCDCCFG_LM_LOWTH_M 0x00007F00U
874 #define PMUD_DCDCCFG_LM_LOWTH_S 8U
875 
876 // Field: [4] ADP_IPEAK_EN
877 //
878 // This bit is used to enable adaptive IPEAK adjustment scheme in hardware.
879 // When this bit is set, DCDC IPEAK value is automatically adjusted to suitable
880 // value by sensing the DCDC load meter output for better DCDC operational
881 // efficiency.
882 // ENUMs:
883 // EN Enable
884 // DIS Disable
885 #define PMUD_DCDCCFG_ADP_IPEAK_EN 0x00000010U
886 #define PMUD_DCDCCFG_ADP_IPEAK_EN_M 0x00000010U
887 #define PMUD_DCDCCFG_ADP_IPEAK_EN_S 4U
888 #define PMUD_DCDCCFG_ADP_IPEAK_EN_EN 0x00000010U
889 #define PMUD_DCDCCFG_ADP_IPEAK_EN_DIS 0x00000000U
890 
891 // Field: [0] LMEN
892 //
893 // This bit is used to enable DCDC load meter. Software can obtain DCDC load
894 // meter value from DCDCSTAT regiser and adjust IPEAK setting in SYS0.TDCDC
895 // register accordingly.
896 // ENUMs:
897 // EN Enable
898 // DIS Disable
899 #define PMUD_DCDCCFG_LMEN 0x00000001U
900 #define PMUD_DCDCCFG_LMEN_M 0x00000001U
901 #define PMUD_DCDCCFG_LMEN_S 0U
902 #define PMUD_DCDCCFG_LMEN_EN 0x00000001U
903 #define PMUD_DCDCCFG_LMEN_DIS 0x00000000U
904 
905 //*****************************************************************************
906 //
907 // Register: PMUD_O_DCDCSTAT
908 //
909 //*****************************************************************************
910 // Field: [10:8] IPEAK
911 //
912 // DCDC IPEAK value. This value is same as what is programmed in
913 // SYS0:TMUTE4.IPEAK when adaptive IPEAK adjustment scheme is not enabled, and
914 // it shows current IPEAK value applied by hardware when adaptive IPEAK
915 // adjustment scheme is enabled.
916 // Note: Software can only support IPEAK = 1
917 #define PMUD_DCDCSTAT_IPEAK_W 3U
918 #define PMUD_DCDCSTAT_IPEAK_M 0x00000700U
919 #define PMUD_DCDCSTAT_IPEAK_S 8U
920 
921 // Field: [6:0] LOAD
922 //
923 // This indicates DCDC load meter output value in percentage scale.
924 // Applicable range is 'd1 to 'd100.
925 #define PMUD_DCDCSTAT_LOAD_W 7U
926 #define PMUD_DCDCSTAT_LOAD_M 0x0000007FU
927 #define PMUD_DCDCSTAT_LOAD_S 0U
928 
929 
930 #endif // __PMUD__