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CC23x0R5DriverLibrary
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Go to the source code of this file.
| #define PMCTL_O_DESC 0x00000000U |
| #define PMCTL_O_DESCEX 0x00000004U |
| #define PMCTL_O_SHTDWN 0x00000008U |
| #define PMCTL_O_SLPCTL 0x0000000CU |
| #define PMCTL_O_WUSTA 0x00000010U |
| #define PMCTL_O_VDDRCTL 0x00000014U |
Referenced by PMCTLGetVoltageRegulator(), and PMCTLSetVoltageRegulator().
| #define PMCTL_O_SYSFSET 0x00000020U |
| #define PMCTL_O_SYSFCLR 0x00000024U |
| #define PMCTL_O_SYSFSTA 0x00000028U |
| #define PMCTL_O_RSTCTL 0x0000002CU |
Referenced by PMCTLResetSystem().
| #define PMCTL_O_RSTSTA 0x00000030U |
Referenced by PMCTLGetResetReason().
| #define PMCTL_O_BOOTSTA 0x00000034U |
| #define PMCTL_O_AONRSTA1 0x0000003CU |
| #define PMCTL_O_AONRSET1 0x00000040U |
| #define PMCTL_O_AONRCLR1 0x00000044U |
| #define PMCTL_O_ETPP 0x00000064U |
| #define PMCTL_O_RETCFG0 0x0000007CU |
| #define PMCTL_O_RETCFG1 0x00000080U |
| #define PMCTL_O_RETCFG2 0x00000084U |
| #define PMCTL_O_RETCFG3 0x00000088U |
| #define PMCTL_O_RETCFG4 0x0000008CU |
| #define PMCTL_O_RETCFG5 0x00000090U |
| #define PMCTL_O_RETCFG6 0x00000094U |
| #define PMCTL_O_RETCFG7 0x00000098U |
| #define PMCTL_DESC_MODID_W 16U |
| #define PMCTL_DESC_MODID_M 0xFFFF0000U |
| #define PMCTL_DESC_MODID_S 16U |
| #define PMCTL_DESC_STDIPOFF_W 4U |
| #define PMCTL_DESC_STDIPOFF_M 0x0000F000U |
| #define PMCTL_DESC_STDIPOFF_S 12U |
| #define PMCTL_DESC_INSTIDX_W 4U |
| #define PMCTL_DESC_INSTIDX_M 0x00000F00U |
| #define PMCTL_DESC_INSTIDX_S 8U |
| #define PMCTL_DESC_MAJREV_W 4U |
| #define PMCTL_DESC_MAJREV_M 0x000000F0U |
| #define PMCTL_DESC_MAJREV_S 4U |
| #define PMCTL_DESC_MINREV_W 4U |
| #define PMCTL_DESC_MINREV_M 0x0000000FU |
| #define PMCTL_DESC_MINREV_S 0U |
| #define PMCTL_DESCEX_FLASHSZ_W 2U |
| #define PMCTL_DESCEX_FLASHSZ_M 0xC0000000U |
| #define PMCTL_DESCEX_FLASHSZ_S 30U |
| #define PMCTL_DESCEX_FLASHSZ_SZ3 0xC0000000U |
| #define PMCTL_DESCEX_FLASHSZ_SZ2 0x80000000U |
| #define PMCTL_DESCEX_FLASHSZ_SZ1 0x40000000U |
| #define PMCTL_DESCEX_FLASHSZ_SZ0 0x00000000U |
| #define PMCTL_DESCEX_SRAMSZ_W 2U |
| #define PMCTL_DESCEX_SRAMSZ_M 0x30000000U |
| #define PMCTL_DESCEX_SRAMSZ_S 28U |
| #define PMCTL_DESCEX_SRAMSZ_SZ3 0x30000000U |
| #define PMCTL_DESCEX_SRAMSZ_SZ2 0x20000000U |
| #define PMCTL_DESCEX_SRAMSZ_SZ1 0x10000000U |
| #define PMCTL_DESCEX_SRAMSZ_SZ0 0x00000000U |
| #define PMCTL_DESCEX_TSD 0x08000000U |
| #define PMCTL_DESCEX_TSD_M 0x08000000U |
| #define PMCTL_DESCEX_TSD_S 27U |
| #define PMCTL_DESCEX_TSD_IP_AVAIL 0x08000000U |
| #define PMCTL_DESCEX_TSD_IP_UNAVAIL 0x00000000U |
| #define PMCTL_DESCEX_LPCMP 0x04000000U |
| #define PMCTL_DESCEX_LPCMP_M 0x04000000U |
| #define PMCTL_DESCEX_LPCMP_S 26U |
| #define PMCTL_DESCEX_LPCMP_IP_AVAIL 0x04000000U |
| #define PMCTL_DESCEX_LPCMP_IP_UNAVAIL 0x00000000U |
| #define PMCTL_SHTDWN_KEY_W 16U |
| #define PMCTL_SHTDWN_KEY_M 0x0000FFFFU |
| #define PMCTL_SHTDWN_KEY_S 0U |
| #define PMCTL_SHTDWN_KEY_VALID 0x0000A5A5U |
| #define PMCTL_SLPCTL_SLPN 0x00000001U |
| #define PMCTL_SLPCTL_SLPN_M 0x00000001U |
| #define PMCTL_SLPCTL_SLPN_S 0U |
| #define PMCTL_SLPCTL_SLPN_DIS 0x00000001U |
| #define PMCTL_SLPCTL_SLPN_EN 0x00000000U |
| #define PMCTL_WUSTA_SRC_W 2U |
| #define PMCTL_WUSTA_SRC_M 0x00000003U |
| #define PMCTL_WUSTA_SRC_S 0U |
| #define PMCTL_WUSTA_SRC_STBY 0x00000002U |
| #define PMCTL_WUSTA_SRC_RST_SHTDWN 0x00000001U |
| #define PMCTL_VDDRCTL_STBY 0x00000002U |
| #define PMCTL_VDDRCTL_STBY_M 0x00000002U |
| #define PMCTL_VDDRCTL_STBY_S 1U |
| #define PMCTL_VDDRCTL_STBY_PSUEDO 0x00000002U |
| #define PMCTL_VDDRCTL_STBY_NORMAL 0x00000000U |
| #define PMCTL_VDDRCTL_SELECT 0x00000001U |
| #define PMCTL_VDDRCTL_SELECT_M 0x00000001U |
Referenced by PMCTLGetVoltageRegulator(), and PMCTLSetVoltageRegulator().
| #define PMCTL_VDDRCTL_SELECT_S 0U |
| #define PMCTL_VDDRCTL_SELECT_DCDC 0x00000001U |
| #define PMCTL_VDDRCTL_SELECT_GLDO 0x00000000U |
| #define PMCTL_SYSFSET_FLAG2 0x00000004U |
| #define PMCTL_SYSFSET_FLAG2_M 0x00000004U |
| #define PMCTL_SYSFSET_FLAG2_S 2U |
| #define PMCTL_SYSFSET_FLAG2_SET 0x00000004U |
| #define PMCTL_SYSFSET_FLAG2_NOEFF 0x00000000U |
| #define PMCTL_SYSFSET_FLAG1 0x00000002U |
| #define PMCTL_SYSFSET_FLAG1_M 0x00000002U |
| #define PMCTL_SYSFSET_FLAG1_S 1U |
| #define PMCTL_SYSFSET_FLAG1_SET 0x00000002U |
| #define PMCTL_SYSFSET_FLAG1_NOEFF 0x00000000U |
| #define PMCTL_SYSFSET_FLAG0 0x00000001U |
| #define PMCTL_SYSFSET_FLAG0_M 0x00000001U |
| #define PMCTL_SYSFSET_FLAG0_S 0U |
| #define PMCTL_SYSFSET_FLAG0_SET 0x00000001U |
| #define PMCTL_SYSFSET_FLAG0_NOEFF 0x00000000U |
| #define PMCTL_SYSFCLR_FLAG2 0x00000004U |
| #define PMCTL_SYSFCLR_FLAG2_M 0x00000004U |
| #define PMCTL_SYSFCLR_FLAG2_S 2U |
| #define PMCTL_SYSFCLR_FLAG2_CLR 0x00000004U |
| #define PMCTL_SYSFCLR_FLAG2_NOEFF 0x00000000U |
| #define PMCTL_SYSFCLR_FLAG1 0x00000002U |
| #define PMCTL_SYSFCLR_FLAG1_M 0x00000002U |
| #define PMCTL_SYSFCLR_FLAG1_S 1U |
| #define PMCTL_SYSFCLR_FLAG1_CLR 0x00000002U |
| #define PMCTL_SYSFCLR_FLAG1_NOEFF 0x00000000U |
| #define PMCTL_SYSFCLR_FLAG0 0x00000001U |
| #define PMCTL_SYSFCLR_FLAG0_M 0x00000001U |
| #define PMCTL_SYSFCLR_FLAG0_S 0U |
| #define PMCTL_SYSFCLR_FLAG0_CLR 0x00000001U |
| #define PMCTL_SYSFCLR_FLAG0_NOEFF 0x00000000U |
| #define PMCTL_SYSFSTA_FLAG2 0x00000004U |
| #define PMCTL_SYSFSTA_FLAG2_M 0x00000004U |
| #define PMCTL_SYSFSTA_FLAG2_S 2U |
| #define PMCTL_SYSFSTA_FLAG2_VAL1 0x00000004U |
| #define PMCTL_SYSFSTA_FLAG2_VAL0 0x00000000U |
| #define PMCTL_SYSFSTA_FLAG1 0x00000002U |
| #define PMCTL_SYSFSTA_FLAG1_M 0x00000002U |
| #define PMCTL_SYSFSTA_FLAG1_S 1U |
| #define PMCTL_SYSFSTA_FLAG1_VAL1 0x00000002U |
| #define PMCTL_SYSFSTA_FLAG0 0x00000001U |
| #define PMCTL_SYSFSTA_FLAG0_M 0x00000001U |
| #define PMCTL_SYSFSTA_FLAG0_S 0U |
| #define PMCTL_SYSFSTA_FLAG0_VAL1 0x00000001U |
| #define PMCTL_SYSFSTA_FLAG0_VAL0 0x00000000U |
| #define PMCTL_RSTCTL_LFLOSS 0x00000004U |
| #define PMCTL_RSTCTL_LFLOSS_M 0x00000004U |
| #define PMCTL_RSTCTL_LFLOSS_S 2U |
| #define PMCTL_RSTCTL_LFLOSS_ARMED 0x00000004U |
| #define PMCTL_RSTCTL_LFLOSS_DISARMED 0x00000000U |
| #define PMCTL_RSTCTL_TSDEN 0x00000002U |
| #define PMCTL_RSTCTL_TSDEN_M 0x00000002U |
| #define PMCTL_RSTCTL_TSDEN_S 1U |
| #define PMCTL_RSTCTL_TSDEN_EN 0x00000002U |
| #define PMCTL_RSTCTL_TSDEN_NOEFF 0x00000000U |
| #define PMCTL_RSTCTL_SYSRST 0x00000001U |
| #define PMCTL_RSTCTL_SYSRST_M 0x00000001U |
| #define PMCTL_RSTCTL_SYSRST_S 0U |
| #define PMCTL_RSTCTL_SYSRST_SET 0x00000001U |
Referenced by PMCTLResetSystem().
| #define PMCTL_RSTCTL_SYSRST_NOEFF 0x00000000U |
| #define PMCTL_RSTSTA_SDDET 0x00020000U |
| #define PMCTL_RSTSTA_SDDET_M 0x00020000U |
| #define PMCTL_RSTSTA_SDDET_S 17U |
| #define PMCTL_RSTSTA_SDDET_TRIG 0x00020000U |
| #define PMCTL_RSTSTA_SDDET_NO_TRIG 0x00000000U |
| #define PMCTL_RSTSTA_IOWUSD 0x00010000U |
| #define PMCTL_RSTSTA_IOWUSD_M 0x00010000U |
| #define PMCTL_RSTSTA_IOWUSD_S 16U |
| #define PMCTL_RSTSTA_IOWUSD_TRIG 0x00010000U |
| #define PMCTL_RSTSTA_IOWUSD_NO_TRIG 0x00000000U |
| #define PMCTL_RSTSTA_SYSSRC_W 4U |
| #define PMCTL_RSTSTA_SYSSRC_M 0x000000F0U |
| #define PMCTL_RSTSTA_SYSSRC_S 4U |
| #define PMCTL_RSTSTA_SYSSRC_DERREV 0x000000F0U |
| #define PMCTL_RSTSTA_SYSSRC_AERREV 0x000000E0U |
| #define PMCTL_RSTSTA_SYSSRC_AFSMEV 0x00000060U |
| #define PMCTL_RSTSTA_SYSSRC_SWDRSTEV 0x00000050U |
| #define PMCTL_RSTSTA_SYSSRC_SYSRSTEV 0x00000040U |
| #define PMCTL_RSTSTA_SYSSRC_WDTEV 0x00000030U |
| #define PMCTL_RSTSTA_SYSSRC_LOCKUPEV 0x00000020U |
| #define PMCTL_RSTSTA_SYSSRC_CPURSTEV 0x00000010U |
| #define PMCTL_RSTSTA_SYSSRC_LFLOSSEV 0x00000000U |
| #define PMCTL_RSTSTA_TSDEV 0x00000008U |
| #define PMCTL_RSTSTA_TSDEV_M 0x00000008U |
| #define PMCTL_RSTSTA_TSDEV_S 3U |
| #define PMCTL_RSTSTA_TSDEV_TRIG 0x00000008U |
| #define PMCTL_RSTSTA_TSDEV_NO_TRIG 0x00000000U |
| #define PMCTL_RSTSTA_RESETSRC_W 3U |
| #define PMCTL_RSTSTA_RESETSRC_M 0x00000007U |
| #define PMCTL_RSTSTA_RESETSRC_S 0U |
| #define PMCTL_RSTSTA_RESETSRC_SYSRESET 0x00000006U |
| #define PMCTL_RSTSTA_RESETSRC_VDDRLOSS 0x00000004U |
| #define PMCTL_RSTSTA_RESETSRC_VDDSLOSS 0x00000002U |
| #define PMCTL_RSTSTA_RESETSRC_PINRESET 0x00000001U |
| #define PMCTL_RSTSTA_RESETSRC_PWRON 0x00000000U |
| #define PMCTL_BOOTSTA_FLAG_W 8U |
| #define PMCTL_BOOTSTA_FLAG_M 0x000000FFU |
| #define PMCTL_BOOTSTA_FLAG_S 0U |
| #define PMCTL_BOOTSTA_FLAG_APP_FAULT_HANDLER 0x000000FFU |
| #define PMCTL_BOOTSTA_FLAG_APP_FAIL_APPTRANSFER 0x000000FEU |
| #define PMCTL_BOOTSTA_FLAG_APP_FAIL_NOAPP 0x000000FDU |
| #define PMCTL_BOOTSTA_FLAG_APP_WAITLOOP_DBGPROBE 0x000000C1U |
| #define PMCTL_BOOTSTA_FLAG_MODE_APP 0x000000C0U |
| #define PMCTL_BOOTSTA_FLAG_BLDR_FAULT_HANDLER 0x000000BFU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_APPTRANSFER 0x000000BEU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_FAIL_EXECUTION_CONTEXT 0x000000BDU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_CMD_PROCESSING 0x000000BCU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_CMD_IDLE 0x000000BBU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_STARTED 0x000000BAU |
| #define PMCTL_BOOTSTA_FLAG_BLDR_WAITLOOP_DBGPROBE 0x00000081U |
| #define PMCTL_BOOTSTA_FLAG_MODE_BLDR 0x00000080U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_FAULT_HANDLER 0x0000003FU |
| #define PMCTL_BOOTSTA_FLAG_BOOT_FAIL_SRAM_REPAIR 0x0000003EU |
| #define PMCTL_BOOTSTA_FLAG_BOOT_WAITLOOP_DBGPROBE 0x00000038U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_EXITED_SACI 0x00000037U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_WAIT_SWD_DISCONNECT 0x00000036U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_ENTERED_SACI 0x00000020U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_GENERAL_TRIMS 0x00000003U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_SRAM_REP_DONE 0x00000002U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_COLD_BOOT 0x00000001U |
| #define PMCTL_BOOTSTA_FLAG_BOOT_RESET 0x00000000U |
| #define PMCTL_AONRSTA1_FLAG_W 18U |
| #define PMCTL_AONRSTA1_FLAG_M 0x0003FFFFU |
| #define PMCTL_AONRSTA1_FLAG_S 0U |
| #define PMCTL_AONRSET1_FLAG_W 18U |
| #define PMCTL_AONRSET1_FLAG_M 0x0003FFFFU |
| #define PMCTL_AONRSET1_FLAG_S 0U |
| #define PMCTL_AONRSET1_FLAG_ALL_SET 0x0003FFFFU |
| #define PMCTL_AONRSET1_FLAG_NOEFF 0x00000000U |
| #define PMCTL_AONRCLR1_FLAG_W 18U |
| #define PMCTL_AONRCLR1_FLAG_M 0x0003FFFFU |
| #define PMCTL_AONRCLR1_FLAG_S 0U |
| #define PMCTL_AONRCLR1_FLAG_ALL_CLR 0x0003FFFFU |
| #define PMCTL_AONRCLR1_FLAG_NOEFF 0x00000000U |
| #define PMCTL_RETCFG0_VAL 0x00000001U |
| #define PMCTL_RETCFG0_VAL_M 0x00000001U |
| #define PMCTL_RETCFG0_VAL_S 0U |
| #define PMCTL_RETCFG1_VAL 0x00000001U |
| #define PMCTL_RETCFG1_VAL_M 0x00000001U |
| #define PMCTL_RETCFG1_VAL_S 0U |
| #define PMCTL_RETCFG2_VAL_W 3U |
| #define PMCTL_RETCFG2_VAL_M 0x00000007U |
| #define PMCTL_RETCFG2_VAL_S 0U |