Go to the source code of this file.
§ NVIC_O_ISER
| #define NVIC_O_ISER 0x00000100U |
§ NVIC_O_ICER
| #define NVIC_O_ICER 0x00000180U |
§ NVIC_O_ISPR
| #define NVIC_O_ISPR 0x00000200U |
§ NVIC_O_ICPR
| #define NVIC_O_ICPR 0x00000280U |
§ NVIC_O_IPR0
| #define NVIC_O_IPR0 0x00000400U |
§ NVIC_O_IPR1
| #define NVIC_O_IPR1 0x00000404U |
§ NVIC_O_IPR2
| #define NVIC_O_IPR2 0x00000408U |
§ NVIC_O_IPR3
| #define NVIC_O_IPR3 0x0000040CU |
§ NVIC_O_IPR4
| #define NVIC_O_IPR4 0x00000410U |
§ NVIC_O_IPR5
| #define NVIC_O_IPR5 0x00000414U |
§ NVIC_O_IPR6
| #define NVIC_O_IPR6 0x00000418U |
§ NVIC_O_IPR7
| #define NVIC_O_IPR7 0x0000041CU |
§ NVIC_ISER_SETENA_W
| #define NVIC_ISER_SETENA_W 32U |
§ NVIC_ISER_SETENA_M
| #define NVIC_ISER_SETENA_M 0xFFFFFFFFU |
§ NVIC_ISER_SETENA_S
| #define NVIC_ISER_SETENA_S 0U |
§ NVIC_ICER_CLRENA_W
| #define NVIC_ICER_CLRENA_W 32U |
§ NVIC_ICER_CLRENA_M
| #define NVIC_ICER_CLRENA_M 0xFFFFFFFFU |
§ NVIC_ICER_CLRENA_S
| #define NVIC_ICER_CLRENA_S 0U |
§ NVIC_ISPR_SETPEND_W
| #define NVIC_ISPR_SETPEND_W 32U |
§ NVIC_ISPR_SETPEND_M
| #define NVIC_ISPR_SETPEND_M 0xFFFFFFFFU |
§ NVIC_ISPR_SETPEND_S
| #define NVIC_ISPR_SETPEND_S 0U |
§ NVIC_ICPR_CLRPEND_W
| #define NVIC_ICPR_CLRPEND_W 32U |
§ NVIC_ICPR_CLRPEND_M
| #define NVIC_ICPR_CLRPEND_M 0xFFFFFFFFU |
§ NVIC_ICPR_CLRPEND_S
| #define NVIC_ICPR_CLRPEND_S 0U |
§ NVIC_IPR0_IP_3_W
| #define NVIC_IPR0_IP_3_W 2U |
§ NVIC_IPR0_IP_3_M
| #define NVIC_IPR0_IP_3_M 0xC0000000U |
§ NVIC_IPR0_IP_3_S
| #define NVIC_IPR0_IP_3_S 30U |
§ NVIC_IPR0_IP_2_W
| #define NVIC_IPR0_IP_2_W 2U |
§ NVIC_IPR0_IP_2_M
| #define NVIC_IPR0_IP_2_M 0x00C00000U |
§ NVIC_IPR0_IP_2_S
| #define NVIC_IPR0_IP_2_S 22U |
§ NVIC_IPR0_IP_1_W
| #define NVIC_IPR0_IP_1_W 2U |
§ NVIC_IPR0_IP_1_M
| #define NVIC_IPR0_IP_1_M 0x0000C000U |
§ NVIC_IPR0_IP_1_S
| #define NVIC_IPR0_IP_1_S 14U |
§ NVIC_IPR0_IP_0_W
| #define NVIC_IPR0_IP_0_W 2U |
§ NVIC_IPR0_IP_0_M
| #define NVIC_IPR0_IP_0_M 0x000000C0U |
§ NVIC_IPR0_IP_0_S
| #define NVIC_IPR0_IP_0_S 6U |
§ NVIC_IPR1_IP_7_W
| #define NVIC_IPR1_IP_7_W 2U |
§ NVIC_IPR1_IP_7_M
| #define NVIC_IPR1_IP_7_M 0xC0000000U |
§ NVIC_IPR1_IP_7_S
| #define NVIC_IPR1_IP_7_S 30U |
§ NVIC_IPR1_IP_6_W
| #define NVIC_IPR1_IP_6_W 2U |
§ NVIC_IPR1_IP_6_M
| #define NVIC_IPR1_IP_6_M 0x00C00000U |
§ NVIC_IPR1_IP_6_S
| #define NVIC_IPR1_IP_6_S 22U |
§ NVIC_IPR1_IP_5_W
| #define NVIC_IPR1_IP_5_W 2U |
§ NVIC_IPR1_IP_5_M
| #define NVIC_IPR1_IP_5_M 0x0000C000U |
§ NVIC_IPR1_IP_5_S
| #define NVIC_IPR1_IP_5_S 14U |
§ NVIC_IPR1_IP_4_W
| #define NVIC_IPR1_IP_4_W 2U |
§ NVIC_IPR1_IP_4_M
| #define NVIC_IPR1_IP_4_M 0x000000C0U |
§ NVIC_IPR1_IP_4_S
| #define NVIC_IPR1_IP_4_S 6U |
§ NVIC_IPR2_IP_11_W
| #define NVIC_IPR2_IP_11_W 2U |
§ NVIC_IPR2_IP_11_M
| #define NVIC_IPR2_IP_11_M 0xC0000000U |
§ NVIC_IPR2_IP_11_S
| #define NVIC_IPR2_IP_11_S 30U |
§ NVIC_IPR2_IP_10_W
| #define NVIC_IPR2_IP_10_W 2U |
§ NVIC_IPR2_IP_10_M
| #define NVIC_IPR2_IP_10_M 0x00C00000U |
§ NVIC_IPR2_IP_10_S
| #define NVIC_IPR2_IP_10_S 22U |
§ NVIC_IPR2_IP_9_W
| #define NVIC_IPR2_IP_9_W 2U |
§ NVIC_IPR2_IP_9_M
| #define NVIC_IPR2_IP_9_M 0x0000C000U |
§ NVIC_IPR2_IP_9_S
| #define NVIC_IPR2_IP_9_S 14U |
§ NVIC_IPR2_IP_8_W
| #define NVIC_IPR2_IP_8_W 2U |
§ NVIC_IPR2_IP_8_M
| #define NVIC_IPR2_IP_8_M 0x000000C0U |
§ NVIC_IPR2_IP_8_S
| #define NVIC_IPR2_IP_8_S 6U |
§ NVIC_IPR3_IP_15_W
| #define NVIC_IPR3_IP_15_W 2U |
§ NVIC_IPR3_IP_15_M
| #define NVIC_IPR3_IP_15_M 0xC0000000U |
§ NVIC_IPR3_IP_15_S
| #define NVIC_IPR3_IP_15_S 30U |
§ NVIC_IPR3_IP_14_W
| #define NVIC_IPR3_IP_14_W 2U |
§ NVIC_IPR3_IP_14_M
| #define NVIC_IPR3_IP_14_M 0x00C00000U |
§ NVIC_IPR3_IP_14_S
| #define NVIC_IPR3_IP_14_S 22U |
§ NVIC_IPR3_IP_13_W
| #define NVIC_IPR3_IP_13_W 2U |
§ NVIC_IPR3_IP_13_M
| #define NVIC_IPR3_IP_13_M 0x0000C000U |
§ NVIC_IPR3_IP_13_S
| #define NVIC_IPR3_IP_13_S 14U |
§ NVIC_IPR3_IP_12_W
| #define NVIC_IPR3_IP_12_W 2U |
§ NVIC_IPR3_IP_12_M
| #define NVIC_IPR3_IP_12_M 0x000000C0U |
§ NVIC_IPR3_IP_12_S
| #define NVIC_IPR3_IP_12_S 6U |
§ NVIC_IPR4_IP_19_W
| #define NVIC_IPR4_IP_19_W 2U |
§ NVIC_IPR4_IP_19_M
| #define NVIC_IPR4_IP_19_M 0xC0000000U |
§ NVIC_IPR4_IP_19_S
| #define NVIC_IPR4_IP_19_S 30U |
§ NVIC_IPR4_IP_18_W
| #define NVIC_IPR4_IP_18_W 2U |
§ NVIC_IPR4_IP_18_M
| #define NVIC_IPR4_IP_18_M 0x00C00000U |
§ NVIC_IPR4_IP_18_S
| #define NVIC_IPR4_IP_18_S 22U |
§ NVIC_IPR4_IP_17_W
| #define NVIC_IPR4_IP_17_W 2U |
§ NVIC_IPR4_IP_17_M
| #define NVIC_IPR4_IP_17_M 0x0000C000U |
§ NVIC_IPR4_IP_17_S
| #define NVIC_IPR4_IP_17_S 14U |
§ NVIC_IPR4_IP_16_W
| #define NVIC_IPR4_IP_16_W 2U |
§ NVIC_IPR4_IP_16_M
| #define NVIC_IPR4_IP_16_M 0x000000C0U |
§ NVIC_IPR4_IP_16_S
| #define NVIC_IPR4_IP_16_S 6U |
§ NVIC_IPR5_IP_23_W
| #define NVIC_IPR5_IP_23_W 2U |
§ NVIC_IPR5_IP_23_M
| #define NVIC_IPR5_IP_23_M 0xC0000000U |
§ NVIC_IPR5_IP_23_S
| #define NVIC_IPR5_IP_23_S 30U |
§ NVIC_IPR5_IP_22_W
| #define NVIC_IPR5_IP_22_W 2U |
§ NVIC_IPR5_IP_22_M
| #define NVIC_IPR5_IP_22_M 0x00C00000U |
§ NVIC_IPR5_IP_22_S
| #define NVIC_IPR5_IP_22_S 22U |
§ NVIC_IPR5_IP_21_W
| #define NVIC_IPR5_IP_21_W 2U |
§ NVIC_IPR5_IP_21_M
| #define NVIC_IPR5_IP_21_M 0x0000C000U |
§ NVIC_IPR5_IP_21_S
| #define NVIC_IPR5_IP_21_S 14U |
§ NVIC_IPR5_IP_20_W
| #define NVIC_IPR5_IP_20_W 2U |
§ NVIC_IPR5_IP_20_M
| #define NVIC_IPR5_IP_20_M 0x000000C0U |
§ NVIC_IPR5_IP_20_S
| #define NVIC_IPR5_IP_20_S 6U |
§ NVIC_IPR6_IP_27_W
| #define NVIC_IPR6_IP_27_W 2U |
§ NVIC_IPR6_IP_27_M
| #define NVIC_IPR6_IP_27_M 0xC0000000U |
§ NVIC_IPR6_IP_27_S
| #define NVIC_IPR6_IP_27_S 30U |
§ NVIC_IPR6_IP_26_W
| #define NVIC_IPR6_IP_26_W 2U |
§ NVIC_IPR6_IP_26_M
| #define NVIC_IPR6_IP_26_M 0x00C00000U |
§ NVIC_IPR6_IP_26_S
| #define NVIC_IPR6_IP_26_S 22U |
§ NVIC_IPR6_IP_25_W
| #define NVIC_IPR6_IP_25_W 2U |
§ NVIC_IPR6_IP_25_M
| #define NVIC_IPR6_IP_25_M 0x0000C000U |
§ NVIC_IPR6_IP_25_S
| #define NVIC_IPR6_IP_25_S 14U |
§ NVIC_IPR6_IP_24_W
| #define NVIC_IPR6_IP_24_W 2U |
§ NVIC_IPR6_IP_24_M
| #define NVIC_IPR6_IP_24_M 0x000000C0U |
§ NVIC_IPR6_IP_24_S
| #define NVIC_IPR6_IP_24_S 6U |
§ NVIC_IPR7_IP_31_W
| #define NVIC_IPR7_IP_31_W 2U |
§ NVIC_IPR7_IP_31_M
| #define NVIC_IPR7_IP_31_M 0xC0000000U |
§ NVIC_IPR7_IP_31_S
| #define NVIC_IPR7_IP_31_S 30U |
§ NVIC_IPR7_IP_30_W
| #define NVIC_IPR7_IP_30_W 2U |
§ NVIC_IPR7_IP_30_M
| #define NVIC_IPR7_IP_30_M 0x00C00000U |
§ NVIC_IPR7_IP_30_S
| #define NVIC_IPR7_IP_30_S 22U |
§ NVIC_IPR7_IP_29_W
| #define NVIC_IPR7_IP_29_W 2U |
§ NVIC_IPR7_IP_29_M
| #define NVIC_IPR7_IP_29_M 0x0000C000U |
§ NVIC_IPR7_IP_29_S
| #define NVIC_IPR7_IP_29_S 14U |
§ NVIC_IPR7_IP_28_W
| #define NVIC_IPR7_IP_28_W 2U |
§ NVIC_IPR7_IP_28_M
| #define NVIC_IPR7_IP_28_M 0x000000C0U |
§ NVIC_IPR7_IP_28_S
| #define NVIC_IPR7_IP_28_S 6U |