CC23x0R5DriverLibrary
Macros
hw_memmap.h File Reference
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Macros

#define FLASH_MAIN_BASE   0x00000000
 
#define FLASH_MAIN_SIZE   0x80000
 
#define ROM_BASE   0x0F000000
 
#define ROM_SIZE   0x3000
 
#define SRAM_BASE   0x20000000
 
#define SRAM_SIZE   0x9000
 
#define PMCTL_BASE   0x40000000
 
#define CKMD_BASE   0x40001000
 
#define RTC_BASE   0x40002000
 
#define IOC_BASE   0x40003000
 
#define SYS0_BASE   0x40004000
 
#define EVTULL_BASE   0x40005000
 
#define PMUD_BASE   0x40006000
 
#define DBGSS_BASE   0x4000F000
 
#define CLKCTL_BASE   0x40020000
 
#define FLASH_BASE   0x40021000
 
#define SYSTIM_BASE   0x40022000
 
#define GPIO_BASE   0x40023000
 
#define VIMS_BASE   0x40024000
 
#define EVTSVT_BASE   0x40025000
 
#define DMA_BASE   0x40026000
 
#define SPI0_BASE   0x40030000
 
#define UART0_BASE   0x40034000
 
#define I2C0_BASE   0x40038000
 
#define ADC_BASE   0x40050000
 
#define LGPT0_BASE   0x40060000
 
#define LGPT1_BASE   0x40061000
 
#define LGPT2_BASE   0x40062000
 
#define LGPT3_BASE   0x40063000
 
#define LRFDDBELL_BASE   0x40080000
 
#define LRFDPBE_BASE   0x40081000
 
#define LRFDPBE32_BASE   0x40081400
 
#define LRFDTXF_BASE   0x40081800
 
#define LRFDRXF_BASE   0x40081C00
 
#define LRFDMDM_BASE   0x40082000
 
#define LRFDMDM32_BASE   0x40082400
 
#define LRFDRFE_BASE   0x40083000
 
#define LRFDRFE32_BASE   0x40083400
 
#define LRFDTRC_BASE   0x40084000
 
#define LRFDS2R_BASE   0x40085000
 
#define LRFD_PBERAM_BASE   0x40090000
 
#define LRFD_PBERAM_SIZE   0x1000
 
#define LRFD_BUFRAM_BASE   0x40092000
 
#define LRFD_BUFRAM_SIZE   0x600
 
#define LRFD_MCERAM_BASE   0x40094000
 
#define LRFD_MCERAM_SIZE   0x1000
 
#define LRFD_RFERAM_BASE   0x40096000
 
#define LRFD_RFERAM_SIZE   0x1000
 
#define LRFD_S2RRAM_BASE   0x40098000
 
#define LRFD_S2RRAM_SIZE   0x1000
 
#define AES_BASE   0x400C0000
 
#define FCFG_BASE   0x4E000000
 
#define FCFG_SIZE   0x400
 
#define CCFG_BASE   0x4E020000
 
#define CCFG_SIZE   0x800
 
#define BPU_BASE   0xE0002000
 
#define NVIC_BASE   0xE000E000
 
#define SYSTICK_BASE   0xE000E010
 
#define SCB_BASE   0xE000ED00
 
#define DCB_BASE   0xE000ED30
 
#define SCSCS_BASE   0xE000EFC0
 
#define CPU_ROM_TABLE_BASE   0xE00FF000
 

Macro Definition Documentation

§ FLASH_MAIN_BASE

#define FLASH_MAIN_BASE   0x00000000

§ FLASH_MAIN_SIZE

#define FLASH_MAIN_SIZE   0x80000

Referenced by FlashGetSize().

§ ROM_BASE

#define ROM_BASE   0x0F000000

§ ROM_SIZE

#define ROM_SIZE   0x3000

§ SRAM_BASE

#define SRAM_BASE   0x20000000

Referenced by uDMASetControlBase().

§ SRAM_SIZE

#define SRAM_SIZE   0x9000

§ PMCTL_BASE

#define PMCTL_BASE   0x40000000

Referenced by PMCTLGetResetReason(), PMCTLGetVoltageRegulator(), PMCTLResetSystem(), and PMCTLSetVoltageRegulator().

§ CKMD_BASE

#define CKMD_BASE   0x40001000

Referenced by CKMDGetInitialAmplitudeThresholdTrim(), CKMDGetInitialIdacTrim(), CKMDGetInitialIrefTrim(), CKMDGetInitialQ1CapTrim(), CKMDGetInitialQ2CapTrim(), CKMDGetTargetAmplitudeThresholdTrim(), CKMDGetTargetIdacTrim(), CKMDGetTargetIrefTrim(), CKMDGetTargetQ1CapTrim(), CKMDGetTargetQ2CapTrim(), CKMDSetInitialAmplitudeThresholdTrim(), CKMDSetInitialCapTrim(), CKMDSetInitialIdacTrim(), CKMDSetInitialIrefTrim(), CKMDSetInitialQ1CapTrim(), CKMDSetInitialQ2CapTrim(), CKMDSetTargetAmplitudeThresholdTrim(), CKMDSetTargetCapTrim(), CKMDSetTargetIdacTrim(), CKMDSetTargetIrefTrim(), CKMDSetTargetQ1CapTrim(), CKMDSetTargetQ2CapTrim(), and SetupTrimDevice().

§ RTC_BASE

#define RTC_BASE   0x40002000

§ IOC_BASE

#define IOC_BASE   0x40003000

§ SYS0_BASE

#define SYS0_BASE   0x40004000

Referenced by ADCSetAdjustmentOffset(), ChipInfoGetVersion(), LPCMPClearEvent(), LPCMPDisable(), LPCMPDisableEvent(), LPCMPDisableWakeup(), LPCMPEnable(), LPCMPEnableEvent(), LPCMPEnableWakeup(), LPCMPIsOutputHigh(), LPCMPSelectNegativeInput(), LPCMPSelectPositiveInput(), LPCMPSetDividerPath(), LPCMPSetDividerRatio(), LPCMPSetPolarity(), and TempDiodeGetTemp().

§ EVTULL_BASE

#define EVTULL_BASE   0x40005000

§ PMUD_BASE

#define PMUD_BASE   0x40006000

Referenced by TempDiodeGetTemp().

§ DBGSS_BASE

#define DBGSS_BASE   0x4000F000

§ CLKCTL_BASE

#define CLKCTL_BASE   0x40020000

Referenced by enableADC(), LRFDApplyClockDependencies(), and TempDiodeGetTemp().

§ FLASH_BASE

#define FLASH_BASE   0x40021000

Referenced by FlashCheckFsmForError(), and FlashCheckFsmForReady().

§ SYSTIM_BASE

#define SYSTIM_BASE   0x40022000

§ GPIO_BASE

#define GPIO_BASE   0x40023000

Referenced by GPIOClearDio(), GPIOClearEventDio(), GPIOClearEventMultiDio(), GPIOClearMultiDio(), GPIOGetEventDio(), GPIOGetEventMultiDio(), GPIOGetOutputEnableDio(), GPIOGetOutputEnableMultiDio(), GPIOReadDio(), GPIOReadMultiDio(), GPIOSetDio(), GPIOSetMultiDio(), GPIOSetOutputEnableDio(), GPIOSetOutputEnableMultiDio(), GPIOToggleDio(), GPIOToggleMultiDio(), GPIOWriteDio(), and GPIOWriteMultiDio().

§ VIMS_BASE

#define VIMS_BASE   0x40024000

Referenced by FlashEraseBank(), FlashEraseSector(), and FlashProgram().

§ EVTSVT_BASE

#define EVTSVT_BASE   0x40025000

§ DMA_BASE

#define DMA_BASE   0x40026000

Referenced by uDMAClearChannelPriority(), uDMAClearErrorStatus(), uDMAClearInt(), uDMADisable(), uDMADisableChannel(), uDMADisableChannelAttribute(), uDMADisableSwEventInt(), uDMAEnable(), uDMAEnableChannel(), uDMAEnableChannelAttribute(), uDMAEnableSwEventInt(), uDMAGetChannelAttribute(), uDMAGetChannelMode(), uDMAGetChannelPriority(), uDMAGetChannelSize(), uDMAGetControlAlternateBase(), uDMAGetControlBase(), uDMAGetErrorStatus(), uDMAGetStatus(), uDMAIntStatus(), uDMAIsChannelEnabled(), uDMARequestChannel(), uDMASetChannelControl(), uDMASetChannelPriority(), uDMASetChannelTransfer(), and uDMASetControlBase().

§ SPI0_BASE

#define SPI0_BASE   0x40030000

§ UART0_BASE

#define UART0_BASE   0x40034000

§ I2C0_BASE

#define I2C0_BASE   0x40038000

§ ADC_BASE

#define ADC_BASE   0x40050000

Referenced by ADCClearInterrupt(), ADCDisableInterrupt(), ADCEnableInterrupt(), ADCIsBusy(), ADCManualTrigger(), ADCMaskedInterruptStatus(), ADCRawInterruptStatus(), ADCReadResult(), ADCReadResultNonBlocking(), ADCSetInput(), ADCSetMemctlRange(), ADCSetResolution(), ADCSetSampleDuration(), and ADCSetSequence().

§ LGPT0_BASE

#define LGPT0_BASE   0x40060000

§ LGPT1_BASE

#define LGPT1_BASE   0x40061000

§ LGPT2_BASE

#define LGPT2_BASE   0x40062000

§ LGPT3_BASE

#define LGPT3_BASE   0x40063000

§ LRFDDBELL_BASE

#define LRFDDBELL_BASE   0x40080000

Referenced by LRFDApplyClockDependencies().

§ LRFDPBE_BASE

#define LRFDPBE_BASE   0x40081000

§ LRFDPBE32_BASE

#define LRFDPBE32_BASE   0x40081400

§ LRFDTXF_BASE

#define LRFDTXF_BASE   0x40081800

§ LRFDRXF_BASE

#define LRFDRXF_BASE   0x40081C00

§ LRFDMDM_BASE

#define LRFDMDM_BASE   0x40082000

§ LRFDMDM32_BASE

#define LRFDMDM32_BASE   0x40082400

§ LRFDRFE_BASE

#define LRFDRFE_BASE   0x40083000

§ LRFDRFE32_BASE

#define LRFDRFE32_BASE   0x40083400

§ LRFDTRC_BASE

#define LRFDTRC_BASE   0x40084000

§ LRFDS2R_BASE

#define LRFDS2R_BASE   0x40085000

§ LRFD_PBERAM_BASE

#define LRFD_PBERAM_BASE   0x40090000

§ LRFD_PBERAM_SIZE

#define LRFD_PBERAM_SIZE   0x1000

§ LRFD_BUFRAM_BASE

#define LRFD_BUFRAM_BASE   0x40092000

§ LRFD_BUFRAM_SIZE

#define LRFD_BUFRAM_SIZE   0x600

§ LRFD_MCERAM_BASE

#define LRFD_MCERAM_BASE   0x40094000

§ LRFD_MCERAM_SIZE

#define LRFD_MCERAM_SIZE   0x1000

§ LRFD_RFERAM_BASE

#define LRFD_RFERAM_BASE   0x40096000

§ LRFD_RFERAM_SIZE

#define LRFD_RFERAM_SIZE   0x1000

§ LRFD_S2RRAM_BASE

#define LRFD_S2RRAM_BASE   0x40098000

§ LRFD_S2RRAM_SIZE

#define LRFD_S2RRAM_SIZE   0x1000

§ AES_BASE

#define AES_BASE   0x400C0000

§ FCFG_BASE

#define FCFG_BASE   0x4E000000

§ FCFG_SIZE

#define FCFG_SIZE   0x400

§ CCFG_BASE

#define CCFG_BASE   0x4E020000

§ CCFG_SIZE

#define CCFG_SIZE   0x800

§ BPU_BASE

#define BPU_BASE   0xE0002000

§ NVIC_BASE

#define NVIC_BASE   0xE000E000

§ SYSTICK_BASE

#define SYSTICK_BASE   0xE000E010

Referenced by SysTickDisable(), SysTickDisableInt(), SysTickEnable(), SysTickEnableInt(), SysTickGetPeriod(), SysTickGetValue(), SysTickRegisterInt(), SysTickSetPeriod(), and SysTickUnregisterInt().

§ SCB_BASE

#define SCB_BASE   0xE000ED00

§ DCB_BASE

#define DCB_BASE   0xE000ED30

§ SCSCS_BASE

#define SCSCS_BASE   0xE000EFC0

§ CPU_ROM_TABLE_BASE

#define CPU_ROM_TABLE_BASE   0xE00FF000