CC23x0R5DriverLibrary
Macros
hw_dma.h File Reference
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Macros

#define DMA_O_STATUS   0x00000000U
 
#define DMA_O_CFG   0x00000004U
 
#define DMA_O_CTRL   0x00000008U
 
#define DMA_O_ALTCTRL   0x0000000CU
 
#define DMA_O_WAITONREQ   0x00000010U
 
#define DMA_O_SOFTREQ   0x00000014U
 
#define DMA_O_SETBURST   0x00000018U
 
#define DMA_O_CLEARBURST   0x0000001CU
 
#define DMA_O_SETREQMASK   0x00000020U
 
#define DMA_O_CLEARREQMASK   0x00000024U
 
#define DMA_O_SETCHANNELEN   0x00000028U
 
#define DMA_O_CLEARCHANNELEN   0x0000002CU
 
#define DMA_O_SETCHNLPRIALT   0x00000030U
 
#define DMA_O_CLEARCHNLPRIALT   0x00000034U
 
#define DMA_O_SETCHNLPRIORITY   0x00000038U
 
#define DMA_O_CLEARCHNLPRIORITY   0x0000003CU
 
#define DMA_O_ERROR   0x0000004CU
 
#define DMA_O_REQDONE   0x00000504U
 
#define DMA_O_DONEMASK   0x00000520U
 
#define DMA_STATUS_TEST_W   4U
 
#define DMA_STATUS_TEST_M   0xF0000000U
 
#define DMA_STATUS_TEST_S   28U
 
#define DMA_STATUS_TOTALCHANNELS_W   5U
 
#define DMA_STATUS_TOTALCHANNELS_M   0x001F0000U
 
#define DMA_STATUS_TOTALCHANNELS_S   16U
 
#define DMA_STATUS_STATE_W   4U
 
#define DMA_STATUS_STATE_M   0x000000F0U
 
#define DMA_STATUS_STATE_S   4U
 
#define DMA_STATUS_MASTERENABLE   0x00000001U
 
#define DMA_STATUS_MASTERENABLE_M   0x00000001U
 
#define DMA_STATUS_MASTERENABLE_S   0U
 
#define DMA_STATUS_MASTERENABLE_EN   0x00000001U
 
#define DMA_STATUS_MASTERENABLE_DIS   0x00000000U
 
#define DMA_CFG_PRTOCTRL_W   3U
 
#define DMA_CFG_PRTOCTRL_M   0x000000E0U
 
#define DMA_CFG_PRTOCTRL_S   5U
 
#define DMA_CFG_MASTERENABLE   0x00000001U
 
#define DMA_CFG_MASTERENABLE_M   0x00000001U
 
#define DMA_CFG_MASTERENABLE_S   0U
 
#define DMA_CFG_MASTERENABLE_EN   0x00000001U
 
#define DMA_CFG_MASTERENABLE_DIS   0x00000000U
 
#define DMA_CTRL_BASEPTR_W   24U
 
#define DMA_CTRL_BASEPTR_M   0xFFFFFF00U
 
#define DMA_CTRL_BASEPTR_S   8U
 
#define DMA_ALTCTRL_BASEPTR_W   32U
 
#define DMA_ALTCTRL_BASEPTR_M   0xFFFFFFFFU
 
#define DMA_ALTCTRL_BASEPTR_S   0U
 
#define DMA_WAITONREQ_CHNLSTATUS_W   8U
 
#define DMA_WAITONREQ_CHNLSTATUS_M   0x000000FFU
 
#define DMA_WAITONREQ_CHNLSTATUS_S   0U
 
#define DMA_SOFTREQ_CHNLS_W   8U
 
#define DMA_SOFTREQ_CHNLS_M   0x000000FFU
 
#define DMA_SOFTREQ_CHNLS_S   0U
 
#define DMA_SETBURST_CHNLS_W   8U
 
#define DMA_SETBURST_CHNLS_M   0x000000FFU
 
#define DMA_SETBURST_CHNLS_S   0U
 
#define DMA_CLEARBURST_CHNLS_W   8U
 
#define DMA_CLEARBURST_CHNLS_M   0x000000FFU
 
#define DMA_CLEARBURST_CHNLS_S   0U
 
#define DMA_SETREQMASK_CHNLS_W   8U
 
#define DMA_SETREQMASK_CHNLS_M   0x000000FFU
 
#define DMA_SETREQMASK_CHNLS_S   0U
 
#define DMA_CLEARREQMASK_CHNLS_W   8U
 
#define DMA_CLEARREQMASK_CHNLS_M   0x000000FFU
 
#define DMA_CLEARREQMASK_CHNLS_S   0U
 
#define DMA_SETCHANNELEN_CHNLS_W   8U
 
#define DMA_SETCHANNELEN_CHNLS_M   0x000000FFU
 
#define DMA_SETCHANNELEN_CHNLS_S   0U
 
#define DMA_CLEARCHANNELEN_CHNLS_W   8U
 
#define DMA_CLEARCHANNELEN_CHNLS_M   0x000000FFU
 
#define DMA_CLEARCHANNELEN_CHNLS_S   0U
 
#define DMA_SETCHNLPRIALT_CHNLS_W   8U
 
#define DMA_SETCHNLPRIALT_CHNLS_M   0x000000FFU
 
#define DMA_SETCHNLPRIALT_CHNLS_S   0U
 
#define DMA_CLEARCHNLPRIALT_CHNLS_W   8U
 
#define DMA_CLEARCHNLPRIALT_CHNLS_M   0x000000FFU
 
#define DMA_CLEARCHNLPRIALT_CHNLS_S   0U
 
#define DMA_SETCHNLPRIORITY_CHNLS_W   8U
 
#define DMA_SETCHNLPRIORITY_CHNLS_M   0x000000FFU
 
#define DMA_SETCHNLPRIORITY_CHNLS_S   0U
 
#define DMA_CLEARCHNLPRIORITY_CHNLS_W   8U
 
#define DMA_CLEARCHNLPRIORITY_CHNLS_M   0x000000FFU
 
#define DMA_CLEARCHNLPRIORITY_CHNLS_S   0U
 
#define DMA_ERROR_STATUS   0x00000001U
 
#define DMA_ERROR_STATUS_M   0x00000001U
 
#define DMA_ERROR_STATUS_S   0U
 
#define DMA_REQDONE_CHNLS_W   8U
 
#define DMA_REQDONE_CHNLS_M   0x000000FFU
 
#define DMA_REQDONE_CHNLS_S   0U
 
#define DMA_DONEMASK_CHNLS_W   8U
 
#define DMA_DONEMASK_CHNLS_M   0x000000FFU
 
#define DMA_DONEMASK_CHNLS_S   0U
 

Macro Definition Documentation

§ DMA_O_STATUS

#define DMA_O_STATUS   0x00000000U

Referenced by uDMAGetStatus().

§ DMA_O_CFG

#define DMA_O_CFG   0x00000004U

Referenced by uDMADisable(), and uDMAEnable().

§ DMA_O_CTRL

#define DMA_O_CTRL   0x00000008U

Referenced by uDMAGetChannelMode(), uDMAGetChannelSize(), uDMAGetControlBase(), uDMASetChannelControl(), uDMASetChannelTransfer(), and uDMASetControlBase().

§ DMA_O_ALTCTRL

#define DMA_O_ALTCTRL   0x0000000CU

Referenced by uDMAGetControlAlternateBase().

§ DMA_O_WAITONREQ

#define DMA_O_WAITONREQ   0x00000010U

§ DMA_O_SOFTREQ

#define DMA_O_SOFTREQ   0x00000014U

Referenced by uDMARequestChannel().

§ DMA_O_SETBURST

#define DMA_O_SETBURST   0x00000018U

Referenced by uDMAEnableChannelAttribute(), and uDMAGetChannelAttribute().

§ DMA_O_CLEARBURST

#define DMA_O_CLEARBURST   0x0000001CU

Referenced by uDMADisableChannelAttribute().

§ DMA_O_SETREQMASK

#define DMA_O_SETREQMASK   0x00000020U

Referenced by uDMAEnableChannelAttribute(), and uDMAGetChannelAttribute().

§ DMA_O_CLEARREQMASK

#define DMA_O_CLEARREQMASK   0x00000024U

Referenced by uDMADisableChannelAttribute().

§ DMA_O_SETCHANNELEN

#define DMA_O_SETCHANNELEN   0x00000028U

Referenced by uDMAEnableChannel(), and uDMAIsChannelEnabled().

§ DMA_O_CLEARCHANNELEN

#define DMA_O_CLEARCHANNELEN   0x0000002CU

Referenced by uDMADisableChannel().

§ DMA_O_SETCHNLPRIALT

#define DMA_O_SETCHNLPRIALT   0x00000030U

Referenced by uDMAEnableChannelAttribute(), and uDMAGetChannelAttribute().

§ DMA_O_CLEARCHNLPRIALT

#define DMA_O_CLEARCHNLPRIALT   0x00000034U

Referenced by uDMADisableChannelAttribute().

§ DMA_O_SETCHNLPRIORITY

#define DMA_O_SETCHNLPRIORITY   0x00000038U

Referenced by uDMAEnableChannelAttribute(), uDMAGetChannelAttribute(), uDMAGetChannelPriority(), and uDMASetChannelPriority().

§ DMA_O_CLEARCHNLPRIORITY

#define DMA_O_CLEARCHNLPRIORITY   0x0000003CU

Referenced by uDMAClearChannelPriority(), and uDMADisableChannelAttribute().

§ DMA_O_ERROR

#define DMA_O_ERROR   0x0000004CU

Referenced by uDMAClearErrorStatus(), and uDMAGetErrorStatus().

§ DMA_O_REQDONE

#define DMA_O_REQDONE   0x00000504U

Referenced by uDMAClearInt(), and uDMAIntStatus().

§ DMA_O_DONEMASK

#define DMA_O_DONEMASK   0x00000520U

Referenced by uDMADisableSwEventInt(), and uDMAEnableSwEventInt().

§ DMA_STATUS_TEST_W

#define DMA_STATUS_TEST_W   4U

§ DMA_STATUS_TEST_M

#define DMA_STATUS_TEST_M   0xF0000000U

§ DMA_STATUS_TEST_S

#define DMA_STATUS_TEST_S   28U

§ DMA_STATUS_TOTALCHANNELS_W

#define DMA_STATUS_TOTALCHANNELS_W   5U

§ DMA_STATUS_TOTALCHANNELS_M

#define DMA_STATUS_TOTALCHANNELS_M   0x001F0000U

§ DMA_STATUS_TOTALCHANNELS_S

#define DMA_STATUS_TOTALCHANNELS_S   16U

§ DMA_STATUS_STATE_W

#define DMA_STATUS_STATE_W   4U

§ DMA_STATUS_STATE_M

#define DMA_STATUS_STATE_M   0x000000F0U

§ DMA_STATUS_STATE_S

#define DMA_STATUS_STATE_S   4U

§ DMA_STATUS_MASTERENABLE

#define DMA_STATUS_MASTERENABLE   0x00000001U

§ DMA_STATUS_MASTERENABLE_M

#define DMA_STATUS_MASTERENABLE_M   0x00000001U

§ DMA_STATUS_MASTERENABLE_S

#define DMA_STATUS_MASTERENABLE_S   0U

§ DMA_STATUS_MASTERENABLE_EN

#define DMA_STATUS_MASTERENABLE_EN   0x00000001U

§ DMA_STATUS_MASTERENABLE_DIS

#define DMA_STATUS_MASTERENABLE_DIS   0x00000000U

§ DMA_CFG_PRTOCTRL_W

#define DMA_CFG_PRTOCTRL_W   3U

§ DMA_CFG_PRTOCTRL_M

#define DMA_CFG_PRTOCTRL_M   0x000000E0U

§ DMA_CFG_PRTOCTRL_S

#define DMA_CFG_PRTOCTRL_S   5U

§ DMA_CFG_MASTERENABLE

#define DMA_CFG_MASTERENABLE   0x00000001U

Referenced by uDMAEnable().

§ DMA_CFG_MASTERENABLE_M

#define DMA_CFG_MASTERENABLE_M   0x00000001U

§ DMA_CFG_MASTERENABLE_S

#define DMA_CFG_MASTERENABLE_S   0U

§ DMA_CFG_MASTERENABLE_EN

#define DMA_CFG_MASTERENABLE_EN   0x00000001U

§ DMA_CFG_MASTERENABLE_DIS

#define DMA_CFG_MASTERENABLE_DIS   0x00000000U

§ DMA_CTRL_BASEPTR_W

#define DMA_CTRL_BASEPTR_W   24U

§ DMA_CTRL_BASEPTR_M

#define DMA_CTRL_BASEPTR_M   0xFFFFFF00U

§ DMA_CTRL_BASEPTR_S

#define DMA_CTRL_BASEPTR_S   8U

§ DMA_ALTCTRL_BASEPTR_W

#define DMA_ALTCTRL_BASEPTR_W   32U

§ DMA_ALTCTRL_BASEPTR_M

#define DMA_ALTCTRL_BASEPTR_M   0xFFFFFFFFU

§ DMA_ALTCTRL_BASEPTR_S

#define DMA_ALTCTRL_BASEPTR_S   0U

§ DMA_WAITONREQ_CHNLSTATUS_W

#define DMA_WAITONREQ_CHNLSTATUS_W   8U

§ DMA_WAITONREQ_CHNLSTATUS_M

#define DMA_WAITONREQ_CHNLSTATUS_M   0x000000FFU

§ DMA_WAITONREQ_CHNLSTATUS_S

#define DMA_WAITONREQ_CHNLSTATUS_S   0U

§ DMA_SOFTREQ_CHNLS_W

#define DMA_SOFTREQ_CHNLS_W   8U

§ DMA_SOFTREQ_CHNLS_M

#define DMA_SOFTREQ_CHNLS_M   0x000000FFU

§ DMA_SOFTREQ_CHNLS_S

#define DMA_SOFTREQ_CHNLS_S   0U

§ DMA_SETBURST_CHNLS_W

#define DMA_SETBURST_CHNLS_W   8U

§ DMA_SETBURST_CHNLS_M

#define DMA_SETBURST_CHNLS_M   0x000000FFU

§ DMA_SETBURST_CHNLS_S

#define DMA_SETBURST_CHNLS_S   0U

§ DMA_CLEARBURST_CHNLS_W

#define DMA_CLEARBURST_CHNLS_W   8U

§ DMA_CLEARBURST_CHNLS_M

#define DMA_CLEARBURST_CHNLS_M   0x000000FFU

§ DMA_CLEARBURST_CHNLS_S

#define DMA_CLEARBURST_CHNLS_S   0U

§ DMA_SETREQMASK_CHNLS_W

#define DMA_SETREQMASK_CHNLS_W   8U

§ DMA_SETREQMASK_CHNLS_M

#define DMA_SETREQMASK_CHNLS_M   0x000000FFU

§ DMA_SETREQMASK_CHNLS_S

#define DMA_SETREQMASK_CHNLS_S   0U

§ DMA_CLEARREQMASK_CHNLS_W

#define DMA_CLEARREQMASK_CHNLS_W   8U

§ DMA_CLEARREQMASK_CHNLS_M

#define DMA_CLEARREQMASK_CHNLS_M   0x000000FFU

§ DMA_CLEARREQMASK_CHNLS_S

#define DMA_CLEARREQMASK_CHNLS_S   0U

§ DMA_SETCHANNELEN_CHNLS_W

#define DMA_SETCHANNELEN_CHNLS_W   8U

§ DMA_SETCHANNELEN_CHNLS_M

#define DMA_SETCHANNELEN_CHNLS_M   0x000000FFU

§ DMA_SETCHANNELEN_CHNLS_S

#define DMA_SETCHANNELEN_CHNLS_S   0U

§ DMA_CLEARCHANNELEN_CHNLS_W

#define DMA_CLEARCHANNELEN_CHNLS_W   8U

§ DMA_CLEARCHANNELEN_CHNLS_M

#define DMA_CLEARCHANNELEN_CHNLS_M   0x000000FFU

§ DMA_CLEARCHANNELEN_CHNLS_S

#define DMA_CLEARCHANNELEN_CHNLS_S   0U

§ DMA_SETCHNLPRIALT_CHNLS_W

#define DMA_SETCHNLPRIALT_CHNLS_W   8U

§ DMA_SETCHNLPRIALT_CHNLS_M

#define DMA_SETCHNLPRIALT_CHNLS_M   0x000000FFU

§ DMA_SETCHNLPRIALT_CHNLS_S

#define DMA_SETCHNLPRIALT_CHNLS_S   0U

§ DMA_CLEARCHNLPRIALT_CHNLS_W

#define DMA_CLEARCHNLPRIALT_CHNLS_W   8U

§ DMA_CLEARCHNLPRIALT_CHNLS_M

#define DMA_CLEARCHNLPRIALT_CHNLS_M   0x000000FFU

§ DMA_CLEARCHNLPRIALT_CHNLS_S

#define DMA_CLEARCHNLPRIALT_CHNLS_S   0U

§ DMA_SETCHNLPRIORITY_CHNLS_W

#define DMA_SETCHNLPRIORITY_CHNLS_W   8U

§ DMA_SETCHNLPRIORITY_CHNLS_M

#define DMA_SETCHNLPRIORITY_CHNLS_M   0x000000FFU

§ DMA_SETCHNLPRIORITY_CHNLS_S

#define DMA_SETCHNLPRIORITY_CHNLS_S   0U

§ DMA_CLEARCHNLPRIORITY_CHNLS_W

#define DMA_CLEARCHNLPRIORITY_CHNLS_W   8U

§ DMA_CLEARCHNLPRIORITY_CHNLS_M

#define DMA_CLEARCHNLPRIORITY_CHNLS_M   0x000000FFU

§ DMA_CLEARCHNLPRIORITY_CHNLS_S

#define DMA_CLEARCHNLPRIORITY_CHNLS_S   0U

§ DMA_ERROR_STATUS

#define DMA_ERROR_STATUS   0x00000001U

Referenced by uDMAClearErrorStatus().

§ DMA_ERROR_STATUS_M

#define DMA_ERROR_STATUS_M   0x00000001U

§ DMA_ERROR_STATUS_S

#define DMA_ERROR_STATUS_S   0U

§ DMA_REQDONE_CHNLS_W

#define DMA_REQDONE_CHNLS_W   8U

§ DMA_REQDONE_CHNLS_M

#define DMA_REQDONE_CHNLS_M   0x000000FFU

§ DMA_REQDONE_CHNLS_S

#define DMA_REQDONE_CHNLS_S   0U

§ DMA_DONEMASK_CHNLS_W

#define DMA_DONEMASK_CHNLS_W   8U

§ DMA_DONEMASK_CHNLS_M

#define DMA_DONEMASK_CHNLS_M   0x000000FFU

§ DMA_DONEMASK_CHNLS_S

#define DMA_DONEMASK_CHNLS_S   0U