![]() |
![]() |
|
CC23x0R5DriverLibrary
|

Go to the source code of this file.
| #define CKMD_O_DESC 0x00000000U |
| #define CKMD_O_IMASK 0x00000044U |
| #define CKMD_O_RIS 0x00000048U |
| #define CKMD_O_MIS 0x0000004CU |
| #define CKMD_O_ISET 0x00000050U |
| #define CKMD_O_ICLR 0x00000054U |
| #define CKMD_O_IMSET 0x00000058U |
| #define CKMD_O_IMCLR 0x0000005CU |
| #define CKMD_O_HFOSCCTL 0x00000080U |
| #define CKMD_O_HFXTCTL 0x00000084U |
| #define CKMD_O_LFOSCCTL 0x0000008CU |
| #define CKMD_O_LFXTCTL 0x00000090U |
| #define CKMD_O_LFQUALCTL 0x00000094U |
| #define CKMD_O_LFINCCTL 0x00000098U |
| #define CKMD_O_LFINCOVR 0x0000009CU |
| #define CKMD_O_AMPADCCTL 0x000000A0U |
| #define CKMD_O_HFTRACKCTL 0x000000A4U |
| #define CKMD_O_LDOCTL 0x000000A8U |
| #define CKMD_O_NABIASCTL 0x000000ACU |
| #define CKMD_O_LFMONCTL 0x000000B0U |
| #define CKMD_O_LFCLKSEL 0x000000C0U |
| #define CKMD_O_TDCCLKSEL 0x000000C4U |
| #define CKMD_O_ADCCLKSEL 0x000000C8U |
| #define CKMD_O_LFCLKSTAT 0x000000E0U |
| #define CKMD_O_HFXTSTAT 0x000000E4U |
| #define CKMD_O_AMPADCSTAT 0x000000E8U |
| #define CKMD_O_TRACKSTAT 0x000000ECU |
| #define CKMD_O_AMPSTAT 0x000000F0U |
| #define CKMD_O_ATBCTL0 0x00000100U |
| #define CKMD_O_ATBCTL1 0x00000104U |
| #define CKMD_O_DTBCTL 0x00000108U |
| #define CKMD_O_TRIM0 0x00000110U |
| #define CKMD_O_TRIM1 0x00000114U |
| #define CKMD_O_HFXTINIT 0x00000118U |
Referenced by CKMDGetInitialAmplitudeThresholdTrim(), CKMDGetInitialIdacTrim(), CKMDGetInitialIrefTrim(), CKMDGetInitialQ1CapTrim(), CKMDGetInitialQ2CapTrim(), CKMDSetInitialAmplitudeThresholdTrim(), CKMDSetInitialCapTrim(), CKMDSetInitialIdacTrim(), CKMDSetInitialIrefTrim(), CKMDSetInitialQ1CapTrim(), CKMDSetInitialQ2CapTrim(), and SetupTrimDevice().
| #define CKMD_O_HFXTTARG 0x0000011CU |
Referenced by CKMDGetTargetAmplitudeThresholdTrim(), CKMDGetTargetIdacTrim(), CKMDGetTargetIrefTrim(), CKMDGetTargetQ1CapTrim(), CKMDGetTargetQ2CapTrim(), CKMDSetTargetAmplitudeThresholdTrim(), CKMDSetTargetCapTrim(), CKMDSetTargetIdacTrim(), CKMDSetTargetIrefTrim(), CKMDSetTargetQ1CapTrim(), CKMDSetTargetQ2CapTrim(), and SetupTrimDevice().
| #define CKMD_O_HFXTDYN 0x00000120U |
| #define CKMD_O_AMPCFG0 0x00000124U |
| #define CKMD_O_AMPCFG1 0x00000128U |
| #define CKMD_O_LOOPCFG 0x0000012CU |
| #define CKMD_O_TDCCTL 0x00000200U |
| #define CKMD_O_TDCSTAT 0x00000204U |
| #define CKMD_O_TDCRESULT 0x00000208U |
| #define CKMD_O_TDCSATCFG 0x0000020CU |
| #define CKMD_O_TDCTRIGSRC 0x00000210U |
| #define CKMD_O_TDCTRIGCNT 0x00000214U |
| #define CKMD_O_TDCTRIGCNTLOAD 0x00000218U |
| #define CKMD_O_TDCTRIGCNTCFG 0x0000021CU |
| #define CKMD_O_TDCPRECTL 0x00000220U |
| #define CKMD_O_TDCPRECNTR 0x00000224U |
| #define CKMD_O_WDTCNT 0x00000300U |
| #define CKMD_O_WDTTEST 0x00000304U |
| #define CKMD_O_WDTLOCK 0x00000308U |
| #define CKMD_DESC_MODID_W 16U |
| #define CKMD_DESC_MODID_M 0xFFFF0000U |
| #define CKMD_DESC_MODID_S 16U |
| #define CKMD_DESC_STDIPOFF_W 4U |
| #define CKMD_DESC_STDIPOFF_M 0x0000F000U |
| #define CKMD_DESC_STDIPOFF_S 12U |
| #define CKMD_DESC_MAJREV_W 4U |
| #define CKMD_DESC_MAJREV_M 0x000000F0U |
| #define CKMD_DESC_MAJREV_S 4U |
| #define CKMD_DESC_MINREV_W 4U |
| #define CKMD_DESC_MINREV_M 0x0000000FU |
| #define CKMD_DESC_MINREV_S 0U |
| #define CKMD_IMASK_LFTICK 0x00020000U |
| #define CKMD_IMASK_LFTICK_M 0x00020000U |
| #define CKMD_IMASK_LFTICK_S 17U |
| #define CKMD_IMASK_LFGEARRSTRT 0x00010000U |
| #define CKMD_IMASK_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_IMASK_LFGEARRSTRT_S 16U |
| #define CKMD_IMASK_AMPSETTLED 0x00008000U |
| #define CKMD_IMASK_AMPSETTLED_M 0x00008000U |
| #define CKMD_IMASK_AMPSETTLED_S 15U |
| #define CKMD_IMASK_AMPCTRLATTARG 0x00004000U |
| #define CKMD_IMASK_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_IMASK_AMPCTRLATTARG_S 14U |
| #define CKMD_IMASK_PRELFEDGE 0x00002000U |
| #define CKMD_IMASK_PRELFEDGE_M 0x00002000U |
| #define CKMD_IMASK_PRELFEDGE_S 13U |
| #define CKMD_IMASK_LFCLKLOSS 0x00001000U |
| #define CKMD_IMASK_LFCLKLOSS_M 0x00001000U |
| #define CKMD_IMASK_LFCLKLOSS_S 12U |
| #define CKMD_IMASK_LFCLKOOR 0x00000800U |
| #define CKMD_IMASK_LFCLKOOR_M 0x00000800U |
| #define CKMD_IMASK_LFCLKOOR_S 11U |
| #define CKMD_IMASK_LFCLKGOOD 0x00000400U |
| #define CKMD_IMASK_LFCLKGOOD_M 0x00000400U |
| #define CKMD_IMASK_LFCLKGOOD_S 10U |
| #define CKMD_IMASK_LFINCUPD 0x00000200U |
| #define CKMD_IMASK_LFINCUPD_M 0x00000200U |
| #define CKMD_IMASK_LFINCUPD_S 9U |
| #define CKMD_IMASK_TDCDONE 0x00000100U |
| #define CKMD_IMASK_TDCDONE_M 0x00000100U |
| #define CKMD_IMASK_TDCDONE_S 8U |
| #define CKMD_IMASK_ADCPEAKUPD 0x00000080U |
| #define CKMD_IMASK_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_IMASK_ADCPEAKUPD_S 7U |
| #define CKMD_IMASK_ADCBIASUPD 0x00000040U |
| #define CKMD_IMASK_ADCBIASUPD_M 0x00000040U |
| #define CKMD_IMASK_ADCBIASUPD_S 6U |
| #define CKMD_IMASK_ADCCOMPUPD 0x00000020U |
| #define CKMD_IMASK_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_IMASK_ADCCOMPUPD_S 5U |
| #define CKMD_IMASK_TRACKREFOOR 0x00000010U |
| #define CKMD_IMASK_TRACKREFOOR_M 0x00000010U |
| #define CKMD_IMASK_TRACKREFOOR_S 4U |
| #define CKMD_IMASK_TRACKREFLOSS 0x00000008U |
| #define CKMD_IMASK_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_IMASK_TRACKREFLOSS_S 3U |
| #define CKMD_IMASK_HFXTAMPGOOD 0x00000004U |
| #define CKMD_IMASK_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_IMASK_HFXTAMPGOOD_S 2U |
| #define CKMD_IMASK_HFXTFAULT 0x00000002U |
| #define CKMD_IMASK_HFXTFAULT_M 0x00000002U |
| #define CKMD_IMASK_HFXTFAULT_S 1U |
| #define CKMD_IMASK_HFXTGOOD 0x00000001U |
| #define CKMD_IMASK_HFXTGOOD_M 0x00000001U |
| #define CKMD_IMASK_HFXTGOOD_S 0U |
| #define CKMD_RIS_LFTICK 0x00020000U |
| #define CKMD_RIS_LFTICK_M 0x00020000U |
| #define CKMD_RIS_LFTICK_S 17U |
| #define CKMD_RIS_LFGEARRSTRT 0x00010000U |
| #define CKMD_RIS_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_RIS_LFGEARRSTRT_S 16U |
| #define CKMD_RIS_AMPSETTLED 0x00008000U |
| #define CKMD_RIS_AMPSETTLED_M 0x00008000U |
| #define CKMD_RIS_AMPSETTLED_S 15U |
| #define CKMD_RIS_AMPCTRLATTARG 0x00004000U |
| #define CKMD_RIS_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_RIS_AMPCTRLATTARG_S 14U |
| #define CKMD_RIS_PRELFEDGE 0x00002000U |
| #define CKMD_RIS_PRELFEDGE_M 0x00002000U |
| #define CKMD_RIS_PRELFEDGE_S 13U |
| #define CKMD_RIS_LFCLKLOSS 0x00001000U |
| #define CKMD_RIS_LFCLKLOSS_M 0x00001000U |
| #define CKMD_RIS_LFCLKLOSS_S 12U |
| #define CKMD_RIS_LFCLKOOR 0x00000800U |
| #define CKMD_RIS_LFCLKOOR_M 0x00000800U |
| #define CKMD_RIS_LFCLKOOR_S 11U |
| #define CKMD_RIS_LFCLKGOOD 0x00000400U |
| #define CKMD_RIS_LFCLKGOOD_M 0x00000400U |
| #define CKMD_RIS_LFCLKGOOD_S 10U |
| #define CKMD_RIS_LFINCUPD 0x00000200U |
| #define CKMD_RIS_LFINCUPD_M 0x00000200U |
| #define CKMD_RIS_LFINCUPD_S 9U |
| #define CKMD_RIS_TDCDONE 0x00000100U |
| #define CKMD_RIS_TDCDONE_M 0x00000100U |
| #define CKMD_RIS_TDCDONE_S 8U |
| #define CKMD_RIS_ADCPEAKUPD 0x00000080U |
| #define CKMD_RIS_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_RIS_ADCPEAKUPD_S 7U |
| #define CKMD_RIS_ADCBIASUPD 0x00000040U |
| #define CKMD_RIS_ADCBIASUPD_M 0x00000040U |
| #define CKMD_RIS_ADCBIASUPD_S 6U |
| #define CKMD_RIS_ADCCOMPUPD 0x00000020U |
| #define CKMD_RIS_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_RIS_ADCCOMPUPD_S 5U |
| #define CKMD_RIS_TRACKREFOOR 0x00000010U |
| #define CKMD_RIS_TRACKREFOOR_M 0x00000010U |
| #define CKMD_RIS_TRACKREFOOR_S 4U |
| #define CKMD_RIS_TRACKREFLOSS 0x00000008U |
| #define CKMD_RIS_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_RIS_TRACKREFLOSS_S 3U |
| #define CKMD_RIS_HFXTAMPGOOD 0x00000004U |
| #define CKMD_RIS_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_RIS_HFXTAMPGOOD_S 2U |
| #define CKMD_RIS_HFXTFAULT 0x00000002U |
| #define CKMD_RIS_HFXTFAULT_M 0x00000002U |
| #define CKMD_RIS_HFXTFAULT_S 1U |
| #define CKMD_RIS_HFXTGOOD 0x00000001U |
| #define CKMD_RIS_HFXTGOOD_M 0x00000001U |
| #define CKMD_RIS_HFXTGOOD_S 0U |
| #define CKMD_MIS_LFTICK 0x00020000U |
| #define CKMD_MIS_LFTICK_M 0x00020000U |
| #define CKMD_MIS_LFTICK_S 17U |
| #define CKMD_MIS_LFGEARRSTRT 0x00010000U |
| #define CKMD_MIS_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_MIS_LFGEARRSTRT_S 16U |
| #define CKMD_MIS_AMPSETTLED 0x00008000U |
| #define CKMD_MIS_AMPSETTLED_M 0x00008000U |
| #define CKMD_MIS_AMPSETTLED_S 15U |
| #define CKMD_MIS_AMPCTRLATTARG 0x00004000U |
| #define CKMD_MIS_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_MIS_AMPCTRLATTARG_S 14U |
| #define CKMD_MIS_PRELFEDGE 0x00002000U |
| #define CKMD_MIS_PRELFEDGE_M 0x00002000U |
| #define CKMD_MIS_PRELFEDGE_S 13U |
| #define CKMD_MIS_LFCLKLOSS 0x00001000U |
| #define CKMD_MIS_LFCLKLOSS_M 0x00001000U |
| #define CKMD_MIS_LFCLKLOSS_S 12U |
| #define CKMD_MIS_LFCLKOOR 0x00000800U |
| #define CKMD_MIS_LFCLKOOR_M 0x00000800U |
| #define CKMD_MIS_LFCLKOOR_S 11U |
| #define CKMD_MIS_LFCLKGOOD 0x00000400U |
| #define CKMD_MIS_LFCLKGOOD_M 0x00000400U |
| #define CKMD_MIS_LFCLKGOOD_S 10U |
| #define CKMD_MIS_LFINCUPD 0x00000200U |
| #define CKMD_MIS_LFINCUPD_M 0x00000200U |
| #define CKMD_MIS_LFINCUPD_S 9U |
| #define CKMD_MIS_TDCDONE 0x00000100U |
| #define CKMD_MIS_TDCDONE_M 0x00000100U |
| #define CKMD_MIS_TDCDONE_S 8U |
| #define CKMD_MIS_ADCPEAKUPD 0x00000080U |
| #define CKMD_MIS_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_MIS_ADCPEAKUPD_S 7U |
| #define CKMD_MIS_ADCBIASUPD 0x00000040U |
| #define CKMD_MIS_ADCBIASUPD_M 0x00000040U |
| #define CKMD_MIS_ADCBIASUPD_S 6U |
| #define CKMD_MIS_ADCCOMPUPD 0x00000020U |
| #define CKMD_MIS_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_MIS_ADCCOMPUPD_S 5U |
| #define CKMD_MIS_TRACKREFOOR 0x00000010U |
| #define CKMD_MIS_TRACKREFOOR_M 0x00000010U |
| #define CKMD_MIS_TRACKREFOOR_S 4U |
| #define CKMD_MIS_TRACKREFLOSS 0x00000008U |
| #define CKMD_MIS_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_MIS_TRACKREFLOSS_S 3U |
| #define CKMD_MIS_HFXTAMPGOOD 0x00000004U |
| #define CKMD_MIS_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_MIS_HFXTAMPGOOD_S 2U |
| #define CKMD_MIS_HFXTFAULT 0x00000002U |
| #define CKMD_MIS_HFXTFAULT_M 0x00000002U |
| #define CKMD_MIS_HFXTFAULT_S 1U |
| #define CKMD_MIS_HFXTGOOD 0x00000001U |
| #define CKMD_MIS_HFXTGOOD_M 0x00000001U |
| #define CKMD_MIS_HFXTGOOD_S 0U |
| #define CKMD_ISET_LFTICK 0x00020000U |
| #define CKMD_ISET_LFTICK_M 0x00020000U |
| #define CKMD_ISET_LFTICK_S 17U |
| #define CKMD_ISET_LFGEARRSTRT 0x00010000U |
| #define CKMD_ISET_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_ISET_LFGEARRSTRT_S 16U |
| #define CKMD_ISET_AMPSETTLED 0x00008000U |
| #define CKMD_ISET_AMPSETTLED_M 0x00008000U |
| #define CKMD_ISET_AMPSETTLED_S 15U |
| #define CKMD_ISET_AMPCTRLATTARG 0x00004000U |
| #define CKMD_ISET_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_ISET_AMPCTRLATTARG_S 14U |
| #define CKMD_ISET_PRELFEDGE 0x00002000U |
| #define CKMD_ISET_PRELFEDGE_M 0x00002000U |
| #define CKMD_ISET_PRELFEDGE_S 13U |
| #define CKMD_ISET_LFCLKLOSS 0x00001000U |
| #define CKMD_ISET_LFCLKLOSS_M 0x00001000U |
| #define CKMD_ISET_LFCLKLOSS_S 12U |
| #define CKMD_ISET_LFCLKOOR 0x00000800U |
| #define CKMD_ISET_LFCLKOOR_M 0x00000800U |
| #define CKMD_ISET_LFCLKOOR_S 11U |
| #define CKMD_ISET_LFCLKGOOD 0x00000400U |
| #define CKMD_ISET_LFCLKGOOD_M 0x00000400U |
| #define CKMD_ISET_LFCLKGOOD_S 10U |
| #define CKMD_ISET_LFINCUPD 0x00000200U |
| #define CKMD_ISET_LFINCUPD_M 0x00000200U |
| #define CKMD_ISET_LFINCUPD_S 9U |
| #define CKMD_ISET_TDCDONE 0x00000100U |
| #define CKMD_ISET_TDCDONE_M 0x00000100U |
| #define CKMD_ISET_TDCDONE_S 8U |
| #define CKMD_ISET_ADCPEAKUPD 0x00000080U |
| #define CKMD_ISET_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_ISET_ADCPEAKUPD_S 7U |
| #define CKMD_ISET_ADCBIASUPD 0x00000040U |
| #define CKMD_ISET_ADCBIASUPD_M 0x00000040U |
| #define CKMD_ISET_ADCBIASUPD_S 6U |
| #define CKMD_ISET_ADCCOMPUPD 0x00000020U |
| #define CKMD_ISET_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_ISET_ADCCOMPUPD_S 5U |
| #define CKMD_ISET_TRACKREFOOR 0x00000010U |
| #define CKMD_ISET_TRACKREFOOR_M 0x00000010U |
| #define CKMD_ISET_TRACKREFOOR_S 4U |
| #define CKMD_ISET_TRACKREFLOSS 0x00000008U |
| #define CKMD_ISET_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_ISET_TRACKREFLOSS_S 3U |
| #define CKMD_ISET_HFXTAMPGOOD 0x00000004U |
| #define CKMD_ISET_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_ISET_HFXTAMPGOOD_S 2U |
| #define CKMD_ISET_HFXTFAULT 0x00000002U |
| #define CKMD_ISET_HFXTFAULT_M 0x00000002U |
| #define CKMD_ISET_HFXTFAULT_S 1U |
| #define CKMD_ISET_HFXTGOOD 0x00000001U |
| #define CKMD_ISET_HFXTGOOD_M 0x00000001U |
| #define CKMD_ISET_HFXTGOOD_S 0U |
| #define CKMD_ICLR_LFTICK 0x00020000U |
| #define CKMD_ICLR_LFTICK_M 0x00020000U |
| #define CKMD_ICLR_LFTICK_S 17U |
| #define CKMD_ICLR_LFGEARRSTRT 0x00010000U |
| #define CKMD_ICLR_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_ICLR_LFGEARRSTRT_S 16U |
| #define CKMD_ICLR_AMPSETTLED 0x00008000U |
| #define CKMD_ICLR_AMPSETTLED_M 0x00008000U |
| #define CKMD_ICLR_AMPSETTLED_S 15U |
| #define CKMD_ICLR_AMPCTRLATTARG 0x00004000U |
| #define CKMD_ICLR_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_ICLR_AMPCTRLATTARG_S 14U |
| #define CKMD_ICLR_PRELFEDGE 0x00002000U |
| #define CKMD_ICLR_PRELFEDGE_M 0x00002000U |
| #define CKMD_ICLR_PRELFEDGE_S 13U |
| #define CKMD_ICLR_LFCLKLOSS 0x00001000U |
| #define CKMD_ICLR_LFCLKLOSS_M 0x00001000U |
| #define CKMD_ICLR_LFCLKLOSS_S 12U |
| #define CKMD_ICLR_LFCLKOOR 0x00000800U |
| #define CKMD_ICLR_LFCLKOOR_M 0x00000800U |
| #define CKMD_ICLR_LFCLKOOR_S 11U |
| #define CKMD_ICLR_LFCLKGOOD 0x00000400U |
| #define CKMD_ICLR_LFCLKGOOD_M 0x00000400U |
| #define CKMD_ICLR_LFCLKGOOD_S 10U |
| #define CKMD_ICLR_LFINCUPD 0x00000200U |
| #define CKMD_ICLR_LFINCUPD_M 0x00000200U |
| #define CKMD_ICLR_LFINCUPD_S 9U |
| #define CKMD_ICLR_TDCDONE 0x00000100U |
| #define CKMD_ICLR_TDCDONE_M 0x00000100U |
| #define CKMD_ICLR_TDCDONE_S 8U |
| #define CKMD_ICLR_ADCPEAKUPD 0x00000080U |
| #define CKMD_ICLR_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_ICLR_ADCPEAKUPD_S 7U |
| #define CKMD_ICLR_ADCBIASUPD 0x00000040U |
| #define CKMD_ICLR_ADCBIASUPD_M 0x00000040U |
| #define CKMD_ICLR_ADCBIASUPD_S 6U |
| #define CKMD_ICLR_ADCCOMPUPD 0x00000020U |
| #define CKMD_ICLR_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_ICLR_ADCCOMPUPD_S 5U |
| #define CKMD_ICLR_TRACKREFOOR 0x00000010U |
| #define CKMD_ICLR_TRACKREFOOR_M 0x00000010U |
| #define CKMD_ICLR_TRACKREFOOR_S 4U |
| #define CKMD_ICLR_TRACKREFLOSS 0x00000008U |
| #define CKMD_ICLR_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_ICLR_TRACKREFLOSS_S 3U |
| #define CKMD_ICLR_HFXTAMPGOOD 0x00000004U |
| #define CKMD_ICLR_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_ICLR_HFXTAMPGOOD_S 2U |
| #define CKMD_ICLR_HFXTFAULT 0x00000002U |
| #define CKMD_ICLR_HFXTFAULT_M 0x00000002U |
| #define CKMD_ICLR_HFXTFAULT_S 1U |
| #define CKMD_ICLR_HFXTGOOD 0x00000001U |
| #define CKMD_ICLR_HFXTGOOD_M 0x00000001U |
| #define CKMD_ICLR_HFXTGOOD_S 0U |
| #define CKMD_IMSET_LFTICK 0x00020000U |
| #define CKMD_IMSET_LFTICK_M 0x00020000U |
| #define CKMD_IMSET_LFTICK_S 17U |
| #define CKMD_IMSET_LFGEARRSTRT 0x00010000U |
| #define CKMD_IMSET_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_IMSET_LFGEARRSTRT_S 16U |
| #define CKMD_IMSET_AMPSETTLED 0x00008000U |
| #define CKMD_IMSET_AMPSETTLED_M 0x00008000U |
| #define CKMD_IMSET_AMPSETTLED_S 15U |
| #define CKMD_IMSET_AMPCTRLATTARG 0x00004000U |
| #define CKMD_IMSET_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_IMSET_AMPCTRLATTARG_S 14U |
| #define CKMD_IMSET_PRELFEDGE 0x00002000U |
| #define CKMD_IMSET_PRELFEDGE_M 0x00002000U |
| #define CKMD_IMSET_PRELFEDGE_S 13U |
| #define CKMD_IMSET_LFCLKLOSS 0x00001000U |
| #define CKMD_IMSET_LFCLKLOSS_M 0x00001000U |
| #define CKMD_IMSET_LFCLKLOSS_S 12U |
| #define CKMD_IMSET_LFCLKOOR 0x00000800U |
| #define CKMD_IMSET_LFCLKOOR_M 0x00000800U |
| #define CKMD_IMSET_LFCLKOOR_S 11U |
| #define CKMD_IMSET_LFCLKGOOD 0x00000400U |
| #define CKMD_IMSET_LFCLKGOOD_M 0x00000400U |
| #define CKMD_IMSET_LFCLKGOOD_S 10U |
| #define CKMD_IMSET_LFINCUPD 0x00000200U |
| #define CKMD_IMSET_LFINCUPD_M 0x00000200U |
| #define CKMD_IMSET_LFINCUPD_S 9U |
| #define CKMD_IMSET_TDCDONE 0x00000100U |
| #define CKMD_IMSET_TDCDONE_M 0x00000100U |
| #define CKMD_IMSET_TDCDONE_S 8U |
| #define CKMD_IMSET_ADCPEAKUPD 0x00000080U |
| #define CKMD_IMSET_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_IMSET_ADCPEAKUPD_S 7U |
| #define CKMD_IMSET_ADCBIASUPD 0x00000040U |
| #define CKMD_IMSET_ADCBIASUPD_M 0x00000040U |
| #define CKMD_IMSET_ADCBIASUPD_S 6U |
| #define CKMD_IMSET_ADCCOMPUPD 0x00000020U |
| #define CKMD_IMSET_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_IMSET_ADCCOMPUPD_S 5U |
| #define CKMD_IMSET_TRACKREFOOR 0x00000010U |
| #define CKMD_IMSET_TRACKREFOOR_M 0x00000010U |
| #define CKMD_IMSET_TRACKREFOOR_S 4U |
| #define CKMD_IMSET_TRACKREFLOSS 0x00000008U |
| #define CKMD_IMSET_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_IMSET_TRACKREFLOSS_S 3U |
| #define CKMD_IMSET_HFXTAMPGOOD 0x00000004U |
| #define CKMD_IMSET_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_IMSET_HFXTAMPGOOD_S 2U |
| #define CKMD_IMSET_HFXTFAULT 0x00000002U |
| #define CKMD_IMSET_HFXTFAULT_M 0x00000002U |
| #define CKMD_IMSET_HFXTFAULT_S 1U |
| #define CKMD_IMSET_HFXTGOOD 0x00000001U |
| #define CKMD_IMSET_HFXTGOOD_M 0x00000001U |
| #define CKMD_IMSET_HFXTGOOD_S 0U |
| #define CKMD_IMCLR_LFTICK 0x00020000U |
| #define CKMD_IMCLR_LFTICK_M 0x00020000U |
| #define CKMD_IMCLR_LFTICK_S 17U |
| #define CKMD_IMCLR_LFGEARRSTRT 0x00010000U |
| #define CKMD_IMCLR_LFGEARRSTRT_M 0x00010000U |
| #define CKMD_IMCLR_LFGEARRSTRT_S 16U |
| #define CKMD_IMCLR_AMPSETTLED 0x00008000U |
| #define CKMD_IMCLR_AMPSETTLED_M 0x00008000U |
| #define CKMD_IMCLR_AMPSETTLED_S 15U |
| #define CKMD_IMCLR_AMPCTRLATTARG 0x00004000U |
| #define CKMD_IMCLR_AMPCTRLATTARG_M 0x00004000U |
| #define CKMD_IMCLR_AMPCTRLATTARG_S 14U |
| #define CKMD_IMCLR_PRELFEDGE 0x00002000U |
| #define CKMD_IMCLR_PRELFEDGE_M 0x00002000U |
| #define CKMD_IMCLR_PRELFEDGE_S 13U |
| #define CKMD_IMCLR_LFCLKLOSS 0x00001000U |
| #define CKMD_IMCLR_LFCLKLOSS_M 0x00001000U |
| #define CKMD_IMCLR_LFCLKLOSS_S 12U |
| #define CKMD_IMCLR_LFCLKOOR 0x00000800U |
| #define CKMD_IMCLR_LFCLKOOR_M 0x00000800U |
| #define CKMD_IMCLR_LFCLKOOR_S 11U |
| #define CKMD_IMCLR_LFCLKGOOD 0x00000400U |
| #define CKMD_IMCLR_LFCLKGOOD_M 0x00000400U |
| #define CKMD_IMCLR_LFCLKGOOD_S 10U |
| #define CKMD_IMCLR_LFINCUPD 0x00000200U |
| #define CKMD_IMCLR_LFINCUPD_M 0x00000200U |
| #define CKMD_IMCLR_LFINCUPD_S 9U |
| #define CKMD_IMCLR_TDCDONE 0x00000100U |
| #define CKMD_IMCLR_TDCDONE_M 0x00000100U |
| #define CKMD_IMCLR_TDCDONE_S 8U |
| #define CKMD_IMCLR_ADCPEAKUPD 0x00000080U |
| #define CKMD_IMCLR_ADCPEAKUPD_M 0x00000080U |
| #define CKMD_IMCLR_ADCPEAKUPD_S 7U |
| #define CKMD_IMCLR_ADCBIASUPD 0x00000040U |
| #define CKMD_IMCLR_ADCBIASUPD_M 0x00000040U |
| #define CKMD_IMCLR_ADCBIASUPD_S 6U |
| #define CKMD_IMCLR_ADCCOMPUPD 0x00000020U |
| #define CKMD_IMCLR_ADCCOMPUPD_M 0x00000020U |
| #define CKMD_IMCLR_ADCCOMPUPD_S 5U |
| #define CKMD_IMCLR_TRACKREFOOR 0x00000010U |
| #define CKMD_IMCLR_TRACKREFOOR_M 0x00000010U |
| #define CKMD_IMCLR_TRACKREFOOR_S 4U |
| #define CKMD_IMCLR_TRACKREFLOSS 0x00000008U |
| #define CKMD_IMCLR_TRACKREFLOSS_M 0x00000008U |
| #define CKMD_IMCLR_TRACKREFLOSS_S 3U |
| #define CKMD_IMCLR_HFXTAMPGOOD 0x00000004U |
| #define CKMD_IMCLR_HFXTAMPGOOD_M 0x00000004U |
| #define CKMD_IMCLR_HFXTAMPGOOD_S 2U |
| #define CKMD_IMCLR_HFXTFAULT 0x00000002U |
| #define CKMD_IMCLR_HFXTFAULT_M 0x00000002U |
| #define CKMD_IMCLR_HFXTFAULT_S 1U |
| #define CKMD_IMCLR_HFXTGOOD 0x00000001U |
| #define CKMD_IMCLR_HFXTGOOD_M 0x00000001U |
| #define CKMD_IMCLR_HFXTGOOD_S 0U |
| #define CKMD_HFOSCCTL_PW_W 8U |
| #define CKMD_HFOSCCTL_PW_M 0xFF000000U |
| #define CKMD_HFOSCCTL_PW_S 24U |
| #define CKMD_HFOSCCTL_CLKSVTOVR 0x00000100U |
| #define CKMD_HFOSCCTL_CLKSVTOVR_M 0x00000100U |
| #define CKMD_HFOSCCTL_CLKSVTOVR_S 8U |
| #define CKMD_HFOSCCTL_CLKSVTOVR_HFXT 0x00000100U |
| #define CKMD_HFOSCCTL_CLKSVTOVR_HFOSC 0x00000000U |
| #define CKMD_HFOSCCTL_FORCEOFF 0x00000002U |
| #define CKMD_HFOSCCTL_FORCEOFF_M 0x00000002U |
| #define CKMD_HFOSCCTL_FORCEOFF_S 1U |
| #define CKMD_HFOSCCTL_QUALBYP 0x00000001U |
| #define CKMD_HFOSCCTL_QUALBYP_M 0x00000001U |
| #define CKMD_HFOSCCTL_QUALBYP_S 0U |
| #define CKMD_HFXTCTL_AMPOVR 0x80000000U |
| #define CKMD_HFXTCTL_AMPOVR_M 0x80000000U |
| #define CKMD_HFXTCTL_AMPOVR_S 31U |
| #define CKMD_HFXTCTL_BIASEN 0x04000000U |
| #define CKMD_HFXTCTL_BIASEN_M 0x04000000U |
| #define CKMD_HFXTCTL_BIASEN_S 26U |
| #define CKMD_HFXTCTL_LPBUFEN 0x02000000U |
| #define CKMD_HFXTCTL_LPBUFEN_M 0x02000000U |
| #define CKMD_HFXTCTL_LPBUFEN_S 25U |
| #define CKMD_HFXTCTL_INJECT 0x01000000U |
| #define CKMD_HFXTCTL_INJECT_M 0x01000000U |
| #define CKMD_HFXTCTL_INJECT_S 24U |
| #define CKMD_HFXTCTL_QUALBYP 0x00800000U |
| #define CKMD_HFXTCTL_QUALBYP_M 0x00800000U |
| #define CKMD_HFXTCTL_QUALBYP_S 23U |
| #define CKMD_HFXTCTL_QUALDLY_W 12U |
| #define CKMD_HFXTCTL_QUALDLY_M 0x000FFF00U |
| #define CKMD_HFXTCTL_QUALDLY_S 8U |
| #define CKMD_HFXTCTL_TCXOMODE 0x00000080U |
| #define CKMD_HFXTCTL_TCXOMODE_M 0x00000080U |
| #define CKMD_HFXTCTL_TCXOMODE_S 7U |
| #define CKMD_HFXTCTL_TCXOTYPE 0x00000040U |
| #define CKMD_HFXTCTL_TCXOTYPE_M 0x00000040U |
| #define CKMD_HFXTCTL_TCXOTYPE_S 6U |
| #define CKMD_HFXTCTL_TCXOTYPE_CMOS 0x00000040U |
| #define CKMD_HFXTCTL_TCXOTYPE_CLIPPEDSINE 0x00000000U |
| #define CKMD_HFXTCTL_AUTOEN 0x00000004U |
| #define CKMD_HFXTCTL_AUTOEN_M 0x00000004U |
| #define CKMD_HFXTCTL_AUTOEN_S 2U |
| #define CKMD_HFXTCTL_HPBUFEN 0x00000002U |
| #define CKMD_HFXTCTL_HPBUFEN_M 0x00000002U |
| #define CKMD_HFXTCTL_HPBUFEN_S 1U |
| #define CKMD_HFXTCTL_EN 0x00000001U |
| #define CKMD_HFXTCTL_EN_M 0x00000001U |
| #define CKMD_HFXTCTL_EN_S 0U |
| #define CKMD_LFOSCCTL_EN 0x00000001U |
| #define CKMD_LFOSCCTL_EN_M 0x00000001U |
| #define CKMD_LFOSCCTL_EN_S 0U |
| #define CKMD_LFXTCTL_LEAKCOMP_W 2U |
| #define CKMD_LFXTCTL_LEAKCOMP_M 0x00006000U |
| #define CKMD_LFXTCTL_LEAKCOMP_S 13U |
| #define CKMD_LFXTCTL_LEAKCOMP_OFF 0x00006000U |
| #define CKMD_LFXTCTL_LEAKCOMP_HALF 0x00002000U |
| #define CKMD_LFXTCTL_LEAKCOMP_FULL 0x00000000U |
| #define CKMD_LFXTCTL_BUFBIAS 0x00001000U |
| #define CKMD_LFXTCTL_BUFBIAS_M 0x00001000U |
| #define CKMD_LFXTCTL_BUFBIAS_S 12U |
| #define CKMD_LFXTCTL_BUFBIAS_MAX 0x00001000U |
| #define CKMD_LFXTCTL_BUFBIAS_MIN 0x00000000U |
| #define CKMD_LFXTCTL_AMPBIAS_W 4U |
| #define CKMD_LFXTCTL_AMPBIAS_M 0x00000F00U |
| #define CKMD_LFXTCTL_AMPBIAS_S 8U |
| #define CKMD_LFXTCTL_BIASBOOST_W 2U |
| #define CKMD_LFXTCTL_BIASBOOST_M 0x000000C0U |
| #define CKMD_LFXTCTL_BIASBOOST_S 6U |
| #define CKMD_LFXTCTL_REGBIAS_W 2U |
| #define CKMD_LFXTCTL_REGBIAS_M 0x00000030U |
| #define CKMD_LFXTCTL_REGBIAS_S 4U |
| #define CKMD_LFXTCTL_HPBUFEN 0x00000004U |
| #define CKMD_LFXTCTL_HPBUFEN_M 0x00000004U |
| #define CKMD_LFXTCTL_HPBUFEN_S 2U |
| #define CKMD_LFXTCTL_AMPREGMODE 0x00000002U |
| #define CKMD_LFXTCTL_AMPREGMODE_M 0x00000002U |
| #define CKMD_LFXTCTL_AMPREGMODE_S 1U |
| #define CKMD_LFXTCTL_AMPREGMODE_LOOPDIS 0x00000002U |
| #define CKMD_LFXTCTL_AMPREGMODE_LOOPEN 0x00000000U |
| #define CKMD_LFXTCTL_EN 0x00000001U |
| #define CKMD_LFXTCTL_EN_M 0x00000001U |
| #define CKMD_LFXTCTL_EN_S 0U |
| #define CKMD_LFQUALCTL_MAXERR_W 6U |
| #define CKMD_LFQUALCTL_MAXERR_M 0x00003F00U |
| #define CKMD_LFQUALCTL_MAXERR_S 8U |
| #define CKMD_LFQUALCTL_CONSEC_W 8U |
| #define CKMD_LFQUALCTL_CONSEC_M 0x000000FFU |
| #define CKMD_LFQUALCTL_CONSEC_S 0U |
| #define CKMD_LFINCCTL_PREVENTSTBY 0x80000000U |
| #define CKMD_LFINCCTL_PREVENTSTBY_M 0x80000000U |
| #define CKMD_LFINCCTL_PREVENTSTBY_S 31U |
| #define CKMD_LFINCCTL_PREVENTSTBY_ON 0x80000000U |
| #define CKMD_LFINCCTL_PREVENTSTBY_OFF 0x00000000U |
| #define CKMD_LFINCCTL_INT_W 22U |
| #define CKMD_LFINCCTL_INT_M 0x3FFFFF00U |
| #define CKMD_LFINCCTL_INT_S 8U |
| #define CKMD_LFINCCTL_STOPGEAR 0x00000080U |
| #define CKMD_LFINCCTL_STOPGEAR_M 0x00000080U |
| #define CKMD_LFINCCTL_STOPGEAR_S 7U |
| #define CKMD_LFINCCTL_STOPGEAR_HIGH 0x00000080U |
| #define CKMD_LFINCCTL_STOPGEAR_LOW 0x00000000U |
| #define CKMD_LFINCCTL_ERRTHR_W 2U |
| #define CKMD_LFINCCTL_ERRTHR_M 0x00000060U |
| #define CKMD_LFINCCTL_ERRTHR_S 5U |
| #define CKMD_LFINCCTL_ERRTHR_SMALL 0x00000060U |
| #define CKMD_LFINCCTL_ERRTHR_MIDSMALL 0x00000040U |
| #define CKMD_LFINCCTL_ERRTHR_MIDLARGE 0x00000020U |
| #define CKMD_LFINCCTL_ERRTHR_LARGE 0x00000000U |
| #define CKMD_LFINCCTL_GEARRSTRT_W 2U |
| #define CKMD_LFINCCTL_GEARRSTRT_M 0x00000018U |
| #define CKMD_LFINCCTL_GEARRSTRT_S 3U |
| #define CKMD_LFINCCTL_GEARRSTRT_TWOTHR 0x00000010U |
| #define CKMD_LFINCCTL_GEARRSTRT_ONETHR 0x00000008U |
| #define CKMD_LFINCCTL_GEARRSTRT_NEVER 0x00000000U |
| #define CKMD_LFINCCTL_SOFTRSTRT 0x00000004U |
| #define CKMD_LFINCCTL_SOFTRSTRT_M 0x00000004U |
| #define CKMD_LFINCCTL_SOFTRSTRT_S 2U |
| #define CKMD_LFINCCTL_SOFTRSTRT_ON 0x00000004U |
| #define CKMD_LFINCCTL_SOFTRSTRT_OFF 0x00000000U |
| #define CKMD_LFINCOVR_OVERRIDE 0x80000000U |
| #define CKMD_LFINCOVR_OVERRIDE_M 0x80000000U |
| #define CKMD_LFINCOVR_OVERRIDE_S 31U |
| #define CKMD_LFINCOVR_LFINC_W 22U |
| #define CKMD_LFINCOVR_LFINC_M 0x003FFFFFU |
| #define CKMD_LFINCOVR_LFINC_S 0U |
| #define CKMD_AMPADCCTL_SWOVR 0x80000000U |
| #define CKMD_AMPADCCTL_SWOVR_M 0x80000000U |
| #define CKMD_AMPADCCTL_SWOVR_S 31U |
| #define CKMD_AMPADCCTL_PEAKDETEN 0x00020000U |
| #define CKMD_AMPADCCTL_PEAKDETEN_M 0x00020000U |
| #define CKMD_AMPADCCTL_PEAKDETEN_S 17U |
| #define CKMD_AMPADCCTL_PEAKDETEN_ENABLE 0x00020000U |
| #define CKMD_AMPADCCTL_PEAKDETEN_DISABLE 0x00000000U |
| #define CKMD_AMPADCCTL_ADCEN 0x00010000U |
| #define CKMD_AMPADCCTL_ADCEN_M 0x00010000U |
| #define CKMD_AMPADCCTL_ADCEN_S 16U |
| #define CKMD_AMPADCCTL_ADCEN_ENABLE 0x00010000U |
| #define CKMD_AMPADCCTL_ADCEN_DISABLE 0x00000000U |
| #define CKMD_AMPADCCTL_COMPVAL_W 7U |
| #define CKMD_AMPADCCTL_COMPVAL_M 0x00007F00U |
| #define CKMD_AMPADCCTL_COMPVAL_S 8U |
| #define CKMD_AMPADCCTL_SRCSEL 0x00000010U |
| #define CKMD_AMPADCCTL_SRCSEL_M 0x00000010U |
| #define CKMD_AMPADCCTL_SRCSEL_S 4U |
| #define CKMD_AMPADCCTL_SRCSEL_PEAK 0x00000010U |
| #define CKMD_AMPADCCTL_SRCSEL_BIAS 0x00000000U |
| #define CKMD_AMPADCCTL_COMPSTRT 0x00000002U |
| #define CKMD_AMPADCCTL_COMPSTRT_M 0x00000002U |
| #define CKMD_AMPADCCTL_COMPSTRT_S 1U |
| #define CKMD_AMPADCCTL_SARSTRT 0x00000001U |
| #define CKMD_AMPADCCTL_SARSTRT_M 0x00000001U |
| #define CKMD_AMPADCCTL_SARSTRT_S 0U |
| #define CKMD_HFTRACKCTL_EN 0x80000000U |
| #define CKMD_HFTRACKCTL_EN_M 0x80000000U |
| #define CKMD_HFTRACKCTL_EN_S 31U |
| #define CKMD_HFTRACKCTL_DSMBYP 0x40000000U |
| #define CKMD_HFTRACKCTL_DSMBYP_M 0x40000000U |
| #define CKMD_HFTRACKCTL_DSMBYP_S 30U |
| #define CKMD_HFTRACKCTL_REFCLK_W 2U |
| #define CKMD_HFTRACKCTL_REFCLK_M 0x0C000000U |
| #define CKMD_HFTRACKCTL_REFCLK_S 26U |
| #define CKMD_HFTRACKCTL_REFCLK_GPI 0x08000000U |
| #define CKMD_HFTRACKCTL_REFCLK_LRF 0x04000000U |
| #define CKMD_HFTRACKCTL_REFCLK_HFXT 0x00000000U |
| #define CKMD_HFTRACKCTL_RATIO_W 26U |
| #define CKMD_HFTRACKCTL_RATIO_M 0x03FFFFFFU |
| #define CKMD_HFTRACKCTL_RATIO_S 0U |
| #define CKMD_HFTRACKCTL_RATIO_REF4M 0x03000000U |
| #define CKMD_HFTRACKCTL_RATIO_REF8M 0x01800000U |
| #define CKMD_HFTRACKCTL_RATIO_REF48M 0x00400000U |
| #define CKMD_LDOCTL_SWOVR 0x80000000U |
| #define CKMD_LDOCTL_SWOVR_M 0x80000000U |
| #define CKMD_LDOCTL_SWOVR_S 31U |
| #define CKMD_LDOCTL_HFXTLVLEN 0x00000010U |
| #define CKMD_LDOCTL_HFXTLVLEN_M 0x00000010U |
| #define CKMD_LDOCTL_HFXTLVLEN_S 4U |
| #define CKMD_LDOCTL_STARTCTL 0x00000008U |
| #define CKMD_LDOCTL_STARTCTL_M 0x00000008U |
| #define CKMD_LDOCTL_STARTCTL_S 3U |
| #define CKMD_LDOCTL_START 0x00000004U |
| #define CKMD_LDOCTL_START_M 0x00000004U |
| #define CKMD_LDOCTL_START_S 2U |
| #define CKMD_LDOCTL_BYPASS 0x00000002U |
| #define CKMD_LDOCTL_BYPASS_M 0x00000002U |
| #define CKMD_LDOCTL_BYPASS_S 1U |
| #define CKMD_LDOCTL_EN 0x00000001U |
| #define CKMD_LDOCTL_EN_M 0x00000001U |
| #define CKMD_LDOCTL_EN_S 0U |
| #define CKMD_NABIASCTL_EN 0x00000001U |
| #define CKMD_NABIASCTL_EN_M 0x00000001U |
| #define CKMD_NABIASCTL_EN_S 0U |
| #define CKMD_LFMONCTL_EN 0x00000001U |
| #define CKMD_LFMONCTL_EN_M 0x00000001U |
| #define CKMD_LFMONCTL_EN_S 0U |
| #define CKMD_LFCLKSEL_PRE_W 2U |
| #define CKMD_LFCLKSEL_PRE_M 0x0000000CU |
| #define CKMD_LFCLKSEL_PRE_S 2U |
| #define CKMD_LFCLKSEL_PRE_EXTLF 0x0000000CU |
| #define CKMD_LFCLKSEL_PRE_LFXT 0x00000008U |
| #define CKMD_LFCLKSEL_PRE_LFOSC 0x00000004U |
| #define CKMD_LFCLKSEL_PRE_NONE 0x00000000U |
| #define CKMD_LFCLKSEL_MAIN_W 2U |
| #define CKMD_LFCLKSEL_MAIN_M 0x00000003U |
| #define CKMD_LFCLKSEL_MAIN_S 0U |
| #define CKMD_LFCLKSEL_MAIN_EXTLF 0x00000003U |
| #define CKMD_LFCLKSEL_MAIN_LFXT 0x00000002U |
| #define CKMD_LFCLKSEL_MAIN_LFOSC 0x00000001U |
| #define CKMD_LFCLKSEL_MAIN_FAKE 0x00000000U |
| #define CKMD_TDCCLKSEL_REFCLK_W 2U |
| #define CKMD_TDCCLKSEL_REFCLK_M 0x00000003U |
| #define CKMD_TDCCLKSEL_REFCLK_S 0U |
| #define CKMD_TDCCLKSEL_REFCLK_GPI 0x00000003U |
| #define CKMD_TDCCLKSEL_REFCLK_CLKULL 0x00000002U |
| #define CKMD_TDCCLKSEL_REFCLK_CLKSVT 0x00000001U |
| #define CKMD_TDCCLKSEL_REFCLK_NONE 0x00000000U |
| #define CKMD_ADCCLKSEL_SRC_W 2U |
| #define CKMD_ADCCLKSEL_SRC_M 0x00000003U |
| #define CKMD_ADCCLKSEL_SRC_S 0U |
| #define CKMD_ADCCLKSEL_SRC_HFXT 0x00000001U |
| #define CKMD_ADCCLKSEL_SRC_CLKSVT 0x00000000U |
| #define CKMD_LFCLKSTAT_GOOD 0x80000000U |
| #define CKMD_LFCLKSTAT_GOOD_M 0x80000000U |
| #define CKMD_LFCLKSTAT_GOOD_S 31U |
| #define CKMD_LFCLKSTAT_FLTSETTLED 0x02000000U |
| #define CKMD_LFCLKSTAT_FLTSETTLED_M 0x02000000U |
| #define CKMD_LFCLKSTAT_FLTSETTLED_S 25U |
| #define CKMD_LFCLKSTAT_LFTICKSRC 0x01000000U |
| #define CKMD_LFCLKSTAT_LFTICKSRC_M 0x01000000U |
| #define CKMD_LFCLKSTAT_LFTICKSRC_S 24U |
| #define CKMD_LFCLKSTAT_LFTICKSRC_FAKE 0x01000000U |
| #define CKMD_LFCLKSTAT_LFTICKSRC_LFCLK 0x00000000U |
| #define CKMD_LFCLKSTAT_LFINCSRC_W 2U |
| #define CKMD_LFCLKSTAT_LFINCSRC_M 0x00C00000U |
| #define CKMD_LFCLKSTAT_LFINCSRC_S 22U |
| #define CKMD_LFCLKSTAT_LFINCSRC_FAKE 0x00C00000U |
| #define CKMD_LFCLKSTAT_LFINCSRC_OVERRIDE 0x00800000U |
| #define CKMD_LFCLKSTAT_LFINCSRC_AVG 0x00400000U |
| #define CKMD_LFCLKSTAT_LFINCSRC_MEAS 0x00000000U |
| #define CKMD_LFCLKSTAT_LFINC_W 22U |
| #define CKMD_LFCLKSTAT_LFINC_M 0x003FFFFFU |
| #define CKMD_LFCLKSTAT_LFINC_S 0U |
| #define CKMD_HFXTSTAT_STARTUPTIME_W 15U |
| #define CKMD_HFXTSTAT_STARTUPTIME_M 0x7FFF0000U |
| #define CKMD_HFXTSTAT_STARTUPTIME_S 16U |
| #define CKMD_HFXTSTAT_FAULT 0x00000002U |
| #define CKMD_HFXTSTAT_FAULT_M 0x00000002U |
| #define CKMD_HFXTSTAT_FAULT_S 1U |
| #define CKMD_HFXTSTAT_GOOD 0x00000001U |
| #define CKMD_HFXTSTAT_GOOD_M 0x00000001U |
| #define CKMD_HFXTSTAT_GOOD_S 0U |
| #define CKMD_AMPADCSTAT_COMPOUT 0x01000000U |
| #define CKMD_AMPADCSTAT_COMPOUT_M 0x01000000U |
| #define CKMD_AMPADCSTAT_COMPOUT_S 24U |
| #define CKMD_AMPADCSTAT_PEAKRAW_W 7U |
| #define CKMD_AMPADCSTAT_PEAKRAW_M 0x007F0000U |
| #define CKMD_AMPADCSTAT_PEAKRAW_S 16U |
| #define CKMD_AMPADCSTAT_PEAK_W 8U |
| #define CKMD_AMPADCSTAT_PEAK_M 0x0000FF00U |
| #define CKMD_AMPADCSTAT_PEAK_S 8U |
| #define CKMD_AMPADCSTAT_BIAS_W 7U |
| #define CKMD_AMPADCSTAT_BIAS_M 0x0000007FU |
| #define CKMD_AMPADCSTAT_BIAS_S 0U |
| #define CKMD_TRACKSTAT_LOOPERRVLD 0x80000000U |
| #define CKMD_TRACKSTAT_LOOPERRVLD_M 0x80000000U |
| #define CKMD_TRACKSTAT_LOOPERRVLD_S 31U |
| #define CKMD_TRACKSTAT_LOOPERR_W 14U |
| #define CKMD_TRACKSTAT_LOOPERR_M 0x3FFF0000U |
| #define CKMD_TRACKSTAT_LOOPERR_S 16U |
| #define CKMD_TRACKSTAT_FINETRIM_W 13U |
| #define CKMD_TRACKSTAT_FINETRIM_M 0x00001FFFU |
| #define CKMD_TRACKSTAT_FINETRIM_S 0U |
| #define CKMD_AMPSTAT_STATE_W 4U |
| #define CKMD_AMPSTAT_STATE_M 0x1E000000U |
| #define CKMD_AMPSTAT_STATE_S 25U |
| #define CKMD_AMPSTAT_STATE_SETTLED 0x1E000000U |
| #define CKMD_AMPSTAT_STATE_UPDATEUP 0x1C000000U |
| #define CKMD_AMPSTAT_STATE_TXCOMODE 0x18000000U |
| #define CKMD_AMPSTAT_STATE_SHUTDN0 0x14000000U |
| #define CKMD_AMPSTAT_STATE_INJWAIT 0x0E000000U |
| #define CKMD_AMPSTAT_STATE_UPDATEDN 0x0C000000U |
| #define CKMD_AMPSTAT_STATE_RAMP0 0x0A000000U |
| #define CKMD_AMPSTAT_STATE_RAMP1 0x08000000U |
| #define CKMD_AMPSTAT_STATE_INJECT 0x06000000U |
| #define CKMD_AMPSTAT_STATE_SHUTDN1 0x04000000U |
| #define CKMD_AMPSTAT_STATE_LDOSTART 0x02000000U |
| #define CKMD_AMPSTAT_STATE_IDLE 0x00000000U |
| #define CKMD_AMPSTAT_IDAC_W 7U |
| #define CKMD_AMPSTAT_IDAC_M 0x01FC0000U |
| #define CKMD_AMPSTAT_IDAC_S 18U |
| #define CKMD_AMPSTAT_IREF_W 4U |
| #define CKMD_AMPSTAT_IREF_M 0x0003C000U |
| #define CKMD_AMPSTAT_IREF_S 14U |
| #define CKMD_AMPSTAT_Q2CAP_W 6U |
| #define CKMD_AMPSTAT_Q2CAP_M 0x00003F00U |
| #define CKMD_AMPSTAT_Q2CAP_S 8U |
| #define CKMD_AMPSTAT_Q1CAP_W 6U |
| #define CKMD_AMPSTAT_Q1CAP_M 0x000000FCU |
| #define CKMD_AMPSTAT_Q1CAP_S 2U |
| #define CKMD_AMPSTAT_CTRLATTARGET 0x00000002U |
| #define CKMD_AMPSTAT_CTRLATTARGET_M 0x00000002U |
| #define CKMD_AMPSTAT_CTRLATTARGET_S 1U |
| #define CKMD_AMPSTAT_AMPGOOD 0x00000001U |
| #define CKMD_AMPSTAT_AMPGOOD_M 0x00000001U |
| #define CKMD_AMPSTAT_AMPGOOD_S 0U |
| #define CKMD_ATBCTL0_SEL_W 19U |
| #define CKMD_ATBCTL0_SEL_M 0x0007FFFFU |
| #define CKMD_ATBCTL0_SEL_S 0U |
| #define CKMD_ATBCTL0_SEL_LFXTTESTCLK 0x00070000U |
| #define CKMD_ATBCTL0_SEL_LFOSCTESTCLK 0x00050000U |
| #define CKMD_ATBCTL0_SEL_HFXTTESTCLK 0x00030000U |
| #define CKMD_ATBCTL0_SEL_HFOSCTESTCLK 0x00010000U |
| #define CKMD_ATBCTL0_SEL_LFMONVTEST 0x00001000U |
| #define CKMD_ATBCTL0_SEL_LFOSCVDDL 0x00000800U |
| #define CKMD_ATBCTL0_SEL_HFOSCIBIAS 0x00000400U |
| #define CKMD_ATBCTL0_SEL_HFOSCVDDL 0x00000200U |
| #define CKMD_ATBCTL0_SEL_HFOSCVREF 0x00000100U |
| #define CKMD_ATBCTL0_SEL_NABIASITEST 0x00000080U |
| #define CKMD_ATBCTL0_SEL_ADCDACOUT 0x00000040U |
| #define CKMD_ATBCTL0_SEL_ADCCOMPIN 0x00000020U |
| #define CKMD_ATBCTL0_SEL_ADCCOMPOUT 0x00000010U |
| #define CKMD_ATBCTL0_SEL_LFXTANA 0x00000008U |
| #define CKMD_ATBCTL0_SEL_LDOITEST 0x00000004U |
| #define CKMD_ATBCTL0_SEL_VDDCKM 0x00000002U |
| #define CKMD_ATBCTL0_SEL_HFXTANA 0x00000001U |
| #define CKMD_ATBCTL0_SEL_OFF 0x00000000U |
| #define CKMD_ATBCTL1_LFOSC_W 2U |
| #define CKMD_ATBCTL1_LFOSC_M 0x00006000U |
| #define CKMD_ATBCTL1_LFOSC_S 13U |
| #define CKMD_ATBCTL1_LFOSC_BOTH 0x00006000U |
| #define CKMD_ATBCTL1_LFOSC_VDDLOCAL 0x00004000U |
| #define CKMD_ATBCTL1_LFOSC_TESTCLK 0x00002000U |
| #define CKMD_ATBCTL1_LFOSC_OFF 0x00000000U |
| #define CKMD_ATBCTL1_NABIAS 0x00001000U |
| #define CKMD_ATBCTL1_NABIAS_M 0x00001000U |
| #define CKMD_ATBCTL1_NABIAS_S 12U |
| #define CKMD_ATBCTL1_LFXT 0x00000400U |
| #define CKMD_ATBCTL1_LFXT_M 0x00000400U |
| #define CKMD_ATBCTL1_LFXT_S 10U |
| #define CKMD_ATBCTL1_LFXT_TESTCLK 0x00000400U |
| #define CKMD_ATBCTL1_LFXT_OFF 0x00000000U |
| #define CKMD_ATBCTL1_LFMON_W 2U |
| #define CKMD_ATBCTL1_LFMON_M 0x00000300U |
| #define CKMD_ATBCTL1_LFMON_S 8U |
| #define CKMD_ATBCTL1_LFMON_TEST2 0x00000200U |
| #define CKMD_ATBCTL1_LFMON_TEST1 0x00000100U |
| #define CKMD_ATBCTL1_LFMON_OFF 0x00000000U |
| #define CKMD_ATBCTL1_HFXT 0x00000080U |
| #define CKMD_ATBCTL1_HFXT_M 0x00000080U |
| #define CKMD_ATBCTL1_HFXT_S 7U |
| #define CKMD_ATBCTL1_HFOSC 0x00000001U |
| #define CKMD_ATBCTL1_HFOSC_M 0x00000001U |
| #define CKMD_ATBCTL1_HFOSC_S 0U |
| #define CKMD_DTBCTL_DSEL2_W 5U |
| #define CKMD_DTBCTL_DSEL2_M 0x007C0000U |
| #define CKMD_DTBCTL_DSEL2_S 18U |
| #define CKMD_DTBCTL_DSEL1_W 5U |
| #define CKMD_DTBCTL_DSEL1_M 0x0003E000U |
| #define CKMD_DTBCTL_DSEL1_S 13U |
| #define CKMD_DTBCTL_DSEL0_W 5U |
| #define CKMD_DTBCTL_DSEL0_M 0x00001F00U |
| #define CKMD_DTBCTL_DSEL0_S 8U |
| #define CKMD_DTBCTL_CLKSEL_W 4U |
| #define CKMD_DTBCTL_CLKSEL_M 0x000000F0U |
| #define CKMD_DTBCTL_CLKSEL_S 4U |
| #define CKMD_DTBCTL_CLKSEL_LFXT 0x000000F0U |
| #define CKMD_DTBCTL_CLKSEL_LFOSC 0x000000E0U |
| #define CKMD_DTBCTL_CLKSEL_HFXT 0x000000D0U |
| #define CKMD_DTBCTL_CLKSEL_HFXTBY8 0x000000C0U |
| #define CKMD_DTBCTL_CLKSEL_HFOSC 0x000000A0U |
| #define CKMD_DTBCTL_CLKSEL_LFCLK 0x00000070U |
| #define CKMD_DTBCTL_CLKSEL_TRACKREF 0x00000040U |
| #define CKMD_DTBCTL_CLKSEL_CLKADC 0x00000020U |
| #define CKMD_DTBCTL_CLKSEL_CLKSVT 0x00000010U |
| #define CKMD_DTBCTL_CLKSEL_CLKULL 0x00000000U |
| #define CKMD_DTBCTL_EN 0x00000001U |
| #define CKMD_DTBCTL_EN_M 0x00000001U |
| #define CKMD_DTBCTL_EN_S 0U |
| #define CKMD_TRIM0_HFOSC_CAP_W 4U |
| #define CKMD_TRIM0_HFOSC_CAP_M 0x000001E0U |
| #define CKMD_TRIM0_HFOSC_CAP_S 5U |
| #define CKMD_TRIM0_HFOSC_COARSE_W 5U |
| #define CKMD_TRIM0_HFOSC_COARSE_M 0x0000001FU |
| #define CKMD_TRIM0_HFOSC_COARSE_S 0U |
| #define CKMD_TRIM1_HFXTSLICER_W 2U |
| #define CKMD_TRIM1_HFXTSLICER_M 0xC0000000U |
| #define CKMD_TRIM1_HFXTSLICER_S 30U |
| #define CKMD_TRIM1_PEAKIBIAS_W 2U |
| #define CKMD_TRIM1_PEAKIBIAS_M 0x30000000U |
| #define CKMD_TRIM1_PEAKIBIAS_S 28U |
| #define CKMD_TRIM1_NABIAS_UDIGLDO 0x08000000U |
| #define CKMD_TRIM1_NABIAS_UDIGLDO_M 0x08000000U |
| #define CKMD_TRIM1_NABIAS_UDIGLDO_S 27U |
| #define CKMD_TRIM1_LDOBW_W 3U |
| #define CKMD_TRIM1_LDOBW_M 0x07000000U |
| #define CKMD_TRIM1_LDOBW_S 24U |
| #define CKMD_TRIM1_LDOFB_W 4U |
| #define CKMD_TRIM1_LDOFB_M 0x00F00000U |
| #define CKMD_TRIM1_LDOFB_S 20U |
| #define CKMD_TRIM1_LFDLY_W 4U |
| #define CKMD_TRIM1_LFDLY_M 0x000F0000U |
| #define CKMD_TRIM1_LFDLY_S 16U |
| #define CKMD_TRIM1_NABIAS_LFOSC 0x00008000U |
| #define CKMD_TRIM1_NABIAS_LFOSC_M 0x00008000U |
| #define CKMD_TRIM1_NABIAS_LFOSC_S 15U |
| #define CKMD_TRIM1_NABIAS_RES_W 7U |
| #define CKMD_TRIM1_NABIAS_RES_M 0x00007F00U |
| #define CKMD_TRIM1_NABIAS_RES_S 8U |
| #define CKMD_TRIM1_LFOSC_CAP_W 8U |
| #define CKMD_TRIM1_LFOSC_CAP_M 0x000000FFU |
| #define CKMD_TRIM1_LFOSC_CAP_S 0U |
| #define CKMD_HFXTINIT_AMPTHR_W 7U |
| #define CKMD_HFXTINIT_AMPTHR_M 0x3F800000U |
Referenced by CKMDGetInitialAmplitudeThresholdTrim(), and CKMDSetInitialAmplitudeThresholdTrim().
| #define CKMD_HFXTINIT_AMPTHR_S 23U |
| #define CKMD_HFXTINIT_IDAC_W 7U |
| #define CKMD_HFXTINIT_IDAC_M 0x007F0000U |
Referenced by CKMDGetInitialIdacTrim(), and CKMDSetInitialIdacTrim().
| #define CKMD_HFXTINIT_IDAC_S 16U |
Referenced by CKMDGetInitialIdacTrim(), CKMDSetInitialIdacTrim(), and SetupTrimDevice().
| #define CKMD_HFXTINIT_IREF_W 4U |
| #define CKMD_HFXTINIT_IREF_M 0x0000F000U |
Referenced by CKMDGetInitialIrefTrim(), and CKMDSetInitialIrefTrim().
| #define CKMD_HFXTINIT_IREF_S 12U |
Referenced by CKMDGetInitialIrefTrim(), CKMDSetInitialIrefTrim(), and SetupTrimDevice().
| #define CKMD_HFXTINIT_Q2CAP_W 6U |
| #define CKMD_HFXTINIT_Q2CAP_M 0x00000FC0U |
Referenced by CKMDGetInitialQ2CapTrim(), CKMDSetInitialCapTrim(), and CKMDSetInitialQ2CapTrim().
| #define CKMD_HFXTINIT_Q2CAP_S 6U |
Referenced by CKMDGetInitialQ2CapTrim(), CKMDSetInitialCapTrim(), CKMDSetInitialQ2CapTrim(), and SetupTrimDevice().
| #define CKMD_HFXTINIT_Q1CAP_W 6U |
| #define CKMD_HFXTINIT_Q1CAP_M 0x0000003FU |
Referenced by CKMDGetInitialQ1CapTrim(), CKMDSetInitialCapTrim(), and CKMDSetInitialQ1CapTrim().
| #define CKMD_HFXTINIT_Q1CAP_S 0U |
Referenced by CKMDGetInitialQ1CapTrim(), CKMDSetInitialCapTrim(), CKMDSetInitialQ1CapTrim(), and SetupTrimDevice().
| #define CKMD_HFXTTARG_AMPHYST_W 2U |
| #define CKMD_HFXTTARG_AMPHYST_M 0xC0000000U |
| #define CKMD_HFXTTARG_AMPHYST_S 30U |
Referenced by SetupTrimDevice().
| #define CKMD_HFXTTARG_AMPTHR_W 7U |
| #define CKMD_HFXTTARG_AMPTHR_M 0x3F800000U |
Referenced by CKMDGetTargetAmplitudeThresholdTrim(), and CKMDSetTargetAmplitudeThresholdTrim().
| #define CKMD_HFXTTARG_AMPTHR_S 23U |
Referenced by CKMDGetTargetAmplitudeThresholdTrim(), CKMDSetTargetAmplitudeThresholdTrim(), and SetupTrimDevice().
| #define CKMD_HFXTTARG_IDAC_W 7U |
| #define CKMD_HFXTTARG_IDAC_M 0x007F0000U |
Referenced by CKMDGetTargetIdacTrim(), and CKMDSetTargetIdacTrim().
| #define CKMD_HFXTTARG_IDAC_S 16U |
Referenced by CKMDGetTargetIdacTrim(), CKMDSetTargetIdacTrim(), and SetupTrimDevice().
| #define CKMD_HFXTTARG_IREF_W 4U |
| #define CKMD_HFXTTARG_IREF_M 0x0000F000U |
Referenced by CKMDGetTargetIrefTrim(), and CKMDSetTargetIrefTrim().
| #define CKMD_HFXTTARG_IREF_S 12U |
Referenced by CKMDGetTargetIrefTrim(), CKMDSetTargetIrefTrim(), and SetupTrimDevice().
| #define CKMD_HFXTTARG_Q2CAP_W 6U |
| #define CKMD_HFXTTARG_Q2CAP_M 0x00000FC0U |
Referenced by CKMDGetTargetQ2CapTrim(), CKMDSetTargetCapTrim(), and CKMDSetTargetQ2CapTrim().
| #define CKMD_HFXTTARG_Q2CAP_S 6U |
Referenced by CKMDGetTargetQ2CapTrim(), CKMDSetTargetCapTrim(), CKMDSetTargetQ2CapTrim(), and SetupTrimDevice().
| #define CKMD_HFXTTARG_Q1CAP_W 6U |
| #define CKMD_HFXTTARG_Q1CAP_M 0x0000003FU |
Referenced by CKMDGetTargetQ1CapTrim(), CKMDSetTargetCapTrim(), and CKMDSetTargetQ1CapTrim().
| #define CKMD_HFXTTARG_Q1CAP_S 0U |
Referenced by CKMDGetTargetQ1CapTrim(), CKMDSetTargetCapTrim(), CKMDSetTargetQ1CapTrim(), and SetupTrimDevice().
| #define CKMD_HFXTDYN_SEL 0x80000000U |
| #define CKMD_HFXTDYN_SEL_M 0x80000000U |
| #define CKMD_HFXTDYN_SEL_S 31U |
| #define CKMD_HFXTDYN_SEL_DYNAMIC 0x80000000U |
| #define CKMD_HFXTDYN_SEL_TARGET 0x00000000U |
| #define CKMD_HFXTDYN_AMPTHR_W 7U |
| #define CKMD_HFXTDYN_AMPTHR_M 0x3F800000U |
| #define CKMD_HFXTDYN_AMPTHR_S 23U |
| #define CKMD_HFXTDYN_IDAC_W 7U |
| #define CKMD_HFXTDYN_IDAC_M 0x007F0000U |
| #define CKMD_HFXTDYN_IDAC_S 16U |
| #define CKMD_HFXTDYN_IREF_W 4U |
| #define CKMD_HFXTDYN_IREF_M 0x0000F000U |
| #define CKMD_HFXTDYN_IREF_S 12U |
| #define CKMD_HFXTDYN_Q2CAP_W 6U |
| #define CKMD_HFXTDYN_Q2CAP_M 0x00000FC0U |
| #define CKMD_HFXTDYN_Q2CAP_S 6U |
| #define CKMD_HFXTDYN_Q1CAP_W 6U |
| #define CKMD_HFXTDYN_Q1CAP_M 0x0000003FU |
| #define CKMD_HFXTDYN_Q1CAP_S 0U |
| #define CKMD_AMPCFG0_Q2DLY_W 4U |
| #define CKMD_AMPCFG0_Q2DLY_M 0xF0000000U |
| #define CKMD_AMPCFG0_Q2DLY_S 28U |
| #define CKMD_AMPCFG0_Q1DLY_W 4U |
| #define CKMD_AMPCFG0_Q1DLY_M 0x0F000000U |
| #define CKMD_AMPCFG0_Q1DLY_S 24U |
| #define CKMD_AMPCFG0_ADCDLY_W 4U |
| #define CKMD_AMPCFG0_ADCDLY_M 0x00F00000U |
| #define CKMD_AMPCFG0_ADCDLY_S 20U |
| #define CKMD_AMPCFG0_LDOSTART_W 5U |
| #define CKMD_AMPCFG0_LDOSTART_M 0x000F8000U |
| #define CKMD_AMPCFG0_LDOSTART_S 15U |
| #define CKMD_AMPCFG0_INJWAIT_W 5U |
| #define CKMD_AMPCFG0_INJWAIT_M 0x00007C00U |
| #define CKMD_AMPCFG0_INJWAIT_S 10U |
| #define CKMD_AMPCFG0_INJTIME_W 5U |
| #define CKMD_AMPCFG0_INJTIME_M 0x000003E0U |
| #define CKMD_AMPCFG0_INJTIME_S 5U |
| #define CKMD_AMPCFG0_FSMRATE_W 5U |
| #define CKMD_AMPCFG0_FSMRATE_M 0x0000001FU |
| #define CKMD_AMPCFG0_FSMRATE_S 0U |
| #define CKMD_AMPCFG0_FSMRATE__250K 0x00000017U |
| #define CKMD_AMPCFG0_FSMRATE__500K 0x0000000BU |
| #define CKMD_AMPCFG0_FSMRATE__1M 0x00000005U |
| #define CKMD_AMPCFG0_FSMRATE__2M 0x00000002U |
| #define CKMD_AMPCFG0_FSMRATE__3M 0x00000001U |
| #define CKMD_AMPCFG0_FSMRATE__6M 0x00000000U |
| #define CKMD_AMPCFG1_IDACDLY_W 4U |
| #define CKMD_AMPCFG1_IDACDLY_M 0xF0000000U |
| #define CKMD_AMPCFG1_IDACDLY_S 28U |
| #define CKMD_AMPCFG1_IREFDLY_W 4U |
| #define CKMD_AMPCFG1_IREFDLY_M 0x0F000000U |
| #define CKMD_AMPCFG1_IREFDLY_S 24U |
| #define CKMD_AMPCFG1_BIASLT_W 12U |
| #define CKMD_AMPCFG1_BIASLT_M 0x00FFF000U |
| #define CKMD_AMPCFG1_BIASLT_S 12U |
| #define CKMD_AMPCFG1_INTERVAL_W 12U |
| #define CKMD_AMPCFG1_INTERVAL_M 0x00000FFFU |
| #define CKMD_AMPCFG1_INTERVAL_S 0U |
| #define CKMD_LOOPCFG_FINETRIM_INIT_W 6U |
| #define CKMD_LOOPCFG_FINETRIM_INIT_M 0xFC000000U |
| #define CKMD_LOOPCFG_FINETRIM_INIT_S 26U |
| #define CKMD_LOOPCFG_BOOST_TARGET_W 5U |
| #define CKMD_LOOPCFG_BOOST_TARGET_M 0x03E00000U |
| #define CKMD_LOOPCFG_BOOST_TARGET_S 21U |
| #define CKMD_LOOPCFG_KP_BOOST_W 3U |
| #define CKMD_LOOPCFG_KP_BOOST_M 0x001C0000U |
| #define CKMD_LOOPCFG_KP_BOOST_S 18U |
| #define CKMD_LOOPCFG_KI_BOOST_W 3U |
| #define CKMD_LOOPCFG_KI_BOOST_M 0x00038000U |
| #define CKMD_LOOPCFG_KI_BOOST_S 15U |
| #define CKMD_LOOPCFG_SETTLED_TARGET_W 5U |
| #define CKMD_LOOPCFG_SETTLED_TARGET_M 0x00007C00U |
| #define CKMD_LOOPCFG_SETTLED_TARGET_S 10U |
| #define CKMD_LOOPCFG_OOR_LIMIT_W 4U |
| #define CKMD_LOOPCFG_OOR_LIMIT_M 0x000003C0U |
| #define CKMD_LOOPCFG_OOR_LIMIT_S 6U |
| #define CKMD_LOOPCFG_KP_W 3U |
| #define CKMD_LOOPCFG_KP_M 0x00000038U |
| #define CKMD_LOOPCFG_KP_S 3U |
| #define CKMD_LOOPCFG_KI_W 3U |
| #define CKMD_LOOPCFG_KI_M 0x00000007U |
| #define CKMD_LOOPCFG_KI_S 0U |
| #define CKMD_TDCCTL_CMD_W 2U |
| #define CKMD_TDCCTL_CMD_M 0x00000003U |
| #define CKMD_TDCCTL_CMD_S 0U |
| #define CKMD_TDCCTL_CMD_ABORT 0x00000003U |
| #define CKMD_TDCCTL_CMD_RUN 0x00000002U |
| #define CKMD_TDCCTL_CMD_RUN_SYNC_START 0x00000001U |
| #define CKMD_TDCCTL_CMD_CLR_RESULT 0x00000000U |
| #define CKMD_TDCSTAT_STOP_BF 0x00000200U |
| #define CKMD_TDCSTAT_STOP_BF_M 0x00000200U |
| #define CKMD_TDCSTAT_STOP_BF_S 9U |
| #define CKMD_TDCSTAT_START_BF 0x00000100U |
| #define CKMD_TDCSTAT_START_BF_M 0x00000100U |
| #define CKMD_TDCSTAT_START_BF_S 8U |
| #define CKMD_TDCSTAT_SAT 0x00000080U |
| #define CKMD_TDCSTAT_SAT_M 0x00000080U |
| #define CKMD_TDCSTAT_SAT_S 7U |
| #define CKMD_TDCSTAT_DONE 0x00000040U |
| #define CKMD_TDCSTAT_DONE_M 0x00000040U |
| #define CKMD_TDCSTAT_DONE_S 6U |
| #define CKMD_TDCSTAT_STATE_W 6U |
| #define CKMD_TDCSTAT_STATE_M 0x0000003FU |
| #define CKMD_TDCSTAT_STATE_S 0U |
| #define CKMD_TDCSTAT_STATE_FORCE_STOP 0x0000002EU |
| #define CKMD_TDCSTAT_STATE_START_FALL 0x0000001EU |
| #define CKMD_TDCSTAT_STATE_WAIT_CLR_CNT_DONE 0x00000016U |
| #define CKMD_TDCSTAT_STATE_POR 0x0000000FU |
| #define CKMD_TDCSTAT_STATE_GET_RESULT 0x0000000EU |
| #define CKMD_TDCSTAT_STATE_WAIT_STOP_CNTDWN 0x0000000CU |
| #define CKMD_TDCSTAT_STATE_WAIT_STOP 0x00000008U |
| #define CKMD_TDCSTAT_STATE_CLR_CNT 0x00000007U |
| #define CKMD_TDCSTAT_STATE_IDLE 0x00000006U |
| #define CKMD_TDCSTAT_STATE_WAIT_START_STOP_CNT_EN 0x00000004U |
| #define CKMD_TDCSTAT_STATE_WAIT_START 0x00000000U |
| #define CKMD_TDCRESULT_VALUE_W 32U |
| #define CKMD_TDCRESULT_VALUE_M 0xFFFFFFFFU |
| #define CKMD_TDCRESULT_VALUE_S 0U |
| #define CKMD_TDCSATCFG_LIMIT_W 5U |
| #define CKMD_TDCSATCFG_LIMIT_M 0x0000001FU |
| #define CKMD_TDCSATCFG_LIMIT_S 0U |
| #define CKMD_TDCSATCFG_LIMIT_R30 0x00000015U |
| #define CKMD_TDCSATCFG_LIMIT_R29 0x00000014U |
| #define CKMD_TDCSATCFG_LIMIT_R28 0x00000013U |
| #define CKMD_TDCSATCFG_LIMIT_R27 0x00000012U |
| #define CKMD_TDCSATCFG_LIMIT_R26 0x00000011U |
| #define CKMD_TDCSATCFG_LIMIT_R25 0x00000010U |
| #define CKMD_TDCSATCFG_LIMIT_R24 0x0000000FU |
| #define CKMD_TDCSATCFG_LIMIT_R23 0x0000000EU |
| #define CKMD_TDCSATCFG_LIMIT_R22 0x0000000DU |
| #define CKMD_TDCSATCFG_LIMIT_R21 0x0000000CU |
| #define CKMD_TDCSATCFG_LIMIT_R20 0x0000000BU |
| #define CKMD_TDCSATCFG_LIMIT_R19 0x0000000AU |
| #define CKMD_TDCSATCFG_LIMIT_R18 0x00000009U |
| #define CKMD_TDCSATCFG_LIMIT_R17 0x00000008U |
| #define CKMD_TDCSATCFG_LIMIT_R16 0x00000007U |
| #define CKMD_TDCSATCFG_LIMIT_R15 0x00000006U |
| #define CKMD_TDCSATCFG_LIMIT_R14 0x00000005U |
| #define CKMD_TDCSATCFG_LIMIT_R13 0x00000004U |
| #define CKMD_TDCSATCFG_LIMIT_R12 0x00000003U |
| #define CKMD_TDCSATCFG_LIMIT_NONE 0x00000000U |
| #define CKMD_TDCTRIGSRC_STOP_POL 0x00008000U |
| #define CKMD_TDCTRIGSRC_STOP_POL_M 0x00008000U |
| #define CKMD_TDCTRIGSRC_STOP_POL_S 15U |
| #define CKMD_TDCTRIGSRC_STOP_POL_LOW 0x00008000U |
| #define CKMD_TDCTRIGSRC_STOP_POL_HIGH 0x00000000U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_W 5U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_M 0x00001F00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_S 8U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_TDC_PRE 0x00001F00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB15 0x00001400U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB14 0x00001300U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB13 0x00001200U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB12 0x00001100U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB11 0x00001000U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB10 0x00000F00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB9 0x00000E00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB8 0x00000D00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB7 0x00000C00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB6 0x00000B00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB5 0x00000A00U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB4 0x00000900U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB3 0x00000800U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB2 0x00000700U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB1 0x00000600U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_DTB0 0x00000500U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_GPI 0x00000400U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_LFCLK_DLY 0x00000300U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_LFXT 0x00000200U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_LFOSC 0x00000100U |
| #define CKMD_TDCTRIGSRC_STOP_SRC_LFTICK 0x00000000U |
| #define CKMD_TDCTRIGSRC_START_POL 0x00000080U |
| #define CKMD_TDCTRIGSRC_START_POL_M 0x00000080U |
| #define CKMD_TDCTRIGSRC_START_POL_S 7U |
| #define CKMD_TDCTRIGSRC_START_POL_LOW 0x00000080U |
| #define CKMD_TDCTRIGSRC_START_POL_HIGH 0x00000000U |
| #define CKMD_TDCTRIGSRC_START_SRC_W 5U |
| #define CKMD_TDCTRIGSRC_START_SRC_M 0x0000001FU |
| #define CKMD_TDCTRIGSRC_START_SRC_S 0U |
| #define CKMD_TDCTRIGSRC_START_SRC_TDC_PRE 0x0000001FU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB15 0x00000014U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB14 0x00000013U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB13 0x00000012U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB12 0x00000011U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB11 0x00000010U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB10 0x0000000FU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB9 0x0000000EU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB8 0x0000000DU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB7 0x0000000CU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB6 0x0000000BU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB5 0x0000000AU |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB4 0x00000009U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB3 0x00000008U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB2 0x00000007U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB1 0x00000006U |
| #define CKMD_TDCTRIGSRC_START_SRC_DTB0 0x00000005U |
| #define CKMD_TDCTRIGSRC_START_SRC_GPI 0x00000004U |
| #define CKMD_TDCTRIGSRC_START_SRC_LFCLK_DLY 0x00000003U |
| #define CKMD_TDCTRIGSRC_START_SRC_LFXT 0x00000002U |
| #define CKMD_TDCTRIGSRC_START_SRC_LFOSC 0x00000001U |
| #define CKMD_TDCTRIGSRC_START_SRC_LFTICK 0x00000000U |
| #define CKMD_TDCTRIGCNT_CNT_W 16U |
| #define CKMD_TDCTRIGCNT_CNT_M 0x0000FFFFU |
| #define CKMD_TDCTRIGCNT_CNT_S 0U |
| #define CKMD_TDCTRIGCNTLOAD_CNT_W 16U |
| #define CKMD_TDCTRIGCNTLOAD_CNT_M 0x0000FFFFU |
| #define CKMD_TDCTRIGCNTLOAD_CNT_S 0U |
| #define CKMD_TDCTRIGCNTCFG_EN 0x00000001U |
| #define CKMD_TDCTRIGCNTCFG_EN_M 0x00000001U |
| #define CKMD_TDCTRIGCNTCFG_EN_S 0U |
| #define CKMD_TDCPRECTL_RESET_N 0x00000080U |
| #define CKMD_TDCPRECTL_RESET_N_M 0x00000080U |
| #define CKMD_TDCPRECTL_RESET_N_S 7U |
| #define CKMD_TDCPRECTL_RATIO 0x00000040U |
| #define CKMD_TDCPRECTL_RATIO_M 0x00000040U |
| #define CKMD_TDCPRECTL_RATIO_S 6U |
| #define CKMD_TDCPRECTL_RATIO_DIV64 0x00000040U |
| #define CKMD_TDCPRECTL_RATIO_DIV16 0x00000000U |
| #define CKMD_TDCPRECTL_SRC_W 5U |
| #define CKMD_TDCPRECTL_SRC_M 0x0000001FU |
| #define CKMD_TDCPRECTL_SRC_S 0U |
| #define CKMD_TDCPRECTL_SRC_HFXT 0x00000016U |
| #define CKMD_TDCPRECTL_SRC_HFOSC 0x00000015U |
| #define CKMD_TDCPRECTL_SRC_DTB15 0x00000014U |
| #define CKMD_TDCPRECTL_SRC_DTB14 0x00000013U |
| #define CKMD_TDCPRECTL_SRC_DTB13 0x00000012U |
| #define CKMD_TDCPRECTL_SRC_DTB12 0x00000011U |
| #define CKMD_TDCPRECTL_SRC_DTB11 0x00000010U |
| #define CKMD_TDCPRECTL_SRC_DTB10 0x0000000FU |
| #define CKMD_TDCPRECTL_SRC_DTB9 0x0000000EU |
| #define CKMD_TDCPRECTL_SRC_DTB8 0x0000000DU |
| #define CKMD_TDCPRECTL_SRC_DTB7 0x0000000CU |
| #define CKMD_TDCPRECTL_SRC_DTB6 0x0000000BU |
| #define CKMD_TDCPRECTL_SRC_DTB5 0x0000000AU |
| #define CKMD_TDCPRECTL_SRC_DTB4 0x00000009U |
| #define CKMD_TDCPRECTL_SRC_DTB3 0x00000008U |
| #define CKMD_TDCPRECTL_SRC_DTB2 0x00000007U |
| #define CKMD_TDCPRECTL_SRC_DTB1 0x00000006U |
| #define CKMD_TDCPRECTL_SRC_DTB0 0x00000005U |
| #define CKMD_TDCPRECTL_SRC_GPI 0x00000004U |
| #define CKMD_TDCPRECTL_SRC_LFCLK_DLY 0x00000003U |
| #define CKMD_TDCPRECTL_SRC_LFXT 0x00000002U |
| #define CKMD_TDCPRECTL_SRC_LFOSC 0x00000001U |
| #define CKMD_TDCPRECTL_SRC_LFTICK 0x00000000U |
| #define CKMD_TDCPRECNTR_CAPT 0x00010000U |
| #define CKMD_TDCPRECNTR_CAPT_M 0x00010000U |
| #define CKMD_TDCPRECNTR_CAPT_S 16U |
| #define CKMD_TDCPRECNTR_CNT_W 16U |
| #define CKMD_TDCPRECNTR_CNT_M 0x0000FFFFU |
| #define CKMD_TDCPRECNTR_CNT_S 0U |
| #define CKMD_WDTCNT_VAL_W 32U |
| #define CKMD_WDTCNT_VAL_M 0xFFFFFFFFU |
| #define CKMD_WDTCNT_VAL_S 0U |
| #define CKMD_WDTTEST_STALLEN 0x00000001U |
| #define CKMD_WDTTEST_STALLEN_M 0x00000001U |
| #define CKMD_WDTTEST_STALLEN_S 0U |
| #define CKMD_WDTTEST_STALLEN_EN 0x00000001U |
| #define CKMD_WDTTEST_STALLEN_DIS 0x00000000U |
| #define CKMD_WDTLOCK_STAT_W 32U |
| #define CKMD_WDTLOCK_STAT_M 0xFFFFFFFFU |
| #define CKMD_WDTLOCK_STAT_S 0U |