Macros
#define	BPU_O_BP_CTRL 0x00000000U

#define	BPU_O_BP_COMP0 0x00000008U

#define	BPU_O_BP_COMP1 0x0000000CU

#define	BPU_O_BP_COMP2 0x00000010U

#define	BPU_O_BP_COMP3 0x00000014U

#define	BPU_O_PIDR4 0x00000FD0U

#define	BPU_O_PIDR5 0x00000FD4U

#define	BPU_O_PIDR6 0x00000FD8U

#define	BPU_O_PIDR7 0x00000FDCU

#define	BPU_O_PIDR0 0x00000FE0U

#define	BPU_O_PIDR1 0x00000FE4U

#define	BPU_O_PIDR2 0x00000FE8U

#define	BPU_O_PIDR3 0x00000FECU

#define	BPU_O_CIDR0 0x00000FF0U

#define	BPU_O_CIDR1 0x00000FF4U

#define	BPU_O_CIDR2 0x00000FF8U

#define	BPU_O_CIDR3 0x00000FFCU

#define	BPU_BP_CTRL_NUM_CODE_W 4U

#define	BPU_BP_CTRL_NUM_CODE_M 0x000000F0U

#define	BPU_BP_CTRL_NUM_CODE_S 4U

#define	BPU_BP_CTRL_KEY 0x00000002U

#define	BPU_BP_CTRL_KEY_M 0x00000002U

#define	BPU_BP_CTRL_KEY_S 1U

#define	BPU_BP_CTRL_ENABLE 0x00000001U

#define	BPU_BP_CTRL_ENABLE_M 0x00000001U

#define	BPU_BP_CTRL_ENABLE_S 0U

#define	BPU_BP_CTRL_ENABLE_BKPT_EN 0x00000001U

#define	BPU_BP_CTRL_ENABLE_BKPT_DIS 0x00000000U

#define	BPU_BP_COMP0_BP_MATCH_W 2U

#define	BPU_BP_COMP0_BP_MATCH_M 0xC0000000U

#define	BPU_BP_COMP0_BP_MATCH_S 30U

#define	BPU_BP_COMP0_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

#define	BPU_BP_COMP0_BP_MATCH_BKPT_COMP_HI 0x80000000U

#define	BPU_BP_COMP0_BP_MATCH_BKPT_COMP_LOW 0x40000000U

#define	BPU_BP_COMP0_BP_MATCH_BKPT_COMP_NONE 0x00000000U

#define	BPU_BP_COMP0_COMP_W 27U

#define	BPU_BP_COMP0_COMP_M 0x1FFFFFFCU

#define	BPU_BP_COMP0_COMP_S 2U

#define	BPU_BP_COMP0_ENABLE 0x00000001U

#define	BPU_BP_COMP0_ENABLE_M 0x00000001U

#define	BPU_BP_COMP0_ENABLE_S 0U

#define	BPU_BP_COMP0_ENABLE_BKPT_COMP_DIS 0x00000001U

#define	BPU_BP_COMP0_ENABLE_BKPT_COMP_EN 0x00000000U

#define	BPU_BP_COMP1_BP_MATCH_W 2U

#define	BPU_BP_COMP1_BP_MATCH_M 0xC0000000U

#define	BPU_BP_COMP1_BP_MATCH_S 30U

#define	BPU_BP_COMP1_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

#define	BPU_BP_COMP1_BP_MATCH_BKPT_COMP_HI 0x80000000U

#define	BPU_BP_COMP1_BP_MATCH_BKPT_COMP_LOW 0x40000000U

#define	BPU_BP_COMP1_BP_MATCH_BKPT_COMP_NONE 0x00000000U

#define	BPU_BP_COMP1_COMP_W 27U

#define	BPU_BP_COMP1_COMP_M 0x1FFFFFFCU

#define	BPU_BP_COMP1_COMP_S 2U

#define	BPU_BP_COMP1_ENABLE 0x00000001U

#define	BPU_BP_COMP1_ENABLE_M 0x00000001U

#define	BPU_BP_COMP1_ENABLE_S 0U

#define	BPU_BP_COMP1_ENABLE_BKPT_COMP_DIS 0x00000001U

#define	BPU_BP_COMP1_ENABLE_BKPT_COMP_EN 0x00000000U

#define	BPU_BP_COMP2_BP_MATCH_W 2U

#define	BPU_BP_COMP2_BP_MATCH_M 0xC0000000U

#define	BPU_BP_COMP2_BP_MATCH_S 30U

#define	BPU_BP_COMP2_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

#define	BPU_BP_COMP2_BP_MATCH_BKPT_COMP_HI 0x80000000U

#define	BPU_BP_COMP2_BP_MATCH_BKPT_COMP_LOW 0x40000000U

#define	BPU_BP_COMP2_BP_MATCH_BKPT_COMP_NONE 0x00000000U

#define	BPU_BP_COMP2_COMP_W 27U

#define	BPU_BP_COMP2_COMP_M 0x1FFFFFFCU

#define	BPU_BP_COMP2_COMP_S 2U

#define	BPU_BP_COMP2_ENABLE 0x00000001U

#define	BPU_BP_COMP2_ENABLE_M 0x00000001U

#define	BPU_BP_COMP2_ENABLE_S 0U

#define	BPU_BP_COMP2_ENABLE_BKPT_COMP_DIS 0x00000001U

#define	BPU_BP_COMP2_ENABLE_BKPT_COMP_EN 0x00000000U

#define	BPU_BP_COMP3_BP_MATCH_W 2U

#define	BPU_BP_COMP3_BP_MATCH_M 0xC0000000U

#define	BPU_BP_COMP3_BP_MATCH_S 30U

#define	BPU_BP_COMP3_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

#define	BPU_BP_COMP3_BP_MATCH_BKPT_COMP_HI 0x80000000U

#define	BPU_BP_COMP3_BP_MATCH_BKPT_COMP_LOW 0x40000000U

#define	BPU_BP_COMP3_BP_MATCH_BKPT_COMP_NONE 0x00000000U

#define	BPU_BP_COMP3_COMP_W 27U

#define	BPU_BP_COMP3_COMP_M 0x1FFFFFFCU

#define	BPU_BP_COMP3_COMP_S 2U

#define	BPU_BP_COMP3_ENABLE 0x00000001U

#define	BPU_BP_COMP3_ENABLE_M 0x00000001U

#define	BPU_BP_COMP3_ENABLE_S 0U

#define	BPU_BP_COMP3_ENABLE_BKPT_COMP_DIS 0x00000001U

#define	BPU_BP_COMP3_ENABLE_BKPT_COMP_EN 0x00000000U

#define	BPU_PIDR4_SIZE_W 4U

#define	BPU_PIDR4_SIZE_M 0x000000F0U

#define	BPU_PIDR4_SIZE_S 4U

#define	BPU_PIDR4_DES_2_W 4U

#define	BPU_PIDR4_DES_2_M 0x0000000FU

#define	BPU_PIDR4_DES_2_S 0U

#define	BPU_PIDR0_PART_0_W 8U

#define	BPU_PIDR0_PART_0_M 0x000000FFU

#define	BPU_PIDR0_PART_0_S 0U

#define	BPU_PIDR1_DES_0_W 4U

#define	BPU_PIDR1_DES_0_M 0x000000F0U

#define	BPU_PIDR1_DES_0_S 4U

#define	BPU_PIDR1_PART_1_W 4U

#define	BPU_PIDR1_PART_1_M 0x0000000FU

#define	BPU_PIDR1_PART_1_S 0U

#define	BPU_PIDR2_REVISION_W 4U

#define	BPU_PIDR2_REVISION_M 0x000000F0U

#define	BPU_PIDR2_REVISION_S 4U

#define	BPU_PIDR2_JEDEC 0x00000008U

#define	BPU_PIDR2_JEDEC_M 0x00000008U

#define	BPU_PIDR2_JEDEC_S 3U

#define	BPU_PIDR2_DES_1_W 3U

#define	BPU_PIDR2_DES_1_M 0x00000007U

#define	BPU_PIDR2_DES_1_S 0U

#define	BPU_PIDR3_REVAND_W 4U

#define	BPU_PIDR3_REVAND_M 0x000000F0U

#define	BPU_PIDR3_REVAND_S 4U

#define	BPU_PIDR3_CMOD_W 4U

#define	BPU_PIDR3_CMOD_M 0x0000000FU

#define	BPU_PIDR3_CMOD_S 0U

#define	BPU_CIDR0_PRMBL_0_W 8U

#define	BPU_CIDR0_PRMBL_0_M 0x000000FFU

#define	BPU_CIDR0_PRMBL_0_S 0U

#define	BPU_CIDR1_CLASS_W 4U

#define	BPU_CIDR1_CLASS_M 0x000000F0U

#define	BPU_CIDR1_CLASS_S 4U

#define	BPU_CIDR1_PRMBL_1_W 4U

#define	BPU_CIDR1_PRMBL_1_M 0x0000000FU

#define	BPU_CIDR1_PRMBL_1_S 0U

#define	BPU_CIDR2_PRMBL_2_W 8U

#define	BPU_CIDR2_PRMBL_2_M 0x000000FFU

#define	BPU_CIDR2_PRMBL_2_S 0U

#define	BPU_CIDR3_PRMBL_3_W 8U

#define	BPU_CIDR3_PRMBL_3_M 0x000000FFU

#define	BPU_CIDR3_PRMBL_3_S 0U

Macro Definition Documentation

§ BPU_O_BP_CTRL

#define BPU_O_BP_CTRL 0x00000000U

§ BPU_O_BP_COMP0

#define BPU_O_BP_COMP0 0x00000008U

§ BPU_O_BP_COMP1

#define BPU_O_BP_COMP1 0x0000000CU

§ BPU_O_BP_COMP2

#define BPU_O_BP_COMP2 0x00000010U

§ BPU_O_BP_COMP3

#define BPU_O_BP_COMP3 0x00000014U

§ BPU_O_PIDR4

#define BPU_O_PIDR4 0x00000FD0U

§ BPU_O_PIDR5

#define BPU_O_PIDR5 0x00000FD4U

§ BPU_O_PIDR6

#define BPU_O_PIDR6 0x00000FD8U

§ BPU_O_PIDR7

#define BPU_O_PIDR7 0x00000FDCU

§ BPU_O_PIDR0

#define BPU_O_PIDR0 0x00000FE0U

§ BPU_O_PIDR1

#define BPU_O_PIDR1 0x00000FE4U

§ BPU_O_PIDR2

#define BPU_O_PIDR2 0x00000FE8U

§ BPU_O_PIDR3

#define BPU_O_PIDR3 0x00000FECU

§ BPU_O_CIDR0

#define BPU_O_CIDR0 0x00000FF0U

§ BPU_O_CIDR1

#define BPU_O_CIDR1 0x00000FF4U

§ BPU_O_CIDR2

#define BPU_O_CIDR2 0x00000FF8U

§ BPU_O_CIDR3

#define BPU_O_CIDR3 0x00000FFCU

§ BPU_BP_CTRL_NUM_CODE_W

#define BPU_BP_CTRL_NUM_CODE_W 4U

§ BPU_BP_CTRL_NUM_CODE_M

#define BPU_BP_CTRL_NUM_CODE_M 0x000000F0U

§ BPU_BP_CTRL_NUM_CODE_S

#define BPU_BP_CTRL_NUM_CODE_S 4U

§ BPU_BP_CTRL_KEY

#define BPU_BP_CTRL_KEY 0x00000002U

§ BPU_BP_CTRL_KEY_M

#define BPU_BP_CTRL_KEY_M 0x00000002U

§ BPU_BP_CTRL_KEY_S

#define BPU_BP_CTRL_KEY_S 1U

§ BPU_BP_CTRL_ENABLE

#define BPU_BP_CTRL_ENABLE 0x00000001U

§ BPU_BP_CTRL_ENABLE_M

#define BPU_BP_CTRL_ENABLE_M 0x00000001U

§ BPU_BP_CTRL_ENABLE_S

#define BPU_BP_CTRL_ENABLE_S 0U

§ BPU_BP_CTRL_ENABLE_BKPT_EN

#define BPU_BP_CTRL_ENABLE_BKPT_EN 0x00000001U

§ BPU_BP_CTRL_ENABLE_BKPT_DIS

#define BPU_BP_CTRL_ENABLE_BKPT_DIS 0x00000000U

§ BPU_BP_COMP0_BP_MATCH_W

#define BPU_BP_COMP0_BP_MATCH_W 2U

§ BPU_BP_COMP0_BP_MATCH_M

#define BPU_BP_COMP0_BP_MATCH_M 0xC0000000U

§ BPU_BP_COMP0_BP_MATCH_S

#define BPU_BP_COMP0_BP_MATCH_S 30U

§ BPU_BP_COMP0_BP_MATCH_BKPT_COMP_BOTH

#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

§ BPU_BP_COMP0_BP_MATCH_BKPT_COMP_HI

#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_HI 0x80000000U

§ BPU_BP_COMP0_BP_MATCH_BKPT_COMP_LOW

#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_LOW 0x40000000U

§ BPU_BP_COMP0_BP_MATCH_BKPT_COMP_NONE

#define BPU_BP_COMP0_BP_MATCH_BKPT_COMP_NONE 0x00000000U

§ BPU_BP_COMP0_COMP_W

#define BPU_BP_COMP0_COMP_W 27U

§ BPU_BP_COMP0_COMP_M

#define BPU_BP_COMP0_COMP_M 0x1FFFFFFCU

§ BPU_BP_COMP0_COMP_S

#define BPU_BP_COMP0_COMP_S 2U

§ BPU_BP_COMP0_ENABLE

#define BPU_BP_COMP0_ENABLE 0x00000001U

§ BPU_BP_COMP0_ENABLE_M

#define BPU_BP_COMP0_ENABLE_M 0x00000001U

§ BPU_BP_COMP0_ENABLE_S

#define BPU_BP_COMP0_ENABLE_S 0U

§ BPU_BP_COMP0_ENABLE_BKPT_COMP_DIS

#define BPU_BP_COMP0_ENABLE_BKPT_COMP_DIS 0x00000001U

§ BPU_BP_COMP0_ENABLE_BKPT_COMP_EN

#define BPU_BP_COMP0_ENABLE_BKPT_COMP_EN 0x00000000U

§ BPU_BP_COMP1_BP_MATCH_W

#define BPU_BP_COMP1_BP_MATCH_W 2U

§ BPU_BP_COMP1_BP_MATCH_M

#define BPU_BP_COMP1_BP_MATCH_M 0xC0000000U

§ BPU_BP_COMP1_BP_MATCH_S

#define BPU_BP_COMP1_BP_MATCH_S 30U

§ BPU_BP_COMP1_BP_MATCH_BKPT_COMP_BOTH

#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

§ BPU_BP_COMP1_BP_MATCH_BKPT_COMP_HI

#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_HI 0x80000000U

§ BPU_BP_COMP1_BP_MATCH_BKPT_COMP_LOW

#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_LOW 0x40000000U

§ BPU_BP_COMP1_BP_MATCH_BKPT_COMP_NONE

#define BPU_BP_COMP1_BP_MATCH_BKPT_COMP_NONE 0x00000000U

§ BPU_BP_COMP1_COMP_W

#define BPU_BP_COMP1_COMP_W 27U

§ BPU_BP_COMP1_COMP_M

#define BPU_BP_COMP1_COMP_M 0x1FFFFFFCU

§ BPU_BP_COMP1_COMP_S

#define BPU_BP_COMP1_COMP_S 2U

§ BPU_BP_COMP1_ENABLE

#define BPU_BP_COMP1_ENABLE 0x00000001U

§ BPU_BP_COMP1_ENABLE_M

#define BPU_BP_COMP1_ENABLE_M 0x00000001U

§ BPU_BP_COMP1_ENABLE_S

#define BPU_BP_COMP1_ENABLE_S 0U

§ BPU_BP_COMP1_ENABLE_BKPT_COMP_DIS

#define BPU_BP_COMP1_ENABLE_BKPT_COMP_DIS 0x00000001U

§ BPU_BP_COMP1_ENABLE_BKPT_COMP_EN

#define BPU_BP_COMP1_ENABLE_BKPT_COMP_EN 0x00000000U

§ BPU_BP_COMP2_BP_MATCH_W

#define BPU_BP_COMP2_BP_MATCH_W 2U

§ BPU_BP_COMP2_BP_MATCH_M

#define BPU_BP_COMP2_BP_MATCH_M 0xC0000000U

§ BPU_BP_COMP2_BP_MATCH_S

#define BPU_BP_COMP2_BP_MATCH_S 30U

§ BPU_BP_COMP2_BP_MATCH_BKPT_COMP_BOTH

#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

§ BPU_BP_COMP2_BP_MATCH_BKPT_COMP_HI

#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_HI 0x80000000U

§ BPU_BP_COMP2_BP_MATCH_BKPT_COMP_LOW

#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_LOW 0x40000000U

§ BPU_BP_COMP2_BP_MATCH_BKPT_COMP_NONE

#define BPU_BP_COMP2_BP_MATCH_BKPT_COMP_NONE 0x00000000U

§ BPU_BP_COMP2_COMP_W

#define BPU_BP_COMP2_COMP_W 27U

§ BPU_BP_COMP2_COMP_M

#define BPU_BP_COMP2_COMP_M 0x1FFFFFFCU

§ BPU_BP_COMP2_COMP_S

#define BPU_BP_COMP2_COMP_S 2U

§ BPU_BP_COMP2_ENABLE

#define BPU_BP_COMP2_ENABLE 0x00000001U

§ BPU_BP_COMP2_ENABLE_M

#define BPU_BP_COMP2_ENABLE_M 0x00000001U

§ BPU_BP_COMP2_ENABLE_S

#define BPU_BP_COMP2_ENABLE_S 0U

§ BPU_BP_COMP2_ENABLE_BKPT_COMP_DIS

#define BPU_BP_COMP2_ENABLE_BKPT_COMP_DIS 0x00000001U

§ BPU_BP_COMP2_ENABLE_BKPT_COMP_EN

#define BPU_BP_COMP2_ENABLE_BKPT_COMP_EN 0x00000000U

§ BPU_BP_COMP3_BP_MATCH_W

#define BPU_BP_COMP3_BP_MATCH_W 2U

§ BPU_BP_COMP3_BP_MATCH_M

#define BPU_BP_COMP3_BP_MATCH_M 0xC0000000U

§ BPU_BP_COMP3_BP_MATCH_S

#define BPU_BP_COMP3_BP_MATCH_S 30U

§ BPU_BP_COMP3_BP_MATCH_BKPT_COMP_BOTH

#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_BOTH 0xC0000000U

§ BPU_BP_COMP3_BP_MATCH_BKPT_COMP_HI

#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_HI 0x80000000U

§ BPU_BP_COMP3_BP_MATCH_BKPT_COMP_LOW

#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_LOW 0x40000000U

§ BPU_BP_COMP3_BP_MATCH_BKPT_COMP_NONE

#define BPU_BP_COMP3_BP_MATCH_BKPT_COMP_NONE 0x00000000U

§ BPU_BP_COMP3_COMP_W

#define BPU_BP_COMP3_COMP_W 27U

§ BPU_BP_COMP3_COMP_M

#define BPU_BP_COMP3_COMP_M 0x1FFFFFFCU

§ BPU_BP_COMP3_COMP_S

#define BPU_BP_COMP3_COMP_S 2U

§ BPU_BP_COMP3_ENABLE

#define BPU_BP_COMP3_ENABLE 0x00000001U

§ BPU_BP_COMP3_ENABLE_M

#define BPU_BP_COMP3_ENABLE_M 0x00000001U

§ BPU_BP_COMP3_ENABLE_S

#define BPU_BP_COMP3_ENABLE_S 0U

§ BPU_BP_COMP3_ENABLE_BKPT_COMP_DIS

#define BPU_BP_COMP3_ENABLE_BKPT_COMP_DIS 0x00000001U

§ BPU_BP_COMP3_ENABLE_BKPT_COMP_EN

#define BPU_BP_COMP3_ENABLE_BKPT_COMP_EN 0x00000000U

§ BPU_PIDR4_SIZE_W

#define BPU_PIDR4_SIZE_W 4U

§ BPU_PIDR4_SIZE_M

#define BPU_PIDR4_SIZE_M 0x000000F0U

§ BPU_PIDR4_SIZE_S

#define BPU_PIDR4_SIZE_S 4U

§ BPU_PIDR4_DES_2_W

#define BPU_PIDR4_DES_2_W 4U

§ BPU_PIDR4_DES_2_M

#define BPU_PIDR4_DES_2_M 0x0000000FU

§ BPU_PIDR4_DES_2_S

#define BPU_PIDR4_DES_2_S 0U

§ BPU_PIDR0_PART_0_W

#define BPU_PIDR0_PART_0_W 8U

§ BPU_PIDR0_PART_0_M

#define BPU_PIDR0_PART_0_M 0x000000FFU

§ BPU_PIDR0_PART_0_S

#define BPU_PIDR0_PART_0_S 0U

§ BPU_PIDR1_DES_0_W

#define BPU_PIDR1_DES_0_W 4U

§ BPU_PIDR1_DES_0_M

#define BPU_PIDR1_DES_0_M 0x000000F0U

§ BPU_PIDR1_DES_0_S

#define BPU_PIDR1_DES_0_S 4U

§ BPU_PIDR1_PART_1_W

#define BPU_PIDR1_PART_1_W 4U

§ BPU_PIDR1_PART_1_M

#define BPU_PIDR1_PART_1_M 0x0000000FU

§ BPU_PIDR1_PART_1_S

#define BPU_PIDR1_PART_1_S 0U

§ BPU_PIDR2_REVISION_W

#define BPU_PIDR2_REVISION_W 4U

§ BPU_PIDR2_REVISION_M

#define BPU_PIDR2_REVISION_M 0x000000F0U

§ BPU_PIDR2_REVISION_S

#define BPU_PIDR2_REVISION_S 4U

§ BPU_PIDR2_JEDEC

#define BPU_PIDR2_JEDEC 0x00000008U

§ BPU_PIDR2_JEDEC_M

#define BPU_PIDR2_JEDEC_M 0x00000008U

§ BPU_PIDR2_JEDEC_S

#define BPU_PIDR2_JEDEC_S 3U

§ BPU_PIDR2_DES_1_W

#define BPU_PIDR2_DES_1_W 3U

§ BPU_PIDR2_DES_1_M

#define BPU_PIDR2_DES_1_M 0x00000007U

§ BPU_PIDR2_DES_1_S

#define BPU_PIDR2_DES_1_S 0U

§ BPU_PIDR3_REVAND_W

#define BPU_PIDR3_REVAND_W 4U

§ BPU_PIDR3_REVAND_M

#define BPU_PIDR3_REVAND_M 0x000000F0U

§ BPU_PIDR3_REVAND_S

#define BPU_PIDR3_REVAND_S 4U

§ BPU_PIDR3_CMOD_W

#define BPU_PIDR3_CMOD_W 4U

§ BPU_PIDR3_CMOD_M

#define BPU_PIDR3_CMOD_M 0x0000000FU

§ BPU_PIDR3_CMOD_S

#define BPU_PIDR3_CMOD_S 0U

§ BPU_CIDR0_PRMBL_0_W

#define BPU_CIDR0_PRMBL_0_W 8U

§ BPU_CIDR0_PRMBL_0_M

#define BPU_CIDR0_PRMBL_0_M 0x000000FFU

§ BPU_CIDR0_PRMBL_0_S

#define BPU_CIDR0_PRMBL_0_S 0U

§ BPU_CIDR1_CLASS_W

#define BPU_CIDR1_CLASS_W 4U

§ BPU_CIDR1_CLASS_M

#define BPU_CIDR1_CLASS_M 0x000000F0U

§ BPU_CIDR1_CLASS_S

#define BPU_CIDR1_CLASS_S 4U

§ BPU_CIDR1_PRMBL_1_W

#define BPU_CIDR1_PRMBL_1_W 4U

§ BPU_CIDR1_PRMBL_1_M

#define BPU_CIDR1_PRMBL_1_M 0x0000000FU

§ BPU_CIDR1_PRMBL_1_S

#define BPU_CIDR1_PRMBL_1_S 0U

§ BPU_CIDR2_PRMBL_2_W

#define BPU_CIDR2_PRMBL_2_W 8U

§ BPU_CIDR2_PRMBL_2_M

#define BPU_CIDR2_PRMBL_2_M 0x000000FFU

§ BPU_CIDR2_PRMBL_2_S

#define BPU_CIDR2_PRMBL_2_S 0U

§ BPU_CIDR3_PRMBL_3_W

#define BPU_CIDR3_PRMBL_3_W 8U

§ BPU_CIDR3_PRMBL_3_M

#define BPU_CIDR3_PRMBL_3_M 0x000000FFU

§ BPU_CIDR3_PRMBL_3_S

#define BPU_CIDR3_PRMBL_3_S 0U

Macros