CC23x0R5DriverLibrary
Macros
hw_adc.h File Reference
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Macros

#define ADC_O_IMASK0   0x00000028U
 
#define ADC_O_RIS0   0x00000030U
 
#define ADC_O_MIS0   0x00000038U
 
#define ADC_O_ISET0   0x00000040U
 
#define ADC_O_ICLR0   0x00000048U
 
#define ADC_O_IMASK1   0x00000058U
 
#define ADC_O_RIS1   0x00000060U
 
#define ADC_O_MIS1   0x00000068U
 
#define ADC_O_ISET1   0x00000070U
 
#define ADC_O_ICLR1   0x00000078U
 
#define ADC_O_IMASK2   0x00000088U
 
#define ADC_O_RIS2   0x00000090U
 
#define ADC_O_MIS2   0x00000098U
 
#define ADC_O_ISET2   0x000000A0U
 
#define ADC_O_ICLR2   0x000000A8U
 
#define ADC_O_CTL0   0x00000100U
 
#define ADC_O_CTL1   0x00000104U
 
#define ADC_O_CTL2   0x00000108U
 
#define ADC_O_CTL3   0x0000010CU
 
#define ADC_O_SCOMP0   0x00000114U
 
#define ADC_O_SCOMP1   0x00000118U
 
#define ADC_O_REFCFG   0x0000011CU
 
#define ADC_O_WCLOW   0x00000148U
 
#define ADC_O_WCHIGH   0x00000150U
 
#define ADC_O_FIFODATA   0x00000160U
 
#define ADC_O_ASCRES   0x00000170U
 
#define ADC_O_MEMCTL0   0x00000180U
 
#define ADC_O_MEMCTL1   0x00000184U
 
#define ADC_O_MEMCTL2   0x00000188U
 
#define ADC_O_MEMCTL3   0x0000018CU
 
#define ADC_O_MEMRES0   0x00000280U
 
#define ADC_O_MEMRES1   0x00000284U
 
#define ADC_O_MEMRES2   0x00000288U
 
#define ADC_O_MEMRES3   0x0000028CU
 
#define ADC_O_STA   0x00000340U
 
#define ADC_O_TEST0   0x00000E00U
 
#define ADC_O_TEST2   0x00000E08U
 
#define ADC_O_TEST3   0x00000E0CU
 
#define ADC_O_TEST4   0x00000E10U
 
#define ADC_O_TEST5   0x00000E14U
 
#define ADC_O_TEST6   0x00000E18U
 
#define ADC_O_DEBUG1   0x00000E20U
 
#define ADC_O_DEBUG2   0x00000E24U
 
#define ADC_O_DEBUG3   0x00000E28U
 
#define ADC_O_DEBUG4   0x00000E2CU
 
#define ADC_IMASK0_MEMRESIFG3   0x00000800U
 
#define ADC_IMASK0_MEMRESIFG3_M   0x00000800U
 
#define ADC_IMASK0_MEMRESIFG3_S   11U
 
#define ADC_IMASK0_MEMRESIFG3_EN   0x00000800U
 
#define ADC_IMASK0_MEMRESIFG3_DIS   0x00000000U
 
#define ADC_IMASK0_MEMRESIFG2   0x00000400U
 
#define ADC_IMASK0_MEMRESIFG2_M   0x00000400U
 
#define ADC_IMASK0_MEMRESIFG2_S   10U
 
#define ADC_IMASK0_MEMRESIFG2_EN   0x00000400U
 
#define ADC_IMASK0_MEMRESIFG2_DIS   0x00000000U
 
#define ADC_IMASK0_MEMRESIFG1   0x00000200U
 
#define ADC_IMASK0_MEMRESIFG1_M   0x00000200U
 
#define ADC_IMASK0_MEMRESIFG1_S   9U
 
#define ADC_IMASK0_MEMRESIFG1_EN   0x00000200U
 
#define ADC_IMASK0_MEMRESIFG1_DIS   0x00000000U
 
#define ADC_IMASK0_MEMRESIFG0   0x00000100U
 
#define ADC_IMASK0_MEMRESIFG0_M   0x00000100U
 
#define ADC_IMASK0_MEMRESIFG0_S   8U
 
#define ADC_IMASK0_MEMRESIFG0_EN   0x00000100U
 
#define ADC_IMASK0_MEMRESIFG0_DIS   0x00000000U
 
#define ADC_IMASK0_ASCDONE   0x00000080U
 
#define ADC_IMASK0_ASCDONE_M   0x00000080U
 
#define ADC_IMASK0_ASCDONE_S   7U
 
#define ADC_IMASK0_ASCDONE_EN   0x00000080U
 
#define ADC_IMASK0_ASCDONE_DIS   0x00000000U
 
#define ADC_IMASK0_UVIFG   0x00000040U
 
#define ADC_IMASK0_UVIFG_M   0x00000040U
 
#define ADC_IMASK0_UVIFG_S   6U
 
#define ADC_IMASK0_UVIFG_EN   0x00000040U
 
#define ADC_IMASK0_UVIFG_DIS   0x00000000U
 
#define ADC_IMASK0_DMADONE   0x00000020U
 
#define ADC_IMASK0_DMADONE_M   0x00000020U
 
#define ADC_IMASK0_DMADONE_S   5U
 
#define ADC_IMASK0_DMADONE_EN   0x00000020U
 
#define ADC_IMASK0_DMADONE_DIS   0x00000000U
 
#define ADC_IMASK0_INIFG   0x00000010U
 
#define ADC_IMASK0_INIFG_M   0x00000010U
 
#define ADC_IMASK0_INIFG_S   4U
 
#define ADC_IMASK0_INIFG_EN   0x00000010U
 
#define ADC_IMASK0_INIFG_DIS   0x00000000U
 
#define ADC_IMASK0_LOWIFG   0x00000008U
 
#define ADC_IMASK0_LOWIFG_M   0x00000008U
 
#define ADC_IMASK0_LOWIFG_S   3U
 
#define ADC_IMASK0_LOWIFG_EN   0x00000008U
 
#define ADC_IMASK0_LOWIFG_DIS   0x00000000U
 
#define ADC_IMASK0_HIGHIFG   0x00000004U
 
#define ADC_IMASK0_HIGHIFG_M   0x00000004U
 
#define ADC_IMASK0_HIGHIFG_S   2U
 
#define ADC_IMASK0_HIGHIFG_EN   0x00000004U
 
#define ADC_IMASK0_HIGHIFG_DIS   0x00000000U
 
#define ADC_IMASK0_TOVIFG   0x00000002U
 
#define ADC_IMASK0_TOVIFG_M   0x00000002U
 
#define ADC_IMASK0_TOVIFG_S   1U
 
#define ADC_IMASK0_TOVIFG_EN   0x00000002U
 
#define ADC_IMASK0_TOVIFG_DIS   0x00000000U
 
#define ADC_IMASK0_OVIFG   0x00000001U
 
#define ADC_IMASK0_OVIFG_M   0x00000001U
 
#define ADC_IMASK0_OVIFG_S   0U
 
#define ADC_IMASK0_OVIFG_EN   0x00000001U
 
#define ADC_IMASK0_OVIFG_DIS   0x00000000U
 
#define ADC_RIS0_MEMRESIFG3   0x00000800U
 
#define ADC_RIS0_MEMRESIFG3_M   0x00000800U
 
#define ADC_RIS0_MEMRESIFG3_S   11U
 
#define ADC_RIS0_MEMRESIFG3_SET   0x00000800U
 
#define ADC_RIS0_MEMRESIFG3_CLR   0x00000000U
 
#define ADC_RIS0_MEMRESIFG2   0x00000400U
 
#define ADC_RIS0_MEMRESIFG2_M   0x00000400U
 
#define ADC_RIS0_MEMRESIFG2_S   10U
 
#define ADC_RIS0_MEMRESIFG2_SET   0x00000400U
 
#define ADC_RIS0_MEMRESIFG2_CLR   0x00000000U
 
#define ADC_RIS0_MEMRESIFG1   0x00000200U
 
#define ADC_RIS0_MEMRESIFG1_M   0x00000200U
 
#define ADC_RIS0_MEMRESIFG1_S   9U
 
#define ADC_RIS0_MEMRESIFG1_SET   0x00000200U
 
#define ADC_RIS0_MEMRESIFG1_CLR   0x00000000U
 
#define ADC_RIS0_MEMRESIFG0   0x00000100U
 
#define ADC_RIS0_MEMRESIFG0_M   0x00000100U
 
#define ADC_RIS0_MEMRESIFG0_S   8U
 
#define ADC_RIS0_MEMRESIFG0_SET   0x00000100U
 
#define ADC_RIS0_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_RIS0_ASCDONE   0x00000080U
 
#define ADC_RIS0_ASCDONE_M   0x00000080U
 
#define ADC_RIS0_ASCDONE_S   7U
 
#define ADC_RIS0_ASCDONE_SET   0x00000080U
 
#define ADC_RIS0_ASCDONE_CLR   0x00000000U
 
#define ADC_RIS0_UVIFG   0x00000040U
 
#define ADC_RIS0_UVIFG_M   0x00000040U
 
#define ADC_RIS0_UVIFG_S   6U
 
#define ADC_RIS0_UVIFG_SET   0x00000040U
 
#define ADC_RIS0_UVIFG_CLR   0x00000000U
 
#define ADC_RIS0_DMADONE   0x00000020U
 
#define ADC_RIS0_DMADONE_M   0x00000020U
 
#define ADC_RIS0_DMADONE_S   5U
 
#define ADC_RIS0_DMADONE_SET   0x00000020U
 
#define ADC_RIS0_DMADONE_CLR   0x00000000U
 
#define ADC_RIS0_INIFG   0x00000010U
 
#define ADC_RIS0_INIFG_M   0x00000010U
 
#define ADC_RIS0_INIFG_S   4U
 
#define ADC_RIS0_INIFG_SET   0x00000010U
 
#define ADC_RIS0_INIFG_CLR   0x00000000U
 
#define ADC_RIS0_LOWIFG   0x00000008U
 
#define ADC_RIS0_LOWIFG_M   0x00000008U
 
#define ADC_RIS0_LOWIFG_S   3U
 
#define ADC_RIS0_LOWIFG_SET   0x00000008U
 
#define ADC_RIS0_LOWIFG_CLR   0x00000000U
 
#define ADC_RIS0_HIGHIFG   0x00000004U
 
#define ADC_RIS0_HIGHIFG_M   0x00000004U
 
#define ADC_RIS0_HIGHIFG_S   2U
 
#define ADC_RIS0_HIGHIFG_SET   0x00000004U
 
#define ADC_RIS0_HIGHIFG_CLR   0x00000000U
 
#define ADC_RIS0_TOVIFG   0x00000002U
 
#define ADC_RIS0_TOVIFG_M   0x00000002U
 
#define ADC_RIS0_TOVIFG_S   1U
 
#define ADC_RIS0_TOVIFG_SET   0x00000002U
 
#define ADC_RIS0_TOVIFG_CLR   0x00000000U
 
#define ADC_RIS0_OVIFG   0x00000001U
 
#define ADC_RIS0_OVIFG_M   0x00000001U
 
#define ADC_RIS0_OVIFG_S   0U
 
#define ADC_RIS0_OVIFG_SET   0x00000001U
 
#define ADC_RIS0_OVIFG_CLR   0x00000000U
 
#define ADC_MIS0_MEMRESIFG3   0x00000800U
 
#define ADC_MIS0_MEMRESIFG3_M   0x00000800U
 
#define ADC_MIS0_MEMRESIFG3_S   11U
 
#define ADC_MIS0_MEMRESIFG3_SET   0x00000800U
 
#define ADC_MIS0_MEMRESIFG3_CLR   0x00000000U
 
#define ADC_MIS0_MEMRESIFG2   0x00000400U
 
#define ADC_MIS0_MEMRESIFG2_M   0x00000400U
 
#define ADC_MIS0_MEMRESIFG2_S   10U
 
#define ADC_MIS0_MEMRESIFG2_SET   0x00000400U
 
#define ADC_MIS0_MEMRESIFG2_CLR   0x00000000U
 
#define ADC_MIS0_MEMRESIFG1   0x00000200U
 
#define ADC_MIS0_MEMRESIFG1_M   0x00000200U
 
#define ADC_MIS0_MEMRESIFG1_S   9U
 
#define ADC_MIS0_MEMRESIFG1_SET   0x00000200U
 
#define ADC_MIS0_MEMRESIFG1_CLR   0x00000000U
 
#define ADC_MIS0_MEMRESIFG0   0x00000100U
 
#define ADC_MIS0_MEMRESIFG0_M   0x00000100U
 
#define ADC_MIS0_MEMRESIFG0_S   8U
 
#define ADC_MIS0_MEMRESIFG0_SET   0x00000100U
 
#define ADC_MIS0_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_MIS0_ASCDONE   0x00000080U
 
#define ADC_MIS0_ASCDONE_M   0x00000080U
 
#define ADC_MIS0_ASCDONE_S   7U
 
#define ADC_MIS0_ASCDONE_SET   0x00000080U
 
#define ADC_MIS0_ASCDONE_CLR   0x00000000U
 
#define ADC_MIS0_UVIFG   0x00000040U
 
#define ADC_MIS0_UVIFG_M   0x00000040U
 
#define ADC_MIS0_UVIFG_S   6U
 
#define ADC_MIS0_UVIFG_SET   0x00000040U
 
#define ADC_MIS0_UVIFG_CLR   0x00000000U
 
#define ADC_MIS0_DMADONE   0x00000020U
 
#define ADC_MIS0_DMADONE_M   0x00000020U
 
#define ADC_MIS0_DMADONE_S   5U
 
#define ADC_MIS0_DMADONE_SET   0x00000020U
 
#define ADC_MIS0_DMADONE_CLR   0x00000000U
 
#define ADC_MIS0_INIFG   0x00000010U
 
#define ADC_MIS0_INIFG_M   0x00000010U
 
#define ADC_MIS0_INIFG_S   4U
 
#define ADC_MIS0_INIFG_SET   0x00000010U
 
#define ADC_MIS0_INIFG_CLR   0x00000000U
 
#define ADC_MIS0_LOWIFG   0x00000008U
 
#define ADC_MIS0_LOWIFG_M   0x00000008U
 
#define ADC_MIS0_LOWIFG_S   3U
 
#define ADC_MIS0_LOWIFG_SET   0x00000008U
 
#define ADC_MIS0_LOWIFG_CLR   0x00000000U
 
#define ADC_MIS0_HIGHIFG   0x00000004U
 
#define ADC_MIS0_HIGHIFG_M   0x00000004U
 
#define ADC_MIS0_HIGHIFG_S   2U
 
#define ADC_MIS0_HIGHIFG_SET   0x00000004U
 
#define ADC_MIS0_HIGHIFG_CLR   0x00000000U
 
#define ADC_MIS0_TOVIFG   0x00000002U
 
#define ADC_MIS0_TOVIFG_M   0x00000002U
 
#define ADC_MIS0_TOVIFG_S   1U
 
#define ADC_MIS0_TOVIFG_SET   0x00000002U
 
#define ADC_MIS0_TOVIFG_CLR   0x00000000U
 
#define ADC_MIS0_OVIFG   0x00000001U
 
#define ADC_MIS0_OVIFG_M   0x00000001U
 
#define ADC_MIS0_OVIFG_S   0U
 
#define ADC_MIS0_OVIFG_SET   0x00000001U
 
#define ADC_MIS0_OVIFG_CLR   0x00000000U
 
#define ADC_ISET0_MEMRESIFG3   0x00000800U
 
#define ADC_ISET0_MEMRESIFG3_M   0x00000800U
 
#define ADC_ISET0_MEMRESIFG3_S   11U
 
#define ADC_ISET0_MEMRESIFG3_SET   0x00000800U
 
#define ADC_ISET0_MEMRESIFG3_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_MEMRESIFG2   0x00000400U
 
#define ADC_ISET0_MEMRESIFG2_M   0x00000400U
 
#define ADC_ISET0_MEMRESIFG2_S   10U
 
#define ADC_ISET0_MEMRESIFG2_SET   0x00000400U
 
#define ADC_ISET0_MEMRESIFG2_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_MEMRESIFG1   0x00000200U
 
#define ADC_ISET0_MEMRESIFG1_M   0x00000200U
 
#define ADC_ISET0_MEMRESIFG1_S   9U
 
#define ADC_ISET0_MEMRESIFG1_SET   0x00000200U
 
#define ADC_ISET0_MEMRESIFG1_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_MEMRESIFG0   0x00000100U
 
#define ADC_ISET0_MEMRESIFG0_M   0x00000100U
 
#define ADC_ISET0_MEMRESIFG0_S   8U
 
#define ADC_ISET0_MEMRESIFG0_SET   0x00000100U
 
#define ADC_ISET0_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_ASCDONE   0x00000080U
 
#define ADC_ISET0_ASCDONE_M   0x00000080U
 
#define ADC_ISET0_ASCDONE_S   7U
 
#define ADC_ISET0_ASCDONE_SET   0x00000080U
 
#define ADC_ISET0_ASCDONE_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_UVIFG   0x00000040U
 
#define ADC_ISET0_UVIFG_M   0x00000040U
 
#define ADC_ISET0_UVIFG_S   6U
 
#define ADC_ISET0_UVIFG_SET   0x00000040U
 
#define ADC_ISET0_UVIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_DMADONE   0x00000020U
 
#define ADC_ISET0_DMADONE_M   0x00000020U
 
#define ADC_ISET0_DMADONE_S   5U
 
#define ADC_ISET0_DMADONE_SET   0x00000020U
 
#define ADC_ISET0_DMADONE_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_INIFG   0x00000010U
 
#define ADC_ISET0_INIFG_M   0x00000010U
 
#define ADC_ISET0_INIFG_S   4U
 
#define ADC_ISET0_INIFG_SET   0x00000010U
 
#define ADC_ISET0_INIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_LOWIFG   0x00000008U
 
#define ADC_ISET0_LOWIFG_M   0x00000008U
 
#define ADC_ISET0_LOWIFG_S   3U
 
#define ADC_ISET0_LOWIFG_SET   0x00000008U
 
#define ADC_ISET0_LOWIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_HIGHIFG   0x00000004U
 
#define ADC_ISET0_HIGHIFG_M   0x00000004U
 
#define ADC_ISET0_HIGHIFG_S   2U
 
#define ADC_ISET0_HIGHIFG_SET   0x00000004U
 
#define ADC_ISET0_HIGHIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_TOVIFG   0x00000002U
 
#define ADC_ISET0_TOVIFG_M   0x00000002U
 
#define ADC_ISET0_TOVIFG_S   1U
 
#define ADC_ISET0_TOVIFG_SET   0x00000002U
 
#define ADC_ISET0_TOVIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET0_OVIFG   0x00000001U
 
#define ADC_ISET0_OVIFG_M   0x00000001U
 
#define ADC_ISET0_OVIFG_S   0U
 
#define ADC_ISET0_OVIFG_SET   0x00000001U
 
#define ADC_ISET0_OVIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_MEMRESIFG3   0x00000800U
 
#define ADC_ICLR0_MEMRESIFG3_M   0x00000800U
 
#define ADC_ICLR0_MEMRESIFG3_S   11U
 
#define ADC_ICLR0_MEMRESIFG3_CLR   0x00000800U
 
#define ADC_ICLR0_MEMRESIFG3_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_MEMRESIFG2   0x00000400U
 
#define ADC_ICLR0_MEMRESIFG2_M   0x00000400U
 
#define ADC_ICLR0_MEMRESIFG2_S   10U
 
#define ADC_ICLR0_MEMRESIFG2_CLR   0x00000400U
 
#define ADC_ICLR0_MEMRESIFG2_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_MEMRESIFG1   0x00000200U
 
#define ADC_ICLR0_MEMRESIFG1_M   0x00000200U
 
#define ADC_ICLR0_MEMRESIFG1_S   9U
 
#define ADC_ICLR0_MEMRESIFG1_CLR   0x00000200U
 
#define ADC_ICLR0_MEMRESIFG1_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_MEMRESIFG0   0x00000100U
 
#define ADC_ICLR0_MEMRESIFG0_M   0x00000100U
 
#define ADC_ICLR0_MEMRESIFG0_S   8U
 
#define ADC_ICLR0_MEMRESIFG0_CLR   0x00000100U
 
#define ADC_ICLR0_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_ASCDONE   0x00000080U
 
#define ADC_ICLR0_ASCDONE_M   0x00000080U
 
#define ADC_ICLR0_ASCDONE_S   7U
 
#define ADC_ICLR0_ASCDONE_CLR   0x00000080U
 
#define ADC_ICLR0_ASCDONE_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_UVIFG   0x00000040U
 
#define ADC_ICLR0_UVIFG_M   0x00000040U
 
#define ADC_ICLR0_UVIFG_S   6U
 
#define ADC_ICLR0_UVIFG_CLR   0x00000040U
 
#define ADC_ICLR0_UVIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_DMADONE   0x00000020U
 
#define ADC_ICLR0_DMADONE_M   0x00000020U
 
#define ADC_ICLR0_DMADONE_S   5U
 
#define ADC_ICLR0_DMADONE_CLR   0x00000020U
 
#define ADC_ICLR0_DMADONE_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_INIFG   0x00000010U
 
#define ADC_ICLR0_INIFG_M   0x00000010U
 
#define ADC_ICLR0_INIFG_S   4U
 
#define ADC_ICLR0_INIFG_CLR   0x00000010U
 
#define ADC_ICLR0_INIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_LOWIFG   0x00000008U
 
#define ADC_ICLR0_LOWIFG_M   0x00000008U
 
#define ADC_ICLR0_LOWIFG_S   3U
 
#define ADC_ICLR0_LOWIFG_CLR   0x00000008U
 
#define ADC_ICLR0_LOWIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_HIGHIFG   0x00000004U
 
#define ADC_ICLR0_HIGHIFG_M   0x00000004U
 
#define ADC_ICLR0_HIGHIFG_S   2U
 
#define ADC_ICLR0_HIGHIFG_CLR   0x00000004U
 
#define ADC_ICLR0_HIGHIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_TOVIFG   0x00000002U
 
#define ADC_ICLR0_TOVIFG_M   0x00000002U
 
#define ADC_ICLR0_TOVIFG_S   1U
 
#define ADC_ICLR0_TOVIFG_CLR   0x00000002U
 
#define ADC_ICLR0_TOVIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR0_OVIFG   0x00000001U
 
#define ADC_ICLR0_OVIFG_M   0x00000001U
 
#define ADC_ICLR0_OVIFG_S   0U
 
#define ADC_ICLR0_OVIFG_CLR   0x00000001U
 
#define ADC_ICLR0_OVIFG_NO_EFFECT   0x00000000U
 
#define ADC_IMASK1_MEMRESIFG0   0x00000100U
 
#define ADC_IMASK1_MEMRESIFG0_M   0x00000100U
 
#define ADC_IMASK1_MEMRESIFG0_S   8U
 
#define ADC_IMASK1_MEMRESIFG0_SET   0x00000100U
 
#define ADC_IMASK1_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_IMASK1_INIFG   0x00000010U
 
#define ADC_IMASK1_INIFG_M   0x00000010U
 
#define ADC_IMASK1_INIFG_S   4U
 
#define ADC_IMASK1_INIFG_SET   0x00000010U
 
#define ADC_IMASK1_INIFG_CLR   0x00000000U
 
#define ADC_IMASK1_LOWIFG   0x00000008U
 
#define ADC_IMASK1_LOWIFG_M   0x00000008U
 
#define ADC_IMASK1_LOWIFG_S   3U
 
#define ADC_IMASK1_LOWIFG_SET   0x00000008U
 
#define ADC_IMASK1_LOWIFG_CLR   0x00000000U
 
#define ADC_IMASK1_HIGHIFG   0x00000004U
 
#define ADC_IMASK1_HIGHIFG_M   0x00000004U
 
#define ADC_IMASK1_HIGHIFG_S   2U
 
#define ADC_IMASK1_HIGHIFG_SET   0x00000004U
 
#define ADC_IMASK1_HIGHIFG_CLR   0x00000000U
 
#define ADC_RIS1_MEMRESIFG0   0x00000100U
 
#define ADC_RIS1_MEMRESIFG0_M   0x00000100U
 
#define ADC_RIS1_MEMRESIFG0_S   8U
 
#define ADC_RIS1_MEMRESIFG0_SET   0x00000100U
 
#define ADC_RIS1_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_RIS1_INIFG   0x00000010U
 
#define ADC_RIS1_INIFG_M   0x00000010U
 
#define ADC_RIS1_INIFG_S   4U
 
#define ADC_RIS1_INIFG_SET   0x00000010U
 
#define ADC_RIS1_INIFG_CLR   0x00000000U
 
#define ADC_RIS1_LOWIFG   0x00000008U
 
#define ADC_RIS1_LOWIFG_M   0x00000008U
 
#define ADC_RIS1_LOWIFG_S   3U
 
#define ADC_RIS1_LOWIFG_SET   0x00000008U
 
#define ADC_RIS1_LOWIFG_CLR   0x00000000U
 
#define ADC_RIS1_HIGHIFG   0x00000004U
 
#define ADC_RIS1_HIGHIFG_M   0x00000004U
 
#define ADC_RIS1_HIGHIFG_S   2U
 
#define ADC_RIS1_HIGHIFG_SET   0x00000004U
 
#define ADC_RIS1_HIGHIFG_CLR   0x00000000U
 
#define ADC_MIS1_MEMRESIFG0   0x00000100U
 
#define ADC_MIS1_MEMRESIFG0_M   0x00000100U
 
#define ADC_MIS1_MEMRESIFG0_S   8U
 
#define ADC_MIS1_MEMRESIFG0_SET   0x00000100U
 
#define ADC_MIS1_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_MIS1_INIFG   0x00000010U
 
#define ADC_MIS1_INIFG_M   0x00000010U
 
#define ADC_MIS1_INIFG_S   4U
 
#define ADC_MIS1_INIFG_SET   0x00000010U
 
#define ADC_MIS1_INIFG_CLR   0x00000000U
 
#define ADC_MIS1_LOWIFG   0x00000008U
 
#define ADC_MIS1_LOWIFG_M   0x00000008U
 
#define ADC_MIS1_LOWIFG_S   3U
 
#define ADC_MIS1_LOWIFG_SET   0x00000008U
 
#define ADC_MIS1_LOWIFG_CLR   0x00000000U
 
#define ADC_MIS1_HIGHIFG   0x00000004U
 
#define ADC_MIS1_HIGHIFG_M   0x00000004U
 
#define ADC_MIS1_HIGHIFG_S   2U
 
#define ADC_MIS1_HIGHIFG_SET   0x00000004U
 
#define ADC_MIS1_HIGHIFG_CLR   0x00000000U
 
#define ADC_ISET1_MEMRESIFG0   0x00000100U
 
#define ADC_ISET1_MEMRESIFG0_M   0x00000100U
 
#define ADC_ISET1_MEMRESIFG0_S   8U
 
#define ADC_ISET1_MEMRESIFG0_SET   0x00000100U
 
#define ADC_ISET1_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_ISET1_INIFG   0x00000010U
 
#define ADC_ISET1_INIFG_M   0x00000010U
 
#define ADC_ISET1_INIFG_S   4U
 
#define ADC_ISET1_INIFG_SET   0x00000010U
 
#define ADC_ISET1_INIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET1_LOWIFG   0x00000008U
 
#define ADC_ISET1_LOWIFG_M   0x00000008U
 
#define ADC_ISET1_LOWIFG_S   3U
 
#define ADC_ISET1_LOWIFG_SET   0x00000008U
 
#define ADC_ISET1_LOWIFG_NO_EFFECT   0x00000000U
 
#define ADC_ISET1_HIGHIFG   0x00000004U
 
#define ADC_ISET1_HIGHIFG_M   0x00000004U
 
#define ADC_ISET1_HIGHIFG_S   2U
 
#define ADC_ISET1_HIGHIFG_SET   0x00000004U
 
#define ADC_ISET1_HIGHIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR1_MEMRESIFG0   0x00000100U
 
#define ADC_ICLR1_MEMRESIFG0_M   0x00000100U
 
#define ADC_ICLR1_MEMRESIFG0_S   8U
 
#define ADC_ICLR1_MEMRESIFG0_CLR   0x00000100U
 
#define ADC_ICLR1_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_ICLR1_INIFG   0x00000010U
 
#define ADC_ICLR1_INIFG_M   0x00000010U
 
#define ADC_ICLR1_INIFG_S   4U
 
#define ADC_ICLR1_INIFG_CLR   0x00000010U
 
#define ADC_ICLR1_INIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR1_LOWIFG   0x00000008U
 
#define ADC_ICLR1_LOWIFG_M   0x00000008U
 
#define ADC_ICLR1_LOWIFG_S   3U
 
#define ADC_ICLR1_LOWIFG_CLR   0x00000008U
 
#define ADC_ICLR1_LOWIFG_NO_EFFECT   0x00000000U
 
#define ADC_ICLR1_HIGHIFG   0x00000004U
 
#define ADC_ICLR1_HIGHIFG_M   0x00000004U
 
#define ADC_ICLR1_HIGHIFG_S   2U
 
#define ADC_ICLR1_HIGHIFG_CLR   0x00000004U
 
#define ADC_ICLR1_HIGHIFG_NO_EFFECT   0x00000000U
 
#define ADC_IMASK2_MEMRESIFG3   0x00000800U
 
#define ADC_IMASK2_MEMRESIFG3_M   0x00000800U
 
#define ADC_IMASK2_MEMRESIFG3_S   11U
 
#define ADC_IMASK2_MEMRESIFG3_SET   0x00000800U
 
#define ADC_IMASK2_MEMRESIFG3_CLR   0x00000000U
 
#define ADC_IMASK2_MEMRESIFG2   0x00000400U
 
#define ADC_IMASK2_MEMRESIFG2_M   0x00000400U
 
#define ADC_IMASK2_MEMRESIFG2_S   10U
 
#define ADC_IMASK2_MEMRESIFG2_SET   0x00000400U
 
#define ADC_IMASK2_MEMRESIFG2_CLR   0x00000000U
 
#define ADC_IMASK2_MEMRESIFG1   0x00000200U
 
#define ADC_IMASK2_MEMRESIFG1_M   0x00000200U
 
#define ADC_IMASK2_MEMRESIFG1_S   9U
 
#define ADC_IMASK2_MEMRESIFG1_SET   0x00000200U
 
#define ADC_IMASK2_MEMRESIFG1_CLR   0x00000000U
 
#define ADC_IMASK2_MEMRESIFG0   0x00000100U
 
#define ADC_IMASK2_MEMRESIFG0_M   0x00000100U
 
#define ADC_IMASK2_MEMRESIFG0_S   8U
 
#define ADC_IMASK2_MEMRESIFG0_SET   0x00000100U
 
#define ADC_IMASK2_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_RIS2_MEMRESIFG3   0x00000800U
 
#define ADC_RIS2_MEMRESIFG3_M   0x00000800U
 
#define ADC_RIS2_MEMRESIFG3_S   11U
 
#define ADC_RIS2_MEMRESIFG3_SET   0x00000800U
 
#define ADC_RIS2_MEMRESIFG3_CLR   0x00000000U
 
#define ADC_RIS2_MEMRESIFG2   0x00000400U
 
#define ADC_RIS2_MEMRESIFG2_M   0x00000400U
 
#define ADC_RIS2_MEMRESIFG2_S   10U
 
#define ADC_RIS2_MEMRESIFG2_SET   0x00000400U
 
#define ADC_RIS2_MEMRESIFG2_CLR   0x00000000U
 
#define ADC_RIS2_MEMRESIFG1   0x00000200U
 
#define ADC_RIS2_MEMRESIFG1_M   0x00000200U
 
#define ADC_RIS2_MEMRESIFG1_S   9U
 
#define ADC_RIS2_MEMRESIFG1_SET   0x00000200U
 
#define ADC_RIS2_MEMRESIFG1_CLR   0x00000000U
 
#define ADC_RIS2_MEMRESIFG0   0x00000100U
 
#define ADC_RIS2_MEMRESIFG0_M   0x00000100U
 
#define ADC_RIS2_MEMRESIFG0_S   8U
 
#define ADC_RIS2_MEMRESIFG0_SET   0x00000100U
 
#define ADC_RIS2_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_MIS2_MEMRESIFG3   0x00000800U
 
#define ADC_MIS2_MEMRESIFG3_M   0x00000800U
 
#define ADC_MIS2_MEMRESIFG3_S   11U
 
#define ADC_MIS2_MEMRESIFG3_SET   0x00000800U
 
#define ADC_MIS2_MEMRESIFG3_CLR   0x00000000U
 
#define ADC_MIS2_MEMRESIFG2   0x00000400U
 
#define ADC_MIS2_MEMRESIFG2_M   0x00000400U
 
#define ADC_MIS2_MEMRESIFG2_S   10U
 
#define ADC_MIS2_MEMRESIFG2_SET   0x00000400U
 
#define ADC_MIS2_MEMRESIFG2_CLR   0x00000000U
 
#define ADC_MIS2_MEMRESIFG1   0x00000200U
 
#define ADC_MIS2_MEMRESIFG1_M   0x00000200U
 
#define ADC_MIS2_MEMRESIFG1_S   9U
 
#define ADC_MIS2_MEMRESIFG1_SET   0x00000200U
 
#define ADC_MIS2_MEMRESIFG1_CLR   0x00000000U
 
#define ADC_MIS2_MEMRESIFG0   0x00000100U
 
#define ADC_MIS2_MEMRESIFG0_M   0x00000100U
 
#define ADC_MIS2_MEMRESIFG0_S   8U
 
#define ADC_MIS2_MEMRESIFG0_SET   0x00000100U
 
#define ADC_MIS2_MEMRESIFG0_CLR   0x00000000U
 
#define ADC_ISET2_MEMRESIFG3   0x00000800U
 
#define ADC_ISET2_MEMRESIFG3_M   0x00000800U
 
#define ADC_ISET2_MEMRESIFG3_S   11U
 
#define ADC_ISET2_MEMRESIFG3_SET   0x00000800U
 
#define ADC_ISET2_MEMRESIFG3_NO_EFFECT   0x00000000U
 
#define ADC_ISET2_MEMRESIFG2   0x00000400U
 
#define ADC_ISET2_MEMRESIFG2_M   0x00000400U
 
#define ADC_ISET2_MEMRESIFG2_S   10U
 
#define ADC_ISET2_MEMRESIFG2_SET   0x00000400U
 
#define ADC_ISET2_MEMRESIFG2_NO_EFFECT   0x00000000U
 
#define ADC_ISET2_MEMRESIFG1   0x00000200U
 
#define ADC_ISET2_MEMRESIFG1_M   0x00000200U
 
#define ADC_ISET2_MEMRESIFG1_S   9U
 
#define ADC_ISET2_MEMRESIFG1_SET   0x00000200U
 
#define ADC_ISET2_MEMRESIFG1_NO_EFFECT   0x00000000U
 
#define ADC_ISET2_MEMRESIFG0   0x00000100U
 
#define ADC_ISET2_MEMRESIFG0_M   0x00000100U
 
#define ADC_ISET2_MEMRESIFG0_S   8U
 
#define ADC_ISET2_MEMRESIFG0_SET   0x00000100U
 
#define ADC_ISET2_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_ICLR2_MEMRESIFG3   0x00000800U
 
#define ADC_ICLR2_MEMRESIFG3_M   0x00000800U
 
#define ADC_ICLR2_MEMRESIFG3_S   11U
 
#define ADC_ICLR2_MEMRESIFG3_CLR   0x00000800U
 
#define ADC_ICLR2_MEMRESIFG3_NO_EFFECT   0x00000000U
 
#define ADC_ICLR2_MEMRESIFG2   0x00000400U
 
#define ADC_ICLR2_MEMRESIFG2_M   0x00000400U
 
#define ADC_ICLR2_MEMRESIFG2_S   10U
 
#define ADC_ICLR2_MEMRESIFG2_CLR   0x00000400U
 
#define ADC_ICLR2_MEMRESIFG2_NO_EFFECT   0x00000000U
 
#define ADC_ICLR2_MEMRESIFG1   0x00000200U
 
#define ADC_ICLR2_MEMRESIFG1_M   0x00000200U
 
#define ADC_ICLR2_MEMRESIFG1_S   9U
 
#define ADC_ICLR2_MEMRESIFG1_CLR   0x00000200U
 
#define ADC_ICLR2_MEMRESIFG1_NO_EFFECT   0x00000000U
 
#define ADC_ICLR2_MEMRESIFG0   0x00000100U
 
#define ADC_ICLR2_MEMRESIFG0_M   0x00000100U
 
#define ADC_ICLR2_MEMRESIFG0_S   8U
 
#define ADC_ICLR2_MEMRESIFG0_CLR   0x00000100U
 
#define ADC_ICLR2_MEMRESIFG0_NO_EFFECT   0x00000000U
 
#define ADC_CTL0_SCLKDIV_W   3U
 
#define ADC_CTL0_SCLKDIV_M   0x07000000U
 
#define ADC_CTL0_SCLKDIV_S   24U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_48   0x07000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_32   0x06000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_24   0x05000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_16   0x04000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_8   0x03000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_4   0x02000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_2   0x01000000U
 
#define ADC_CTL0_SCLKDIV_DIV_BY_1   0x00000000U
 
#define ADC_CTL0_PWRDN   0x00010000U
 
#define ADC_CTL0_PWRDN_M   0x00010000U
 
#define ADC_CTL0_PWRDN_S   16U
 
#define ADC_CTL0_PWRDN_MANUAL   0x00010000U
 
#define ADC_CTL0_PWRDN_AUTO   0x00000000U
 
#define ADC_CTL0_ENC   0x00000001U
 
#define ADC_CTL0_ENC_M   0x00000001U
 
#define ADC_CTL0_ENC_S   0U
 
#define ADC_CTL0_ENC_ON   0x00000001U
 
#define ADC_CTL0_ENC_OFF   0x00000000U
 
#define ADC_CTL1_SAMPMODE   0x00100000U
 
#define ADC_CTL1_SAMPMODE_M   0x00100000U
 
#define ADC_CTL1_SAMPMODE_S   20U
 
#define ADC_CTL1_SAMPMODE_MANUAL   0x00100000U
 
#define ADC_CTL1_SAMPMODE_AUTO   0x00000000U
 
#define ADC_CTL1_CONSEQ_W   2U
 
#define ADC_CTL1_CONSEQ_M   0x00030000U
 
#define ADC_CTL1_CONSEQ_S   16U
 
#define ADC_CTL1_CONSEQ_REPEATSEQUENCE   0x00030000U
 
#define ADC_CTL1_CONSEQ_REPEATSINGLE   0x00020000U
 
#define ADC_CTL1_CONSEQ_SEQUENCE   0x00010000U
 
#define ADC_CTL1_CONSEQ_SINGLE   0x00000000U
 
#define ADC_CTL1_SC   0x00000100U
 
#define ADC_CTL1_SC_M   0x00000100U
 
#define ADC_CTL1_SC_S   8U
 
#define ADC_CTL1_SC_START   0x00000100U
 
#define ADC_CTL1_SC_STOP   0x00000000U
 
#define ADC_CTL1_TRIGSRC   0x00000001U
 
#define ADC_CTL1_TRIGSRC_M   0x00000001U
 
#define ADC_CTL1_TRIGSRC_S   0U
 
#define ADC_CTL1_TRIGSRC_EVENT   0x00000001U
 
#define ADC_CTL1_TRIGSRC_SOFTWARE   0x00000000U
 
#define ADC_CTL2_ENDADD_W   5U
 
#define ADC_CTL2_ENDADD_M   0x1F000000U
 
#define ADC_CTL2_ENDADD_S   24U
 
#define ADC_CTL2_ENDADD_ADDR_03   0x03000000U
 
#define ADC_CTL2_ENDADD_ADDR_02   0x02000000U
 
#define ADC_CTL2_ENDADD_ADDR_01   0x01000000U
 
#define ADC_CTL2_ENDADD_ADDR_00   0x00000000U
 
#define ADC_CTL2_STARTADD_W   5U
 
#define ADC_CTL2_STARTADD_M   0x001F0000U
 
#define ADC_CTL2_STARTADD_S   16U
 
#define ADC_CTL2_STARTADD_ADDR_03   0x00030000U
 
#define ADC_CTL2_STARTADD_ADDR_02   0x00020000U
 
#define ADC_CTL2_STARTADD_ADDR_01   0x00010000U
 
#define ADC_CTL2_STARTADD_ADDR_00   0x00000000U
 
#define ADC_CTL2_FIFOEN   0x00000400U
 
#define ADC_CTL2_FIFOEN_M   0x00000400U
 
#define ADC_CTL2_FIFOEN_S   10U
 
#define ADC_CTL2_FIFOEN_EN   0x00000400U
 
#define ADC_CTL2_FIFOEN_DIS   0x00000000U
 
#define ADC_CTL2_DMAEN   0x00000100U
 
#define ADC_CTL2_DMAEN_M   0x00000100U
 
#define ADC_CTL2_DMAEN_S   8U
 
#define ADC_CTL2_DMAEN_EN   0x00000100U
 
#define ADC_CTL2_DMAEN_DIS   0x00000000U
 
#define ADC_CTL2_RES_W   2U
 
#define ADC_CTL2_RES_M   0x00000006U
 
#define ADC_CTL2_RES_S   1U
 
#define ADC_CTL2_RES_BIT_8   0x00000004U
 
#define ADC_CTL2_RES_BIT_10   0x00000002U
 
#define ADC_CTL2_RES_BIT_12   0x00000000U
 
#define ADC_CTL2_DF   0x00000001U
 
#define ADC_CTL2_DF_M   0x00000001U
 
#define ADC_CTL2_DF_S   0U
 
#define ADC_CTL2_DF_SIGNED   0x00000001U
 
#define ADC_CTL2_DF_UNSIGNED   0x00000000U
 
#define ADC_CTL3_ASCVRSEL_W   2U
 
#define ADC_CTL3_ASCVRSEL_M   0x00003000U
 
#define ADC_CTL3_ASCVRSEL_S   12U
 
#define ADC_CTL3_ASCVRSEL_INTREF   0x00002000U
 
#define ADC_CTL3_ASCVRSEL_EXTREF   0x00001000U
 
#define ADC_CTL3_ASCVRSEL_VDDS   0x00000000U
 
#define ADC_CTL3_ASCSTIME   0x00000100U
 
#define ADC_CTL3_ASCSTIME_M   0x00000100U
 
#define ADC_CTL3_ASCSTIME_S   8U
 
#define ADC_CTL3_ASCSTIME_SEL_SCOMP1   0x00000100U
 
#define ADC_CTL3_ASCSTIME_SEL_SCOMP0   0x00000000U
 
#define ADC_CTL3_ASCCHSEL_W   5U
 
#define ADC_CTL3_ASCCHSEL_M   0x0000001FU
 
#define ADC_CTL3_ASCCHSEL_S   0U
 
#define ADC_CTL3_ASCCHSEL_CHAN_15   0x0000000FU
 
#define ADC_CTL3_ASCCHSEL_CHAN_14   0x0000000EU
 
#define ADC_CTL3_ASCCHSEL_CHAN_13   0x0000000DU
 
#define ADC_CTL3_ASCCHSEL_CHAN_12   0x0000000CU
 
#define ADC_CTL3_ASCCHSEL_CHAN_11   0x0000000BU
 
#define ADC_CTL3_ASCCHSEL_CHAN_10   0x0000000AU
 
#define ADC_CTL3_ASCCHSEL_CHAN_9   0x00000009U
 
#define ADC_CTL3_ASCCHSEL_CHAN_8   0x00000008U
 
#define ADC_CTL3_ASCCHSEL_CHAN_7   0x00000007U
 
#define ADC_CTL3_ASCCHSEL_CHAN_6   0x00000006U
 
#define ADC_CTL3_ASCCHSEL_CHAN_5   0x00000005U
 
#define ADC_CTL3_ASCCHSEL_CHAN_4   0x00000004U
 
#define ADC_CTL3_ASCCHSEL_CHAN_3   0x00000003U
 
#define ADC_CTL3_ASCCHSEL_CHAN_2   0x00000002U
 
#define ADC_CTL3_ASCCHSEL_CHAN_1   0x00000001U
 
#define ADC_CTL3_ASCCHSEL_CHAN_0   0x00000000U
 
#define ADC_SCOMP0_VAL_W   10U
 
#define ADC_SCOMP0_VAL_M   0x000003FFU
 
#define ADC_SCOMP0_VAL_S   0U
 
#define ADC_SCOMP1_VAL_W   10U
 
#define ADC_SCOMP1_VAL_M   0x000003FFU
 
#define ADC_SCOMP1_VAL_S   0U
 
#define ADC_REFCFG_IBPROG_W   2U
 
#define ADC_REFCFG_IBPROG_M   0x00000018U
 
#define ADC_REFCFG_IBPROG_S   3U
 
#define ADC_REFCFG_IBPROG_VAL3   0x00000018U
 
#define ADC_REFCFG_IBPROG_VAL2   0x00000010U
 
#define ADC_REFCFG_IBPROG_VAL1   0x00000008U
 
#define ADC_REFCFG_IBPROG_VAL0   0x00000000U
 
#define ADC_REFCFG_SPARE   0x00000004U
 
#define ADC_REFCFG_SPARE_M   0x00000004U
 
#define ADC_REFCFG_SPARE_S   2U
 
#define ADC_REFCFG_REFVSEL   0x00000002U
 
#define ADC_REFCFG_REFVSEL_M   0x00000002U
 
#define ADC_REFCFG_REFVSEL_S   1U
 
#define ADC_REFCFG_REFVSEL_V1P4   0x00000002U
 
#define ADC_REFCFG_REFVSEL_V2P5   0x00000000U
 
#define ADC_REFCFG_REFEN   0x00000001U
 
#define ADC_REFCFG_REFEN_M   0x00000001U
 
#define ADC_REFCFG_REFEN_S   0U
 
#define ADC_REFCFG_REFEN_EN   0x00000001U
 
#define ADC_REFCFG_REFEN_DIS   0x00000000U
 
#define ADC_WCLOW_DATA_W   16U
 
#define ADC_WCLOW_DATA_M   0x0000FFFFU
 
#define ADC_WCLOW_DATA_S   0U
 
#define ADC_WCHIGH_DATA_W   16U
 
#define ADC_WCHIGH_DATA_M   0x0000FFFFU
 
#define ADC_WCHIGH_DATA_S   0U
 
#define ADC_FIFODATA_DATA_W   32U
 
#define ADC_FIFODATA_DATA_M   0xFFFFFFFFU
 
#define ADC_FIFODATA_DATA_S   0U
 
#define ADC_ASCRES_DATA_W   16U
 
#define ADC_ASCRES_DATA_M   0x0000FFFFU
 
#define ADC_ASCRES_DATA_S   0U
 
#define ADC_MEMCTL0_WINCOMP   0x10000000U
 
#define ADC_MEMCTL0_WINCOMP_M   0x10000000U
 
#define ADC_MEMCTL0_WINCOMP_S   28U
 
#define ADC_MEMCTL0_WINCOMP_EN   0x10000000U
 
#define ADC_MEMCTL0_WINCOMP_DIS   0x00000000U
 
#define ADC_MEMCTL0_TRG   0x01000000U
 
#define ADC_MEMCTL0_TRG_M   0x01000000U
 
#define ADC_MEMCTL0_TRG_S   24U
 
#define ADC_MEMCTL0_TRG_TRIGGER_NEXT   0x01000000U
 
#define ADC_MEMCTL0_TRG_AUTO_NEXT   0x00000000U
 
#define ADC_MEMCTL0_STIME   0x00001000U
 
#define ADC_MEMCTL0_STIME_M   0x00001000U
 
#define ADC_MEMCTL0_STIME_S   12U
 
#define ADC_MEMCTL0_STIME_SEL_SCOMP1   0x00001000U
 
#define ADC_MEMCTL0_STIME_SEL_SCOMP0   0x00000000U
 
#define ADC_MEMCTL0_VRSEL_W   2U
 
#define ADC_MEMCTL0_VRSEL_M   0x00000300U
 
#define ADC_MEMCTL0_VRSEL_S   8U
 
#define ADC_MEMCTL0_VRSEL_INTREF   0x00000200U
 
#define ADC_MEMCTL0_VRSEL_EXTREF   0x00000100U
 
#define ADC_MEMCTL0_VRSEL_VDDS   0x00000000U
 
#define ADC_MEMCTL0_CHANSEL_W   5U
 
#define ADC_MEMCTL0_CHANSEL_M   0x0000001FU
 
#define ADC_MEMCTL0_CHANSEL_S   0U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_15   0x0000000FU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_14   0x0000000EU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_13   0x0000000DU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_12   0x0000000CU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_11   0x0000000BU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_10   0x0000000AU
 
#define ADC_MEMCTL0_CHANSEL_CHAN_9   0x00000009U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_8   0x00000008U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_7   0x00000007U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_6   0x00000006U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_5   0x00000005U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_4   0x00000004U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_3   0x00000003U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_2   0x00000002U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_1   0x00000001U
 
#define ADC_MEMCTL0_CHANSEL_CHAN_0   0x00000000U
 
#define ADC_MEMCTL1_WINCOMP   0x10000000U
 
#define ADC_MEMCTL1_WINCOMP_M   0x10000000U
 
#define ADC_MEMCTL1_WINCOMP_S   28U
 
#define ADC_MEMCTL1_WINCOMP_EN   0x10000000U
 
#define ADC_MEMCTL1_WINCOMP_DIS   0x00000000U
 
#define ADC_MEMCTL1_TRG   0x01000000U
 
#define ADC_MEMCTL1_TRG_M   0x01000000U
 
#define ADC_MEMCTL1_TRG_S   24U
 
#define ADC_MEMCTL1_TRG_TRIGGER_NEXT   0x01000000U
 
#define ADC_MEMCTL1_TRG_AUTO_NEXT   0x00000000U
 
#define ADC_MEMCTL1_STIME   0x00001000U
 
#define ADC_MEMCTL1_STIME_M   0x00001000U
 
#define ADC_MEMCTL1_STIME_S   12U
 
#define ADC_MEMCTL1_STIME_SEL_SCOMP1   0x00001000U
 
#define ADC_MEMCTL1_STIME_SEL_SCOMP0   0x00000000U
 
#define ADC_MEMCTL1_VRSEL_W   2U
 
#define ADC_MEMCTL1_VRSEL_M   0x00000300U
 
#define ADC_MEMCTL1_VRSEL_S   8U
 
#define ADC_MEMCTL1_VRSEL_INTREF   0x00000200U
 
#define ADC_MEMCTL1_VRSEL_EXTREF   0x00000100U
 
#define ADC_MEMCTL1_VRSEL_VDDS   0x00000000U
 
#define ADC_MEMCTL1_CHANSEL_W   5U
 
#define ADC_MEMCTL1_CHANSEL_M   0x0000001FU
 
#define ADC_MEMCTL1_CHANSEL_S   0U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_15   0x0000000FU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_14   0x0000000EU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_13   0x0000000DU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_12   0x0000000CU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_11   0x0000000BU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_10   0x0000000AU
 
#define ADC_MEMCTL1_CHANSEL_CHAN_9   0x00000009U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_8   0x00000008U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_7   0x00000007U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_6   0x00000006U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_5   0x00000005U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_4   0x00000004U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_3   0x00000003U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_2   0x00000002U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_1   0x00000001U
 
#define ADC_MEMCTL1_CHANSEL_CHAN_0   0x00000000U
 
#define ADC_MEMCTL2_WINCOMP   0x10000000U
 
#define ADC_MEMCTL2_WINCOMP_M   0x10000000U
 
#define ADC_MEMCTL2_WINCOMP_S   28U
 
#define ADC_MEMCTL2_WINCOMP_EN   0x10000000U
 
#define ADC_MEMCTL2_WINCOMP_DIS   0x00000000U
 
#define ADC_MEMCTL2_TRG   0x01000000U
 
#define ADC_MEMCTL2_TRG_M   0x01000000U
 
#define ADC_MEMCTL2_TRG_S   24U
 
#define ADC_MEMCTL2_TRG_TRIGGER_NEXT   0x01000000U
 
#define ADC_MEMCTL2_TRG_AUTO_NEXT   0x00000000U
 
#define ADC_MEMCTL2_STIME   0x00001000U
 
#define ADC_MEMCTL2_STIME_M   0x00001000U
 
#define ADC_MEMCTL2_STIME_S   12U
 
#define ADC_MEMCTL2_STIME_SEL_SCOMP1   0x00001000U
 
#define ADC_MEMCTL2_STIME_SEL_SCOMP0   0x00000000U
 
#define ADC_MEMCTL2_VRSEL_W   2U
 
#define ADC_MEMCTL2_VRSEL_M   0x00000300U
 
#define ADC_MEMCTL2_VRSEL_S   8U
 
#define ADC_MEMCTL2_VRSEL_INTREF   0x00000200U
 
#define ADC_MEMCTL2_VRSEL_EXTREF   0x00000100U
 
#define ADC_MEMCTL2_VRSEL_VDDS   0x00000000U
 
#define ADC_MEMCTL2_CHANSEL_W   5U
 
#define ADC_MEMCTL2_CHANSEL_M   0x0000001FU
 
#define ADC_MEMCTL2_CHANSEL_S   0U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_15   0x0000000FU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_14   0x0000000EU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_13   0x0000000DU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_12   0x0000000CU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_11   0x0000000BU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_10   0x0000000AU
 
#define ADC_MEMCTL2_CHANSEL_CHAN_9   0x00000009U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_8   0x00000008U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_7   0x00000007U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_6   0x00000006U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_5   0x00000005U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_4   0x00000004U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_3   0x00000003U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_2   0x00000002U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_1   0x00000001U
 
#define ADC_MEMCTL2_CHANSEL_CHAN_0   0x00000000U
 
#define ADC_MEMCTL3_WINCOMP   0x10000000U
 
#define ADC_MEMCTL3_WINCOMP_M   0x10000000U
 
#define ADC_MEMCTL3_WINCOMP_S   28U
 
#define ADC_MEMCTL3_WINCOMP_EN   0x10000000U
 
#define ADC_MEMCTL3_WINCOMP_DIS   0x00000000U
 
#define ADC_MEMCTL3_TRG   0x01000000U
 
#define ADC_MEMCTL3_TRG_M   0x01000000U
 
#define ADC_MEMCTL3_TRG_S   24U
 
#define ADC_MEMCTL3_TRG_TRIGGER_NEXT   0x01000000U
 
#define ADC_MEMCTL3_TRG_AUTO_NEXT   0x00000000U
 
#define ADC_MEMCTL3_STIME   0x00001000U
 
#define ADC_MEMCTL3_STIME_M   0x00001000U
 
#define ADC_MEMCTL3_STIME_S   12U
 
#define ADC_MEMCTL3_STIME_SEL_SCOMP1   0x00001000U
 
#define ADC_MEMCTL3_STIME_SEL_SCOMP0   0x00000000U
 
#define ADC_MEMCTL3_VRSEL_W   2U
 
#define ADC_MEMCTL3_VRSEL_M   0x00000300U
 
#define ADC_MEMCTL3_VRSEL_S   8U
 
#define ADC_MEMCTL3_VRSEL_INTREF   0x00000200U
 
#define ADC_MEMCTL3_VRSEL_EXTREF   0x00000100U
 
#define ADC_MEMCTL3_VRSEL_VDDS   0x00000000U
 
#define ADC_MEMCTL3_CHANSEL_W   5U
 
#define ADC_MEMCTL3_CHANSEL_M   0x0000001FU
 
#define ADC_MEMCTL3_CHANSEL_S   0U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_15   0x0000000FU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_14   0x0000000EU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_13   0x0000000DU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_12   0x0000000CU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_11   0x0000000BU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_10   0x0000000AU
 
#define ADC_MEMCTL3_CHANSEL_CHAN_9   0x00000009U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_8   0x00000008U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_7   0x00000007U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_6   0x00000006U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_5   0x00000005U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_4   0x00000004U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_3   0x00000003U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_2   0x00000002U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_1   0x00000001U
 
#define ADC_MEMCTL3_CHANSEL_CHAN_0   0x00000000U
 
#define ADC_MEMRES0_DATA_W   16U
 
#define ADC_MEMRES0_DATA_M   0x0000FFFFU
 
#define ADC_MEMRES0_DATA_S   0U
 
#define ADC_MEMRES1_DATA_W   16U
 
#define ADC_MEMRES1_DATA_M   0x0000FFFFU
 
#define ADC_MEMRES1_DATA_S   0U
 
#define ADC_MEMRES2_DATA_W   16U
 
#define ADC_MEMRES2_DATA_M   0x0000FFFFU
 
#define ADC_MEMRES2_DATA_S   0U
 
#define ADC_MEMRES3_DATA_W   16U
 
#define ADC_MEMRES3_DATA_M   0x0000FFFFU
 
#define ADC_MEMRES3_DATA_S   0U
 
#define ADC_STA_ASCACT   0x00000004U
 
#define ADC_STA_ASCACT_M   0x00000004U
 
#define ADC_STA_ASCACT_S   2U
 
#define ADC_STA_ASCACT_ACTIVE   0x00000004U
 
#define ADC_STA_ASCACT_IDLE   0x00000000U
 
#define ADC_STA_BUSY   0x00000001U
 
#define ADC_STA_BUSY_M   0x00000001U
 
#define ADC_STA_BUSY_S   0U
 
#define ADC_STA_BUSY_ACTIVE   0x00000001U
 
#define ADC_STA_BUSY_IDLE   0x00000000U
 
#define ADC_TEST0_ATEST0_EN   0x40000000U
 
#define ADC_TEST0_ATEST0_EN_M   0x40000000U
 
#define ADC_TEST0_ATEST0_EN_S   30U
 
#define ADC_TEST0_ATEST0_EN_EN   0x40000000U
 
#define ADC_TEST0_ATEST0_EN_DIS   0x00000000U
 
#define ADC_TEST0_ATEST1_EN   0x20000000U
 
#define ADC_TEST0_ATEST1_EN_M   0x20000000U
 
#define ADC_TEST0_ATEST1_EN_S   29U
 
#define ADC_TEST0_ATEST1_EN_EN   0x20000000U
 
#define ADC_TEST0_ATEST1_EN_DIS   0x00000000U
 
#define ADC_TEST0_ATEST1_MUXSEL_W   5U
 
#define ADC_TEST0_ATEST1_MUXSEL_M   0x00001F00U
 
#define ADC_TEST0_ATEST1_MUXSEL_S   8U
 
#define ADC_TEST0_ATEST1_MUXSEL_VAL16   0x00001000U
 
#define ADC_TEST0_ATEST1_MUXSEL_VAL8   0x00000800U
 
#define ADC_TEST0_ATEST1_MUXSEL_VAL4   0x00000400U
 
#define ADC_TEST0_ATEST1_MUXSEL_VAL2   0x00000200U
 
#define ADC_TEST0_ATEST1_MUXSEL_VAL1   0x00000100U
 
#define ADC_TEST0_ATEST0_MUXSEL_W   5U
 
#define ADC_TEST0_ATEST0_MUXSEL_M   0x0000001FU
 
#define ADC_TEST0_ATEST0_MUXSEL_S   0U
 
#define ADC_TEST0_ATEST0_MUXSEL_VAL16   0x00000010U
 
#define ADC_TEST0_ATEST0_MUXSEL_VAL8   0x00000008U
 
#define ADC_TEST0_ATEST0_MUXSEL_VAL4   0x00000004U
 
#define ADC_TEST0_ATEST0_MUXSEL_VAL2   0x00000002U
 
#define ADC_TEST0_ATEST0_MUXSEL_VAL1   0x00000001U
 
#define ADC_TEST2_CDAC_OVST_EN   0x80000000U
 
#define ADC_TEST2_CDAC_OVST_EN_M   0x80000000U
 
#define ADC_TEST2_CDAC_OVST_EN_S   31U
 
#define ADC_TEST2_LATCH_TRIM_EN   0x01000000U
 
#define ADC_TEST2_LATCH_TRIM_EN_M   0x01000000U
 
#define ADC_TEST2_LATCH_TRIM_EN_S   24U
 
#define ADC_TEST2_COMP_GAIN_TRIM   0x00100000U
 
#define ADC_TEST2_COMP_GAIN_TRIM_M   0x00100000U
 
#define ADC_TEST2_COMP_GAIN_TRIM_S   20U
 
#define ADC_TEST2_MUX_TEST_SEL   0x00000100U
 
#define ADC_TEST2_MUX_TEST_SEL_M   0x00000100U
 
#define ADC_TEST2_MUX_TEST_SEL_S   8U
 
#define ADC_TEST3_CAL_ACUML_W   32U
 
#define ADC_TEST3_CAL_ACUML_M   0xFFFFFFFFU
 
#define ADC_TEST3_CAL_ACUML_S   0U
 
#define ADC_TEST4_HW_STEP_SEL_DIS   0x80000000U
 
#define ADC_TEST4_HW_STEP_SEL_DIS_M   0x80000000U
 
#define ADC_TEST4_HW_STEP_SEL_DIS_S   31U
 
#define ADC_TEST4_CAL_MODE_EN   0x01000000U
 
#define ADC_TEST4_CAL_MODE_EN_M   0x01000000U
 
#define ADC_TEST4_CAL_MODE_EN_S   24U
 
#define ADC_TEST4_CAL_STEP_SEL_W   6U
 
#define ADC_TEST4_CAL_STEP_SEL_M   0x003F0000U
 
#define ADC_TEST4_CAL_STEP_SEL_S   16U
 
#define ADC_TEST5_CAL_CAP_CTL_W   10U
 
#define ADC_TEST5_CAL_CAP_CTL_M   0x000003FFU
 
#define ADC_TEST5_CAL_CAP_CTL_S   0U
 
#define ADC_TEST6_ATESTSEL_W   4U
 
#define ADC_TEST6_ATESTSEL_M   0x0000000FU
 
#define ADC_TEST6_ATESTSEL_S   0U
 
#define ADC_TEST6_ATESTSEL_VAL8   0x00000008U
 
#define ADC_TEST6_ATESTSEL_VAL4   0x00000004U
 
#define ADC_TEST6_ATESTSEL_VAL2   0x00000002U
 
#define ADC_TEST6_ATESTSEL_VAL1   0x00000001U
 
#define ADC_TEST6_ATESTSEL_VAL0   0x00000000U
 
#define ADC_DEBUG1_CTRL_W   32U
 
#define ADC_DEBUG1_CTRL_M   0xFFFFFFFFU
 
#define ADC_DEBUG1_CTRL_S   0U
 
#define ADC_DEBUG2_VTOI_CTRL_W   2U
 
#define ADC_DEBUG2_VTOI_CTRL_M   0x30000000U
 
#define ADC_DEBUG2_VTOI_CTRL_S   28U
 
#define ADC_DEBUG2_VTOI_TESTMODE_EN   0x01000000U
 
#define ADC_DEBUG2_VTOI_TESTMODE_EN_M   0x01000000U
 
#define ADC_DEBUG2_VTOI_TESTMODE_EN_S   24U
 
#define ADC_DEBUG3_DEC1_DIS   0x00000020U
 
#define ADC_DEBUG3_DEC1_DIS_M   0x00000020U
 
#define ADC_DEBUG3_DEC1_DIS_S   5U
 
#define ADC_DEBUG3_DEC0_DIS   0x00000010U
 
#define ADC_DEBUG3_DEC0_DIS_M   0x00000010U
 
#define ADC_DEBUG3_DEC0_DIS_S   4U
 
#define ADC_DEBUG3_BOOST_ENZ   0x00000001U
 
#define ADC_DEBUG3_BOOST_ENZ_M   0x00000001U
 
#define ADC_DEBUG3_BOOST_ENZ_S   0U
 
#define ADC_DEBUG4_ADC_CTRL0_W   16U
 
#define ADC_DEBUG4_ADC_CTRL0_M   0x0000FFFFU
 
#define ADC_DEBUG4_ADC_CTRL0_S   0U
 

Macro Definition Documentation

§ ADC_O_IMASK0

#define ADC_O_IMASK0   0x00000028U

Referenced by ADCDisableInterrupt(), and ADCEnableInterrupt().

§ ADC_O_RIS0

#define ADC_O_RIS0   0x00000030U

Referenced by ADCRawInterruptStatus().

§ ADC_O_MIS0

#define ADC_O_MIS0   0x00000038U

Referenced by ADCMaskedInterruptStatus().

§ ADC_O_ISET0

#define ADC_O_ISET0   0x00000040U

§ ADC_O_ICLR0

#define ADC_O_ICLR0   0x00000048U

Referenced by ADCClearInterrupt().

§ ADC_O_IMASK1

#define ADC_O_IMASK1   0x00000058U

§ ADC_O_RIS1

#define ADC_O_RIS1   0x00000060U

§ ADC_O_MIS1

#define ADC_O_MIS1   0x00000068U

§ ADC_O_ISET1

#define ADC_O_ISET1   0x00000070U

§ ADC_O_ICLR1

#define ADC_O_ICLR1   0x00000078U

§ ADC_O_IMASK2

#define ADC_O_IMASK2   0x00000088U

§ ADC_O_RIS2

#define ADC_O_RIS2   0x00000090U

§ ADC_O_MIS2

#define ADC_O_MIS2   0x00000098U

§ ADC_O_ISET2

#define ADC_O_ISET2   0x000000A0U

§ ADC_O_ICLR2

#define ADC_O_ICLR2   0x000000A8U

§ ADC_O_CTL0

#define ADC_O_CTL0   0x00000100U

Referenced by ADCManualTrigger(), and ADCSetSampleDuration().

§ ADC_O_CTL1

#define ADC_O_CTL1   0x00000104U

Referenced by ADCManualTrigger(), and ADCSetSequence().

§ ADC_O_CTL2

#define ADC_O_CTL2   0x00000108U

Referenced by ADCSetMemctlRange(), and ADCSetResolution().

§ ADC_O_CTL3

#define ADC_O_CTL3   0x0000010CU

§ ADC_O_SCOMP0

#define ADC_O_SCOMP0   0x00000114U

Referenced by ADCSetSampleDuration().

§ ADC_O_SCOMP1

#define ADC_O_SCOMP1   0x00000118U

§ ADC_O_REFCFG

#define ADC_O_REFCFG   0x0000011CU

Referenced by ADCSetInput().

§ ADC_O_WCLOW

#define ADC_O_WCLOW   0x00000148U

§ ADC_O_WCHIGH

#define ADC_O_WCHIGH   0x00000150U

§ ADC_O_FIFODATA

#define ADC_O_FIFODATA   0x00000160U

§ ADC_O_ASCRES

#define ADC_O_ASCRES   0x00000170U

§ ADC_O_MEMCTL0

#define ADC_O_MEMCTL0   0x00000180U

Referenced by ADCSetInput().

§ ADC_O_MEMCTL1

#define ADC_O_MEMCTL1   0x00000184U

§ ADC_O_MEMCTL2

#define ADC_O_MEMCTL2   0x00000188U

§ ADC_O_MEMCTL3

#define ADC_O_MEMCTL3   0x0000018CU

§ ADC_O_MEMRES0

#define ADC_O_MEMRES0   0x00000280U

Referenced by ADCReadResult(), and ADCReadResultNonBlocking().

§ ADC_O_MEMRES1

#define ADC_O_MEMRES1   0x00000284U

§ ADC_O_MEMRES2

#define ADC_O_MEMRES2   0x00000288U

§ ADC_O_MEMRES3

#define ADC_O_MEMRES3   0x0000028CU

§ ADC_O_STA

#define ADC_O_STA   0x00000340U

Referenced by ADCIsBusy(), and ADCReadResult().

§ ADC_O_TEST0

#define ADC_O_TEST0   0x00000E00U

§ ADC_O_TEST2

#define ADC_O_TEST2   0x00000E08U

§ ADC_O_TEST3

#define ADC_O_TEST3   0x00000E0CU

§ ADC_O_TEST4

#define ADC_O_TEST4   0x00000E10U

§ ADC_O_TEST5

#define ADC_O_TEST5   0x00000E14U

§ ADC_O_TEST6

#define ADC_O_TEST6   0x00000E18U

§ ADC_O_DEBUG1

#define ADC_O_DEBUG1   0x00000E20U

§ ADC_O_DEBUG2

#define ADC_O_DEBUG2   0x00000E24U

§ ADC_O_DEBUG3

#define ADC_O_DEBUG3   0x00000E28U

§ ADC_O_DEBUG4

#define ADC_O_DEBUG4   0x00000E2CU

§ ADC_IMASK0_MEMRESIFG3

#define ADC_IMASK0_MEMRESIFG3   0x00000800U

§ ADC_IMASK0_MEMRESIFG3_M

#define ADC_IMASK0_MEMRESIFG3_M   0x00000800U

§ ADC_IMASK0_MEMRESIFG3_S

#define ADC_IMASK0_MEMRESIFG3_S   11U

§ ADC_IMASK0_MEMRESIFG3_EN

#define ADC_IMASK0_MEMRESIFG3_EN   0x00000800U

§ ADC_IMASK0_MEMRESIFG3_DIS

#define ADC_IMASK0_MEMRESIFG3_DIS   0x00000000U

§ ADC_IMASK0_MEMRESIFG2

#define ADC_IMASK0_MEMRESIFG2   0x00000400U

§ ADC_IMASK0_MEMRESIFG2_M

#define ADC_IMASK0_MEMRESIFG2_M   0x00000400U

§ ADC_IMASK0_MEMRESIFG2_S

#define ADC_IMASK0_MEMRESIFG2_S   10U

§ ADC_IMASK0_MEMRESIFG2_EN

#define ADC_IMASK0_MEMRESIFG2_EN   0x00000400U

§ ADC_IMASK0_MEMRESIFG2_DIS

#define ADC_IMASK0_MEMRESIFG2_DIS   0x00000000U

§ ADC_IMASK0_MEMRESIFG1

#define ADC_IMASK0_MEMRESIFG1   0x00000200U

§ ADC_IMASK0_MEMRESIFG1_M

#define ADC_IMASK0_MEMRESIFG1_M   0x00000200U

§ ADC_IMASK0_MEMRESIFG1_S

#define ADC_IMASK0_MEMRESIFG1_S   9U

§ ADC_IMASK0_MEMRESIFG1_EN

#define ADC_IMASK0_MEMRESIFG1_EN   0x00000200U

§ ADC_IMASK0_MEMRESIFG1_DIS

#define ADC_IMASK0_MEMRESIFG1_DIS   0x00000000U

§ ADC_IMASK0_MEMRESIFG0

#define ADC_IMASK0_MEMRESIFG0   0x00000100U

§ ADC_IMASK0_MEMRESIFG0_M

#define ADC_IMASK0_MEMRESIFG0_M   0x00000100U

§ ADC_IMASK0_MEMRESIFG0_S

#define ADC_IMASK0_MEMRESIFG0_S   8U

§ ADC_IMASK0_MEMRESIFG0_EN

#define ADC_IMASK0_MEMRESIFG0_EN   0x00000100U

§ ADC_IMASK0_MEMRESIFG0_DIS

#define ADC_IMASK0_MEMRESIFG0_DIS   0x00000000U

§ ADC_IMASK0_ASCDONE

#define ADC_IMASK0_ASCDONE   0x00000080U

§ ADC_IMASK0_ASCDONE_M

#define ADC_IMASK0_ASCDONE_M   0x00000080U

§ ADC_IMASK0_ASCDONE_S

#define ADC_IMASK0_ASCDONE_S   7U

§ ADC_IMASK0_ASCDONE_EN

#define ADC_IMASK0_ASCDONE_EN   0x00000080U

§ ADC_IMASK0_ASCDONE_DIS

#define ADC_IMASK0_ASCDONE_DIS   0x00000000U

§ ADC_IMASK0_UVIFG

#define ADC_IMASK0_UVIFG   0x00000040U

§ ADC_IMASK0_UVIFG_M

#define ADC_IMASK0_UVIFG_M   0x00000040U

§ ADC_IMASK0_UVIFG_S

#define ADC_IMASK0_UVIFG_S   6U

§ ADC_IMASK0_UVIFG_EN

#define ADC_IMASK0_UVIFG_EN   0x00000040U

§ ADC_IMASK0_UVIFG_DIS

#define ADC_IMASK0_UVIFG_DIS   0x00000000U

§ ADC_IMASK0_DMADONE

#define ADC_IMASK0_DMADONE   0x00000020U

§ ADC_IMASK0_DMADONE_M

#define ADC_IMASK0_DMADONE_M   0x00000020U

§ ADC_IMASK0_DMADONE_S

#define ADC_IMASK0_DMADONE_S   5U

§ ADC_IMASK0_DMADONE_EN

#define ADC_IMASK0_DMADONE_EN   0x00000020U

§ ADC_IMASK0_DMADONE_DIS

#define ADC_IMASK0_DMADONE_DIS   0x00000000U

§ ADC_IMASK0_INIFG

#define ADC_IMASK0_INIFG   0x00000010U

§ ADC_IMASK0_INIFG_M

#define ADC_IMASK0_INIFG_M   0x00000010U

§ ADC_IMASK0_INIFG_S

#define ADC_IMASK0_INIFG_S   4U

§ ADC_IMASK0_INIFG_EN

#define ADC_IMASK0_INIFG_EN   0x00000010U

§ ADC_IMASK0_INIFG_DIS

#define ADC_IMASK0_INIFG_DIS   0x00000000U

§ ADC_IMASK0_LOWIFG

#define ADC_IMASK0_LOWIFG   0x00000008U

§ ADC_IMASK0_LOWIFG_M

#define ADC_IMASK0_LOWIFG_M   0x00000008U

§ ADC_IMASK0_LOWIFG_S

#define ADC_IMASK0_LOWIFG_S   3U

§ ADC_IMASK0_LOWIFG_EN

#define ADC_IMASK0_LOWIFG_EN   0x00000008U

§ ADC_IMASK0_LOWIFG_DIS

#define ADC_IMASK0_LOWIFG_DIS   0x00000000U

§ ADC_IMASK0_HIGHIFG

#define ADC_IMASK0_HIGHIFG   0x00000004U

§ ADC_IMASK0_HIGHIFG_M

#define ADC_IMASK0_HIGHIFG_M   0x00000004U

§ ADC_IMASK0_HIGHIFG_S

#define ADC_IMASK0_HIGHIFG_S   2U

§ ADC_IMASK0_HIGHIFG_EN

#define ADC_IMASK0_HIGHIFG_EN   0x00000004U

§ ADC_IMASK0_HIGHIFG_DIS

#define ADC_IMASK0_HIGHIFG_DIS   0x00000000U

§ ADC_IMASK0_TOVIFG

#define ADC_IMASK0_TOVIFG   0x00000002U

§ ADC_IMASK0_TOVIFG_M

#define ADC_IMASK0_TOVIFG_M   0x00000002U

§ ADC_IMASK0_TOVIFG_S

#define ADC_IMASK0_TOVIFG_S   1U

§ ADC_IMASK0_TOVIFG_EN

#define ADC_IMASK0_TOVIFG_EN   0x00000002U

§ ADC_IMASK0_TOVIFG_DIS

#define ADC_IMASK0_TOVIFG_DIS   0x00000000U

§ ADC_IMASK0_OVIFG

#define ADC_IMASK0_OVIFG   0x00000001U

§ ADC_IMASK0_OVIFG_M

#define ADC_IMASK0_OVIFG_M   0x00000001U

§ ADC_IMASK0_OVIFG_S

#define ADC_IMASK0_OVIFG_S   0U

§ ADC_IMASK0_OVIFG_EN

#define ADC_IMASK0_OVIFG_EN   0x00000001U

§ ADC_IMASK0_OVIFG_DIS

#define ADC_IMASK0_OVIFG_DIS   0x00000000U

§ ADC_RIS0_MEMRESIFG3

#define ADC_RIS0_MEMRESIFG3   0x00000800U

§ ADC_RIS0_MEMRESIFG3_M

#define ADC_RIS0_MEMRESIFG3_M   0x00000800U

§ ADC_RIS0_MEMRESIFG3_S

#define ADC_RIS0_MEMRESIFG3_S   11U

§ ADC_RIS0_MEMRESIFG3_SET

#define ADC_RIS0_MEMRESIFG3_SET   0x00000800U

§ ADC_RIS0_MEMRESIFG3_CLR

#define ADC_RIS0_MEMRESIFG3_CLR   0x00000000U

§ ADC_RIS0_MEMRESIFG2

#define ADC_RIS0_MEMRESIFG2   0x00000400U

§ ADC_RIS0_MEMRESIFG2_M

#define ADC_RIS0_MEMRESIFG2_M   0x00000400U

§ ADC_RIS0_MEMRESIFG2_S

#define ADC_RIS0_MEMRESIFG2_S   10U

§ ADC_RIS0_MEMRESIFG2_SET

#define ADC_RIS0_MEMRESIFG2_SET   0x00000400U

§ ADC_RIS0_MEMRESIFG2_CLR

#define ADC_RIS0_MEMRESIFG2_CLR   0x00000000U

§ ADC_RIS0_MEMRESIFG1

#define ADC_RIS0_MEMRESIFG1   0x00000200U

§ ADC_RIS0_MEMRESIFG1_M

#define ADC_RIS0_MEMRESIFG1_M   0x00000200U

§ ADC_RIS0_MEMRESIFG1_S

#define ADC_RIS0_MEMRESIFG1_S   9U

§ ADC_RIS0_MEMRESIFG1_SET

#define ADC_RIS0_MEMRESIFG1_SET   0x00000200U

§ ADC_RIS0_MEMRESIFG1_CLR

#define ADC_RIS0_MEMRESIFG1_CLR   0x00000000U

§ ADC_RIS0_MEMRESIFG0

#define ADC_RIS0_MEMRESIFG0   0x00000100U

§ ADC_RIS0_MEMRESIFG0_M

#define ADC_RIS0_MEMRESIFG0_M   0x00000100U

§ ADC_RIS0_MEMRESIFG0_S

#define ADC_RIS0_MEMRESIFG0_S   8U

§ ADC_RIS0_MEMRESIFG0_SET

#define ADC_RIS0_MEMRESIFG0_SET   0x00000100U

§ ADC_RIS0_MEMRESIFG0_CLR

#define ADC_RIS0_MEMRESIFG0_CLR   0x00000000U

§ ADC_RIS0_ASCDONE

#define ADC_RIS0_ASCDONE   0x00000080U

§ ADC_RIS0_ASCDONE_M

#define ADC_RIS0_ASCDONE_M   0x00000080U

§ ADC_RIS0_ASCDONE_S

#define ADC_RIS0_ASCDONE_S   7U

§ ADC_RIS0_ASCDONE_SET

#define ADC_RIS0_ASCDONE_SET   0x00000080U

§ ADC_RIS0_ASCDONE_CLR

#define ADC_RIS0_ASCDONE_CLR   0x00000000U

§ ADC_RIS0_UVIFG

#define ADC_RIS0_UVIFG   0x00000040U

§ ADC_RIS0_UVIFG_M

#define ADC_RIS0_UVIFG_M   0x00000040U

§ ADC_RIS0_UVIFG_S

#define ADC_RIS0_UVIFG_S   6U

§ ADC_RIS0_UVIFG_SET

#define ADC_RIS0_UVIFG_SET   0x00000040U

§ ADC_RIS0_UVIFG_CLR

#define ADC_RIS0_UVIFG_CLR   0x00000000U

§ ADC_RIS0_DMADONE

#define ADC_RIS0_DMADONE   0x00000020U

§ ADC_RIS0_DMADONE_M

#define ADC_RIS0_DMADONE_M   0x00000020U

§ ADC_RIS0_DMADONE_S

#define ADC_RIS0_DMADONE_S   5U

§ ADC_RIS0_DMADONE_SET

#define ADC_RIS0_DMADONE_SET   0x00000020U

§ ADC_RIS0_DMADONE_CLR

#define ADC_RIS0_DMADONE_CLR   0x00000000U

§ ADC_RIS0_INIFG

#define ADC_RIS0_INIFG   0x00000010U

§ ADC_RIS0_INIFG_M

#define ADC_RIS0_INIFG_M   0x00000010U

§ ADC_RIS0_INIFG_S

#define ADC_RIS0_INIFG_S   4U

§ ADC_RIS0_INIFG_SET

#define ADC_RIS0_INIFG_SET   0x00000010U

§ ADC_RIS0_INIFG_CLR

#define ADC_RIS0_INIFG_CLR   0x00000000U

§ ADC_RIS0_LOWIFG

#define ADC_RIS0_LOWIFG   0x00000008U

§ ADC_RIS0_LOWIFG_M

#define ADC_RIS0_LOWIFG_M   0x00000008U

§ ADC_RIS0_LOWIFG_S

#define ADC_RIS0_LOWIFG_S   3U

§ ADC_RIS0_LOWIFG_SET

#define ADC_RIS0_LOWIFG_SET   0x00000008U

§ ADC_RIS0_LOWIFG_CLR

#define ADC_RIS0_LOWIFG_CLR   0x00000000U

§ ADC_RIS0_HIGHIFG

#define ADC_RIS0_HIGHIFG   0x00000004U

§ ADC_RIS0_HIGHIFG_M

#define ADC_RIS0_HIGHIFG_M   0x00000004U

§ ADC_RIS0_HIGHIFG_S

#define ADC_RIS0_HIGHIFG_S   2U

§ ADC_RIS0_HIGHIFG_SET

#define ADC_RIS0_HIGHIFG_SET   0x00000004U

§ ADC_RIS0_HIGHIFG_CLR

#define ADC_RIS0_HIGHIFG_CLR   0x00000000U

§ ADC_RIS0_TOVIFG

#define ADC_RIS0_TOVIFG   0x00000002U

§ ADC_RIS0_TOVIFG_M

#define ADC_RIS0_TOVIFG_M   0x00000002U

§ ADC_RIS0_TOVIFG_S

#define ADC_RIS0_TOVIFG_S   1U

§ ADC_RIS0_TOVIFG_SET

#define ADC_RIS0_TOVIFG_SET   0x00000002U

§ ADC_RIS0_TOVIFG_CLR

#define ADC_RIS0_TOVIFG_CLR   0x00000000U

§ ADC_RIS0_OVIFG

#define ADC_RIS0_OVIFG   0x00000001U

§ ADC_RIS0_OVIFG_M

#define ADC_RIS0_OVIFG_M   0x00000001U

§ ADC_RIS0_OVIFG_S

#define ADC_RIS0_OVIFG_S   0U

§ ADC_RIS0_OVIFG_SET

#define ADC_RIS0_OVIFG_SET   0x00000001U

§ ADC_RIS0_OVIFG_CLR

#define ADC_RIS0_OVIFG_CLR   0x00000000U

§ ADC_MIS0_MEMRESIFG3

#define ADC_MIS0_MEMRESIFG3   0x00000800U

§ ADC_MIS0_MEMRESIFG3_M

#define ADC_MIS0_MEMRESIFG3_M   0x00000800U

§ ADC_MIS0_MEMRESIFG3_S

#define ADC_MIS0_MEMRESIFG3_S   11U

§ ADC_MIS0_MEMRESIFG3_SET

#define ADC_MIS0_MEMRESIFG3_SET   0x00000800U

§ ADC_MIS0_MEMRESIFG3_CLR

#define ADC_MIS0_MEMRESIFG3_CLR   0x00000000U

§ ADC_MIS0_MEMRESIFG2

#define ADC_MIS0_MEMRESIFG2   0x00000400U

§ ADC_MIS0_MEMRESIFG2_M

#define ADC_MIS0_MEMRESIFG2_M   0x00000400U

§ ADC_MIS0_MEMRESIFG2_S

#define ADC_MIS0_MEMRESIFG2_S   10U

§ ADC_MIS0_MEMRESIFG2_SET

#define ADC_MIS0_MEMRESIFG2_SET   0x00000400U

§ ADC_MIS0_MEMRESIFG2_CLR

#define ADC_MIS0_MEMRESIFG2_CLR   0x00000000U

§ ADC_MIS0_MEMRESIFG1

#define ADC_MIS0_MEMRESIFG1   0x00000200U

§ ADC_MIS0_MEMRESIFG1_M

#define ADC_MIS0_MEMRESIFG1_M   0x00000200U

§ ADC_MIS0_MEMRESIFG1_S

#define ADC_MIS0_MEMRESIFG1_S   9U

§ ADC_MIS0_MEMRESIFG1_SET

#define ADC_MIS0_MEMRESIFG1_SET   0x00000200U

§ ADC_MIS0_MEMRESIFG1_CLR

#define ADC_MIS0_MEMRESIFG1_CLR   0x00000000U

§ ADC_MIS0_MEMRESIFG0

#define ADC_MIS0_MEMRESIFG0   0x00000100U

§ ADC_MIS0_MEMRESIFG0_M

#define ADC_MIS0_MEMRESIFG0_M   0x00000100U

§ ADC_MIS0_MEMRESIFG0_S

#define ADC_MIS0_MEMRESIFG0_S   8U

§ ADC_MIS0_MEMRESIFG0_SET

#define ADC_MIS0_MEMRESIFG0_SET   0x00000100U

§ ADC_MIS0_MEMRESIFG0_CLR

#define ADC_MIS0_MEMRESIFG0_CLR   0x00000000U

§ ADC_MIS0_ASCDONE

#define ADC_MIS0_ASCDONE   0x00000080U

§ ADC_MIS0_ASCDONE_M

#define ADC_MIS0_ASCDONE_M   0x00000080U

§ ADC_MIS0_ASCDONE_S

#define ADC_MIS0_ASCDONE_S   7U

§ ADC_MIS0_ASCDONE_SET

#define ADC_MIS0_ASCDONE_SET   0x00000080U

§ ADC_MIS0_ASCDONE_CLR

#define ADC_MIS0_ASCDONE_CLR   0x00000000U

§ ADC_MIS0_UVIFG

#define ADC_MIS0_UVIFG   0x00000040U

§ ADC_MIS0_UVIFG_M

#define ADC_MIS0_UVIFG_M   0x00000040U

§ ADC_MIS0_UVIFG_S

#define ADC_MIS0_UVIFG_S   6U

§ ADC_MIS0_UVIFG_SET

#define ADC_MIS0_UVIFG_SET   0x00000040U

§ ADC_MIS0_UVIFG_CLR

#define ADC_MIS0_UVIFG_CLR   0x00000000U

§ ADC_MIS0_DMADONE

#define ADC_MIS0_DMADONE   0x00000020U

§ ADC_MIS0_DMADONE_M

#define ADC_MIS0_DMADONE_M   0x00000020U

§ ADC_MIS0_DMADONE_S

#define ADC_MIS0_DMADONE_S   5U

§ ADC_MIS0_DMADONE_SET

#define ADC_MIS0_DMADONE_SET   0x00000020U

§ ADC_MIS0_DMADONE_CLR

#define ADC_MIS0_DMADONE_CLR   0x00000000U

§ ADC_MIS0_INIFG

#define ADC_MIS0_INIFG   0x00000010U

§ ADC_MIS0_INIFG_M

#define ADC_MIS0_INIFG_M   0x00000010U

§ ADC_MIS0_INIFG_S

#define ADC_MIS0_INIFG_S   4U

§ ADC_MIS0_INIFG_SET

#define ADC_MIS0_INIFG_SET   0x00000010U

§ ADC_MIS0_INIFG_CLR

#define ADC_MIS0_INIFG_CLR   0x00000000U

§ ADC_MIS0_LOWIFG

#define ADC_MIS0_LOWIFG   0x00000008U

§ ADC_MIS0_LOWIFG_M

#define ADC_MIS0_LOWIFG_M   0x00000008U

§ ADC_MIS0_LOWIFG_S

#define ADC_MIS0_LOWIFG_S   3U

§ ADC_MIS0_LOWIFG_SET

#define ADC_MIS0_LOWIFG_SET   0x00000008U

§ ADC_MIS0_LOWIFG_CLR

#define ADC_MIS0_LOWIFG_CLR   0x00000000U

§ ADC_MIS0_HIGHIFG

#define ADC_MIS0_HIGHIFG   0x00000004U

§ ADC_MIS0_HIGHIFG_M

#define ADC_MIS0_HIGHIFG_M   0x00000004U

§ ADC_MIS0_HIGHIFG_S

#define ADC_MIS0_HIGHIFG_S   2U

§ ADC_MIS0_HIGHIFG_SET

#define ADC_MIS0_HIGHIFG_SET   0x00000004U

§ ADC_MIS0_HIGHIFG_CLR

#define ADC_MIS0_HIGHIFG_CLR   0x00000000U

§ ADC_MIS0_TOVIFG

#define ADC_MIS0_TOVIFG   0x00000002U

§ ADC_MIS0_TOVIFG_M

#define ADC_MIS0_TOVIFG_M   0x00000002U

§ ADC_MIS0_TOVIFG_S

#define ADC_MIS0_TOVIFG_S   1U

§ ADC_MIS0_TOVIFG_SET

#define ADC_MIS0_TOVIFG_SET   0x00000002U

§ ADC_MIS0_TOVIFG_CLR

#define ADC_MIS0_TOVIFG_CLR   0x00000000U

§ ADC_MIS0_OVIFG

#define ADC_MIS0_OVIFG   0x00000001U

§ ADC_MIS0_OVIFG_M

#define ADC_MIS0_OVIFG_M   0x00000001U

§ ADC_MIS0_OVIFG_S

#define ADC_MIS0_OVIFG_S   0U

§ ADC_MIS0_OVIFG_SET

#define ADC_MIS0_OVIFG_SET   0x00000001U

§ ADC_MIS0_OVIFG_CLR

#define ADC_MIS0_OVIFG_CLR   0x00000000U

§ ADC_ISET0_MEMRESIFG3

#define ADC_ISET0_MEMRESIFG3   0x00000800U

§ ADC_ISET0_MEMRESIFG3_M

#define ADC_ISET0_MEMRESIFG3_M   0x00000800U

§ ADC_ISET0_MEMRESIFG3_S

#define ADC_ISET0_MEMRESIFG3_S   11U

§ ADC_ISET0_MEMRESIFG3_SET

#define ADC_ISET0_MEMRESIFG3_SET   0x00000800U

§ ADC_ISET0_MEMRESIFG3_NO_EFFECT

#define ADC_ISET0_MEMRESIFG3_NO_EFFECT   0x00000000U

§ ADC_ISET0_MEMRESIFG2

#define ADC_ISET0_MEMRESIFG2   0x00000400U

§ ADC_ISET0_MEMRESIFG2_M

#define ADC_ISET0_MEMRESIFG2_M   0x00000400U

§ ADC_ISET0_MEMRESIFG2_S

#define ADC_ISET0_MEMRESIFG2_S   10U

§ ADC_ISET0_MEMRESIFG2_SET

#define ADC_ISET0_MEMRESIFG2_SET   0x00000400U

§ ADC_ISET0_MEMRESIFG2_NO_EFFECT

#define ADC_ISET0_MEMRESIFG2_NO_EFFECT   0x00000000U

§ ADC_ISET0_MEMRESIFG1

#define ADC_ISET0_MEMRESIFG1   0x00000200U

§ ADC_ISET0_MEMRESIFG1_M

#define ADC_ISET0_MEMRESIFG1_M   0x00000200U

§ ADC_ISET0_MEMRESIFG1_S

#define ADC_ISET0_MEMRESIFG1_S   9U

§ ADC_ISET0_MEMRESIFG1_SET

#define ADC_ISET0_MEMRESIFG1_SET   0x00000200U

§ ADC_ISET0_MEMRESIFG1_NO_EFFECT

#define ADC_ISET0_MEMRESIFG1_NO_EFFECT   0x00000000U

§ ADC_ISET0_MEMRESIFG0

#define ADC_ISET0_MEMRESIFG0   0x00000100U

§ ADC_ISET0_MEMRESIFG0_M

#define ADC_ISET0_MEMRESIFG0_M   0x00000100U

§ ADC_ISET0_MEMRESIFG0_S

#define ADC_ISET0_MEMRESIFG0_S   8U

§ ADC_ISET0_MEMRESIFG0_SET

#define ADC_ISET0_MEMRESIFG0_SET   0x00000100U

§ ADC_ISET0_MEMRESIFG0_NO_EFFECT

#define ADC_ISET0_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_ISET0_ASCDONE

#define ADC_ISET0_ASCDONE   0x00000080U

§ ADC_ISET0_ASCDONE_M

#define ADC_ISET0_ASCDONE_M   0x00000080U

§ ADC_ISET0_ASCDONE_S

#define ADC_ISET0_ASCDONE_S   7U

§ ADC_ISET0_ASCDONE_SET

#define ADC_ISET0_ASCDONE_SET   0x00000080U

§ ADC_ISET0_ASCDONE_NO_EFFECT

#define ADC_ISET0_ASCDONE_NO_EFFECT   0x00000000U

§ ADC_ISET0_UVIFG

#define ADC_ISET0_UVIFG   0x00000040U

§ ADC_ISET0_UVIFG_M

#define ADC_ISET0_UVIFG_M   0x00000040U

§ ADC_ISET0_UVIFG_S

#define ADC_ISET0_UVIFG_S   6U

§ ADC_ISET0_UVIFG_SET

#define ADC_ISET0_UVIFG_SET   0x00000040U

§ ADC_ISET0_UVIFG_NO_EFFECT

#define ADC_ISET0_UVIFG_NO_EFFECT   0x00000000U

§ ADC_ISET0_DMADONE

#define ADC_ISET0_DMADONE   0x00000020U

§ ADC_ISET0_DMADONE_M

#define ADC_ISET0_DMADONE_M   0x00000020U

§ ADC_ISET0_DMADONE_S

#define ADC_ISET0_DMADONE_S   5U

§ ADC_ISET0_DMADONE_SET

#define ADC_ISET0_DMADONE_SET   0x00000020U

§ ADC_ISET0_DMADONE_NO_EFFECT

#define ADC_ISET0_DMADONE_NO_EFFECT   0x00000000U

§ ADC_ISET0_INIFG

#define ADC_ISET0_INIFG   0x00000010U

§ ADC_ISET0_INIFG_M

#define ADC_ISET0_INIFG_M   0x00000010U

§ ADC_ISET0_INIFG_S

#define ADC_ISET0_INIFG_S   4U

§ ADC_ISET0_INIFG_SET

#define ADC_ISET0_INIFG_SET   0x00000010U

§ ADC_ISET0_INIFG_NO_EFFECT

#define ADC_ISET0_INIFG_NO_EFFECT   0x00000000U

§ ADC_ISET0_LOWIFG

#define ADC_ISET0_LOWIFG   0x00000008U

§ ADC_ISET0_LOWIFG_M

#define ADC_ISET0_LOWIFG_M   0x00000008U

§ ADC_ISET0_LOWIFG_S

#define ADC_ISET0_LOWIFG_S   3U

§ ADC_ISET0_LOWIFG_SET

#define ADC_ISET0_LOWIFG_SET   0x00000008U

§ ADC_ISET0_LOWIFG_NO_EFFECT

#define ADC_ISET0_LOWIFG_NO_EFFECT   0x00000000U

§ ADC_ISET0_HIGHIFG

#define ADC_ISET0_HIGHIFG   0x00000004U

§ ADC_ISET0_HIGHIFG_M

#define ADC_ISET0_HIGHIFG_M   0x00000004U

§ ADC_ISET0_HIGHIFG_S

#define ADC_ISET0_HIGHIFG_S   2U

§ ADC_ISET0_HIGHIFG_SET

#define ADC_ISET0_HIGHIFG_SET   0x00000004U

§ ADC_ISET0_HIGHIFG_NO_EFFECT

#define ADC_ISET0_HIGHIFG_NO_EFFECT   0x00000000U

§ ADC_ISET0_TOVIFG

#define ADC_ISET0_TOVIFG   0x00000002U

§ ADC_ISET0_TOVIFG_M

#define ADC_ISET0_TOVIFG_M   0x00000002U

§ ADC_ISET0_TOVIFG_S

#define ADC_ISET0_TOVIFG_S   1U

§ ADC_ISET0_TOVIFG_SET

#define ADC_ISET0_TOVIFG_SET   0x00000002U

§ ADC_ISET0_TOVIFG_NO_EFFECT

#define ADC_ISET0_TOVIFG_NO_EFFECT   0x00000000U

§ ADC_ISET0_OVIFG

#define ADC_ISET0_OVIFG   0x00000001U

§ ADC_ISET0_OVIFG_M

#define ADC_ISET0_OVIFG_M   0x00000001U

§ ADC_ISET0_OVIFG_S

#define ADC_ISET0_OVIFG_S   0U

§ ADC_ISET0_OVIFG_SET

#define ADC_ISET0_OVIFG_SET   0x00000001U

§ ADC_ISET0_OVIFG_NO_EFFECT

#define ADC_ISET0_OVIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_MEMRESIFG3

#define ADC_ICLR0_MEMRESIFG3   0x00000800U

§ ADC_ICLR0_MEMRESIFG3_M

#define ADC_ICLR0_MEMRESIFG3_M   0x00000800U

§ ADC_ICLR0_MEMRESIFG3_S

#define ADC_ICLR0_MEMRESIFG3_S   11U

§ ADC_ICLR0_MEMRESIFG3_CLR

#define ADC_ICLR0_MEMRESIFG3_CLR   0x00000800U

§ ADC_ICLR0_MEMRESIFG3_NO_EFFECT

#define ADC_ICLR0_MEMRESIFG3_NO_EFFECT   0x00000000U

§ ADC_ICLR0_MEMRESIFG2

#define ADC_ICLR0_MEMRESIFG2   0x00000400U

§ ADC_ICLR0_MEMRESIFG2_M

#define ADC_ICLR0_MEMRESIFG2_M   0x00000400U

§ ADC_ICLR0_MEMRESIFG2_S

#define ADC_ICLR0_MEMRESIFG2_S   10U

§ ADC_ICLR0_MEMRESIFG2_CLR

#define ADC_ICLR0_MEMRESIFG2_CLR   0x00000400U

§ ADC_ICLR0_MEMRESIFG2_NO_EFFECT

#define ADC_ICLR0_MEMRESIFG2_NO_EFFECT   0x00000000U

§ ADC_ICLR0_MEMRESIFG1

#define ADC_ICLR0_MEMRESIFG1   0x00000200U

§ ADC_ICLR0_MEMRESIFG1_M

#define ADC_ICLR0_MEMRESIFG1_M   0x00000200U

§ ADC_ICLR0_MEMRESIFG1_S

#define ADC_ICLR0_MEMRESIFG1_S   9U

§ ADC_ICLR0_MEMRESIFG1_CLR

#define ADC_ICLR0_MEMRESIFG1_CLR   0x00000200U

§ ADC_ICLR0_MEMRESIFG1_NO_EFFECT

#define ADC_ICLR0_MEMRESIFG1_NO_EFFECT   0x00000000U

§ ADC_ICLR0_MEMRESIFG0

#define ADC_ICLR0_MEMRESIFG0   0x00000100U

§ ADC_ICLR0_MEMRESIFG0_M

#define ADC_ICLR0_MEMRESIFG0_M   0x00000100U

§ ADC_ICLR0_MEMRESIFG0_S

#define ADC_ICLR0_MEMRESIFG0_S   8U

§ ADC_ICLR0_MEMRESIFG0_CLR

#define ADC_ICLR0_MEMRESIFG0_CLR   0x00000100U

§ ADC_ICLR0_MEMRESIFG0_NO_EFFECT

#define ADC_ICLR0_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_ICLR0_ASCDONE

#define ADC_ICLR0_ASCDONE   0x00000080U

§ ADC_ICLR0_ASCDONE_M

#define ADC_ICLR0_ASCDONE_M   0x00000080U

§ ADC_ICLR0_ASCDONE_S

#define ADC_ICLR0_ASCDONE_S   7U

§ ADC_ICLR0_ASCDONE_CLR

#define ADC_ICLR0_ASCDONE_CLR   0x00000080U

§ ADC_ICLR0_ASCDONE_NO_EFFECT

#define ADC_ICLR0_ASCDONE_NO_EFFECT   0x00000000U

§ ADC_ICLR0_UVIFG

#define ADC_ICLR0_UVIFG   0x00000040U

§ ADC_ICLR0_UVIFG_M

#define ADC_ICLR0_UVIFG_M   0x00000040U

§ ADC_ICLR0_UVIFG_S

#define ADC_ICLR0_UVIFG_S   6U

§ ADC_ICLR0_UVIFG_CLR

#define ADC_ICLR0_UVIFG_CLR   0x00000040U

§ ADC_ICLR0_UVIFG_NO_EFFECT

#define ADC_ICLR0_UVIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_DMADONE

#define ADC_ICLR0_DMADONE   0x00000020U

§ ADC_ICLR0_DMADONE_M

#define ADC_ICLR0_DMADONE_M   0x00000020U

§ ADC_ICLR0_DMADONE_S

#define ADC_ICLR0_DMADONE_S   5U

§ ADC_ICLR0_DMADONE_CLR

#define ADC_ICLR0_DMADONE_CLR   0x00000020U

§ ADC_ICLR0_DMADONE_NO_EFFECT

#define ADC_ICLR0_DMADONE_NO_EFFECT   0x00000000U

§ ADC_ICLR0_INIFG

#define ADC_ICLR0_INIFG   0x00000010U

§ ADC_ICLR0_INIFG_M

#define ADC_ICLR0_INIFG_M   0x00000010U

§ ADC_ICLR0_INIFG_S

#define ADC_ICLR0_INIFG_S   4U

§ ADC_ICLR0_INIFG_CLR

#define ADC_ICLR0_INIFG_CLR   0x00000010U

§ ADC_ICLR0_INIFG_NO_EFFECT

#define ADC_ICLR0_INIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_LOWIFG

#define ADC_ICLR0_LOWIFG   0x00000008U

§ ADC_ICLR0_LOWIFG_M

#define ADC_ICLR0_LOWIFG_M   0x00000008U

§ ADC_ICLR0_LOWIFG_S

#define ADC_ICLR0_LOWIFG_S   3U

§ ADC_ICLR0_LOWIFG_CLR

#define ADC_ICLR0_LOWIFG_CLR   0x00000008U

§ ADC_ICLR0_LOWIFG_NO_EFFECT

#define ADC_ICLR0_LOWIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_HIGHIFG

#define ADC_ICLR0_HIGHIFG   0x00000004U

§ ADC_ICLR0_HIGHIFG_M

#define ADC_ICLR0_HIGHIFG_M   0x00000004U

§ ADC_ICLR0_HIGHIFG_S

#define ADC_ICLR0_HIGHIFG_S   2U

§ ADC_ICLR0_HIGHIFG_CLR

#define ADC_ICLR0_HIGHIFG_CLR   0x00000004U

§ ADC_ICLR0_HIGHIFG_NO_EFFECT

#define ADC_ICLR0_HIGHIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_TOVIFG

#define ADC_ICLR0_TOVIFG   0x00000002U

§ ADC_ICLR0_TOVIFG_M

#define ADC_ICLR0_TOVIFG_M   0x00000002U

§ ADC_ICLR0_TOVIFG_S

#define ADC_ICLR0_TOVIFG_S   1U

§ ADC_ICLR0_TOVIFG_CLR

#define ADC_ICLR0_TOVIFG_CLR   0x00000002U

§ ADC_ICLR0_TOVIFG_NO_EFFECT

#define ADC_ICLR0_TOVIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR0_OVIFG

#define ADC_ICLR0_OVIFG   0x00000001U

§ ADC_ICLR0_OVIFG_M

#define ADC_ICLR0_OVIFG_M   0x00000001U

§ ADC_ICLR0_OVIFG_S

#define ADC_ICLR0_OVIFG_S   0U

§ ADC_ICLR0_OVIFG_CLR

#define ADC_ICLR0_OVIFG_CLR   0x00000001U

§ ADC_ICLR0_OVIFG_NO_EFFECT

#define ADC_ICLR0_OVIFG_NO_EFFECT   0x00000000U

§ ADC_IMASK1_MEMRESIFG0

#define ADC_IMASK1_MEMRESIFG0   0x00000100U

§ ADC_IMASK1_MEMRESIFG0_M

#define ADC_IMASK1_MEMRESIFG0_M   0x00000100U

§ ADC_IMASK1_MEMRESIFG0_S

#define ADC_IMASK1_MEMRESIFG0_S   8U

§ ADC_IMASK1_MEMRESIFG0_SET

#define ADC_IMASK1_MEMRESIFG0_SET   0x00000100U

§ ADC_IMASK1_MEMRESIFG0_CLR

#define ADC_IMASK1_MEMRESIFG0_CLR   0x00000000U

§ ADC_IMASK1_INIFG

#define ADC_IMASK1_INIFG   0x00000010U

§ ADC_IMASK1_INIFG_M

#define ADC_IMASK1_INIFG_M   0x00000010U

§ ADC_IMASK1_INIFG_S

#define ADC_IMASK1_INIFG_S   4U

§ ADC_IMASK1_INIFG_SET

#define ADC_IMASK1_INIFG_SET   0x00000010U

§ ADC_IMASK1_INIFG_CLR

#define ADC_IMASK1_INIFG_CLR   0x00000000U

§ ADC_IMASK1_LOWIFG

#define ADC_IMASK1_LOWIFG   0x00000008U

§ ADC_IMASK1_LOWIFG_M

#define ADC_IMASK1_LOWIFG_M   0x00000008U

§ ADC_IMASK1_LOWIFG_S

#define ADC_IMASK1_LOWIFG_S   3U

§ ADC_IMASK1_LOWIFG_SET

#define ADC_IMASK1_LOWIFG_SET   0x00000008U

§ ADC_IMASK1_LOWIFG_CLR

#define ADC_IMASK1_LOWIFG_CLR   0x00000000U

§ ADC_IMASK1_HIGHIFG

#define ADC_IMASK1_HIGHIFG   0x00000004U

§ ADC_IMASK1_HIGHIFG_M

#define ADC_IMASK1_HIGHIFG_M   0x00000004U

§ ADC_IMASK1_HIGHIFG_S

#define ADC_IMASK1_HIGHIFG_S   2U

§ ADC_IMASK1_HIGHIFG_SET

#define ADC_IMASK1_HIGHIFG_SET   0x00000004U

§ ADC_IMASK1_HIGHIFG_CLR

#define ADC_IMASK1_HIGHIFG_CLR   0x00000000U

§ ADC_RIS1_MEMRESIFG0

#define ADC_RIS1_MEMRESIFG0   0x00000100U

§ ADC_RIS1_MEMRESIFG0_M

#define ADC_RIS1_MEMRESIFG0_M   0x00000100U

§ ADC_RIS1_MEMRESIFG0_S

#define ADC_RIS1_MEMRESIFG0_S   8U

§ ADC_RIS1_MEMRESIFG0_SET

#define ADC_RIS1_MEMRESIFG0_SET   0x00000100U

§ ADC_RIS1_MEMRESIFG0_CLR

#define ADC_RIS1_MEMRESIFG0_CLR   0x00000000U

§ ADC_RIS1_INIFG

#define ADC_RIS1_INIFG   0x00000010U

§ ADC_RIS1_INIFG_M

#define ADC_RIS1_INIFG_M   0x00000010U

§ ADC_RIS1_INIFG_S

#define ADC_RIS1_INIFG_S   4U

§ ADC_RIS1_INIFG_SET

#define ADC_RIS1_INIFG_SET   0x00000010U

§ ADC_RIS1_INIFG_CLR

#define ADC_RIS1_INIFG_CLR   0x00000000U

§ ADC_RIS1_LOWIFG

#define ADC_RIS1_LOWIFG   0x00000008U

§ ADC_RIS1_LOWIFG_M

#define ADC_RIS1_LOWIFG_M   0x00000008U

§ ADC_RIS1_LOWIFG_S

#define ADC_RIS1_LOWIFG_S   3U

§ ADC_RIS1_LOWIFG_SET

#define ADC_RIS1_LOWIFG_SET   0x00000008U

§ ADC_RIS1_LOWIFG_CLR

#define ADC_RIS1_LOWIFG_CLR   0x00000000U

§ ADC_RIS1_HIGHIFG

#define ADC_RIS1_HIGHIFG   0x00000004U

§ ADC_RIS1_HIGHIFG_M

#define ADC_RIS1_HIGHIFG_M   0x00000004U

§ ADC_RIS1_HIGHIFG_S

#define ADC_RIS1_HIGHIFG_S   2U

§ ADC_RIS1_HIGHIFG_SET

#define ADC_RIS1_HIGHIFG_SET   0x00000004U

§ ADC_RIS1_HIGHIFG_CLR

#define ADC_RIS1_HIGHIFG_CLR   0x00000000U

§ ADC_MIS1_MEMRESIFG0

#define ADC_MIS1_MEMRESIFG0   0x00000100U

§ ADC_MIS1_MEMRESIFG0_M

#define ADC_MIS1_MEMRESIFG0_M   0x00000100U

§ ADC_MIS1_MEMRESIFG0_S

#define ADC_MIS1_MEMRESIFG0_S   8U

§ ADC_MIS1_MEMRESIFG0_SET

#define ADC_MIS1_MEMRESIFG0_SET   0x00000100U

§ ADC_MIS1_MEMRESIFG0_CLR

#define ADC_MIS1_MEMRESIFG0_CLR   0x00000000U

§ ADC_MIS1_INIFG

#define ADC_MIS1_INIFG   0x00000010U

§ ADC_MIS1_INIFG_M

#define ADC_MIS1_INIFG_M   0x00000010U

§ ADC_MIS1_INIFG_S

#define ADC_MIS1_INIFG_S   4U

§ ADC_MIS1_INIFG_SET

#define ADC_MIS1_INIFG_SET   0x00000010U

§ ADC_MIS1_INIFG_CLR

#define ADC_MIS1_INIFG_CLR   0x00000000U

§ ADC_MIS1_LOWIFG

#define ADC_MIS1_LOWIFG   0x00000008U

§ ADC_MIS1_LOWIFG_M

#define ADC_MIS1_LOWIFG_M   0x00000008U

§ ADC_MIS1_LOWIFG_S

#define ADC_MIS1_LOWIFG_S   3U

§ ADC_MIS1_LOWIFG_SET

#define ADC_MIS1_LOWIFG_SET   0x00000008U

§ ADC_MIS1_LOWIFG_CLR

#define ADC_MIS1_LOWIFG_CLR   0x00000000U

§ ADC_MIS1_HIGHIFG

#define ADC_MIS1_HIGHIFG   0x00000004U

§ ADC_MIS1_HIGHIFG_M

#define ADC_MIS1_HIGHIFG_M   0x00000004U

§ ADC_MIS1_HIGHIFG_S

#define ADC_MIS1_HIGHIFG_S   2U

§ ADC_MIS1_HIGHIFG_SET

#define ADC_MIS1_HIGHIFG_SET   0x00000004U

§ ADC_MIS1_HIGHIFG_CLR

#define ADC_MIS1_HIGHIFG_CLR   0x00000000U

§ ADC_ISET1_MEMRESIFG0

#define ADC_ISET1_MEMRESIFG0   0x00000100U

§ ADC_ISET1_MEMRESIFG0_M

#define ADC_ISET1_MEMRESIFG0_M   0x00000100U

§ ADC_ISET1_MEMRESIFG0_S

#define ADC_ISET1_MEMRESIFG0_S   8U

§ ADC_ISET1_MEMRESIFG0_SET

#define ADC_ISET1_MEMRESIFG0_SET   0x00000100U

§ ADC_ISET1_MEMRESIFG0_NO_EFFECT

#define ADC_ISET1_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_ISET1_INIFG

#define ADC_ISET1_INIFG   0x00000010U

§ ADC_ISET1_INIFG_M

#define ADC_ISET1_INIFG_M   0x00000010U

§ ADC_ISET1_INIFG_S

#define ADC_ISET1_INIFG_S   4U

§ ADC_ISET1_INIFG_SET

#define ADC_ISET1_INIFG_SET   0x00000010U

§ ADC_ISET1_INIFG_NO_EFFECT

#define ADC_ISET1_INIFG_NO_EFFECT   0x00000000U

§ ADC_ISET1_LOWIFG

#define ADC_ISET1_LOWIFG   0x00000008U

§ ADC_ISET1_LOWIFG_M

#define ADC_ISET1_LOWIFG_M   0x00000008U

§ ADC_ISET1_LOWIFG_S

#define ADC_ISET1_LOWIFG_S   3U

§ ADC_ISET1_LOWIFG_SET

#define ADC_ISET1_LOWIFG_SET   0x00000008U

§ ADC_ISET1_LOWIFG_NO_EFFECT

#define ADC_ISET1_LOWIFG_NO_EFFECT   0x00000000U

§ ADC_ISET1_HIGHIFG

#define ADC_ISET1_HIGHIFG   0x00000004U

§ ADC_ISET1_HIGHIFG_M

#define ADC_ISET1_HIGHIFG_M   0x00000004U

§ ADC_ISET1_HIGHIFG_S

#define ADC_ISET1_HIGHIFG_S   2U

§ ADC_ISET1_HIGHIFG_SET

#define ADC_ISET1_HIGHIFG_SET   0x00000004U

§ ADC_ISET1_HIGHIFG_NO_EFFECT

#define ADC_ISET1_HIGHIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR1_MEMRESIFG0

#define ADC_ICLR1_MEMRESIFG0   0x00000100U

§ ADC_ICLR1_MEMRESIFG0_M

#define ADC_ICLR1_MEMRESIFG0_M   0x00000100U

§ ADC_ICLR1_MEMRESIFG0_S

#define ADC_ICLR1_MEMRESIFG0_S   8U

§ ADC_ICLR1_MEMRESIFG0_CLR

#define ADC_ICLR1_MEMRESIFG0_CLR   0x00000100U

§ ADC_ICLR1_MEMRESIFG0_NO_EFFECT

#define ADC_ICLR1_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_ICLR1_INIFG

#define ADC_ICLR1_INIFG   0x00000010U

§ ADC_ICLR1_INIFG_M

#define ADC_ICLR1_INIFG_M   0x00000010U

§ ADC_ICLR1_INIFG_S

#define ADC_ICLR1_INIFG_S   4U

§ ADC_ICLR1_INIFG_CLR

#define ADC_ICLR1_INIFG_CLR   0x00000010U

§ ADC_ICLR1_INIFG_NO_EFFECT

#define ADC_ICLR1_INIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR1_LOWIFG

#define ADC_ICLR1_LOWIFG   0x00000008U

§ ADC_ICLR1_LOWIFG_M

#define ADC_ICLR1_LOWIFG_M   0x00000008U

§ ADC_ICLR1_LOWIFG_S

#define ADC_ICLR1_LOWIFG_S   3U

§ ADC_ICLR1_LOWIFG_CLR

#define ADC_ICLR1_LOWIFG_CLR   0x00000008U

§ ADC_ICLR1_LOWIFG_NO_EFFECT

#define ADC_ICLR1_LOWIFG_NO_EFFECT   0x00000000U

§ ADC_ICLR1_HIGHIFG

#define ADC_ICLR1_HIGHIFG   0x00000004U

§ ADC_ICLR1_HIGHIFG_M

#define ADC_ICLR1_HIGHIFG_M   0x00000004U

§ ADC_ICLR1_HIGHIFG_S

#define ADC_ICLR1_HIGHIFG_S   2U

§ ADC_ICLR1_HIGHIFG_CLR

#define ADC_ICLR1_HIGHIFG_CLR   0x00000004U

§ ADC_ICLR1_HIGHIFG_NO_EFFECT

#define ADC_ICLR1_HIGHIFG_NO_EFFECT   0x00000000U

§ ADC_IMASK2_MEMRESIFG3

#define ADC_IMASK2_MEMRESIFG3   0x00000800U

§ ADC_IMASK2_MEMRESIFG3_M

#define ADC_IMASK2_MEMRESIFG3_M   0x00000800U

§ ADC_IMASK2_MEMRESIFG3_S

#define ADC_IMASK2_MEMRESIFG3_S   11U

§ ADC_IMASK2_MEMRESIFG3_SET

#define ADC_IMASK2_MEMRESIFG3_SET   0x00000800U

§ ADC_IMASK2_MEMRESIFG3_CLR

#define ADC_IMASK2_MEMRESIFG3_CLR   0x00000000U

§ ADC_IMASK2_MEMRESIFG2

#define ADC_IMASK2_MEMRESIFG2   0x00000400U

§ ADC_IMASK2_MEMRESIFG2_M

#define ADC_IMASK2_MEMRESIFG2_M   0x00000400U

§ ADC_IMASK2_MEMRESIFG2_S

#define ADC_IMASK2_MEMRESIFG2_S   10U

§ ADC_IMASK2_MEMRESIFG2_SET

#define ADC_IMASK2_MEMRESIFG2_SET   0x00000400U

§ ADC_IMASK2_MEMRESIFG2_CLR

#define ADC_IMASK2_MEMRESIFG2_CLR   0x00000000U

§ ADC_IMASK2_MEMRESIFG1

#define ADC_IMASK2_MEMRESIFG1   0x00000200U

§ ADC_IMASK2_MEMRESIFG1_M

#define ADC_IMASK2_MEMRESIFG1_M   0x00000200U

§ ADC_IMASK2_MEMRESIFG1_S

#define ADC_IMASK2_MEMRESIFG1_S   9U

§ ADC_IMASK2_MEMRESIFG1_SET

#define ADC_IMASK2_MEMRESIFG1_SET   0x00000200U

§ ADC_IMASK2_MEMRESIFG1_CLR

#define ADC_IMASK2_MEMRESIFG1_CLR   0x00000000U

§ ADC_IMASK2_MEMRESIFG0

#define ADC_IMASK2_MEMRESIFG0   0x00000100U

§ ADC_IMASK2_MEMRESIFG0_M

#define ADC_IMASK2_MEMRESIFG0_M   0x00000100U

§ ADC_IMASK2_MEMRESIFG0_S

#define ADC_IMASK2_MEMRESIFG0_S   8U

§ ADC_IMASK2_MEMRESIFG0_SET

#define ADC_IMASK2_MEMRESIFG0_SET   0x00000100U

§ ADC_IMASK2_MEMRESIFG0_CLR

#define ADC_IMASK2_MEMRESIFG0_CLR   0x00000000U

§ ADC_RIS2_MEMRESIFG3

#define ADC_RIS2_MEMRESIFG3   0x00000800U

§ ADC_RIS2_MEMRESIFG3_M

#define ADC_RIS2_MEMRESIFG3_M   0x00000800U

§ ADC_RIS2_MEMRESIFG3_S

#define ADC_RIS2_MEMRESIFG3_S   11U

§ ADC_RIS2_MEMRESIFG3_SET

#define ADC_RIS2_MEMRESIFG3_SET   0x00000800U

§ ADC_RIS2_MEMRESIFG3_CLR

#define ADC_RIS2_MEMRESIFG3_CLR   0x00000000U

§ ADC_RIS2_MEMRESIFG2

#define ADC_RIS2_MEMRESIFG2   0x00000400U

§ ADC_RIS2_MEMRESIFG2_M

#define ADC_RIS2_MEMRESIFG2_M   0x00000400U

§ ADC_RIS2_MEMRESIFG2_S

#define ADC_RIS2_MEMRESIFG2_S   10U

§ ADC_RIS2_MEMRESIFG2_SET

#define ADC_RIS2_MEMRESIFG2_SET   0x00000400U

§ ADC_RIS2_MEMRESIFG2_CLR

#define ADC_RIS2_MEMRESIFG2_CLR   0x00000000U

§ ADC_RIS2_MEMRESIFG1

#define ADC_RIS2_MEMRESIFG1   0x00000200U

§ ADC_RIS2_MEMRESIFG1_M

#define ADC_RIS2_MEMRESIFG1_M   0x00000200U

§ ADC_RIS2_MEMRESIFG1_S

#define ADC_RIS2_MEMRESIFG1_S   9U

§ ADC_RIS2_MEMRESIFG1_SET

#define ADC_RIS2_MEMRESIFG1_SET   0x00000200U

§ ADC_RIS2_MEMRESIFG1_CLR

#define ADC_RIS2_MEMRESIFG1_CLR   0x00000000U

§ ADC_RIS2_MEMRESIFG0

#define ADC_RIS2_MEMRESIFG0   0x00000100U

§ ADC_RIS2_MEMRESIFG0_M

#define ADC_RIS2_MEMRESIFG0_M   0x00000100U

§ ADC_RIS2_MEMRESIFG0_S

#define ADC_RIS2_MEMRESIFG0_S   8U

§ ADC_RIS2_MEMRESIFG0_SET

#define ADC_RIS2_MEMRESIFG0_SET   0x00000100U

§ ADC_RIS2_MEMRESIFG0_CLR

#define ADC_RIS2_MEMRESIFG0_CLR   0x00000000U

§ ADC_MIS2_MEMRESIFG3

#define ADC_MIS2_MEMRESIFG3   0x00000800U

§ ADC_MIS2_MEMRESIFG3_M

#define ADC_MIS2_MEMRESIFG3_M   0x00000800U

§ ADC_MIS2_MEMRESIFG3_S

#define ADC_MIS2_MEMRESIFG3_S   11U

§ ADC_MIS2_MEMRESIFG3_SET

#define ADC_MIS2_MEMRESIFG3_SET   0x00000800U

§ ADC_MIS2_MEMRESIFG3_CLR

#define ADC_MIS2_MEMRESIFG3_CLR   0x00000000U

§ ADC_MIS2_MEMRESIFG2

#define ADC_MIS2_MEMRESIFG2   0x00000400U

§ ADC_MIS2_MEMRESIFG2_M

#define ADC_MIS2_MEMRESIFG2_M   0x00000400U

§ ADC_MIS2_MEMRESIFG2_S

#define ADC_MIS2_MEMRESIFG2_S   10U

§ ADC_MIS2_MEMRESIFG2_SET

#define ADC_MIS2_MEMRESIFG2_SET   0x00000400U

§ ADC_MIS2_MEMRESIFG2_CLR

#define ADC_MIS2_MEMRESIFG2_CLR   0x00000000U

§ ADC_MIS2_MEMRESIFG1

#define ADC_MIS2_MEMRESIFG1   0x00000200U

§ ADC_MIS2_MEMRESIFG1_M

#define ADC_MIS2_MEMRESIFG1_M   0x00000200U

§ ADC_MIS2_MEMRESIFG1_S

#define ADC_MIS2_MEMRESIFG1_S   9U

§ ADC_MIS2_MEMRESIFG1_SET

#define ADC_MIS2_MEMRESIFG1_SET   0x00000200U

§ ADC_MIS2_MEMRESIFG1_CLR

#define ADC_MIS2_MEMRESIFG1_CLR   0x00000000U

§ ADC_MIS2_MEMRESIFG0

#define ADC_MIS2_MEMRESIFG0   0x00000100U

§ ADC_MIS2_MEMRESIFG0_M

#define ADC_MIS2_MEMRESIFG0_M   0x00000100U

§ ADC_MIS2_MEMRESIFG0_S

#define ADC_MIS2_MEMRESIFG0_S   8U

§ ADC_MIS2_MEMRESIFG0_SET

#define ADC_MIS2_MEMRESIFG0_SET   0x00000100U

§ ADC_MIS2_MEMRESIFG0_CLR

#define ADC_MIS2_MEMRESIFG0_CLR   0x00000000U

§ ADC_ISET2_MEMRESIFG3

#define ADC_ISET2_MEMRESIFG3   0x00000800U

§ ADC_ISET2_MEMRESIFG3_M

#define ADC_ISET2_MEMRESIFG3_M   0x00000800U

§ ADC_ISET2_MEMRESIFG3_S

#define ADC_ISET2_MEMRESIFG3_S   11U

§ ADC_ISET2_MEMRESIFG3_SET

#define ADC_ISET2_MEMRESIFG3_SET   0x00000800U

§ ADC_ISET2_MEMRESIFG3_NO_EFFECT

#define ADC_ISET2_MEMRESIFG3_NO_EFFECT   0x00000000U

§ ADC_ISET2_MEMRESIFG2

#define ADC_ISET2_MEMRESIFG2   0x00000400U

§ ADC_ISET2_MEMRESIFG2_M

#define ADC_ISET2_MEMRESIFG2_M   0x00000400U

§ ADC_ISET2_MEMRESIFG2_S

#define ADC_ISET2_MEMRESIFG2_S   10U

§ ADC_ISET2_MEMRESIFG2_SET

#define ADC_ISET2_MEMRESIFG2_SET   0x00000400U

§ ADC_ISET2_MEMRESIFG2_NO_EFFECT

#define ADC_ISET2_MEMRESIFG2_NO_EFFECT   0x00000000U

§ ADC_ISET2_MEMRESIFG1

#define ADC_ISET2_MEMRESIFG1   0x00000200U

§ ADC_ISET2_MEMRESIFG1_M

#define ADC_ISET2_MEMRESIFG1_M   0x00000200U

§ ADC_ISET2_MEMRESIFG1_S

#define ADC_ISET2_MEMRESIFG1_S   9U

§ ADC_ISET2_MEMRESIFG1_SET

#define ADC_ISET2_MEMRESIFG1_SET   0x00000200U

§ ADC_ISET2_MEMRESIFG1_NO_EFFECT

#define ADC_ISET2_MEMRESIFG1_NO_EFFECT   0x00000000U

§ ADC_ISET2_MEMRESIFG0

#define ADC_ISET2_MEMRESIFG0   0x00000100U

§ ADC_ISET2_MEMRESIFG0_M

#define ADC_ISET2_MEMRESIFG0_M   0x00000100U

§ ADC_ISET2_MEMRESIFG0_S

#define ADC_ISET2_MEMRESIFG0_S   8U

§ ADC_ISET2_MEMRESIFG0_SET

#define ADC_ISET2_MEMRESIFG0_SET   0x00000100U

§ ADC_ISET2_MEMRESIFG0_NO_EFFECT

#define ADC_ISET2_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_ICLR2_MEMRESIFG3

#define ADC_ICLR2_MEMRESIFG3   0x00000800U

§ ADC_ICLR2_MEMRESIFG3_M

#define ADC_ICLR2_MEMRESIFG3_M   0x00000800U

§ ADC_ICLR2_MEMRESIFG3_S

#define ADC_ICLR2_MEMRESIFG3_S   11U

§ ADC_ICLR2_MEMRESIFG3_CLR

#define ADC_ICLR2_MEMRESIFG3_CLR   0x00000800U

§ ADC_ICLR2_MEMRESIFG3_NO_EFFECT

#define ADC_ICLR2_MEMRESIFG3_NO_EFFECT   0x00000000U

§ ADC_ICLR2_MEMRESIFG2

#define ADC_ICLR2_MEMRESIFG2   0x00000400U

§ ADC_ICLR2_MEMRESIFG2_M

#define ADC_ICLR2_MEMRESIFG2_M   0x00000400U

§ ADC_ICLR2_MEMRESIFG2_S

#define ADC_ICLR2_MEMRESIFG2_S   10U

§ ADC_ICLR2_MEMRESIFG2_CLR

#define ADC_ICLR2_MEMRESIFG2_CLR   0x00000400U

§ ADC_ICLR2_MEMRESIFG2_NO_EFFECT

#define ADC_ICLR2_MEMRESIFG2_NO_EFFECT   0x00000000U

§ ADC_ICLR2_MEMRESIFG1

#define ADC_ICLR2_MEMRESIFG1   0x00000200U

§ ADC_ICLR2_MEMRESIFG1_M

#define ADC_ICLR2_MEMRESIFG1_M   0x00000200U

§ ADC_ICLR2_MEMRESIFG1_S

#define ADC_ICLR2_MEMRESIFG1_S   9U

§ ADC_ICLR2_MEMRESIFG1_CLR

#define ADC_ICLR2_MEMRESIFG1_CLR   0x00000200U

§ ADC_ICLR2_MEMRESIFG1_NO_EFFECT

#define ADC_ICLR2_MEMRESIFG1_NO_EFFECT   0x00000000U

§ ADC_ICLR2_MEMRESIFG0

#define ADC_ICLR2_MEMRESIFG0   0x00000100U

§ ADC_ICLR2_MEMRESIFG0_M

#define ADC_ICLR2_MEMRESIFG0_M   0x00000100U

§ ADC_ICLR2_MEMRESIFG0_S

#define ADC_ICLR2_MEMRESIFG0_S   8U

§ ADC_ICLR2_MEMRESIFG0_CLR

#define ADC_ICLR2_MEMRESIFG0_CLR   0x00000100U

§ ADC_ICLR2_MEMRESIFG0_NO_EFFECT

#define ADC_ICLR2_MEMRESIFG0_NO_EFFECT   0x00000000U

§ ADC_CTL0_SCLKDIV_W

#define ADC_CTL0_SCLKDIV_W   3U

§ ADC_CTL0_SCLKDIV_M

#define ADC_CTL0_SCLKDIV_M   0x07000000U

Referenced by ADCSetSampleDuration().

§ ADC_CTL0_SCLKDIV_S

#define ADC_CTL0_SCLKDIV_S   24U

§ ADC_CTL0_SCLKDIV_DIV_BY_48

#define ADC_CTL0_SCLKDIV_DIV_BY_48   0x07000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_32

#define ADC_CTL0_SCLKDIV_DIV_BY_32   0x06000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_24

#define ADC_CTL0_SCLKDIV_DIV_BY_24   0x05000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_16

#define ADC_CTL0_SCLKDIV_DIV_BY_16   0x04000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_8

#define ADC_CTL0_SCLKDIV_DIV_BY_8   0x03000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_4

#define ADC_CTL0_SCLKDIV_DIV_BY_4   0x02000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_2

#define ADC_CTL0_SCLKDIV_DIV_BY_2   0x01000000U

§ ADC_CTL0_SCLKDIV_DIV_BY_1

#define ADC_CTL0_SCLKDIV_DIV_BY_1   0x00000000U

§ ADC_CTL0_PWRDN

#define ADC_CTL0_PWRDN   0x00010000U

§ ADC_CTL0_PWRDN_M

#define ADC_CTL0_PWRDN_M   0x00010000U

§ ADC_CTL0_PWRDN_S

#define ADC_CTL0_PWRDN_S   16U

§ ADC_CTL0_PWRDN_MANUAL

#define ADC_CTL0_PWRDN_MANUAL   0x00010000U

§ ADC_CTL0_PWRDN_AUTO

#define ADC_CTL0_PWRDN_AUTO   0x00000000U

§ ADC_CTL0_ENC

#define ADC_CTL0_ENC   0x00000001U

§ ADC_CTL0_ENC_M

#define ADC_CTL0_ENC_M   0x00000001U

§ ADC_CTL0_ENC_S

#define ADC_CTL0_ENC_S   0U

§ ADC_CTL0_ENC_ON

#define ADC_CTL0_ENC_ON   0x00000001U

Referenced by ADCManualTrigger().

§ ADC_CTL0_ENC_OFF

#define ADC_CTL0_ENC_OFF   0x00000000U

§ ADC_CTL1_SAMPMODE

#define ADC_CTL1_SAMPMODE   0x00100000U

§ ADC_CTL1_SAMPMODE_M

#define ADC_CTL1_SAMPMODE_M   0x00100000U

Referenced by ADCManualTrigger().

§ ADC_CTL1_SAMPMODE_S

#define ADC_CTL1_SAMPMODE_S   20U

§ ADC_CTL1_SAMPMODE_MANUAL

#define ADC_CTL1_SAMPMODE_MANUAL   0x00100000U

§ ADC_CTL1_SAMPMODE_AUTO

#define ADC_CTL1_SAMPMODE_AUTO   0x00000000U

Referenced by ADCManualTrigger().

§ ADC_CTL1_CONSEQ_W

#define ADC_CTL1_CONSEQ_W   2U

§ ADC_CTL1_CONSEQ_M

#define ADC_CTL1_CONSEQ_M   0x00030000U

Referenced by ADCSetSequence().

§ ADC_CTL1_CONSEQ_S

#define ADC_CTL1_CONSEQ_S   16U

§ ADC_CTL1_CONSEQ_REPEATSEQUENCE

#define ADC_CTL1_CONSEQ_REPEATSEQUENCE   0x00030000U

§ ADC_CTL1_CONSEQ_REPEATSINGLE

#define ADC_CTL1_CONSEQ_REPEATSINGLE   0x00020000U

§ ADC_CTL1_CONSEQ_SEQUENCE

#define ADC_CTL1_CONSEQ_SEQUENCE   0x00010000U

§ ADC_CTL1_CONSEQ_SINGLE

#define ADC_CTL1_CONSEQ_SINGLE   0x00000000U

§ ADC_CTL1_SC

#define ADC_CTL1_SC   0x00000100U

§ ADC_CTL1_SC_M

#define ADC_CTL1_SC_M   0x00000100U

Referenced by ADCManualTrigger().

§ ADC_CTL1_SC_S

#define ADC_CTL1_SC_S   8U

§ ADC_CTL1_SC_START

#define ADC_CTL1_SC_START   0x00000100U

Referenced by ADCManualTrigger().

§ ADC_CTL1_SC_STOP

#define ADC_CTL1_SC_STOP   0x00000000U

§ ADC_CTL1_TRIGSRC

#define ADC_CTL1_TRIGSRC   0x00000001U

§ ADC_CTL1_TRIGSRC_M

#define ADC_CTL1_TRIGSRC_M   0x00000001U

Referenced by ADCManualTrigger().

§ ADC_CTL1_TRIGSRC_S

#define ADC_CTL1_TRIGSRC_S   0U

§ ADC_CTL1_TRIGSRC_EVENT

#define ADC_CTL1_TRIGSRC_EVENT   0x00000001U

§ ADC_CTL1_TRIGSRC_SOFTWARE

#define ADC_CTL1_TRIGSRC_SOFTWARE   0x00000000U

Referenced by ADCManualTrigger().

§ ADC_CTL2_ENDADD_W

#define ADC_CTL2_ENDADD_W   5U

§ ADC_CTL2_ENDADD_M

#define ADC_CTL2_ENDADD_M   0x1F000000U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_ENDADD_S

#define ADC_CTL2_ENDADD_S   24U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_ENDADD_ADDR_03

#define ADC_CTL2_ENDADD_ADDR_03   0x03000000U

§ ADC_CTL2_ENDADD_ADDR_02

#define ADC_CTL2_ENDADD_ADDR_02   0x02000000U

§ ADC_CTL2_ENDADD_ADDR_01

#define ADC_CTL2_ENDADD_ADDR_01   0x01000000U

§ ADC_CTL2_ENDADD_ADDR_00

#define ADC_CTL2_ENDADD_ADDR_00   0x00000000U

§ ADC_CTL2_STARTADD_W

#define ADC_CTL2_STARTADD_W   5U

§ ADC_CTL2_STARTADD_M

#define ADC_CTL2_STARTADD_M   0x001F0000U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_STARTADD_S

#define ADC_CTL2_STARTADD_S   16U

Referenced by ADCSetMemctlRange().

§ ADC_CTL2_STARTADD_ADDR_03

#define ADC_CTL2_STARTADD_ADDR_03   0x00030000U

§ ADC_CTL2_STARTADD_ADDR_02

#define ADC_CTL2_STARTADD_ADDR_02   0x00020000U

§ ADC_CTL2_STARTADD_ADDR_01

#define ADC_CTL2_STARTADD_ADDR_01   0x00010000U

§ ADC_CTL2_STARTADD_ADDR_00

#define ADC_CTL2_STARTADD_ADDR_00   0x00000000U

§ ADC_CTL2_FIFOEN

#define ADC_CTL2_FIFOEN   0x00000400U

§ ADC_CTL2_FIFOEN_M

#define ADC_CTL2_FIFOEN_M   0x00000400U

§ ADC_CTL2_FIFOEN_S

#define ADC_CTL2_FIFOEN_S   10U

§ ADC_CTL2_FIFOEN_EN

#define ADC_CTL2_FIFOEN_EN   0x00000400U

§ ADC_CTL2_FIFOEN_DIS

#define ADC_CTL2_FIFOEN_DIS   0x00000000U

§ ADC_CTL2_DMAEN

#define ADC_CTL2_DMAEN   0x00000100U

§ ADC_CTL2_DMAEN_M

#define ADC_CTL2_DMAEN_M   0x00000100U

§ ADC_CTL2_DMAEN_S

#define ADC_CTL2_DMAEN_S   8U

§ ADC_CTL2_DMAEN_EN

#define ADC_CTL2_DMAEN_EN   0x00000100U

§ ADC_CTL2_DMAEN_DIS

#define ADC_CTL2_DMAEN_DIS   0x00000000U

§ ADC_CTL2_RES_W

#define ADC_CTL2_RES_W   2U

§ ADC_CTL2_RES_M

#define ADC_CTL2_RES_M   0x00000006U

Referenced by ADCSetResolution().

§ ADC_CTL2_RES_S

#define ADC_CTL2_RES_S   1U

§ ADC_CTL2_RES_BIT_8

#define ADC_CTL2_RES_BIT_8   0x00000004U

§ ADC_CTL2_RES_BIT_10

#define ADC_CTL2_RES_BIT_10   0x00000002U

§ ADC_CTL2_RES_BIT_12

#define ADC_CTL2_RES_BIT_12   0x00000000U

§ ADC_CTL2_DF

#define ADC_CTL2_DF   0x00000001U

§ ADC_CTL2_DF_M

#define ADC_CTL2_DF_M   0x00000001U

§ ADC_CTL2_DF_S

#define ADC_CTL2_DF_S   0U

§ ADC_CTL2_DF_SIGNED

#define ADC_CTL2_DF_SIGNED   0x00000001U

§ ADC_CTL2_DF_UNSIGNED

#define ADC_CTL2_DF_UNSIGNED   0x00000000U

§ ADC_CTL3_ASCVRSEL_W

#define ADC_CTL3_ASCVRSEL_W   2U

§ ADC_CTL3_ASCVRSEL_M

#define ADC_CTL3_ASCVRSEL_M   0x00003000U

§ ADC_CTL3_ASCVRSEL_S

#define ADC_CTL3_ASCVRSEL_S   12U

§ ADC_CTL3_ASCVRSEL_INTREF

#define ADC_CTL3_ASCVRSEL_INTREF   0x00002000U

§ ADC_CTL3_ASCVRSEL_EXTREF

#define ADC_CTL3_ASCVRSEL_EXTREF   0x00001000U

§ ADC_CTL3_ASCVRSEL_VDDS

#define ADC_CTL3_ASCVRSEL_VDDS   0x00000000U

§ ADC_CTL3_ASCSTIME

#define ADC_CTL3_ASCSTIME   0x00000100U

§ ADC_CTL3_ASCSTIME_M

#define ADC_CTL3_ASCSTIME_M   0x00000100U

§ ADC_CTL3_ASCSTIME_S

#define ADC_CTL3_ASCSTIME_S   8U

§ ADC_CTL3_ASCSTIME_SEL_SCOMP1

#define ADC_CTL3_ASCSTIME_SEL_SCOMP1   0x00000100U

§ ADC_CTL3_ASCSTIME_SEL_SCOMP0

#define ADC_CTL3_ASCSTIME_SEL_SCOMP0   0x00000000U

§ ADC_CTL3_ASCCHSEL_W

#define ADC_CTL3_ASCCHSEL_W   5U

§ ADC_CTL3_ASCCHSEL_M

#define ADC_CTL3_ASCCHSEL_M   0x0000001FU

§ ADC_CTL3_ASCCHSEL_S

#define ADC_CTL3_ASCCHSEL_S   0U

§ ADC_CTL3_ASCCHSEL_CHAN_15

#define ADC_CTL3_ASCCHSEL_CHAN_15   0x0000000FU

§ ADC_CTL3_ASCCHSEL_CHAN_14

#define ADC_CTL3_ASCCHSEL_CHAN_14   0x0000000EU

§ ADC_CTL3_ASCCHSEL_CHAN_13

#define ADC_CTL3_ASCCHSEL_CHAN_13   0x0000000DU

§ ADC_CTL3_ASCCHSEL_CHAN_12

#define ADC_CTL3_ASCCHSEL_CHAN_12   0x0000000CU

§ ADC_CTL3_ASCCHSEL_CHAN_11

#define ADC_CTL3_ASCCHSEL_CHAN_11   0x0000000BU

§ ADC_CTL3_ASCCHSEL_CHAN_10

#define ADC_CTL3_ASCCHSEL_CHAN_10   0x0000000AU

§ ADC_CTL3_ASCCHSEL_CHAN_9

#define ADC_CTL3_ASCCHSEL_CHAN_9   0x00000009U

§ ADC_CTL3_ASCCHSEL_CHAN_8

#define ADC_CTL3_ASCCHSEL_CHAN_8   0x00000008U

§ ADC_CTL3_ASCCHSEL_CHAN_7

#define ADC_CTL3_ASCCHSEL_CHAN_7   0x00000007U

§ ADC_CTL3_ASCCHSEL_CHAN_6

#define ADC_CTL3_ASCCHSEL_CHAN_6   0x00000006U

§ ADC_CTL3_ASCCHSEL_CHAN_5

#define ADC_CTL3_ASCCHSEL_CHAN_5   0x00000005U

§ ADC_CTL3_ASCCHSEL_CHAN_4

#define ADC_CTL3_ASCCHSEL_CHAN_4   0x00000004U

§ ADC_CTL3_ASCCHSEL_CHAN_3

#define ADC_CTL3_ASCCHSEL_CHAN_3   0x00000003U

§ ADC_CTL3_ASCCHSEL_CHAN_2

#define ADC_CTL3_ASCCHSEL_CHAN_2   0x00000002U

§ ADC_CTL3_ASCCHSEL_CHAN_1

#define ADC_CTL3_ASCCHSEL_CHAN_1   0x00000001U

§ ADC_CTL3_ASCCHSEL_CHAN_0

#define ADC_CTL3_ASCCHSEL_CHAN_0   0x00000000U

§ ADC_SCOMP0_VAL_W

#define ADC_SCOMP0_VAL_W   10U

§ ADC_SCOMP0_VAL_M

#define ADC_SCOMP0_VAL_M   0x000003FFU

Referenced by ADCSetSampleDuration().

§ ADC_SCOMP0_VAL_S

#define ADC_SCOMP0_VAL_S   0U

§ ADC_SCOMP1_VAL_W

#define ADC_SCOMP1_VAL_W   10U

§ ADC_SCOMP1_VAL_M

#define ADC_SCOMP1_VAL_M   0x000003FFU

§ ADC_SCOMP1_VAL_S

#define ADC_SCOMP1_VAL_S   0U

§ ADC_REFCFG_IBPROG_W

#define ADC_REFCFG_IBPROG_W   2U

§ ADC_REFCFG_IBPROG_M

#define ADC_REFCFG_IBPROG_M   0x00000018U

§ ADC_REFCFG_IBPROG_S

#define ADC_REFCFG_IBPROG_S   3U

§ ADC_REFCFG_IBPROG_VAL3

#define ADC_REFCFG_IBPROG_VAL3   0x00000018U

§ ADC_REFCFG_IBPROG_VAL2

#define ADC_REFCFG_IBPROG_VAL2   0x00000010U

§ ADC_REFCFG_IBPROG_VAL1

#define ADC_REFCFG_IBPROG_VAL1   0x00000008U

§ ADC_REFCFG_IBPROG_VAL0

#define ADC_REFCFG_IBPROG_VAL0   0x00000000U

Referenced by ADCSetInput().

§ ADC_REFCFG_SPARE

#define ADC_REFCFG_SPARE   0x00000004U

§ ADC_REFCFG_SPARE_M

#define ADC_REFCFG_SPARE_M   0x00000004U

§ ADC_REFCFG_SPARE_S

#define ADC_REFCFG_SPARE_S   2U

§ ADC_REFCFG_REFVSEL

#define ADC_REFCFG_REFVSEL   0x00000002U

§ ADC_REFCFG_REFVSEL_M

#define ADC_REFCFG_REFVSEL_M   0x00000002U

§ ADC_REFCFG_REFVSEL_S

#define ADC_REFCFG_REFVSEL_S   1U

§ ADC_REFCFG_REFVSEL_V1P4

#define ADC_REFCFG_REFVSEL_V1P4   0x00000002U

Referenced by ADCSetInput().

§ ADC_REFCFG_REFVSEL_V2P5

#define ADC_REFCFG_REFVSEL_V2P5   0x00000000U

Referenced by ADCSetInput().

§ ADC_REFCFG_REFEN

#define ADC_REFCFG_REFEN   0x00000001U

§ ADC_REFCFG_REFEN_M

#define ADC_REFCFG_REFEN_M   0x00000001U

§ ADC_REFCFG_REFEN_S

#define ADC_REFCFG_REFEN_S   0U

§ ADC_REFCFG_REFEN_EN

#define ADC_REFCFG_REFEN_EN   0x00000001U

Referenced by ADCSetInput().

§ ADC_REFCFG_REFEN_DIS

#define ADC_REFCFG_REFEN_DIS   0x00000000U

Referenced by ADCSetInput().

§ ADC_WCLOW_DATA_W

#define ADC_WCLOW_DATA_W   16U

§ ADC_WCLOW_DATA_M

#define ADC_WCLOW_DATA_M   0x0000FFFFU

§ ADC_WCLOW_DATA_S

#define ADC_WCLOW_DATA_S   0U

§ ADC_WCHIGH_DATA_W

#define ADC_WCHIGH_DATA_W   16U

§ ADC_WCHIGH_DATA_M

#define ADC_WCHIGH_DATA_M   0x0000FFFFU

§ ADC_WCHIGH_DATA_S

#define ADC_WCHIGH_DATA_S   0U

§ ADC_FIFODATA_DATA_W

#define ADC_FIFODATA_DATA_W   32U

§ ADC_FIFODATA_DATA_M

#define ADC_FIFODATA_DATA_M   0xFFFFFFFFU

§ ADC_FIFODATA_DATA_S

#define ADC_FIFODATA_DATA_S   0U

§ ADC_ASCRES_DATA_W

#define ADC_ASCRES_DATA_W   16U

§ ADC_ASCRES_DATA_M

#define ADC_ASCRES_DATA_M   0x0000FFFFU

§ ADC_ASCRES_DATA_S

#define ADC_ASCRES_DATA_S   0U

§ ADC_MEMCTL0_WINCOMP

#define ADC_MEMCTL0_WINCOMP   0x10000000U

§ ADC_MEMCTL0_WINCOMP_M

#define ADC_MEMCTL0_WINCOMP_M   0x10000000U

§ ADC_MEMCTL0_WINCOMP_S

#define ADC_MEMCTL0_WINCOMP_S   28U

§ ADC_MEMCTL0_WINCOMP_EN

#define ADC_MEMCTL0_WINCOMP_EN   0x10000000U

§ ADC_MEMCTL0_WINCOMP_DIS

#define ADC_MEMCTL0_WINCOMP_DIS   0x00000000U

§ ADC_MEMCTL0_TRG

#define ADC_MEMCTL0_TRG   0x01000000U

§ ADC_MEMCTL0_TRG_M

#define ADC_MEMCTL0_TRG_M   0x01000000U

§ ADC_MEMCTL0_TRG_S

#define ADC_MEMCTL0_TRG_S   24U

§ ADC_MEMCTL0_TRG_TRIGGER_NEXT

#define ADC_MEMCTL0_TRG_TRIGGER_NEXT   0x01000000U

§ ADC_MEMCTL0_TRG_AUTO_NEXT

#define ADC_MEMCTL0_TRG_AUTO_NEXT   0x00000000U

§ ADC_MEMCTL0_STIME

#define ADC_MEMCTL0_STIME   0x00001000U

§ ADC_MEMCTL0_STIME_M

#define ADC_MEMCTL0_STIME_M   0x00001000U

§ ADC_MEMCTL0_STIME_S

#define ADC_MEMCTL0_STIME_S   12U

§ ADC_MEMCTL0_STIME_SEL_SCOMP1

#define ADC_MEMCTL0_STIME_SEL_SCOMP1   0x00001000U

§ ADC_MEMCTL0_STIME_SEL_SCOMP0

#define ADC_MEMCTL0_STIME_SEL_SCOMP0   0x00000000U

§ ADC_MEMCTL0_VRSEL_W

#define ADC_MEMCTL0_VRSEL_W   2U

§ ADC_MEMCTL0_VRSEL_M

#define ADC_MEMCTL0_VRSEL_M   0x00000300U

Referenced by ADCSetInput().

§ ADC_MEMCTL0_VRSEL_S

#define ADC_MEMCTL0_VRSEL_S   8U

§ ADC_MEMCTL0_VRSEL_INTREF

#define ADC_MEMCTL0_VRSEL_INTREF   0x00000200U

Referenced by ADCSetInput().

§ ADC_MEMCTL0_VRSEL_EXTREF

#define ADC_MEMCTL0_VRSEL_EXTREF   0x00000100U

Referenced by ADCSetInput().

§ ADC_MEMCTL0_VRSEL_VDDS

#define ADC_MEMCTL0_VRSEL_VDDS   0x00000000U

Referenced by ADCSetInput().

§ ADC_MEMCTL0_CHANSEL_W

#define ADC_MEMCTL0_CHANSEL_W   5U

§ ADC_MEMCTL0_CHANSEL_M

#define ADC_MEMCTL0_CHANSEL_M   0x0000001FU

Referenced by ADCSetInput().

§ ADC_MEMCTL0_CHANSEL_S

#define ADC_MEMCTL0_CHANSEL_S   0U

§ ADC_MEMCTL0_CHANSEL_CHAN_15

#define ADC_MEMCTL0_CHANSEL_CHAN_15   0x0000000FU

§ ADC_MEMCTL0_CHANSEL_CHAN_14

#define ADC_MEMCTL0_CHANSEL_CHAN_14   0x0000000EU

Referenced by enableADC().

§ ADC_MEMCTL0_CHANSEL_CHAN_13

#define ADC_MEMCTL0_CHANSEL_CHAN_13   0x0000000DU

§ ADC_MEMCTL0_CHANSEL_CHAN_12

#define ADC_MEMCTL0_CHANSEL_CHAN_12   0x0000000CU

§ ADC_MEMCTL0_CHANSEL_CHAN_11

#define ADC_MEMCTL0_CHANSEL_CHAN_11   0x0000000BU

§ ADC_MEMCTL0_CHANSEL_CHAN_10

#define ADC_MEMCTL0_CHANSEL_CHAN_10   0x0000000AU

§ ADC_MEMCTL0_CHANSEL_CHAN_9

#define ADC_MEMCTL0_CHANSEL_CHAN_9   0x00000009U

§ ADC_MEMCTL0_CHANSEL_CHAN_8

#define ADC_MEMCTL0_CHANSEL_CHAN_8   0x00000008U

§ ADC_MEMCTL0_CHANSEL_CHAN_7

#define ADC_MEMCTL0_CHANSEL_CHAN_7   0x00000007U

§ ADC_MEMCTL0_CHANSEL_CHAN_6

#define ADC_MEMCTL0_CHANSEL_CHAN_6   0x00000006U

§ ADC_MEMCTL0_CHANSEL_CHAN_5

#define ADC_MEMCTL0_CHANSEL_CHAN_5   0x00000005U

§ ADC_MEMCTL0_CHANSEL_CHAN_4

#define ADC_MEMCTL0_CHANSEL_CHAN_4   0x00000004U

§ ADC_MEMCTL0_CHANSEL_CHAN_3

#define ADC_MEMCTL0_CHANSEL_CHAN_3   0x00000003U

§ ADC_MEMCTL0_CHANSEL_CHAN_2

#define ADC_MEMCTL0_CHANSEL_CHAN_2   0x00000002U

§ ADC_MEMCTL0_CHANSEL_CHAN_1

#define ADC_MEMCTL0_CHANSEL_CHAN_1   0x00000001U

§ ADC_MEMCTL0_CHANSEL_CHAN_0

#define ADC_MEMCTL0_CHANSEL_CHAN_0   0x00000000U

§ ADC_MEMCTL1_WINCOMP

#define ADC_MEMCTL1_WINCOMP   0x10000000U

§ ADC_MEMCTL1_WINCOMP_M

#define ADC_MEMCTL1_WINCOMP_M   0x10000000U

§ ADC_MEMCTL1_WINCOMP_S

#define ADC_MEMCTL1_WINCOMP_S   28U

§ ADC_MEMCTL1_WINCOMP_EN

#define ADC_MEMCTL1_WINCOMP_EN   0x10000000U

§ ADC_MEMCTL1_WINCOMP_DIS

#define ADC_MEMCTL1_WINCOMP_DIS   0x00000000U

§ ADC_MEMCTL1_TRG

#define ADC_MEMCTL1_TRG   0x01000000U

§ ADC_MEMCTL1_TRG_M

#define ADC_MEMCTL1_TRG_M   0x01000000U

§ ADC_MEMCTL1_TRG_S

#define ADC_MEMCTL1_TRG_S   24U

§ ADC_MEMCTL1_TRG_TRIGGER_NEXT

#define ADC_MEMCTL1_TRG_TRIGGER_NEXT   0x01000000U

§ ADC_MEMCTL1_TRG_AUTO_NEXT

#define ADC_MEMCTL1_TRG_AUTO_NEXT   0x00000000U

§ ADC_MEMCTL1_STIME

#define ADC_MEMCTL1_STIME   0x00001000U

§ ADC_MEMCTL1_STIME_M

#define ADC_MEMCTL1_STIME_M   0x00001000U

§ ADC_MEMCTL1_STIME_S

#define ADC_MEMCTL1_STIME_S   12U

§ ADC_MEMCTL1_STIME_SEL_SCOMP1

#define ADC_MEMCTL1_STIME_SEL_SCOMP1   0x00001000U

§ ADC_MEMCTL1_STIME_SEL_SCOMP0

#define ADC_MEMCTL1_STIME_SEL_SCOMP0   0x00000000U

§ ADC_MEMCTL1_VRSEL_W

#define ADC_MEMCTL1_VRSEL_W   2U

§ ADC_MEMCTL1_VRSEL_M

#define ADC_MEMCTL1_VRSEL_M   0x00000300U

§ ADC_MEMCTL1_VRSEL_S

#define ADC_MEMCTL1_VRSEL_S   8U

§ ADC_MEMCTL1_VRSEL_INTREF

#define ADC_MEMCTL1_VRSEL_INTREF   0x00000200U

§ ADC_MEMCTL1_VRSEL_EXTREF

#define ADC_MEMCTL1_VRSEL_EXTREF   0x00000100U

§ ADC_MEMCTL1_VRSEL_VDDS

#define ADC_MEMCTL1_VRSEL_VDDS   0x00000000U

§ ADC_MEMCTL1_CHANSEL_W

#define ADC_MEMCTL1_CHANSEL_W   5U

§ ADC_MEMCTL1_CHANSEL_M

#define ADC_MEMCTL1_CHANSEL_M   0x0000001FU

§ ADC_MEMCTL1_CHANSEL_S

#define ADC_MEMCTL1_CHANSEL_S   0U

§ ADC_MEMCTL1_CHANSEL_CHAN_15

#define ADC_MEMCTL1_CHANSEL_CHAN_15   0x0000000FU

§ ADC_MEMCTL1_CHANSEL_CHAN_14

#define ADC_MEMCTL1_CHANSEL_CHAN_14   0x0000000EU

§ ADC_MEMCTL1_CHANSEL_CHAN_13

#define ADC_MEMCTL1_CHANSEL_CHAN_13   0x0000000DU

§ ADC_MEMCTL1_CHANSEL_CHAN_12

#define ADC_MEMCTL1_CHANSEL_CHAN_12   0x0000000CU

§ ADC_MEMCTL1_CHANSEL_CHAN_11

#define ADC_MEMCTL1_CHANSEL_CHAN_11   0x0000000BU

§ ADC_MEMCTL1_CHANSEL_CHAN_10

#define ADC_MEMCTL1_CHANSEL_CHAN_10   0x0000000AU

§ ADC_MEMCTL1_CHANSEL_CHAN_9

#define ADC_MEMCTL1_CHANSEL_CHAN_9   0x00000009U

§ ADC_MEMCTL1_CHANSEL_CHAN_8

#define ADC_MEMCTL1_CHANSEL_CHAN_8   0x00000008U

§ ADC_MEMCTL1_CHANSEL_CHAN_7

#define ADC_MEMCTL1_CHANSEL_CHAN_7   0x00000007U

§ ADC_MEMCTL1_CHANSEL_CHAN_6

#define ADC_MEMCTL1_CHANSEL_CHAN_6   0x00000006U

§ ADC_MEMCTL1_CHANSEL_CHAN_5

#define ADC_MEMCTL1_CHANSEL_CHAN_5   0x00000005U

§ ADC_MEMCTL1_CHANSEL_CHAN_4

#define ADC_MEMCTL1_CHANSEL_CHAN_4   0x00000004U

§ ADC_MEMCTL1_CHANSEL_CHAN_3

#define ADC_MEMCTL1_CHANSEL_CHAN_3   0x00000003U

§ ADC_MEMCTL1_CHANSEL_CHAN_2

#define ADC_MEMCTL1_CHANSEL_CHAN_2   0x00000002U

§ ADC_MEMCTL1_CHANSEL_CHAN_1

#define ADC_MEMCTL1_CHANSEL_CHAN_1   0x00000001U

§ ADC_MEMCTL1_CHANSEL_CHAN_0

#define ADC_MEMCTL1_CHANSEL_CHAN_0   0x00000000U

§ ADC_MEMCTL2_WINCOMP

#define ADC_MEMCTL2_WINCOMP   0x10000000U

§ ADC_MEMCTL2_WINCOMP_M

#define ADC_MEMCTL2_WINCOMP_M   0x10000000U

§ ADC_MEMCTL2_WINCOMP_S

#define ADC_MEMCTL2_WINCOMP_S   28U

§ ADC_MEMCTL2_WINCOMP_EN

#define ADC_MEMCTL2_WINCOMP_EN   0x10000000U

§ ADC_MEMCTL2_WINCOMP_DIS

#define ADC_MEMCTL2_WINCOMP_DIS   0x00000000U

§ ADC_MEMCTL2_TRG

#define ADC_MEMCTL2_TRG   0x01000000U

§ ADC_MEMCTL2_TRG_M

#define ADC_MEMCTL2_TRG_M   0x01000000U

§ ADC_MEMCTL2_TRG_S

#define ADC_MEMCTL2_TRG_S   24U

§ ADC_MEMCTL2_TRG_TRIGGER_NEXT

#define ADC_MEMCTL2_TRG_TRIGGER_NEXT   0x01000000U

§ ADC_MEMCTL2_TRG_AUTO_NEXT

#define ADC_MEMCTL2_TRG_AUTO_NEXT   0x00000000U

§ ADC_MEMCTL2_STIME

#define ADC_MEMCTL2_STIME   0x00001000U

§ ADC_MEMCTL2_STIME_M

#define ADC_MEMCTL2_STIME_M   0x00001000U

§ ADC_MEMCTL2_STIME_S

#define ADC_MEMCTL2_STIME_S   12U

§ ADC_MEMCTL2_STIME_SEL_SCOMP1

#define ADC_MEMCTL2_STIME_SEL_SCOMP1   0x00001000U

§ ADC_MEMCTL2_STIME_SEL_SCOMP0

#define ADC_MEMCTL2_STIME_SEL_SCOMP0   0x00000000U

§ ADC_MEMCTL2_VRSEL_W

#define ADC_MEMCTL2_VRSEL_W   2U

§ ADC_MEMCTL2_VRSEL_M

#define ADC_MEMCTL2_VRSEL_M   0x00000300U

§ ADC_MEMCTL2_VRSEL_S

#define ADC_MEMCTL2_VRSEL_S   8U

§ ADC_MEMCTL2_VRSEL_INTREF

#define ADC_MEMCTL2_VRSEL_INTREF   0x00000200U

§ ADC_MEMCTL2_VRSEL_EXTREF

#define ADC_MEMCTL2_VRSEL_EXTREF   0x00000100U

§ ADC_MEMCTL2_VRSEL_VDDS

#define ADC_MEMCTL2_VRSEL_VDDS   0x00000000U

§ ADC_MEMCTL2_CHANSEL_W

#define ADC_MEMCTL2_CHANSEL_W   5U

§ ADC_MEMCTL2_CHANSEL_M

#define ADC_MEMCTL2_CHANSEL_M   0x0000001FU

§ ADC_MEMCTL2_CHANSEL_S

#define ADC_MEMCTL2_CHANSEL_S   0U

§ ADC_MEMCTL2_CHANSEL_CHAN_15

#define ADC_MEMCTL2_CHANSEL_CHAN_15   0x0000000FU

§ ADC_MEMCTL2_CHANSEL_CHAN_14

#define ADC_MEMCTL2_CHANSEL_CHAN_14   0x0000000EU

§ ADC_MEMCTL2_CHANSEL_CHAN_13

#define ADC_MEMCTL2_CHANSEL_CHAN_13   0x0000000DU

§ ADC_MEMCTL2_CHANSEL_CHAN_12

#define ADC_MEMCTL2_CHANSEL_CHAN_12   0x0000000CU

§ ADC_MEMCTL2_CHANSEL_CHAN_11

#define ADC_MEMCTL2_CHANSEL_CHAN_11   0x0000000BU

§ ADC_MEMCTL2_CHANSEL_CHAN_10

#define ADC_MEMCTL2_CHANSEL_CHAN_10   0x0000000AU

§ ADC_MEMCTL2_CHANSEL_CHAN_9

#define ADC_MEMCTL2_CHANSEL_CHAN_9   0x00000009U

§ ADC_MEMCTL2_CHANSEL_CHAN_8

#define ADC_MEMCTL2_CHANSEL_CHAN_8   0x00000008U

§ ADC_MEMCTL2_CHANSEL_CHAN_7

#define ADC_MEMCTL2_CHANSEL_CHAN_7   0x00000007U

§ ADC_MEMCTL2_CHANSEL_CHAN_6

#define ADC_MEMCTL2_CHANSEL_CHAN_6   0x00000006U

§ ADC_MEMCTL2_CHANSEL_CHAN_5

#define ADC_MEMCTL2_CHANSEL_CHAN_5   0x00000005U

§ ADC_MEMCTL2_CHANSEL_CHAN_4

#define ADC_MEMCTL2_CHANSEL_CHAN_4   0x00000004U

§ ADC_MEMCTL2_CHANSEL_CHAN_3

#define ADC_MEMCTL2_CHANSEL_CHAN_3   0x00000003U

§ ADC_MEMCTL2_CHANSEL_CHAN_2

#define ADC_MEMCTL2_CHANSEL_CHAN_2   0x00000002U

§ ADC_MEMCTL2_CHANSEL_CHAN_1

#define ADC_MEMCTL2_CHANSEL_CHAN_1   0x00000001U

§ ADC_MEMCTL2_CHANSEL_CHAN_0

#define ADC_MEMCTL2_CHANSEL_CHAN_0   0x00000000U

§ ADC_MEMCTL3_WINCOMP

#define ADC_MEMCTL3_WINCOMP   0x10000000U

§ ADC_MEMCTL3_WINCOMP_M

#define ADC_MEMCTL3_WINCOMP_M   0x10000000U

§ ADC_MEMCTL3_WINCOMP_S

#define ADC_MEMCTL3_WINCOMP_S   28U

§ ADC_MEMCTL3_WINCOMP_EN

#define ADC_MEMCTL3_WINCOMP_EN   0x10000000U

§ ADC_MEMCTL3_WINCOMP_DIS

#define ADC_MEMCTL3_WINCOMP_DIS   0x00000000U

§ ADC_MEMCTL3_TRG

#define ADC_MEMCTL3_TRG   0x01000000U

§ ADC_MEMCTL3_TRG_M

#define ADC_MEMCTL3_TRG_M   0x01000000U

§ ADC_MEMCTL3_TRG_S

#define ADC_MEMCTL3_TRG_S   24U

§ ADC_MEMCTL3_TRG_TRIGGER_NEXT

#define ADC_MEMCTL3_TRG_TRIGGER_NEXT   0x01000000U

§ ADC_MEMCTL3_TRG_AUTO_NEXT

#define ADC_MEMCTL3_TRG_AUTO_NEXT   0x00000000U

§ ADC_MEMCTL3_STIME

#define ADC_MEMCTL3_STIME   0x00001000U

§ ADC_MEMCTL3_STIME_M

#define ADC_MEMCTL3_STIME_M   0x00001000U

§ ADC_MEMCTL3_STIME_S

#define ADC_MEMCTL3_STIME_S   12U

§ ADC_MEMCTL3_STIME_SEL_SCOMP1

#define ADC_MEMCTL3_STIME_SEL_SCOMP1   0x00001000U

§ ADC_MEMCTL3_STIME_SEL_SCOMP0

#define ADC_MEMCTL3_STIME_SEL_SCOMP0   0x00000000U

§ ADC_MEMCTL3_VRSEL_W

#define ADC_MEMCTL3_VRSEL_W   2U

§ ADC_MEMCTL3_VRSEL_M

#define ADC_MEMCTL3_VRSEL_M   0x00000300U

§ ADC_MEMCTL3_VRSEL_S

#define ADC_MEMCTL3_VRSEL_S   8U

§ ADC_MEMCTL3_VRSEL_INTREF

#define ADC_MEMCTL3_VRSEL_INTREF   0x00000200U

§ ADC_MEMCTL3_VRSEL_EXTREF

#define ADC_MEMCTL3_VRSEL_EXTREF   0x00000100U

§ ADC_MEMCTL3_VRSEL_VDDS

#define ADC_MEMCTL3_VRSEL_VDDS   0x00000000U

§ ADC_MEMCTL3_CHANSEL_W

#define ADC_MEMCTL3_CHANSEL_W   5U

§ ADC_MEMCTL3_CHANSEL_M

#define ADC_MEMCTL3_CHANSEL_M   0x0000001FU

§ ADC_MEMCTL3_CHANSEL_S

#define ADC_MEMCTL3_CHANSEL_S   0U

§ ADC_MEMCTL3_CHANSEL_CHAN_15

#define ADC_MEMCTL3_CHANSEL_CHAN_15   0x0000000FU

§ ADC_MEMCTL3_CHANSEL_CHAN_14

#define ADC_MEMCTL3_CHANSEL_CHAN_14   0x0000000EU

§ ADC_MEMCTL3_CHANSEL_CHAN_13

#define ADC_MEMCTL3_CHANSEL_CHAN_13   0x0000000DU

§ ADC_MEMCTL3_CHANSEL_CHAN_12

#define ADC_MEMCTL3_CHANSEL_CHAN_12   0x0000000CU

§ ADC_MEMCTL3_CHANSEL_CHAN_11

#define ADC_MEMCTL3_CHANSEL_CHAN_11   0x0000000BU

§ ADC_MEMCTL3_CHANSEL_CHAN_10

#define ADC_MEMCTL3_CHANSEL_CHAN_10   0x0000000AU

§ ADC_MEMCTL3_CHANSEL_CHAN_9

#define ADC_MEMCTL3_CHANSEL_CHAN_9   0x00000009U

§ ADC_MEMCTL3_CHANSEL_CHAN_8

#define ADC_MEMCTL3_CHANSEL_CHAN_8   0x00000008U

§ ADC_MEMCTL3_CHANSEL_CHAN_7

#define ADC_MEMCTL3_CHANSEL_CHAN_7   0x00000007U

§ ADC_MEMCTL3_CHANSEL_CHAN_6

#define ADC_MEMCTL3_CHANSEL_CHAN_6   0x00000006U

§ ADC_MEMCTL3_CHANSEL_CHAN_5

#define ADC_MEMCTL3_CHANSEL_CHAN_5   0x00000005U

§ ADC_MEMCTL3_CHANSEL_CHAN_4

#define ADC_MEMCTL3_CHANSEL_CHAN_4   0x00000004U

§ ADC_MEMCTL3_CHANSEL_CHAN_3

#define ADC_MEMCTL3_CHANSEL_CHAN_3   0x00000003U

§ ADC_MEMCTL3_CHANSEL_CHAN_2

#define ADC_MEMCTL3_CHANSEL_CHAN_2   0x00000002U

§ ADC_MEMCTL3_CHANSEL_CHAN_1

#define ADC_MEMCTL3_CHANSEL_CHAN_1   0x00000001U

§ ADC_MEMCTL3_CHANSEL_CHAN_0

#define ADC_MEMCTL3_CHANSEL_CHAN_0   0x00000000U

§ ADC_MEMRES0_DATA_W

#define ADC_MEMRES0_DATA_W   16U

§ ADC_MEMRES0_DATA_M

#define ADC_MEMRES0_DATA_M   0x0000FFFFU

§ ADC_MEMRES0_DATA_S

#define ADC_MEMRES0_DATA_S   0U

§ ADC_MEMRES1_DATA_W

#define ADC_MEMRES1_DATA_W   16U

§ ADC_MEMRES1_DATA_M

#define ADC_MEMRES1_DATA_M   0x0000FFFFU

§ ADC_MEMRES1_DATA_S

#define ADC_MEMRES1_DATA_S   0U

§ ADC_MEMRES2_DATA_W

#define ADC_MEMRES2_DATA_W   16U

§ ADC_MEMRES2_DATA_M

#define ADC_MEMRES2_DATA_M   0x0000FFFFU

§ ADC_MEMRES2_DATA_S

#define ADC_MEMRES2_DATA_S   0U

§ ADC_MEMRES3_DATA_W

#define ADC_MEMRES3_DATA_W   16U

§ ADC_MEMRES3_DATA_M

#define ADC_MEMRES3_DATA_M   0x0000FFFFU

§ ADC_MEMRES3_DATA_S

#define ADC_MEMRES3_DATA_S   0U

§ ADC_STA_ASCACT

#define ADC_STA_ASCACT   0x00000004U

§ ADC_STA_ASCACT_M

#define ADC_STA_ASCACT_M   0x00000004U

§ ADC_STA_ASCACT_S

#define ADC_STA_ASCACT_S   2U

§ ADC_STA_ASCACT_ACTIVE

#define ADC_STA_ASCACT_ACTIVE   0x00000004U

§ ADC_STA_ASCACT_IDLE

#define ADC_STA_ASCACT_IDLE   0x00000000U

§ ADC_STA_BUSY

#define ADC_STA_BUSY   0x00000001U

§ ADC_STA_BUSY_M

#define ADC_STA_BUSY_M   0x00000001U

§ ADC_STA_BUSY_S

#define ADC_STA_BUSY_S   0U

§ ADC_STA_BUSY_ACTIVE

#define ADC_STA_BUSY_ACTIVE   0x00000001U

Referenced by ADCIsBusy(), and ADCReadResult().

§ ADC_STA_BUSY_IDLE

#define ADC_STA_BUSY_IDLE   0x00000000U

§ ADC_TEST0_ATEST0_EN

#define ADC_TEST0_ATEST0_EN   0x40000000U

§ ADC_TEST0_ATEST0_EN_M

#define ADC_TEST0_ATEST0_EN_M   0x40000000U

§ ADC_TEST0_ATEST0_EN_S

#define ADC_TEST0_ATEST0_EN_S   30U

§ ADC_TEST0_ATEST0_EN_EN

#define ADC_TEST0_ATEST0_EN_EN   0x40000000U

§ ADC_TEST0_ATEST0_EN_DIS

#define ADC_TEST0_ATEST0_EN_DIS   0x00000000U

§ ADC_TEST0_ATEST1_EN

#define ADC_TEST0_ATEST1_EN   0x20000000U

§ ADC_TEST0_ATEST1_EN_M

#define ADC_TEST0_ATEST1_EN_M   0x20000000U

§ ADC_TEST0_ATEST1_EN_S

#define ADC_TEST0_ATEST1_EN_S   29U

§ ADC_TEST0_ATEST1_EN_EN

#define ADC_TEST0_ATEST1_EN_EN   0x20000000U

§ ADC_TEST0_ATEST1_EN_DIS

#define ADC_TEST0_ATEST1_EN_DIS   0x00000000U

§ ADC_TEST0_ATEST1_MUXSEL_W

#define ADC_TEST0_ATEST1_MUXSEL_W   5U

§ ADC_TEST0_ATEST1_MUXSEL_M

#define ADC_TEST0_ATEST1_MUXSEL_M   0x00001F00U

§ ADC_TEST0_ATEST1_MUXSEL_S

#define ADC_TEST0_ATEST1_MUXSEL_S   8U

§ ADC_TEST0_ATEST1_MUXSEL_VAL16

#define ADC_TEST0_ATEST1_MUXSEL_VAL16   0x00001000U

§ ADC_TEST0_ATEST1_MUXSEL_VAL8

#define ADC_TEST0_ATEST1_MUXSEL_VAL8   0x00000800U

§ ADC_TEST0_ATEST1_MUXSEL_VAL4

#define ADC_TEST0_ATEST1_MUXSEL_VAL4   0x00000400U

§ ADC_TEST0_ATEST1_MUXSEL_VAL2

#define ADC_TEST0_ATEST1_MUXSEL_VAL2   0x00000200U

§ ADC_TEST0_ATEST1_MUXSEL_VAL1

#define ADC_TEST0_ATEST1_MUXSEL_VAL1   0x00000100U

§ ADC_TEST0_ATEST0_MUXSEL_W

#define ADC_TEST0_ATEST0_MUXSEL_W   5U

§ ADC_TEST0_ATEST0_MUXSEL_M

#define ADC_TEST0_ATEST0_MUXSEL_M   0x0000001FU

§ ADC_TEST0_ATEST0_MUXSEL_S

#define ADC_TEST0_ATEST0_MUXSEL_S   0U

§ ADC_TEST0_ATEST0_MUXSEL_VAL16

#define ADC_TEST0_ATEST0_MUXSEL_VAL16   0x00000010U

§ ADC_TEST0_ATEST0_MUXSEL_VAL8

#define ADC_TEST0_ATEST0_MUXSEL_VAL8   0x00000008U

§ ADC_TEST0_ATEST0_MUXSEL_VAL4

#define ADC_TEST0_ATEST0_MUXSEL_VAL4   0x00000004U

§ ADC_TEST0_ATEST0_MUXSEL_VAL2

#define ADC_TEST0_ATEST0_MUXSEL_VAL2   0x00000002U

§ ADC_TEST0_ATEST0_MUXSEL_VAL1

#define ADC_TEST0_ATEST0_MUXSEL_VAL1   0x00000001U

§ ADC_TEST2_CDAC_OVST_EN

#define ADC_TEST2_CDAC_OVST_EN   0x80000000U

§ ADC_TEST2_CDAC_OVST_EN_M

#define ADC_TEST2_CDAC_OVST_EN_M   0x80000000U

§ ADC_TEST2_CDAC_OVST_EN_S

#define ADC_TEST2_CDAC_OVST_EN_S   31U

§ ADC_TEST2_LATCH_TRIM_EN

#define ADC_TEST2_LATCH_TRIM_EN   0x01000000U

§ ADC_TEST2_LATCH_TRIM_EN_M

#define ADC_TEST2_LATCH_TRIM_EN_M   0x01000000U

§ ADC_TEST2_LATCH_TRIM_EN_S

#define ADC_TEST2_LATCH_TRIM_EN_S   24U

§ ADC_TEST2_COMP_GAIN_TRIM

#define ADC_TEST2_COMP_GAIN_TRIM   0x00100000U

§ ADC_TEST2_COMP_GAIN_TRIM_M

#define ADC_TEST2_COMP_GAIN_TRIM_M   0x00100000U

§ ADC_TEST2_COMP_GAIN_TRIM_S

#define ADC_TEST2_COMP_GAIN_TRIM_S   20U

§ ADC_TEST2_MUX_TEST_SEL

#define ADC_TEST2_MUX_TEST_SEL   0x00000100U

§ ADC_TEST2_MUX_TEST_SEL_M

#define ADC_TEST2_MUX_TEST_SEL_M   0x00000100U

§ ADC_TEST2_MUX_TEST_SEL_S

#define ADC_TEST2_MUX_TEST_SEL_S   8U

§ ADC_TEST3_CAL_ACUML_W

#define ADC_TEST3_CAL_ACUML_W   32U

§ ADC_TEST3_CAL_ACUML_M

#define ADC_TEST3_CAL_ACUML_M   0xFFFFFFFFU

§ ADC_TEST3_CAL_ACUML_S

#define ADC_TEST3_CAL_ACUML_S   0U

§ ADC_TEST4_HW_STEP_SEL_DIS

#define ADC_TEST4_HW_STEP_SEL_DIS   0x80000000U

§ ADC_TEST4_HW_STEP_SEL_DIS_M

#define ADC_TEST4_HW_STEP_SEL_DIS_M   0x80000000U

§ ADC_TEST4_HW_STEP_SEL_DIS_S

#define ADC_TEST4_HW_STEP_SEL_DIS_S   31U

§ ADC_TEST4_CAL_MODE_EN

#define ADC_TEST4_CAL_MODE_EN   0x01000000U

§ ADC_TEST4_CAL_MODE_EN_M

#define ADC_TEST4_CAL_MODE_EN_M   0x01000000U

§ ADC_TEST4_CAL_MODE_EN_S

#define ADC_TEST4_CAL_MODE_EN_S   24U

§ ADC_TEST4_CAL_STEP_SEL_W

#define ADC_TEST4_CAL_STEP_SEL_W   6U

§ ADC_TEST4_CAL_STEP_SEL_M

#define ADC_TEST4_CAL_STEP_SEL_M   0x003F0000U

§ ADC_TEST4_CAL_STEP_SEL_S

#define ADC_TEST4_CAL_STEP_SEL_S   16U

§ ADC_TEST5_CAL_CAP_CTL_W

#define ADC_TEST5_CAL_CAP_CTL_W   10U

§ ADC_TEST5_CAL_CAP_CTL_M

#define ADC_TEST5_CAL_CAP_CTL_M   0x000003FFU

§ ADC_TEST5_CAL_CAP_CTL_S

#define ADC_TEST5_CAL_CAP_CTL_S   0U

§ ADC_TEST6_ATESTSEL_W

#define ADC_TEST6_ATESTSEL_W   4U

§ ADC_TEST6_ATESTSEL_M

#define ADC_TEST6_ATESTSEL_M   0x0000000FU

§ ADC_TEST6_ATESTSEL_S

#define ADC_TEST6_ATESTSEL_S   0U

§ ADC_TEST6_ATESTSEL_VAL8

#define ADC_TEST6_ATESTSEL_VAL8   0x00000008U

§ ADC_TEST6_ATESTSEL_VAL4

#define ADC_TEST6_ATESTSEL_VAL4   0x00000004U

§ ADC_TEST6_ATESTSEL_VAL2

#define ADC_TEST6_ATESTSEL_VAL2   0x00000002U

§ ADC_TEST6_ATESTSEL_VAL1

#define ADC_TEST6_ATESTSEL_VAL1   0x00000001U

§ ADC_TEST6_ATESTSEL_VAL0

#define ADC_TEST6_ATESTSEL_VAL0   0x00000000U

§ ADC_DEBUG1_CTRL_W

#define ADC_DEBUG1_CTRL_W   32U

§ ADC_DEBUG1_CTRL_M

#define ADC_DEBUG1_CTRL_M   0xFFFFFFFFU

§ ADC_DEBUG1_CTRL_S

#define ADC_DEBUG1_CTRL_S   0U

§ ADC_DEBUG2_VTOI_CTRL_W

#define ADC_DEBUG2_VTOI_CTRL_W   2U

§ ADC_DEBUG2_VTOI_CTRL_M

#define ADC_DEBUG2_VTOI_CTRL_M   0x30000000U

§ ADC_DEBUG2_VTOI_CTRL_S

#define ADC_DEBUG2_VTOI_CTRL_S   28U

§ ADC_DEBUG2_VTOI_TESTMODE_EN

#define ADC_DEBUG2_VTOI_TESTMODE_EN   0x01000000U

§ ADC_DEBUG2_VTOI_TESTMODE_EN_M

#define ADC_DEBUG2_VTOI_TESTMODE_EN_M   0x01000000U

§ ADC_DEBUG2_VTOI_TESTMODE_EN_S

#define ADC_DEBUG2_VTOI_TESTMODE_EN_S   24U

§ ADC_DEBUG3_DEC1_DIS

#define ADC_DEBUG3_DEC1_DIS   0x00000020U

§ ADC_DEBUG3_DEC1_DIS_M

#define ADC_DEBUG3_DEC1_DIS_M   0x00000020U

§ ADC_DEBUG3_DEC1_DIS_S

#define ADC_DEBUG3_DEC1_DIS_S   5U

§ ADC_DEBUG3_DEC0_DIS

#define ADC_DEBUG3_DEC0_DIS   0x00000010U

§ ADC_DEBUG3_DEC0_DIS_M

#define ADC_DEBUG3_DEC0_DIS_M   0x00000010U

§ ADC_DEBUG3_DEC0_DIS_S

#define ADC_DEBUG3_DEC0_DIS_S   4U

§ ADC_DEBUG3_BOOST_ENZ

#define ADC_DEBUG3_BOOST_ENZ   0x00000001U

§ ADC_DEBUG3_BOOST_ENZ_M

#define ADC_DEBUG3_BOOST_ENZ_M   0x00000001U

§ ADC_DEBUG3_BOOST_ENZ_S

#define ADC_DEBUG3_BOOST_ENZ_S   0U

§ ADC_DEBUG4_ADC_CTRL0_W

#define ADC_DEBUG4_ADC_CTRL0_W   16U

§ ADC_DEBUG4_ADC_CTRL0_M

#define ADC_DEBUG4_ADC_CTRL0_M   0x0000FFFFU

§ ADC_DEBUG4_ADC_CTRL0_S

#define ADC_DEBUG4_ADC_CTRL0_S   0U