MCUSW
Cdd Ipc User Guide

Introduction

This document details Cdd Ipc module implementations

  • Supported AUTOSAR Release : 4.3.1
  • Supported Configuration Variants : Pre-Compile
  • Vendor ID : CDD_IPC_VENDOR_ID (44)
  • Module ID : CDD_MODULE_ID (255)

Cdd Ipc modules allows core hosting MCAL/AUTOSAR to communicate with other cores (processing entities, with-in SoC) hosting PDK based IPC driver. This driver could be used to transmit and receive variable length messages between cores, via logical communication channel ID's. Can be mapped to Sender-Receiver AUTOSAR interface, for data oriented communication between core that host AUTOSAR / NON AUTOSAR processing entities.

Some of key points to note

  1. Can inter-operate with PDK Ipc driver only
  2. Depends on the built-in mailbox hardware to notify arrival of new message
  3. Relies on shared memory (message would be copied into shared area and destination core notified, the destination core would read this message)
  4. Not configurable (via Cdd Ipc configuration parameters) to use different mailbox, FIFO & user
  5. Interrupt are used, to signal presence of new message destined to this core
  6. Refer IPC CDD Profiled Performance to determine the CPU Hz need to transport / receive a message

Cdd Driver Architecture/Design

Please refer the Cdd IPC design page, which is included as part of release [2]


Functional Description

demo_cdd_ipc_ctrl_ep.png
Cdd Ipc Architecture

As depicted in architecture figure above, Cdd Ipc implementation relies on mailbox, shared memory to transport messages between cores. The shared memory & other associated memories are provided via the configurator, Refer Shared Memory Configuration for details.

It's recommended to not change the recommended configuration for these parameters, unless the user comprehends methods to change memory location (and/or size) of the shared memory.

Communication Channel

A communication channel provides a logical communication channel between two processors. Identified uniquely by an un-signed sequential integer, represented by configurator defined symbolic name.

Refer (SDK Install Directory)/mcusw.xx.yy.zz.bb/mcal_drv/mcal/examples_config/CddIpc_Demo_Cfg/output/generated/include/Cdd_IpcCfg.h for the generated communication channel identifiers.

There could be multiple unique communication channel between any given 2 cores.

End Point

There are two primary identifiers, identifying the end-points for a core. This is used by the driver to identify the source / destination of a message.

  • LocalEp : An unique, non-repetitive integer on the core that hosts MCAL/AUTOSAR
  • RemoteProcId : An unique processor identifiers, which determines the core that this communication channel is associated with (i.e. to be able to send and receive message to / from that core)
  • RemoteEp : An unique, non-repetitive integer on the remote core

Notes on EndPoints

  1. Shall be unique on a core (either local or remote cores)
  2. Need not be same i.e. localEp = X and remoteEp = Y, is a valid
  3. A communication channel shall have unique end-points, i.e. localEp shall be unique and on remote cores, remoteEp shall be unique

Buffer for each channel

  • MaxNumMsgQueued : Number of messages that could potentially be received & queued in the driver before, these messages could be received by applications
  • MaxMsgSize : Size of the largest message that could be received
    The MaxNumMsgQueued & MaxMsgSize is used to determine the memory reserved by the driver. The memory is reserved in (SDK Install Directory)/mcusw.xx.yy.zz.bb/mcal_drv/mcal/examples_config/CddIpc_Demo_Cfg/output/generated/src/Cdd_IpcCfg.c with variable (s) Cdd_IpcCommChBuf_<Channel ID>

Control End Point

The demo application by default uses control channel/Announce API's to notify remote cores of service availability. This feature could be turned OFF Refer for steps to turn OFF

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Interrupt to ISR mapping

The following table lists the interrupt details, required for applications to register ISR to receive interrupt on the core that hosts MCAL/IPC

AM65xx

Host Core Remote Core Cluster User Int No Routed Level 0 Route Level 1 Route Comments
MCU 1 0 MPU 1 0 0 0 436 Yes In = 120, Out = 184 In = 184, Out = 176 Register ISR Cdd_IpcIrqMbxFromMpu_10 for 176
MCU 1 0 MCU 1 1 0 1 437 Yes In = 121, Out = 185 In = 185, Out = 177 Register ISR Cdd_IpcIrqMbxFromMcu_11 for 177
  • Level 0 Router = NAVSS0_INTR0_INTR_ROUTER
  • Level 1 Router = MAIN2MCU_LVL_INTRTR0

J721E / CDD IPC Example on MCU 10

Please note the SCI Client / DMSC Firmware API are invoked to route interrupt to MCU 10 (via routers or no routers)

Host Core Remote Core Cluster User Int No on MCU 10Comments
MCU 1 0 MPU 1 0 0 1 376 ISR Cdd_IpcIrqMbxFromMpu_10
MCU 1 0 MCU 2 0 7 0 377 ISR Cdd_IpcIrqMbxFromMcu_20
MCU 1 0 MCU 2 1 7 0 377 ISR Cdd_IpcIrqMbxFromMcu_21

J721E / CDD IPC Example on MCU 21

Host Core Remote Core Cluster User Int No on MCU 21 Comments
MCU 2 1 MCU 1 1 2 0 177 ISR Cdd_IpcIrqMbxFromMcu_11
MCU 2 1 MPU 1 0 0 1 376 ISR Cdd_IpcIrqMbxFromMpu_10
MCU 2 1 MCU 2 0 7 0 377 ISR Cdd_IpcIrqMbxFromMcu_20

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Configuration

The design document details the various configurable parameters of this implementation, please refer section Configurator of 2

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Power-up

The driver doesn't configure the functional clock and power for the Mailbox module. It is expected that the Secondary Bootloader (SBL) powers up the required modules. Please refer SBL documentation.

Note that, this implementation will NOT reset the Mailbox. Un Expected/stale messages could be delivered by the driver. It's recommended to drain stale messages before announcing the availability via service API Cdd_IpcAnnounce () if enabled.

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Build and Running the Application

Please follow steps detailed in section (Build) to build library or example.

Build MCAL example application

The MCAL example application could be built with the command

$ cd (SDK Install Directory)/mcusw.xx.yy.zz.bb/build
$ make cdd_ipc_app CORE=mcu1_0 BOARD=j721e_evm SOC=j721e -sj
$ OR
$ make cdd_ipc_app CORE=mcu1_0 BOARD=am65xx_evm SOC=am65xx -sj
  • The generated executable is available at
    • (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_app/bin/(SoC)_evm/cdd_ipc_app_mcu1_0_(BUILD_PROFILE).xer5f
    • e.g. (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_app/bin/j721e_evm/cdd_ipc_app_mcu1_0_release.xer5f
    • (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_app/bin/am65xx_evm/cdd_ipc_app_mcu1_0_release.xer5f

Building the remote core example application

The remote core application implementation is available at (SDK Install Directory)/mcusw.xx.yy.zz.bb/mcuss_demos/inter_core_comm/ipc_remote

DRA80X

$ cd (SDK Install Directory)/mcusw.xx.yy.zz.bb/build
$ make ipc_remote_app CORE=mpu1_0 BUILD_OS_TYPE=tirtos -sj

To Build remote core example for other cores, change the variable CORE to require core name. e.g. to build for MCU 1 1 set CORE=mcu1_1

The default/recommended configuration will not enable communication example with MCU 1 1. Ensure to update the configuration to support MCU 1 1. The picture below highlights the

cdd_ipc_ug_mcu11_inclusion.png
Configuration for MCU 1 1

The PDK CSL would require an update to enable MCU 1 1. The changes below highlight the required changes in (SDK Install directory)/(PDK Install Directory)/packages/ti/csl/csl_component.mk

diff --git a/csl_component.mk b/csl_component.mk
index b611ebb..0ad961a 100644
--- a/csl_component.mk
+++ b/csl_component.mk
@@ -118,6 +118,9 @@ ifeq ($(BUILD_ARP32), yes)
 csl_$(SOC)_CORELIST += arp32_1
 endif
 endif
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+csl_$(SOC)_CORELIST += mcu1_1
+endif
 export csl_$(SOC)_CORELIST

J721E

$ cd (SDK Install Directory)/mcusw.xx.yy.zz.bb/build
$ make ipc_remote_app CORE=mpu1_0 BOARD=j721e_evm SOC=j721e BUILD_OS_TYPE=tirtos -sj
$ make ipc_remote_app CORE=mcu2_0 BOARD=j721e_evm SOC=j721e BUILD_OS_TYPE=tirtos -sj
$ make ipc_remote_app CORE=mcu2_1 BOARD=j721e_evm SOC=j721e BUILD_OS_TYPE=tirtos -sj
  • The generated executable is available at
    • (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/ipc_remote_app/bin/(SoC)_evm/ipc_remote_app_mpu1_0_(BUILD_PROFILE).xer5f
    • e.g. (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/ipc_remote_app/bin/j721e_evm/ipc_remote_app_mcu2_0_release.xa53fg
    • e.g. (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/ipc_remote_app/bin/am65xx_evm/ipc_remote_app_mpu1_0_release.xa53fg

Building the MCAL IPC profiling application

Refer IPC Profiling Application for details on the profiling application.

$ cd (SDK Install Directory)/mcusw.xx.yy.zz.bb/build
$ make cdd_ipc_profile_app CORE=mcu1_0 BUILD_OS_TYPE=tirtos -sj
  • The generated executable is available at
    • (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_profile_app/bin/(SoC)_evm/cdd_ipc_profile_app_mcu1_0_(BUILD_PROFILE).xer5f
    • e.g. (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_profile_app/bin/j721e_evm/cdd_ipc_profile_app_mcu1_0_release.xer5f
    • e.g. (SDK Install Directory)/mcusw.xx.yy.zz.bb/binary/cdd_ipc_profile_app/bin/am65xx_evm/cdd_ipc_profile_app_mcu1_0_release.xer5f

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Steps to run example application

Running the example application via CCS

DRA80X

The steps below allows one to run example application on AM65xx EVM

  1. Connect to MCU PULSAR CORTEX R5 0
  2. Connect to Cortex A53 0 0
  3. Load MCAL example application cdd_ipc_app_mcu1_0_release.xer5f available at into MCU PULSAR CORTEX R5 0
  4. Load Remote example application ipc_remote_app_mpu1_0_release.xa53fg available at into Cortex A53 0 0
  5. Run both core, in any order
  6. Output can be observed on CCS console/UART terminal refer Expected Example Output
Running the profiling application via CCS

The steps below allows one to run profiling application on AM65xx EVM

  1. Connect to MCU PULSAR CORTEX R5 0
  2. Connect to Cortex A53 0 0
  3. Load MCAL example application cdd_ipc_profile_app_mcu1_0_release.xer5f available at into MCU PULSAR CORTEX R5 0
  4. Load Remote example application ipc_remote_app_mpu1_0_release.xa53fg available at into Cortex A53 0 0
  5. Run both core, in any order
  6. Output can be observed on CCS console/UART terminal

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J721E
MCU 1 0

The steps below allows one to run example application on J721E EVM

  1. Connect to MCU CORTEX R5 0
  2. Connect to Cortex A72 0 0
  3. Connect to MAIN R5 0 0 (MAIN_Cortex_R5_0_0)
  4. Connect to MAIN R5 0 1 (MAIN_Cortex_R5_0_1)
  5. Load MCAL example application cdd_ipc_app_mcu1_0_release.xer5f available at into MCU PULSAR CORTEX R5 0
  6. Load Remote example application ipc_remote_app_mpu1_0_release.xer5f available at into Cortex A72 0 0
  7. Load Remote example application ipc_remote_app_mcu2_0_release.xer5f available at into MAIN R5 0 0
  8. Load Remote example application ipc_remote_app_mcu2_1_release.xer5f available at into MAIN R5 0 1
  9. Run remote cores (A72)
  10. Run application on MCU 1 0
  11. Run remaining remote cores (MCU 2 0, MCU 2 1)
  12. Output can be observed on CCS console/UART terminal refer Expected Example Output
MCU 2 1

The steps below allows one to run example application on J721E EVM

By default the example application is configured to be hosted on MCU 1 0. This requires to over-ridden to be able to host it on MCU 21. Following list of steps highlights the steps required.

  1. In file (SDK Install Directory)/mcusw/mcuss_demos/inter_core_comm/ipc_remote/main_tirtos.c
  2. Update the variable IpcRemoteApp_DstProc to IPC_MCU2_1
  3. Re Build Remote application as detailed in (J721E)

Steps to run


  1. Connect to MAIN R5 0 1 (MAIN_Cortex_R5_0_1)
  2. Connect to Cortex A72 0 0
  3. Connect to MAIN R5 0 0 (MAIN_Cortex_R5_0_0)
  4. Connect to MCU R5 1 1 (MCU_Cortex_R5_0_1)
  5. Load MCAL example application cdd_ipc_app_mcu2_1_release.xer5f available at into MAIN CORTEX R5 1
  6. Load Remote example application ipc_remote_app_mpu1_0_release.xer5f available at into Cortex A72 0 0
  7. Load Remote example application ipc_remote_app_mcu2_0_release.xer5f available at into MAIN R5 0 0
  8. Load Remote example application ipc_remote_app_mcu1_1_release.xer5f available at into MCU R5 0 1
  9. Run remote cores (A72)
  10. Run application on MCU 2 1
  11. Run remaining remote cores (MCU 2 0, MCU 1 1)
  12. Output can be observed on CCS console/UART terminal refer Expected Example Output. Note that UART port dedicated for main domain would be used, refer (J721E EVM)

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Memory Mapping

Various objects of this implementation (e.g. variables, functions, constants) are defined under different sections. The linker command file at (Examples Linker File (Select memory location to hold example binary)) defines separate section for these objects. When the driver is integrated, it is expected that these sections are created and placed in appropriate memory locations. (Locations of these objects depend on the system design and performance needs)

Section CDD_IPC_CODE CDD_IPC_VAR CDD_IPC_VAR_NOINIT CDD_IPC_CONST CDD_IPC_CONFIG
CDD_IPC_DATA_NO_INIT_UNSPECIFIED_SECTION (.data) USED
CDD_IPC_DATA_INIT_32_SECTION USED
CDD_IPC_TEXT_SECTION USED
CDD_IPC_DATA_NO_INIT_8_SECTION USED
CDD_IPC_CONFIG_SECTION USED
CDD_IPC_ISR_TEXT_SECTION USED
GPT_CONFIG_SECTION USED

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Dependencies on SW Modules


DET

This implementation depends on the DET in order to report development errors and can be turned OFF. Refer to the Development Error Reporting section for detailed error codes.

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SchM

This implementation requires 1 level of exclusive access to guard critical sections. Invokes SchM_Enter_Cdd_Ipc_IPC_EXCLUSIVE_AREA_0(), SchM_Exit_Cdd_Ipc_IPC_EXCLUSIVE_AREA_0() to enter critical section and exit.

In the example implementation (SchM_Cdd_Ipc.c), all the interrupts on CPU are disabled. However, disabling of the enabled Mailbox related interrupts should suffice.

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File Structure

Cdd Ipc File Structure

cdd_ipc_dir_src.png
CDD Ipc Implementation Directory Structure
  • Driver implemented by: Cdd_Ipc.c, Cdd_IpcIrq.c & Cdd_IpcPriv.h core driver files
  • Example Configuration by: Cdd_IpcCfg.c and Cdd_IpcCfg.h
  • Example Application by: CddIpcApp.c & CddIpcApp.h
  • Remote Core Application by: main_tirtos.c, ipc_utils.c & proc_depends_am65xx.c

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Customizing Examples Application


Turn OFF Use Of Control End Point

IPC demo applications use atleast 2 applications running on 2 different cores. Namely ipc_remote_app & cdd_ipc_app OR cdd_ipc_profile_app , these two applications would have to be re built when this features requires to be turned OFF

  1. Update MCAL configuration
    1. Example Application
      1. The configuration used by this application is present in (SDK Install Directory)/mcusw/mcal_drv/mcal/examples_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu1_0
        • OR Incase application is being hosted on MCU 2 1 (SDK Install Directory)/mcusw/mcal_drv/mcal/examples_config/CddIpc_Demo_Cfg/output/generated/soc/j721e/mcu2_1
        • OR Incase DRA80x is being used (SDK Install Directory)/mcusw/mcal_drv/mcal/examples_config/CddIpc_Demo_Cfg/output/generated/soc/am65xx/mcu1_0
      2. Update the configurator to TURN OFF as show below
        cdd_ipc_ug_no_announce.png
        Announce API turned OFF
      3. Regenerate the configuration and copy the same into location specified above
      • Alternately
      1. Set the macro CDD_IPC_ANNOUNCE_API to STD_OFF in Cdd_IpcCfg.h
      2. Re compile the MCAL demo application User Guide
    2. Profiling Application
  2. Update Remote Application configuration

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Error Handling


Development Error Reporting

Development errors are reported to the DET using the service Det_ReportError(), when enabled. The driver interface files (Cdd_IpcCfg.h shown in the driver directory structure of the File Structure section)

Refer Design Document for detailed Error Codes

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Error codes

Production error are reported to DET via Det_ReportError(). Only the error codes in the Cdd Ipc driver specifications are reported which are listed in [] (Runtime Errors)

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API Description

The AUTOSAR BSW Eth Driver specification details the APIs [2].

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Example Application

Flow Chart

The flow chart below depicts the demo application

  • ipc_remote_app_mpu1_0_release.xa53fg would be hosted on Remote Core (MPU 1 0)
  • cdd_ipc_app_mcu1_0_release.xer5f would be hosted on Local Core (MCU 1 0)
demo_cdd_ipc_flowchart.png
Cdd Ipc Demo Application flow chart

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Example Logs

DRA80X

CDD_IPC_APP : CDD IPC MCAL Version Info
CDD_IPC_APP :---------------------
CDD_IPC_APP : Vendor ID           : 44
CDD_IPC_APP : Module ID           : 255
CDD_IPC_APP : SW Major Version    : 1
CDD_IPC_APP : SW Minor Version    : 0
CDD_IPC_APP : SW Patch Version    : 0

CDD_IPC_APP :
CDD_IPC_APP : Sample Application - STARTS !!!
CDD_IPC_APP : Received ping 0 Iteration 10 from MPU 1 0
CDD_IPC_APP : Received ping 1 Iteration 9 from MPU 1 0
CDD_IPC_APP : Received ping 2 Iteration 8 from MPU 1 0
CDD_IPC_APP : Received ping 3 Iteration 7 from MPU 1 0
CDD_IPC_APP : Received ping 4 Iteration 6 from MPU 1 0
CDD_IPC_APP : Received ping 5 Iteration 5 from MPU 1 0
CDD_IPC_APP : Received ping 6 Iteration 4 from MPU 1 0
CDD_IPC_APP : Received ping 7 Iteration 3 from MPU 1 0
CDD_IPC_APP : Received ping 8 Iteration 2 from MPU 1 0
CDD_IPC_APP : Received ping 9 Iteration 1 from MPU 1 0
CDD_IPC_APP : Transmitted and Received 10 times
CDD_IPC_APP : Sample Application - Completes !!!

J721E MCU 1 0

CDD_IPC_APP : CDD IPC MCAL Version Info
CDD_IPC_APP :---------------------
CDD_IPC_APP : Vendor ID           : 44
CDD_IPC_APP : Module ID           : 255
CDD_IPC_APP : SW Major Version    : 1
CDD_IPC_APP : SW Minor Version    : 0
CDD_IPC_APP : SW Patch Version    : 0
 
CDD_IPC_APP :
CDD_IPC_APP : Sample Application - STARTS !!! 
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MCU 2 1
CDD_IPC_APP : Received ping 0 Iteration 10 from MCU 2 1
CDD_IPC_APP : Received ping 1 Iteration 9 from MCU 2 1
CDD_IPC_APP : Received ping 2 Iteration 8 from MCU 2 1
CDD_IPC_APP : Received ping 3 Iteration 7 from MCU 2 1
CDD_IPC_APP : Received ping 4 Iteration 6 from MCU 2 1
CDD_IPC_APP : Received ping 5 Iteration 5 from MCU 2 1
CDD_IPC_APP : Received ping 6 Iteration 4 from MCU 2 1
CDD_IPC_APP : Received ping 7 Iteration 3 from MCU 2 1
CDD_IPC_APP : Received ping 8 Iteration 2 from MCU 2 1
CDD_IPC_APP : Received ping 9 Iteration 1 from MCU 2 1
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MPU 1 0
CDD_IPC_APP : Received ping 0 Iteration 10 from MPU 1 0
CDD_IPC_APP : Received ping 1 Iteration 9 from MPU 1 0
CDD_IPC_APP : Received ping 2 Iteration 8 from MPU 1 0
CDD_IPC_APP : Received ping 3 Iteration 7 from MPU 1 0
CDD_IPC_APP : Received ping 4 Iteration 6 from MPU 1 0
CDD_IPC_APP : Received ping 5 Iteration 5 from MPU 1 0
CDD_IPC_APP : Received ping 6 Iteration 4 from MPU 1 0
CDD_IPC_APP : Received ping 7 Iteration 3 from MPU 1 0
CDD_IPC_APP : Received ping 8 Iteration 2 from MPU 1 0
CDD_IPC_APP : Received ping 9 Iteration 1 from MPU 1 0
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MCU 2 0
CDD_IPC_APP : Received ping 0 Iteration 10 from MCU 2 0
CDD_IPC_APP : Received ping 1 Iteration 9 from MCU 2 0
CDD_IPC_APP : Received ping 2 Iteration 8 from MCU 2 0
CDD_IPC_APP : Received ping 3 Iteration 7 from MCU 2 0
CDD_IPC_APP : Received ping 4 Iteration 6 from MCU 2 0
CDD_IPC_APP : Received ping 5 Iteration 5 from MCU 2 0
CDD_IPC_APP : Received ping 6 Iteration 4 from MCU 2 0
CDD_IPC_APP : Received ping 7 Iteration 3 from MCU 2 0
CDD_IPC_APP : Received ping 8 Iteration 2 from MCU 2 0
CDD_IPC_APP : Received ping 9 Iteration 1 from MCU 2 0
CDD_IPC_APP : Transmitted and Received 10 times
CDD_IPC_APP : Sample Application - Completes !!!

J721E MCU 2 1

CDD_IPC_APP : CDD IPC MCAL Version Info
CDD_IPC_APP :---------------------
CDD_IPC_APP : Vendor ID           : 44
CDD_IPC_APP : Module ID           : 255
CDD_IPC_APP : SW Major Version    : 1
CDD_IPC_APP : SW Minor Version    : 0
CDD_IPC_APP : SW Patch Version    : 0

CDD_IPC_APP :
CDD_IPC_APP : Sample Application - STARTS !!!
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MCU 1 1
CDD_IPC_APP : Received ping 0 Iteration 10 from MCU 1 1
CDD_IPC_APP : Received ping 1 Iteration 9 from MCU 1 1
CDD_IPC_APP : Received ping 2 Iteration 8 from MCU 1 1
CDD_IPC_APP : Received ping 3 Iteration 7 from MCU 1 1
CDD_IPC_APP : Received ping 4 Iteration 6 from MCU 1 1
CDD_IPC_APP : Received ping 5 Iteration 5 from MCU 1 1
CDD_IPC_APP : Received ping 6 Iteration 4 from MCU 1 1
CDD_IPC_APP : Received ping 7 Iteration 3 from MCU 1 1
CDD_IPC_APP : Received ping 8 Iteration 2 from MCU 1 1
CDD_IPC_APP : Received ping 9 Iteration 1 from MCU 1 1
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MCU 2 0
CDD_IPC_APP : Received ping 0 Iteration 10 from MCU 2 0
CDD_IPC_APP : Received ping 1 Iteration 9 from MCU 2 0
CDD_IPC_APP : Received ping 2 Iteration 8 from MCU 2 0
CDD_IPC_APP : Received ping 3 Iteration 7 from MCU 2 0
CDD_IPC_APP : Received ping 4 Iteration 6 from MCU 2 0
CDD_IPC_APP : Received ping 5 Iteration 5 from MCU 2 0
CDD_IPC_APP : Received ping 6 Iteration 4 from MCU 2 0
CDD_IPC_APP : Received ping 7 Iteration 3 from MCU 2 0
CDD_IPC_APP : Received ping 8 Iteration 2 from MCU 2 0
CDD_IPC_APP : Received ping 9 Iteration 1 from MCU 2 0
CDD_IPC_APP : Received ti.ipc4.ping-pong as ctrl MSG from MPU 1 0
CDD_IPC_APP : Received ping 0 Iteration 10 from MPU 1 0
CDD_IPC_APP : Received ping 1 Iteration 9 from MPU 1 0
CDD_IPC_APP : Received ping 2 Iteration 8 from MPU 1 0
CDD_IPC_APP : Received ping 3 Iteration 7 from MPU 1 0
CDD_IPC_APP : Received ping 4 Iteration 6 from MPU 1 0
CDD_IPC_APP : Received ping 5 Iteration 5 from MPU 1 0
CDD_IPC_APP : Received ping 6 Iteration 4 from MPU 1 0
CDD_IPC_APP : Received ping 7 Iteration 3 from MPU 1 0
CDD_IPC_APP : Received ping 8 Iteration 2 from MPU 1 0
CDD_IPC_APP : Received ping 9 Iteration 1 from MPU 1 0
CDD_IPC_APP : Transmitted and Received 10 times
CDD_IPC_APP : Sample Application - Completes !!!

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References

Sl No Specification Comment / Link
1 AUTOSAR 4.3.1 AUTOSAR Specification for CDD Driver & Integration Intranet Link
2 - Design Page (Cdd IPC Design Document)

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Document Revision History

Revision Date Author Description Status
0.1 14 Apr 2019 Sujith S First version Pending Review
0.2 18 Apr 2019 Sujith S Addressed Review comments Approved
0.3 12 Jul 2019 Sujith S Included updates based on J721E Approved
0.4 16 Oct 2018 Sujith S Added Logs from J721E testing Approved