AM62Ax MCU+ SDK  11.01.00
V0/sdlr_ecc.h
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32  * Name : sdlr_ecc.h
33 */
34 
35 #ifndef SDLR_ECC_AGGR_H_
36 #define SDLR_ECC_AGGR_H_
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif
42 #include <sdl/sdlr.h>
43 #include <stdint.h>
44 
45 /**************************************************************************
46 * Hardware Region :
47 **************************************************************************/
48 
49 
50 /**************************************************************************
51 * Register Overlay Structure
52 **************************************************************************/
53 
54 typedef struct {
55  volatile uint32_t REV; /* Aggregator Revision Register */
56  volatile uint8_t Resv_8[4];
57  volatile uint32_t VECTOR; /* ECC Vector Register */
58  volatile uint32_t STAT; /* Misc Status */
59  volatile uint32_t RESERVED_SVBUS[8]; /* Reserved Area for Serial VBUS Registers */
60  volatile uint8_t Resv_60[12];
61  volatile uint32_t SEC_EOI_REG; /* EOI Register */
62  volatile uint32_t SEC_STATUS_REG0; /* Interrupt Status Register 0 */
63  volatile uint8_t Resv_128[60];
64  volatile uint32_t SEC_ENABLE_SET_REG0; /* Interrupt Enable Set Register 0 */
65  volatile uint8_t Resv_192[60];
66  volatile uint32_t SEC_ENABLE_CLR_REG0; /* Interrupt Enable Clear Register 0 */
67  volatile uint8_t Resv_316[120];
68  volatile uint32_t DED_EOI_REG; /* EOI Register */
69  volatile uint32_t DED_STATUS_REG0; /* Interrupt Status Register 0 */
70  volatile uint8_t Resv_384[60];
71  volatile uint32_t DED_ENABLE_SET_REG0; /* Interrupt Enable Set Register 0 */
72  volatile uint8_t Resv_448[60];
73  volatile uint32_t DED_ENABLE_CLR_REG0; /* Interrupt Enable Clear Register 0 */
74  volatile uint8_t Resv_512[60];
75  volatile uint32_t AGGR_ENABLE_SET; /* AGGR interrupt enable set Register */
76  volatile uint32_t AGGR_ENABLE_CLR; /* AGGR interrupt enable clear Register */
77  volatile uint32_t AGGR_STATUS_SET; /* AGGR interrupt status set Register */
78  volatile uint32_t AGGR_STATUS_CLR; /* AGGR interrupt status clear Register */
80 
81 
82 /**************************************************************************
83 * Register Macros
84 **************************************************************************/
85 
86 #define SDL_ECC_AGGR_REV (0x00000000U)
87 #define SDL_ECC_AGGR_VECTOR (0x00000008U)
88 #define SDL_ECC_AGGR_STAT (0x0000000CU)
89 #define SDL_ECC_AGGR_RESERVED_SVBUS(RESERVED_SVBUS) (0x00000010U+((RESERVED_SVBUS)*0x4U))
90 #define SDL_ECC_AGGR_SEC_EOI_REG (0x0000003CU)
91 #define SDL_ECC_AGGR_SEC_STATUS_REG0 (0x00000040U)
92 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0 (0x00000080U)
93 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0 (0x000000C0U)
94 #define SDL_ECC_AGGR_DED_EOI_REG (0x0000013CU)
95 #define SDL_ECC_AGGR_DED_STATUS_REG0 (0x00000140U)
96 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0 (0x00000180U)
97 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0 (0x000001C0U)
98 #define SDL_ECC_AGGR_AGGR_ENABLE_SET (0x00000200U)
99 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR (0x00000204U)
100 #define SDL_ECC_AGGR_AGGR_STATUS_SET (0x00000208U)
101 #define SDL_ECC_AGGR_AGGR_STATUS_CLR (0x0000020CU)
102 
103 /**************************************************************************
104 * Field Definition Macros
105 **************************************************************************/
106 
107 
108 /* REV */
109 
110 #define SDL_ECC_AGGR_REV_SCHEME_MASK (0xC0000000U)
111 #define SDL_ECC_AGGR_REV_SCHEME_SHIFT (0x0000001EU)
112 #define SDL_ECC_AGGR_REV_SCHEME_MAX (0x00000003U)
113 
114 #define SDL_ECC_AGGR_REV_BU_MASK (0x30000000U)
115 #define SDL_ECC_AGGR_REV_BU_SHIFT (0x0000001CU)
116 #define SDL_ECC_AGGR_REV_BU_MAX (0x00000003U)
117 
118 #define SDL_ECC_AGGR_REV_MODULE_ID_MASK (0x0FFF0000U)
119 #define SDL_ECC_AGGR_REV_MODULE_ID_SHIFT (0x00000010U)
120 #define SDL_ECC_AGGR_REV_MODULE_ID_MAX (0x00000FFFU)
121 
122 #define SDL_ECC_AGGR_REV_REVRTL_MASK (0x0000F800U)
123 #define SDL_ECC_AGGR_REV_REVRTL_SHIFT (0x0000000BU)
124 #define SDL_ECC_AGGR_REV_REVRTL_MAX (0x0000001FU)
125 
126 #define SDL_ECC_AGGR_REV_REVMAJ_MASK (0x00000700U)
127 #define SDL_ECC_AGGR_REV_REVMAJ_SHIFT (0x00000008U)
128 #define SDL_ECC_AGGR_REV_REVMAJ_MAX (0x00000007U)
129 
130 #define SDL_ECC_AGGR_REV_CUSTOM_MASK (0x000000C0U)
131 #define SDL_ECC_AGGR_REV_CUSTOM_SHIFT (0x00000006U)
132 #define SDL_ECC_AGGR_REV_CUSTOM_MAX (0x00000003U)
133 
134 #define SDL_ECC_AGGR_REV_REVMIN_MASK (0x0000003FU)
135 #define SDL_ECC_AGGR_REV_REVMIN_SHIFT (0x00000000U)
136 #define SDL_ECC_AGGR_REV_REVMIN_MAX (0x0000003FU)
137 
138 /* VECTOR */
139 
140 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK (0x000007FFU)
141 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT (0x00000000U)
142 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX (0x000007FFU)
143 
144 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)
145 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (0x0000000FU)
146 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX (0x00000001U)
147 
148 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00FF0000U)
149 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (0x00000010U)
150 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX (0x000000FFU)
151 
152 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)
153 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (0x00000018U)
154 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX (0x00000001U)
155 
156 /* STAT */
157 
158 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MASK (0x000007FFU)
159 #define SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT (0x00000000U)
160 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MAX (0x000007FFU)
161 
162 /* RESERVED_SVBUS */
163 
164 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK (0xFFFFFFFFU)
165 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT (0x00000000U)
166 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX (0xFFFFFFFFU)
167 
168 /* SEC_EOI_REG */
169 
170 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK (0x00000001U)
171 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT (0x00000000U)
172 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX (0x00000001U)
173 
174 /* SEC_STATUS_REG0 */
175 
176 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
177 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
178 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
179 
180 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
181 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
182 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
183 
184 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
185 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
186 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
187 
188 /* SEC_ENABLE_SET_REG0 */
189 
190 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
191 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
192 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
193 
194 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
195 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
196 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
197 
198 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
199 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
200 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
201 
202 /* SEC_ENABLE_CLR_REG0 */
203 
204 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
205 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
206 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
207 
208 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
209 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
210 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
211 
212 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
213 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
214 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
215 
216 /* DED_EOI_REG */
217 
218 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK (0x00000001U)
219 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT (0x00000000U)
220 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX (0x00000001U)
221 
222 /* DED_STATUS_REG0 */
223 
224 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
225 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
226 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
227 
228 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
229 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
230 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
231 
232 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
233 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
234 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
235 
236 /* DED_ENABLE_SET_REG0 */
237 
238 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
239 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
240 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
241 
242 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
243 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
244 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
245 
246 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
247 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
248 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
249 
250 /* DED_ENABLE_CLR_REG0 */
251 
252 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
253 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
254 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
255 
256 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
257 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
258 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
259 
260 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
261 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
262 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
263 
264 /* AGGR_ENABLE_SET */
265 
266 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK (0x00000001U)
267 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT (0x00000000U)
268 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX (0x00000001U)
269 
270 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK (0x00000002U)
271 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT (0x00000001U)
272 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX (0x00000001U)
273 
274 /* AGGR_ENABLE_CLR */
275 
276 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK (0x00000001U)
277 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT (0x00000000U)
278 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX (0x00000001U)
279 
280 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK (0x00000002U)
281 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT (0x00000001U)
282 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX (0x00000001U)
283 
284 /* AGGR_STATUS_SET */
285 
286 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK (0x00000003U)
287 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT (0x00000000U)
288 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX (0x00000003U)
289 
290 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK (0x0000000CU)
291 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT (0x00000002U)
292 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX (0x00000003U)
293 
294 /* AGGR_STATUS_CLR */
295 
296 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK (0x00000003U)
297 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT (0x00000000U)
298 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX (0x00000003U)
299 
300 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK (0x0000000CU)
301 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT (0x00000002U)
302 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX (0x00000003U)
303 
304 #ifdef __cplusplus
305 }
306 #endif
307 #endif
SDL_ecc_aggrRegs::SEC_EOI_REG
volatile uint32_t SEC_EOI_REG
Definition: V0/sdlr_ecc.h:61
SDL_ecc_aggrRegs::SEC_STATUS_REG0
volatile uint32_t SEC_STATUS_REG0
Definition: V0/sdlr_ecc.h:62
SDL_ecc_aggrRegs::DED_ENABLE_CLR_REG0
volatile uint32_t DED_ENABLE_CLR_REG0
Definition: V0/sdlr_ecc.h:73
SDL_ecc_aggrRegs
Definition: V0/sdlr_ecc.h:54
SDL_ecc_aggrRegs::DED_STATUS_REG0
volatile uint32_t DED_STATUS_REG0
Definition: V0/sdlr_ecc.h:69
SDL_ecc_aggrRegs::SEC_ENABLE_CLR_REG0
volatile uint32_t SEC_ENABLE_CLR_REG0
Definition: V0/sdlr_ecc.h:66
SDL_ecc_aggrRegs::AGGR_STATUS_SET
volatile uint32_t AGGR_STATUS_SET
Definition: V0/sdlr_ecc.h:77
SDL_ecc_aggrRegs::SEC_ENABLE_SET_REG0
volatile uint32_t SEC_ENABLE_SET_REG0
Definition: V0/sdlr_ecc.h:64
SDL_ecc_aggrRegs::AGGR_ENABLE_SET
volatile uint32_t AGGR_ENABLE_SET
Definition: V0/sdlr_ecc.h:75
SDL_ecc_aggrRegs::AGGR_STATUS_CLR
volatile uint32_t AGGR_STATUS_CLR
Definition: V0/sdlr_ecc.h:78
SDL_ecc_aggrRegs::REV
volatile uint32_t REV
Definition: V0/sdlr_ecc.h:55
SDL_ecc_aggrRegs::DED_ENABLE_SET_REG0
volatile uint32_t DED_ENABLE_SET_REG0
Definition: V0/sdlr_ecc.h:71
SDL_ecc_aggrRegs::DED_EOI_REG
volatile uint32_t DED_EOI_REG
Definition: V0/sdlr_ecc.h:68
SDL_ecc_aggrRegs::AGGR_ENABLE_CLR
volatile uint32_t AGGR_ENABLE_CLR
Definition: V0/sdlr_ecc.h:76
sdlr.h
This file contains the macro definations for Register layer.
SDL_ecc_aggrRegs::STAT
volatile uint32_t STAT
Definition: V0/sdlr_ecc.h:58
SDL_ecc_aggrRegs::VECTOR
volatile uint32_t VECTOR
Definition: V0/sdlr_ecc.h:57