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AM62Ax MCU+ SDK
11.01.00
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35 #ifndef SDLR_ECC_AGGR_H_
36 #define SDLR_ECC_AGGR_H_
55 volatile uint32_t
REV;
56 volatile uint8_t Resv_8[4];
59 volatile uint32_t RESERVED_SVBUS[8];
60 volatile uint8_t Resv_60[12];
63 volatile uint8_t Resv_128[60];
65 volatile uint8_t Resv_192[60];
67 volatile uint8_t Resv_316[120];
70 volatile uint8_t Resv_384[60];
72 volatile uint8_t Resv_448[60];
74 volatile uint8_t Resv_512[60];
86 #define SDL_ECC_AGGR_REV (0x00000000U)
87 #define SDL_ECC_AGGR_VECTOR (0x00000008U)
88 #define SDL_ECC_AGGR_STAT (0x0000000CU)
89 #define SDL_ECC_AGGR_RESERVED_SVBUS(RESERVED_SVBUS) (0x00000010U+((RESERVED_SVBUS)*0x4U))
90 #define SDL_ECC_AGGR_SEC_EOI_REG (0x0000003CU)
91 #define SDL_ECC_AGGR_SEC_STATUS_REG0 (0x00000040U)
92 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0 (0x00000080U)
93 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0 (0x000000C0U)
94 #define SDL_ECC_AGGR_DED_EOI_REG (0x0000013CU)
95 #define SDL_ECC_AGGR_DED_STATUS_REG0 (0x00000140U)
96 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0 (0x00000180U)
97 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0 (0x000001C0U)
98 #define SDL_ECC_AGGR_AGGR_ENABLE_SET (0x00000200U)
99 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR (0x00000204U)
100 #define SDL_ECC_AGGR_AGGR_STATUS_SET (0x00000208U)
101 #define SDL_ECC_AGGR_AGGR_STATUS_CLR (0x0000020CU)
110 #define SDL_ECC_AGGR_REV_SCHEME_MASK (0xC0000000U)
111 #define SDL_ECC_AGGR_REV_SCHEME_SHIFT (0x0000001EU)
112 #define SDL_ECC_AGGR_REV_SCHEME_MAX (0x00000003U)
114 #define SDL_ECC_AGGR_REV_BU_MASK (0x30000000U)
115 #define SDL_ECC_AGGR_REV_BU_SHIFT (0x0000001CU)
116 #define SDL_ECC_AGGR_REV_BU_MAX (0x00000003U)
118 #define SDL_ECC_AGGR_REV_MODULE_ID_MASK (0x0FFF0000U)
119 #define SDL_ECC_AGGR_REV_MODULE_ID_SHIFT (0x00000010U)
120 #define SDL_ECC_AGGR_REV_MODULE_ID_MAX (0x00000FFFU)
122 #define SDL_ECC_AGGR_REV_REVRTL_MASK (0x0000F800U)
123 #define SDL_ECC_AGGR_REV_REVRTL_SHIFT (0x0000000BU)
124 #define SDL_ECC_AGGR_REV_REVRTL_MAX (0x0000001FU)
126 #define SDL_ECC_AGGR_REV_REVMAJ_MASK (0x00000700U)
127 #define SDL_ECC_AGGR_REV_REVMAJ_SHIFT (0x00000008U)
128 #define SDL_ECC_AGGR_REV_REVMAJ_MAX (0x00000007U)
130 #define SDL_ECC_AGGR_REV_CUSTOM_MASK (0x000000C0U)
131 #define SDL_ECC_AGGR_REV_CUSTOM_SHIFT (0x00000006U)
132 #define SDL_ECC_AGGR_REV_CUSTOM_MAX (0x00000003U)
134 #define SDL_ECC_AGGR_REV_REVMIN_MASK (0x0000003FU)
135 #define SDL_ECC_AGGR_REV_REVMIN_SHIFT (0x00000000U)
136 #define SDL_ECC_AGGR_REV_REVMIN_MAX (0x0000003FU)
140 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MASK (0x000007FFU)
141 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_SHIFT (0x00000000U)
142 #define SDL_ECC_AGGR_VECTOR_ECC_VECTOR_MAX (0x000007FFU)
144 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MASK (0x00008000U)
145 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_SHIFT (0x0000000FU)
146 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_MAX (0x00000001U)
148 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MASK (0x00FF0000U)
149 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_SHIFT (0x00000010U)
150 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_ADDRESS_MAX (0x000000FFU)
152 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MASK (0x01000000U)
153 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_SHIFT (0x00000018U)
154 #define SDL_ECC_AGGR_VECTOR_RD_SVBUS_DONE_MAX (0x00000001U)
158 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MASK (0x000007FFU)
159 #define SDL_ECC_AGGR_STAT_NUM_RAMS_SHIFT (0x00000000U)
160 #define SDL_ECC_AGGR_STAT_NUM_RAMS_MAX (0x000007FFU)
164 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MASK (0xFFFFFFFFU)
165 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_SHIFT (0x00000000U)
166 #define SDL_ECC_AGGR_RESERVED_SVBUS_DATA_MAX (0xFFFFFFFFU)
170 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MASK (0x00000001U)
171 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_SHIFT (0x00000000U)
172 #define SDL_ECC_AGGR_SEC_EOI_REG_EOI_WR_MAX (0x00000001U)
176 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
177 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
178 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
180 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
181 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
182 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
184 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
185 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
186 #define SDL_ECC_AGGR_SEC_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
190 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
191 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
192 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
194 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
195 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
196 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
198 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
199 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
200 #define SDL_ECC_AGGR_SEC_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
204 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
205 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
206 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
208 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
209 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
210 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
212 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
213 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
214 #define SDL_ECC_AGGR_SEC_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
218 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MASK (0x00000001U)
219 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_SHIFT (0x00000000U)
220 #define SDL_ECC_AGGR_DED_EOI_REG_EOI_WR_MAX (0x00000001U)
224 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MASK (0x00000001U)
225 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_SHIFT (0x00000000U)
226 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC0_PEND_MAX (0x00000001U)
228 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MASK (0x00000002U)
229 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_SHIFT (0x00000001U)
230 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC1_PEND_MAX (0x00000001U)
232 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MASK (0x00000004U)
233 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_SHIFT (0x00000002U)
234 #define SDL_ECC_AGGR_DED_STATUS_REG0_RAMECC2_PEND_MAX (0x00000001U)
238 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MASK (0x00000001U)
239 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_SHIFT (0x00000000U)
240 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC0_ENABLE_SET_MAX (0x00000001U)
242 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MASK (0x00000002U)
243 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_SHIFT (0x00000001U)
244 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC1_ENABLE_SET_MAX (0x00000001U)
246 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MASK (0x00000004U)
247 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_SHIFT (0x00000002U)
248 #define SDL_ECC_AGGR_DED_ENABLE_SET_REG0_RAMECC2_ENABLE_SET_MAX (0x00000001U)
252 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MASK (0x00000001U)
253 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_SHIFT (0x00000000U)
254 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC0_ENABLE_CLR_MAX (0x00000001U)
256 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MASK (0x00000002U)
257 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_SHIFT (0x00000001U)
258 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC1_ENABLE_CLR_MAX (0x00000001U)
260 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MASK (0x00000004U)
261 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_SHIFT (0x00000002U)
262 #define SDL_ECC_AGGR_DED_ENABLE_CLR_REG0_RAMECC2_ENABLE_CLR_MAX (0x00000001U)
266 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MASK (0x00000001U)
267 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_SHIFT (0x00000000U)
268 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_PARITY_MAX (0x00000001U)
270 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MASK (0x00000002U)
271 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_SHIFT (0x00000001U)
272 #define SDL_ECC_AGGR_AGGR_ENABLE_SET_TIMEOUT_MAX (0x00000001U)
276 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MASK (0x00000001U)
277 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_SHIFT (0x00000000U)
278 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_PARITY_MAX (0x00000001U)
280 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MASK (0x00000002U)
281 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_SHIFT (0x00000001U)
282 #define SDL_ECC_AGGR_AGGR_ENABLE_CLR_TIMEOUT_MAX (0x00000001U)
286 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MASK (0x00000003U)
287 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_SHIFT (0x00000000U)
288 #define SDL_ECC_AGGR_AGGR_STATUS_SET_PARITY_MAX (0x00000003U)
290 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MASK (0x0000000CU)
291 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_SHIFT (0x00000002U)
292 #define SDL_ECC_AGGR_AGGR_STATUS_SET_TIMEOUT_MAX (0x00000003U)
296 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MASK (0x00000003U)
297 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_SHIFT (0x00000000U)
298 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_PARITY_MAX (0x00000003U)
300 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MASK (0x0000000CU)
301 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_SHIFT (0x00000002U)
302 #define SDL_ECC_AGGR_AGGR_STATUS_CLR_TIMEOUT_MAX (0x00000003U)
volatile uint32_t SEC_EOI_REG
Definition: V0/sdlr_ecc.h:61
volatile uint32_t SEC_STATUS_REG0
Definition: V0/sdlr_ecc.h:62
volatile uint32_t DED_ENABLE_CLR_REG0
Definition: V0/sdlr_ecc.h:73
Definition: V0/sdlr_ecc.h:54
volatile uint32_t DED_STATUS_REG0
Definition: V0/sdlr_ecc.h:69
volatile uint32_t SEC_ENABLE_CLR_REG0
Definition: V0/sdlr_ecc.h:66
volatile uint32_t AGGR_STATUS_SET
Definition: V0/sdlr_ecc.h:77
volatile uint32_t SEC_ENABLE_SET_REG0
Definition: V0/sdlr_ecc.h:64
volatile uint32_t AGGR_ENABLE_SET
Definition: V0/sdlr_ecc.h:75
volatile uint32_t AGGR_STATUS_CLR
Definition: V0/sdlr_ecc.h:78
volatile uint32_t REV
Definition: V0/sdlr_ecc.h:55
volatile uint32_t DED_ENABLE_SET_REG0
Definition: V0/sdlr_ecc.h:71
volatile uint32_t DED_EOI_REG
Definition: V0/sdlr_ecc.h:68
volatile uint32_t AGGR_ENABLE_CLR
Definition: V0/sdlr_ecc.h:76
This file contains the macro definations for Register layer.
volatile uint32_t STAT
Definition: V0/sdlr_ecc.h:58
volatile uint32_t VECTOR
Definition: V0/sdlr_ecc.h:57