46 #ifndef SAFETY_CHECKERS_SOC_H_
47 #define SAFETY_CHECKERS_SOC_H_
72 #define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS (0x400000UL)
73 #define SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS (0x680000UL)
74 #define SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS (0x4040000UL)
77 #define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM (0x02U)
78 #define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM (0x0BU)
79 #define SAFETY_CHECKERS_PM_PD_STAT_NUM (0x0EU)
80 #define SAFETY_CHECKERS_PM_MD_STAT_NUM (0x3FU)
83 #define SAFETY_CHECKERS_PM_PLL0_LENGTH (0xA4U)
84 #define SAFETY_CHECKERS_PM_PLL1_LENGTH (0x9CU)
85 #define SAFETY_CHECKERS_PM_PLL2_LENGTH (0xA8U)
86 #define SAFETY_CHECKERS_PM_PLL5_LENGTH (0x88U)
87 #define SAFETY_CHECKERS_PM_PLL7_LENGTH (0x84U)
88 #define SAFETY_CHECKERS_PM_PLL8_LENGTH (0x84U)
89 #define SAFETY_CHECKERS_PM_PLL12_LENGTH (0x84U)
90 #define SAFETY_CHECKERS_PM_PLL15_LENGTH (0x8CU)
91 #define SAFETY_CHECKERS_PM_PLL17_LENGTH (0x84U)
92 #define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH (0x9CU)
95 #define TIFS_CHECKER_FWL_MAX_NUM (0x18U)
101 #define SAFETY_CHECKERS_PM_PSC_REGDUMP_SIZE (SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM + \
102 SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM + \
103 SAFETY_CHECKERS_PM_PD_STAT_NUM + \
104 SAFETY_CHECKERS_PM_MD_STAT_NUM)
114 #define SAFETY_CHECKERS_PM_PLL_REGDUMP_SIZE (150U)
117 #define SAFETY_CHECKERS_RM_BA0_IR (CSL_TIMESYNC_EVENT_ROUTER0_INTR_ROUTER_CFG_BASE)
118 #define SAFETY_CHECKERS_RM_BA1_IR (CSL_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
119 #define SAFETY_CHECKERS_RM_BA2_IR (CSL_MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
120 #define SAFETY_CHECKERS_RM_BA3_IR (CSL_CMP_EVENT_INTROUTER0_INTR_ROUTER_CFG_BASE)
128 #define SAFETY_CHECKERS_RM_REGDUMP_SIZE (3290U)
131 #define SAFETY_CHECKERS_RM_IR_REG0_NUM (26U)
132 #define SAFETY_CHECKERS_RM_IR_REG1_NUM (13U)
133 #define SAFETY_CHECKERS_RM_IR_REG2_NUM (36U)
134 #define SAFETY_CHECKERS_RM_IR_REG3_NUM (42U)
137 #define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM (2U)
140 #define SAFETY_CHECKERS_RM_BA0_IA_IMAP (CSL_DMASS0_INTAGGR_IMAP_BASE)
141 #define SAFETY_CHECKERS_RM_BA1_IA_IMAP (CSL_DMASS1_INTAGGR_IMAP_BASE)
144 #define SAFETY_CHECKERS_RM_REG0_IA_IMAP (1536U)
145 #define SAFETY_CHECKERS_RM_REG1_IA_IMAP (128U)
148 #define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP (1U)
151 #define SAFETY_CHECKERS_RM_BA0_RA (CSL_DMASS0_BCDMA_RING_BASE)
152 #define SAFETY_CHECKERS_RM_BA1_RA (CSL_DMASS0_PKTDMA_RING_BASE)
153 #define SAFETY_CHECKERS_RM_BA2_RA (CSL_DMASS0_RINGACC_CFG_BASE)
154 #define SAFETY_CHECKERS_RM_BA3_RA (CSL_DMASS1_BCDMA_RING_BASE)
157 #define SAFETY_CHECKERS_RM_RA_REG0_NUM (82U)
158 #define SAFETY_CHECKERS_RM_RA_REG1_NUM (150U)
159 #define SAFETY_CHECKERS_RM_RA_REG2_NUM (20U)
160 #define SAFETY_CHECKERS_RM_RA_REG3_NUM (6U)
163 #define SAFETY_CHECKERS_RM_SUBMOD0_RA (3U)
164 #define SAFETY_CHECKERS_RM_RA_SUBMOD1 (5U)
167 #define SAFETY_CHECKERS_RM_BA0_UDMA_TX (CSL_DMASS0_BCDMA_TCHAN_BASE)
168 #define SAFETY_CHECKERS_RM_BA1_UDMA_TX (CSL_DMASS0_PKTDMA_TCHAN_BASE)
171 #define SAFETY_CHECKERS_RM_REG0_UDMA_TX (22U)
172 #define SAFETY_CHECKERS_RM_REG1_UDMA_TX (29U)
175 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX (5U)
178 #define SAFETY_CHECKERS_RM_BA0_UDMA_RX (CSL_DMASS0_BCDMA_RCHAN_BASE)
179 #define SAFETY_CHECKERS_RM_BA1_UDMA_RX (CSL_DMASS0_PKTDMA_RCHAN_BASE)
180 #define SAFETY_CHECKERS_RM_BA2_UDMA_RX (CSL_DMASS1_BCDMA_RCHAN_BASE)
183 #define SAFETY_CHECKERS_RM_REG0_UDMA_RX (28U)
184 #define SAFETY_CHECKERS_RM_REG1_UDMA_RX (24U)
185 #define SAFETY_CHECKERS_RM_REG2_UDMA_RX (6U)
188 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX (4U)
191 #define SAFETY_CHECKERS_RM_BA0_UDMA_FLW (CSL_DMASS0_PKTDMA_RFLOW_BASE)
194 #define SAFETY_CHECKERS_RM_REG0_UDMA_FLW (51U)
197 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW (1U)
200 #define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG (CSL_DMASS0_BCDMA_GCFG_BASE)
201 #define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG (CSL_DMASS0_PKTDMA_GCFG_BASE)
202 #define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG (CSL_DMASS1_BCDMA_GCFG_BASE)
205 #define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG (1U)
206 #define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG (1U)
207 #define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG (1U)
210 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG (13U)
211 #define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG (14U)
212 #define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG (13U)
233 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
234 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
235 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U};
238 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
239 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
240 0x8CU, 0x94U, 0x98U, 0x9CU};
243 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
244 0x40U, 0x44U, 0x60U, 0x64U, 0x84U, 0x88U, 0x8CU,
245 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U, 0xA8U};
248 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
249 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U};
252 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
253 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
256 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
257 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
260 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
261 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
264 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
265 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
269 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
270 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
273 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
274 0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
275 0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU};
328 {
SAFETY_CHECKERS_RM_BA0_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
329 {
SAFETY_CHECKERS_RM_BA1_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
330 {
SAFETY_CHECKERS_RM_BA2_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
331 {
SAFETY_CHECKERS_RM_BA3_IR,
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM,
SAFETY_CHECKERS_RM_IR_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
333 {
SAFETY_CHECKERS_RM_BA0_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG0_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
334 {
SAFETY_CHECKERS_RM_BA1_IA_IMAP,
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP,
SAFETY_CHECKERS_RM_REG1_IA_IMAP,
SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
336 {
SAFETY_CHECKERS_RM_BA0_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG0_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
337 {
SAFETY_CHECKERS_RM_BA1_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG1_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
338 {
SAFETY_CHECKERS_RM_BA2_RA,
SAFETY_CHECKERS_RM_RA_SUBMOD1,
SAFETY_CHECKERS_RM_RA_REG2_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
339 {
SAFETY_CHECKERS_RM_BA3_RA,
SAFETY_CHECKERS_RM_SUBMOD0_RA,
SAFETY_CHECKERS_RM_RA_REG3_NUM,
SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
341 {
SAFETY_CHECKERS_RM_BA0_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG0_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
342 {
SAFETY_CHECKERS_RM_BA1_UDMA_TX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX,
SAFETY_CHECKERS_RM_REG1_UDMA_TX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
344 {
SAFETY_CHECKERS_RM_BA0_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG0_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
345 {
SAFETY_CHECKERS_RM_BA1_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG1_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
346 {
SAFETY_CHECKERS_RM_BA2_UDMA_RX,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX,
SAFETY_CHECKERS_RM_REG2_UDMA_RX,
SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
348 {
SAFETY_CHECKERS_RM_BA0_UDMA_FLW,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG0_UDMA_FLW,
SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
350 {
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
351 {
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
352 {
SAFETY_CHECKERS_RM_BA2_UDMA_GCFG,
SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG2_UDMA_GCFG,
SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},