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AM275 FreeRTOS SDK
11.01.00
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Go to the documentation of this file.
73 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
75 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
77 #define UDMA_INST_ID_START (UDMA_INST_ID_2)
79 #define UDMA_INST_ID_MAX (UDMA_INST_ID_3)
81 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
93 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
96 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
98 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U)
101 #define UDMA_SOC_CFG_PROXY_PRESENT (0U)
104 #define UDMA_SOC_CFG_CLEC_PRESENT (0U)
107 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
110 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U)
113 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
126 #define UDMA_TX_UHC_CHANS_FDEPTH (0U)
128 #define UDMA_TX_HC_CHANS_FDEPTH (0U)
130 #define UDMA_TX_CHANS_FDEPTH (192U)
142 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
144 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
146 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
148 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
152 #define UDMA_NUM_MAPPED_TX_GROUP (4U)
161 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
162 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
163 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
164 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
168 #define UDMA_NUM_MAPPED_RX_GROUP (4U)
177 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
178 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
179 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
180 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
191 #define UDMA_UTC_TYPE_DRU (0U)
192 #define UDMA_UTC_TYPE_DRU_VHWA (1U)
194 #define UDMA_DEFAULT_UTC_CH_BUS_PRIORITY (4U)
196 #define UDMA_DEFAULT_UTC_CH_BUS_QOS (4U)
198 #define UDMA_DEFAULT_UTC_CH_BUS_ORDERID (0U)
200 #define CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET (0x8000U | 0x4820U)
202 #define UDMA_DEFAULT_UTC_CH_DMA_PRIORITY \
203 (TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
206 #define UDMA_DEFAULT_UTC_DRU_QUEUE_ID (CSL_DRU_QUEUE_ID_3)
209 #define UDMA_NUM_UTC_INSTANCE (2U)
220 #define UDMA_UTC_ID_MSMC_DRU0 (UDMA_UTC_ID0)
221 #define UDMA_UTC_ID_VPAC_TC0 (UDMA_UTC_ID1)
225 #define UDMA_UTC_START_CH_DRU0 (0U)
227 #define UDMA_UTC_NUM_CH_DRU0 (32U)
229 #define UDMA_UTC_START_THREAD_ID_DRU0 (0x8000U | 0x4800U)
232 #define UDMA_UTC_START_CH_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET - CSL_PSILCFG_DMSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
234 #define UDMA_UTC_NUM_CH_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT)
236 #define UDMA_UTC_START_THREAD_ID_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET)
239 #define UDMA_UTC_BASE_DRU0 (CSL_C7X256V0_DRU_BASE)
240 #define UDMA_UTC_BASE_DRU1 (CSL_C7X256V1_DRU_BASE)
255 #define UDMA_CORE_ID_MPU1_0 (0U)
256 #define UDMA_CORE_ID_MCU2_0 (1U)
257 #define UDMA_CORE_ID_MCU2_1 (2U)
258 #define UDMA_CORE_ID_MCU1_0 (3U)
259 #define UDMA_CORE_ID_MCU1_1 (4U)
261 #define UDMA_NUM_CORE (5U)
280 #define UDMA_DRU_CORE_ID_MPU1_0 (CSL_DRU_CORE_ID_2)
281 #define UDMA_DRU_CORE_ID_MCU2_0 (CSL_DRU_CORE_ID_2)
282 #define UDMA_DRU_CORE_ID_MCU2_1 (CSL_DRU_CORE_ID_2)
283 #define UDMA_DRU_CORE_ID_MCU3_0 (CSL_DRU_CORE_ID_2)
284 #define UDMA_DRU_CORE_ID_MCU3_1 (CSL_DRU_CORE_ID_2)
285 #define UDMA_DRU_CORE_ID_C7X_1 (CSL_DRU_CORE_ID_0)
286 #define UDMA_DRU_CORE_ID_C66X_1 (CSL_DRU_CORE_ID_1)
287 #define UDMA_DRU_CORE_ID_C66X_2 (CSL_DRU_CORE_ID_2)
288 #define UDMA_DRU_CORE_ID_MCU1_0 (CSL_DRU_CORE_ID_2)
289 #define UDMA_DRU_CORE_ID_MCU1_1 (CSL_DRU_CORE_ID_2)
302 #define UDMA_RM_RES_ID_BC_UHC (0U)
304 #define UDMA_RM_RES_ID_BC_HC (1U)
306 #define UDMA_RM_RES_ID_BC (2U)
308 #define UDMA_RM_RES_ID_TX_UHC (3U)
310 #define UDMA_RM_RES_ID_TX_HC (4U)
312 #define UDMA_RM_RES_ID_TX (5U)
314 #define UDMA_RM_RES_ID_RX_UHC (6U)
316 #define UDMA_RM_RES_ID_RX_HC (7U)
318 #define UDMA_RM_RES_ID_RX (8U)
320 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
322 #define UDMA_RM_RES_ID_VINTR (10U)
324 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
326 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
328 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
330 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
332 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
334 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
336 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
338 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
340 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
342 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
344 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
346 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
348 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
350 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
352 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
354 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
356 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
358 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
360 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
362 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
364 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
366 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
368 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
370 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
372 #define UDMA_RM_NUM_BCDMA_RES (11U)
374 #define UDMA_RM_NUM_PKTDMA_RES (35U)
376 #define UDMA_RM_NUM_RES (35U)
381 #define UDMA_RM_NUM_SHARED_RES (2U)
384 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
387 #define UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
398 #define UDMA_PSIL_CH_CPSW2_RX (0x4500U)
399 #define UDMA_PSIL_CH_SAUL0_RX (0x7504U)
400 #define UDMA_PSIL_CH_ICSS_G0_RX (0x4100U)
401 #define UDMA_PSIL_CH_ICSS_G1_RX (0x4200U)
403 #define UDMA_PSIL_CH_CPSW2_TX (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
404 #define UDMA_PSIL_CH_SAUL0_TX (0xf500U)
405 #define UDMA_PSIL_CH_ICSS_G0_TX (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
406 #define UDMA_PSIL_CH_ICSS_G1_TX (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
408 #define UDMA_PSIL_CH_CPSW2_TX_CNT (8U)
409 #define UDMA_PSIL_CH_SAUL0_TX_CNT (2U)
410 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (9U)
411 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (9U)
413 #define UDMA_PSIL_CH_CPSW2_RX_CNT (1U)
414 #define UDMA_PSIL_CH_SAUL0_RX_CNT (4U)
415 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (5U)
416 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (5U)
442 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)
443 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 1U)
444 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 2U)
445 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 3U)
446 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 4U)
447 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 5U)
448 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 6U)
449 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 7U)
450 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 8U)
451 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 9U)
452 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 10U)
453 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 11U)
454 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4480U + 0U)
455 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4480U + 1U)
456 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4480U + 2U)
457 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4480U + 3U)
458 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH0_RX (0x4480U + 4U)
459 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH1_RX (0x4480U + 5U)
460 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH2_RX (0x4480U + 6U)
461 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH3_RX (0x4480U + 7U)
465 #define UDMA_PDMA_CH_MAIN0_UART0_RX (0x4400 + 0U)
466 #define UDMA_PDMA_CH_MAIN0_UART1_RX (0x4400 + 1U)
467 #define UDMA_PDMA_CH_MAIN0_UART2_RX (0x4400 + 2U)
468 #define UDMA_PDMA_CH_MAIN0_UART3_RX (0x4400 + 3U)
469 #define UDMA_PDMA_CH_MAIN0_UART4_RX (0x4400 + 4U)
470 #define UDMA_PDMA_CH_MAIN0_UART5_RX (0x4400 + 5U)
471 #define UDMA_PDMA_CH_MAIN0_UART6_RX (0x4400 + 6U)
475 #define UDMA_PDMA_CH_MAIN0_MCASP0_RX (0x4500U + 0U)
476 #define UDMA_PDMA_CH_MAIN0_MCASP1_RX (0x4500U + 1U)
477 #define UDMA_PDMA_CH_MAIN0_MCASP2_RX (0x4500U + 2U)
478 #define UDMA_PDMA_CH_MAIN0_MCASP3_RX (0x4580U + 0U)
479 #define UDMA_PDMA_CH_MAIN0_MCASP4_RX (0x4580U + 1U)
483 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH0_RX (0x4100U + 0U)
484 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH1_RX (0x4100U + 1U)
485 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH2_RX (0x4100U + 2U)
486 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH3_RX (0x4100U + 3U)
487 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH4_RX (0x4100U + 4U)
488 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH5_RX (0x4100U + 5U)
489 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH6_RX (0x4100U + 6U)
490 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH7_RX (0x4100U + 7U)
491 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH8_RX (0x4100U + 8U)
492 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH9_RX (0x4100U + 9U)
493 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH10_RX (0x4100U + 10U)
494 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH11_RX (0x4100U + 11U)
495 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH12_RX (0x4100U + 12U)
496 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH13_RX (0x4100U + 13U)
497 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH14_RX (0x4100U + 14U)
498 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH15_RX (0x4100U + 15U)
499 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH16_RX (0x4100U + 16U)
500 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH17_RX (0x4100U + 17U)
501 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH18_RX (0x4100U + 18U)
502 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH19_RX (0x4100U + 19U)
503 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH20_RX (0x4100U + 20U)
504 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH21_RX (0x4100U + 21U)
505 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH22_RX (0x4100U + 22U)
506 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH23_RX (0x4100U + 23U)
507 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH24_RX (0x4100U + 24U)
508 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH25_RX (0x4100U + 25U)
509 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH26_RX (0x4100U + 26U)
510 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH27_RX (0x4100U + 27U)
511 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH28_RX (0x4100U + 28U)
512 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH29_RX (0x4100U + 29U)
513 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH30_RX (0x4100U + 30U)
514 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH31_RX (0x4100U + 31U)
519 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH0_RX (0x4180U + 0U)
520 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH1_RX (0x4180U + 1U)
521 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH2_RX (0x4180U + 2U)
522 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH3_RX (0x4180U + 3U)
523 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH4_RX (0x4180U + 4U)
524 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH5_RX (0x4180U + 5U)
525 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH6_RX (0x4180U + 6U)
526 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH7_RX (0x4180U + 7U)
527 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH8_RX (0x4180U + 8U)
528 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH9_RX (0x4180U + 9U)
529 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH10_RX (0x4180U + 10U)
530 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH11_RX (0x4180U + 11U)
531 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH12_RX (0x4180U + 12U)
532 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH13_RX (0x4180U + 13U)
533 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH14_RX (0x4180U + 14U)
534 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH15_RX (0x4180U + 15U)
535 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH16_RX (0x4180U + 16U)
536 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH17_RX (0x4180U + 17U)
537 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH18_RX (0x4180U + 18U)
538 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH19_RX (0x4180U + 19U)
539 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH20_RX (0x4180U + 20U)
540 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH21_RX (0x4180U + 21U)
541 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH22_RX (0x4180U + 22U)
542 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH23_RX (0x4180U + 23U)
543 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH24_RX (0x4180U + 24U)
544 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH25_RX (0x4180U + 25U)
545 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH26_RX (0x4180U + 26U)
546 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH27_RX (0x4180U + 27U)
547 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH28_RX (0x4180U + 28U)
548 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH29_RX (0x4180U + 29U)
549 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH30_RX (0x4180U + 30U)
550 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH31_RX (0x4180U + 31U)
566 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
567 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
568 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
569 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
570 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
571 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
572 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
573 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
574 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
575 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
576 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
577 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
578 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
579 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
580 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
581 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
585 #define UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
586 #define UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
587 #define UDMA_PDMA_CH_MAIN0_UART2_TX (UDMA_PDMA_CH_MAIN0_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
588 #define UDMA_PDMA_CH_MAIN0_UART3_TX (UDMA_PDMA_CH_MAIN0_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
589 #define UDMA_PDMA_CH_MAIN0_UART4_TX (UDMA_PDMA_CH_MAIN0_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
590 #define UDMA_PDMA_CH_MAIN0_UART5_TX (UDMA_PDMA_CH_MAIN0_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
591 #define UDMA_PDMA_CH_MAIN0_UART6_TX (UDMA_PDMA_CH_MAIN0_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
595 #define UDMA_PDMA_CH_MAIN0_MCASP0_TX (UDMA_PDMA_CH_MAIN0_MCASP0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
596 #define UDMA_PDMA_CH_MAIN0_MCASP1_TX (UDMA_PDMA_CH_MAIN0_MCASP1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
597 #define UDMA_PDMA_CH_MAIN0_MCASP2_TX (UDMA_PDMA_CH_MAIN0_MCASP2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
598 #define UDMA_PDMA_CH_MAIN0_MCASP3_TX (UDMA_PDMA_CH_MAIN0_MCASP3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
599 #define UDMA_PDMA_CH_MAIN0_MCASP4_TX (UDMA_PDMA_CH_MAIN0_MCASP4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
603 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH0_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
604 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH1_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
605 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH2_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
606 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH3_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
607 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH4_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
608 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH5_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
609 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH6_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
610 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH7_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH7_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
611 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH8_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH8_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
612 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH9_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH9_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
613 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH10_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH10_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
614 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH11_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH11_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
615 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH12_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH12_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
616 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH13_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH13_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
617 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH14_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH14_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
618 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH15_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH15_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
619 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH16_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH16_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
620 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH17_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH17_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
621 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH18_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH18_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
622 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH19_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH19_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
623 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH20_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH20_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
624 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH21_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH21_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
625 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH22_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH22_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
626 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH23_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH23_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
627 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH24_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH24_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
628 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH25_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH25_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
629 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH26_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH26_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
630 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH27_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH27_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
631 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH28_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH28_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
632 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH29_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH29_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
633 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH30_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH30_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
634 #define UDMA_PDMA_CH_MAIN0_AASRC0_CH31_TX (UDMA_PDMA_CH_MAIN0_AASRC0_CH31_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
636 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH0_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
637 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH1_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
638 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH2_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
639 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH3_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
640 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH4_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
641 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH5_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
642 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH6_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
643 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH7_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH7_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
644 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH8_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH8_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
645 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH9_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH9_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
646 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH10_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH10_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
647 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH11_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH11_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
648 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH12_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH12_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
649 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH13_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH13_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
650 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH14_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH14_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
651 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH15_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH15_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
652 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH16_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH16_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
653 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH17_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH17_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
654 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH18_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH18_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
655 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH19_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH19_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
656 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH20_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH20_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
657 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH21_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH21_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
658 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH22_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH22_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
659 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH23_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH23_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
660 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH24_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH24_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
661 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH25_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH25_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
662 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH26_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH26_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
663 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH27_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH27_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
664 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH28_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH28_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
665 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH29_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH29_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
666 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH30_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH30_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
667 #define UDMA_PDMA_CH_MAIN0_AASRC1_CH31_TX (UDMA_PDMA_CH_MAIN0_AASRC1_CH31_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
683 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (0x4400U + 0U)
684 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (0x4400U + 1U)
685 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (0x4400U + 2U)
686 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (0x4400U + 3U)
690 #define UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 4U)
691 #define UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 5U)
692 #define UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 6U)
693 #define UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 7U)
694 #define UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 8U)
698 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (0x4400U + 9U)
699 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (0x4400U + 10U)
700 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (0x4400U + 11U)
701 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (0x4400U + 12U)
702 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (0x4400U + 13U)
703 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (0x4400U + 14U)
707 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4400U + 15U)
708 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4400U + 16U)
724 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
725 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
726 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
727 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
731 #define UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
732 #define UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
733 #define UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
734 #define UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
735 #define UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
739 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
740 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
741 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
742 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
743 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
744 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
748 #define UDMA_C7X_CORE_INTR_OFFSET (52U)
750 #define UDMA_C7X_CORE_NUM_INTR (10U)
753 #define UDMA_VINT_CLEC_OFFSET (256U - 64)
void * Udma_defaultPhyToVirtFxnC7x(uint64_t phyAddr, uint32_t chNum, void *appData)
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint8_t Udma_isValidInstance(uint32_t instId)
Returns TRUE if the given UDMA Instance ID is valid for this SoC.
uint64_t Udma_defaultVirtToPhyFxnC7x(const void *virtAddr, uint32_t chNum, void *appData)