AM275 FreeRTOS SDK  11.01.00
AASRC Clock Zone Configuration

Introduction

This is AASRC clock zone related configuration parameters and APIs

Files

file  aasrc_clocking.h
 AASRC clocking related parameters and API.
 

Functions

int32_t AASRC_ClkZoneRxConfig (uint8_t clockZoneIdx, AASRC_Handle drvHandle)
 AASRC input clock zone configuration. More...
 
int32_t AASRC_ClkZoneTxConfig (uint8_t clockZoneIdx, AASRC_Handle drvHandle)
 AASRC output clock zone configuration. More...
 
int32_t AASRC_IsClockZoneRxSettled (AASRC_ChHandle chHandle, bool *isClkSettled)
 Check if the queried AASRC input clock zone is settled. More...
 
int32_t AASRC_IsClockZoneTxSettled (AASRC_ChHandle chHandle, bool *isClkSettled)
 Check if the queried AASRC output clock zone is settled. More...
 
int32_t AASRC_GetClkZoneRxFrequency (AASRC_ChHandle chHandle, float *clkFrequency)
 Reads AASRC input clock frequency for a given clock zone. More...
 
int32_t AASRC_GetClkZoneTxFrequency (AASRC_ChHandle chHandle, float *clkFrequency)
 Reads AASRC output clock frequency for a given clock zone. More...
 

Macros

#define AASRC_RXSYNC_PIN_COUNT   (4U)
 Maximum number of rxsync pins. More...
 
#define AASRC_TXSYNC_PIN_COUNT   (4U)
 Maximum number of txsync pins. More...
 
#define AASRC_INPUT_CLOCK_ZONE_COUNT   (4U)
 Maximum number of input and output clock zones. More...
 
#define AASRC_OUTPUT_CLOCK_ZONE_COUNT   (4U)
 
#define AASRC_INTERNAL_CLOCK_DIVISOR_MAX_VAL   (1U << 14U)
 Maximum number of input and output clock zones. More...
 
#define AASRC_AUDIO_CLK_FREQUENCY_MAX   (216U)
 Maximum supported audio frequency by AASRC. More...
 
#define AASRC_CLK_RATIO_MAX   (16U)
 Maximum clock ration supported by an AASRC channel. More...
 
#define AASRC_CLK_SRC_MAX_FOR_DIVIDER   (96U)
 Maximum clock ration supported by an AASRC channel. More...
 
#define AASRC_CLOCKZONE_CONTROL_REG_OFFSET   (0x00000080U)
 Clock Zone Control Register Offset. More...
 
#define AASRC_INPUT_CLOCKZONE_CONTROL(x)
 Find base address of Input Clock Zone 'x' Control Register. More...
 
#define AASRC_OUTPUT_CLOCKZONE_CONTROL(x)
 Find base address of Ouput Clock Zone 'x' Control Register. More...
 
#define AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET   (0x00000080U)
 Clock Zone Recovery Loop Register Offset. More...
 
#define AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_LO(x)
 Find base address of Input Clock Zone 'x' Recovery Loop Low Register
More...
 
#define AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_HI(x)
 Find base address of Input Clock Zone 'x' Recovery Loop High Register
More...
 
#define AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_LO(x)
 Find base address of Output Clock Zone 'x' Recovery Loop Low Register
More...
 
#define AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_HI(x)
 Find base address of Output Clock Zone 'x' Recovery Loop High Register
More...
 

RxSync Pins

AASRC IP Core RxSync Pins

#define AASRC_RXSYNC0_IDX   (0U)
 
#define AASRC_RXSYNC1_IDX   (1U)
 
#define AASRC_RXSYNC2_IDX   (2U)
 
#define AASRC_RXSYNC3_IDX   (3U)
 

TxSync Pins

AASRC IP Core TxSync Pins

#define AASRC_TXSYNC0_IDX   (0U)
 
#define AASRC_TXSYNC1_IDX   (1U)
 
#define AASRC_TXSYNC2_IDX   (2U)
 
#define AASRC_TXSYNC3_IDX   (3U)
 

Input Clock Zones

AASRC Input Clock Zones

#define AASRC_INPUT_CLOCK_ZONE0_IDX   (0U)
 
#define AASRC_INPUT_CLOCK_ZONE1_IDX   (1U)
 
#define AASRC_INPUT_CLOCK_ZONE2_IDX   (2U)
 
#define AASRC_INPUT_CLOCK_ZONE3_IDX   (3U)
 

Output Clock Zones

AASRC Output Clock Zones

#define AASRC_OUTPUT_CLOCK_ZONE0_IDX   (0U)
 
#define AASRC_OUTPUT_CLOCK_ZONE1_IDX   (1U)
 
#define AASRC_OUTPUT_CLOCK_ZONE2_IDX   (2U)
 
#define AASRC_OUTPUT_CLOCK_ZONE3_IDX   (3U)
 

Macro Definition Documentation

◆ AASRC_RXSYNC_PIN_COUNT

#define AASRC_RXSYNC_PIN_COUNT   (4U)

Maximum number of rxsync pins.

◆ AASRC_TXSYNC_PIN_COUNT

#define AASRC_TXSYNC_PIN_COUNT   (4U)

Maximum number of txsync pins.

◆ AASRC_RXSYNC0_IDX

#define AASRC_RXSYNC0_IDX   (0U)

◆ AASRC_RXSYNC1_IDX

#define AASRC_RXSYNC1_IDX   (1U)

◆ AASRC_RXSYNC2_IDX

#define AASRC_RXSYNC2_IDX   (2U)

◆ AASRC_RXSYNC3_IDX

#define AASRC_RXSYNC3_IDX   (3U)

◆ AASRC_TXSYNC0_IDX

#define AASRC_TXSYNC0_IDX   (0U)

◆ AASRC_TXSYNC1_IDX

#define AASRC_TXSYNC1_IDX   (1U)

◆ AASRC_TXSYNC2_IDX

#define AASRC_TXSYNC2_IDX   (2U)

◆ AASRC_TXSYNC3_IDX

#define AASRC_TXSYNC3_IDX   (3U)

◆ AASRC_INPUT_CLOCK_ZONE_COUNT

#define AASRC_INPUT_CLOCK_ZONE_COUNT   (4U)

Maximum number of input and output clock zones.

◆ AASRC_OUTPUT_CLOCK_ZONE_COUNT

#define AASRC_OUTPUT_CLOCK_ZONE_COUNT   (4U)

◆ AASRC_INPUT_CLOCK_ZONE0_IDX

#define AASRC_INPUT_CLOCK_ZONE0_IDX   (0U)

◆ AASRC_INPUT_CLOCK_ZONE1_IDX

#define AASRC_INPUT_CLOCK_ZONE1_IDX   (1U)

◆ AASRC_INPUT_CLOCK_ZONE2_IDX

#define AASRC_INPUT_CLOCK_ZONE2_IDX   (2U)

◆ AASRC_INPUT_CLOCK_ZONE3_IDX

#define AASRC_INPUT_CLOCK_ZONE3_IDX   (3U)

◆ AASRC_OUTPUT_CLOCK_ZONE0_IDX

#define AASRC_OUTPUT_CLOCK_ZONE0_IDX   (0U)

◆ AASRC_OUTPUT_CLOCK_ZONE1_IDX

#define AASRC_OUTPUT_CLOCK_ZONE1_IDX   (1U)

◆ AASRC_OUTPUT_CLOCK_ZONE2_IDX

#define AASRC_OUTPUT_CLOCK_ZONE2_IDX   (2U)

◆ AASRC_OUTPUT_CLOCK_ZONE3_IDX

#define AASRC_OUTPUT_CLOCK_ZONE3_IDX   (3U)

◆ AASRC_INTERNAL_CLOCK_DIVISOR_MAX_VAL

#define AASRC_INTERNAL_CLOCK_DIVISOR_MAX_VAL   (1U << 14U)

Maximum number of input and output clock zones.

◆ AASRC_AUDIO_CLK_FREQUENCY_MAX

#define AASRC_AUDIO_CLK_FREQUENCY_MAX   (216U)

Maximum supported audio frequency by AASRC.

◆ AASRC_CLK_RATIO_MAX

#define AASRC_CLK_RATIO_MAX   (16U)

Maximum clock ration supported by an AASRC channel.

◆ AASRC_CLK_SRC_MAX_FOR_DIVIDER

#define AASRC_CLK_SRC_MAX_FOR_DIVIDER   (96U)

Maximum clock ration supported by an AASRC channel.

◆ AASRC_CLOCKZONE_CONTROL_REG_OFFSET

#define AASRC_CLOCKZONE_CONTROL_REG_OFFSET   (0x00000080U)

Clock Zone Control Register Offset.

◆ AASRC_INPUT_CLOCKZONE_CONTROL

#define AASRC_INPUT_CLOCKZONE_CONTROL (   x)
Value:
((uint32_t) CSL_AASRC_CFG_INPUT_CLOCKZONE_CONTROL_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCKZONE_CONTROL_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Input Clock Zone 'x' Control Register.

◆ AASRC_OUTPUT_CLOCKZONE_CONTROL

#define AASRC_OUTPUT_CLOCKZONE_CONTROL (   x)
Value:
((uint32_t) CSL_AASRC_CFG_OUTPUT_CLOCKZONE_CONTROL_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCKZONE_CONTROL_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Ouput Clock Zone 'x' Control Register.

◆ AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET

#define AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET   (0x00000080U)

Clock Zone Recovery Loop Register Offset.

◆ AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_LO

#define AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_LO (   x)
Value:
((uint32_t) CSL_AASRC_CFG_INPUT_CLOCK_RECOVERY_LOOP_RATE_LO_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Input Clock Zone 'x' Recovery Loop Low Register

◆ AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_HI

#define AASRC_INPUT_CLOCK_RECOVERY_LOOP_RATE_HI (   x)
Value:
((uint32_t) CSL_AASRC_CFG_INPUT_CLOCK_RECOVERY_LOOP_RATE_HI_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Input Clock Zone 'x' Recovery Loop High Register

◆ AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_LO

#define AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_LO (   x)
Value:
((uint32_t) CSL_AASRC_CFG_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_LO_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Output Clock Zone 'x' Recovery Loop Low Register

◆ AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_HI

#define AASRC_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_HI (   x)
Value:
((uint32_t) CSL_AASRC_CFG_OUTPUT_CLOCK_RECOVERY_LOOP_RATE_HI_0 + \
(uint32_t) ((uint32_t) AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET * \
(uint32_t) (x)))

Find base address of Output Clock Zone 'x' Recovery Loop High Register

Function Documentation

◆ AASRC_ClkZoneRxConfig()

int32_t AASRC_ClkZoneRxConfig ( uint8_t  clockZoneIdx,
AASRC_Handle  drvHandle 
)

AASRC input clock zone configuration.

configure given input clock zone based on the parameters set on the AASRC_ClockZoneConfig structure. AASRC_ClkZoneHandle locates the clock zone.

Parameters
clockZoneIdx[IN] Input Clock Zone Index
drvHandleAASRC_Handle returned from AASRC_open()
Returns
AASRC_ErrorCodes

◆ AASRC_ClkZoneTxConfig()

int32_t AASRC_ClkZoneTxConfig ( uint8_t  clockZoneIdx,
AASRC_Handle  drvHandle 
)

AASRC output clock zone configuration.

configure given output clock zone based on the parameters set on the AASRC_ClockZoneConfig structure. AASRC_ClkZoneHandle locates the clock zone.

Parameters
clockZoneIdx[IN] Output Clock Zone Index
drvHandleAASRC_Handle returned from AASRC_open()
Returns
AASRC_ErrorCodes

◆ AASRC_IsClockZoneRxSettled()

int32_t AASRC_IsClockZoneRxSettled ( AASRC_ChHandle  chHandle,
bool *  isClkSettled 
)

Check if the queried AASRC input clock zone is settled.

Check the status of the settle flag for a given input clock zone. It is necessary to make sure that the input clock is settled before the input internal clock rate is measured using AASRC_GetClkZoneTxFrequency(). It is a good idea to make sure that both input and output clocks are settled before enabling the AASRC channel. AASRC_ClkZoneHandle locates the clock zone.

Parameters
chHandle[IN] channel handle returned from AASRC_chOpen()
isClkSettled* [OUT] returns "true" if clock is settled, false if not
Returns
AASRC_ErrorCodes

◆ AASRC_IsClockZoneTxSettled()

int32_t AASRC_IsClockZoneTxSettled ( AASRC_ChHandle  chHandle,
bool *  isClkSettled 
)

Check if the queried AASRC output clock zone is settled.

Check the status of the settle flag for a given output clock zone. It is necessary to make sure that the output clock is settled before the output internal clock rate is measured using AASRC_GetClkZoneTxFrequency(). It is a good idea to make sure that both input and output clocks are settled before enabling the AASRC channel. AASRC_ClkZoneHandle locates the clock zone.

Parameters
chHandle[IN] channel handle returned from AASRC_chOpen()
isClkSettled* [OUT] returns "true" if clock is settled, false if not
Returns
AASRC_ErrorCodes

◆ AASRC_GetClkZoneRxFrequency()

int32_t AASRC_GetClkZoneRxFrequency ( AASRC_ChHandle  chHandle,
float *  clkFrequency 
)

Reads AASRC input clock frequency for a given clock zone.

Precondition
required clkZonehandle is initialized by AASRC_ClkZoneRxConfig()

Reads the frequency (in KHz) for a given input clock zone. AASRC_ClkZoneHandle locates the clock zone.

Parameters
chHandle[IN] channel handle returned from AASRC_chOpen()
clkFrequency* [OUT] input clock zone frequency in KHz
See also
AASRC_ClkZoneRxConfig()
AASRC_IsClockZoneRxSettled()
Returns
AASRC_ErrorCodes

◆ AASRC_GetClkZoneTxFrequency()

int32_t AASRC_GetClkZoneTxFrequency ( AASRC_ChHandle  chHandle,
float *  clkFrequency 
)

Reads AASRC output clock frequency for a given clock zone.

Precondition
required clkZonehandle is initialized by AASRC_ClkZoneTxConfig()

Reads the frequency (in KHz) for a given output clock zone. AASRC_ClkZoneHandle locates the clock zone.

Parameters
chHandle[IN] channel handle returned from AASRC_chOpen()
clkFrequency* [OUT] output clock zone frequency in KHz
See also
AASRC_ClkZoneTxConfig()
AASRC_IsClockZoneTxSettled()
Returns
AASRC_ErrorCodes
AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET
#define AASRC_CLOCK_RECOVERY_LOOP_RATE_REG_OFFSET
Clock Zone Recovery Loop Register Offset.
Definition: aasrc_clocking.h:155
AASRC_CLOCKZONE_CONTROL_REG_OFFSET
#define AASRC_CLOCKZONE_CONTROL_REG_OFFSET
Clock Zone Control Register Offset.
Definition: aasrc_clocking.h:144