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AM275 FreeRTOS SDK
11.00.00
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73 #define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
75 #define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
77 #define UDMA_INST_ID_START (UDMA_INST_ID_2)
79 #define UDMA_INST_ID_MAX (UDMA_INST_ID_3)
81 #define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
93 #define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
96 #define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
98 #define UDMA_SOC_CFG_UDMAP_PRESENT (0U)
101 #define UDMA_SOC_CFG_PROXY_PRESENT (0U)
104 #define UDMA_SOC_CFG_CLEC_PRESENT (0U)
107 #define UDMA_SOC_CFG_RA_NORMAL_PRESENT (0U)
110 #define UDMA_SOC_CFG_RING_MON_PRESENT (0U)
113 #define UDMA_SOC_CFG_APPLY_RING_WORKAROUND (0U)
126 #define UDMA_TX_UHC_CHANS_FDEPTH (0U)
128 #define UDMA_TX_HC_CHANS_FDEPTH (0U)
130 #define UDMA_TX_CHANS_FDEPTH (192U)
142 #define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
144 #define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
146 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
148 #define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
152 #define UDMA_NUM_MAPPED_TX_GROUP (4U)
161 #define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
162 #define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
163 #define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
164 #define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
168 #define UDMA_NUM_MAPPED_RX_GROUP (4U)
177 #define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
178 #define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
179 #define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
180 #define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
191 #define UDMA_UTC_TYPE_DRU (0U)
192 #define UDMA_UTC_TYPE_DRU_VHWA (1U)
194 #define UDMA_DEFAULT_UTC_CH_BUS_PRIORITY (4U)
196 #define UDMA_DEFAULT_UTC_CH_BUS_QOS (4U)
198 #define UDMA_DEFAULT_UTC_CH_BUS_ORDERID (0U)
200 #define CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET (0x8000U | 0x4820U)
202 #define UDMA_DEFAULT_UTC_CH_DMA_PRIORITY \
203 (TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
206 #define UDMA_DEFAULT_UTC_DRU_QUEUE_ID (CSL_DRU_QUEUE_ID_3)
209 #define UDMA_NUM_UTC_INSTANCE (2U)
220 #define UDMA_UTC_ID_MSMC_DRU0 (UDMA_UTC_ID0)
221 #define UDMA_UTC_ID_VPAC_TC0 (UDMA_UTC_ID1)
225 #define UDMA_UTC_START_CH_DRU0 (0U)
227 #define UDMA_UTC_NUM_CH_DRU0 (32U)
229 #define UDMA_UTC_START_THREAD_ID_DRU0 (0x8000U | 0x4800U)
232 #define UDMA_UTC_START_CH_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_OFFSET - CSL_PSILCFG_DMSS_MAIN_MSMC0_PSILS_THREAD_OFFSET)
234 #define UDMA_UTC_NUM_CH_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILS_THREAD_CNT)
236 #define UDMA_UTC_START_THREAD_ID_VPAC_TC0 (CSL_PSILCFG_DMSS_MAIN_VPAC_TC0_CC_PSILD_THREAD_OFFSET)
239 #define UDMA_UTC_BASE_DRU0 (CSL_C7X256V0_DRU_BASE)
240 #define UDMA_UTC_BASE_DRU1 (CSL_C7X256V1_DRU_BASE)
255 #define UDMA_CORE_ID_MPU1_0 (0U)
256 #define UDMA_CORE_ID_MCU2_0 (1U)
257 #define UDMA_CORE_ID_MCU2_1 (2U)
258 #define UDMA_CORE_ID_MCU1_0 (3U)
259 #define UDMA_CORE_ID_MCU1_1 (4U)
261 #define UDMA_NUM_CORE (5U)
280 #define UDMA_DRU_CORE_ID_MPU1_0 (CSL_DRU_CORE_ID_2)
281 #define UDMA_DRU_CORE_ID_MCU2_0 (CSL_DRU_CORE_ID_2)
282 #define UDMA_DRU_CORE_ID_MCU2_1 (CSL_DRU_CORE_ID_2)
283 #define UDMA_DRU_CORE_ID_MCU3_0 (CSL_DRU_CORE_ID_2)
284 #define UDMA_DRU_CORE_ID_MCU3_1 (CSL_DRU_CORE_ID_2)
285 #define UDMA_DRU_CORE_ID_C7X_1 (CSL_DRU_CORE_ID_0)
286 #define UDMA_DRU_CORE_ID_C66X_1 (CSL_DRU_CORE_ID_1)
287 #define UDMA_DRU_CORE_ID_C66X_2 (CSL_DRU_CORE_ID_2)
288 #define UDMA_DRU_CORE_ID_MCU1_0 (CSL_DRU_CORE_ID_2)
289 #define UDMA_DRU_CORE_ID_MCU1_1 (CSL_DRU_CORE_ID_2)
302 #define UDMA_RM_RES_ID_BC_UHC (0U)
304 #define UDMA_RM_RES_ID_BC_HC (1U)
306 #define UDMA_RM_RES_ID_BC (2U)
308 #define UDMA_RM_RES_ID_TX_UHC (3U)
310 #define UDMA_RM_RES_ID_TX_HC (4U)
312 #define UDMA_RM_RES_ID_TX (5U)
314 #define UDMA_RM_RES_ID_RX_UHC (6U)
316 #define UDMA_RM_RES_ID_RX_HC (7U)
318 #define UDMA_RM_RES_ID_RX (8U)
320 #define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
322 #define UDMA_RM_RES_ID_VINTR (10U)
324 #define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
326 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
328 #define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
330 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
332 #define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
334 #define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
336 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
338 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
340 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
342 #define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
344 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
346 #define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
348 #define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
350 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
352 #define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
354 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
356 #define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
358 #define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
360 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
362 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
364 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
366 #define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
368 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
370 #define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
372 #define UDMA_RM_NUM_BCDMA_RES (11U)
374 #define UDMA_RM_NUM_PKTDMA_RES (35U)
376 #define UDMA_RM_NUM_RES (35U)
381 #define UDMA_RM_NUM_SHARED_RES (2U)
384 #define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
387 #define UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
398 #define UDMA_PSIL_CH_CPSW2_RX (0x4500U)
399 #define UDMA_PSIL_CH_SAUL0_RX (0x7504U)
400 #define UDMA_PSIL_CH_ICSS_G0_RX (0x4100U)
401 #define UDMA_PSIL_CH_ICSS_G1_RX (0x4200U)
403 #define UDMA_PSIL_CH_CPSW2_TX (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
404 #define UDMA_PSIL_CH_SAUL0_TX (0xf500U)
405 #define UDMA_PSIL_CH_ICSS_G0_TX (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
406 #define UDMA_PSIL_CH_ICSS_G1_TX (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
408 #define UDMA_PSIL_CH_CPSW2_TX_CNT (8U)
409 #define UDMA_PSIL_CH_SAUL0_TX_CNT (2U)
410 #define UDMA_PSIL_CH_ICSS_G0_TX_CNT (9U)
411 #define UDMA_PSIL_CH_ICSS_G1_TX_CNT (9U)
413 #define UDMA_PSIL_CH_CPSW2_RX_CNT (1U)
414 #define UDMA_PSIL_CH_SAUL0_RX_CNT (4U)
415 #define UDMA_PSIL_CH_ICSS_G0_RX_CNT (5U)
416 #define UDMA_PSIL_CH_ICSS_G1_RX_CNT (5U)
442 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)
443 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 1U)
444 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 2U)
445 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 3U)
446 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 4U)
447 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 5U)
448 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 6U)
449 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 7U)
450 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 8U)
451 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 9U)
452 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 10U)
453 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 11U)
454 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4480U + 0U)
455 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4480U + 1U)
456 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4480U + 2U)
457 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4480U + 3U)
458 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH0_RX (0x4480U + 4U)
459 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH1_RX (0x4480U + 5U)
460 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH2_RX (0x4480U + 6U)
461 #define UDMA_PDMA_CH_MAIN0_MCSPI4_CH3_RX (0x4480U + 7U)
465 #define UDMA_PDMA_CH_MAIN0_UART0_RX (0x4400 + 0U)
466 #define UDMA_PDMA_CH_MAIN0_UART1_RX (0x4400 + 1U)
467 #define UDMA_PDMA_CH_MAIN0_UART2_RX (0x4400 + 2U)
468 #define UDMA_PDMA_CH_MAIN0_UART3_RX (0x4400 + 3U)
469 #define UDMA_PDMA_CH_MAIN0_UART4_RX (0x4400 + 4U)
470 #define UDMA_PDMA_CH_MAIN0_UART5_RX (0x4400 + 5U)
471 #define UDMA_PDMA_CH_MAIN0_UART6_RX (0x4400 + 6U)
475 #define UDMA_PDMA_CH_MAIN0_MCASP0_RX (0x4500U + 0U)
476 #define UDMA_PDMA_CH_MAIN0_MCASP1_RX (0x4500U + 1U)
477 #define UDMA_PDMA_CH_MAIN0_MCASP2_RX (0x4500U + 2U)
478 #define UDMA_PDMA_CH_MAIN0_MCASP3_RX (0x4580U + 0U)
479 #define UDMA_PDMA_CH_MAIN0_MCASP4_RX (0x4580U + 1U)
495 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
496 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
497 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
498 #define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
499 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
500 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
501 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
502 #define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
503 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
504 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
505 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
506 #define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
507 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
508 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
509 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
510 #define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
514 #define UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
515 #define UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
516 #define UDMA_PDMA_CH_MAIN0_UART2_TX (UDMA_PDMA_CH_MAIN0_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
517 #define UDMA_PDMA_CH_MAIN0_UART3_TX (UDMA_PDMA_CH_MAIN0_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
518 #define UDMA_PDMA_CH_MAIN0_UART4_TX (UDMA_PDMA_CH_MAIN0_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
519 #define UDMA_PDMA_CH_MAIN0_UART5_TX (UDMA_PDMA_CH_MAIN0_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
520 #define UDMA_PDMA_CH_MAIN0_UART6_TX (UDMA_PDMA_CH_MAIN0_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
524 #define UDMA_PDMA_CH_MAIN0_MCASP0_TX (UDMA_PDMA_CH_MAIN0_MCASP0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
525 #define UDMA_PDMA_CH_MAIN0_MCASP1_TX (UDMA_PDMA_CH_MAIN0_MCASP1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
526 #define UDMA_PDMA_CH_MAIN0_MCASP2_TX (UDMA_PDMA_CH_MAIN0_MCASP2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
527 #define UDMA_PDMA_CH_MAIN0_MCASP3_TX (UDMA_PDMA_CH_MAIN0_MCASP3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
528 #define UDMA_PDMA_CH_MAIN0_MCASP4_TX (UDMA_PDMA_CH_MAIN0_MCASP4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
544 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (0x4400U + 0U)
545 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (0x4400U + 1U)
546 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (0x4400U + 2U)
547 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (0x4400U + 3U)
551 #define UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 4U)
552 #define UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 5U)
553 #define UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 6U)
554 #define UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 7U)
555 #define UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 8U)
559 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (0x4400U + 9U)
560 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (0x4400U + 10U)
561 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (0x4400U + 11U)
562 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (0x4400U + 12U)
563 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (0x4400U + 13U)
564 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (0x4400U + 14U)
568 #define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4400U + 15U)
569 #define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4400U + 16U)
585 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
586 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
587 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
588 #define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
592 #define UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
593 #define UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
594 #define UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
595 #define UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
596 #define UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
600 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
601 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
602 #define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
603 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
604 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
605 #define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
609 #define UDMA_C7X_CORE_INTR_OFFSET (52U)
611 #define UDMA_C7X_CORE_NUM_INTR (10U)
614 #define UDMA_VINT_CLEC_OFFSET (256U - 64)
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
uint8_t Udma_isValidInstance(uint32_t instId)
Returns TRUE if the given UDMA Instance ID is valid for this SoC.
uint64_t Udma_defaultVirtToPhyFxnC7x(const void *virtAddr, uint32_t chNum, void *appData)
void * Udma_defaultPhyToVirtFxnC7x(uint64_t phyAddr, uint32_t chNum, void *appData)