41 #ifndef INCLUDE_SDL_ECC_SOC_H_
42 #define INCLUDE_SDL_ECC_SOC_H_
47 #include <sdl/ecc/sdl_ip_ecc.h>
48 #include <sdl/include/sdl_types.h>
49 #include <sdl/esm/soc/am275x/sdl_esm_core.h>
52 #include <sdl/include/am275x/sdlr_soc_ecc_aggr.h>
53 #include <sdl/include/am275x/sdlr_intr_esm0.h>
54 #include <sdl/include/am275x/sdlr_intr_wkup_esm0.h>
55 #include <sdl/include/am275x/sdlr_soc_baseaddress.h>
60 #define SDL_C7X256V1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
61 #define SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (0U)
62 #define SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
63 #define SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_RAM_IDS_TOTAL_ENTRIES (1U)
64 #define SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_RAM_IDS_TOTAL_ENTRIES (1U)
65 #define SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
66 #define SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
67 #define SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (15U)
68 #define SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
69 #define SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
70 #define SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
71 #define SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (16U)
72 #define SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (12U)
73 #define SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
74 #define SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
75 #define SDL_C7X256V0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
76 #define SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
77 #define SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
78 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
79 #define SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_RAM_IDS_TOTAL_ENTRIES (1U)
80 #define SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
81 #define SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
83 #define SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
84 #define SDL_SMS0_SMS_HSM_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
85 #define SDL_SMS0_SMS_TIFS_ECC_RAM_IDS_TOTAL_ENTRIES (2U)
86 #define SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
87 #define SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
88 #define SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
89 #define SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
90 #define SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
91 #define SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
92 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
93 #define SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (2U)
94 #define SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (30U)
95 #define SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (30U)
96 #define SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (30U)
97 #define SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (30U)
98 #define SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
99 #define SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
100 #define SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
101 #define SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
102 #define SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_RAM_IDS_TOTAL_ENTRIES (4U)
103 #define SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
104 #define SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
105 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
106 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
107 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
108 #define SDL_DMASS0_ECC_AGGR_0_RAM_IDS_TOTAL_ENTRIES (28U)
109 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
110 #define SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_RAM_IDS_TOTAL_ENTRIES (1U)
111 #define SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_RAM_IDS_TOTAL_ENTRIES (1U)
112 #define SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
113 #define SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
114 #define SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (0U)
115 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (55U)
122 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_REGS_BASE)),
123 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_REGS_BASE)),
146 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_FSS0_OSPI0_OSPI_CFG_VBUSP_OSPI_WRAP_ECC_AGGR_VBP_BASE)),
169 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_REGS_BASE)),
170 ((
SDL_ecc_aggrRegs *)((uintptr_t)SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_REGS_BASE)),
182 { SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
183 SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
184 SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)
false) },
194 { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
195 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
196 { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
197 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
198 { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
199 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
200 { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
201 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
211 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
212 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
213 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
214 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
215 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
216 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
226 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
227 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
228 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
229 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
230 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
231 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
232 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
233 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
234 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
235 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
236 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
237 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
238 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
239 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
240 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
241 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
242 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
243 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
244 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
245 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
246 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
247 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
248 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
249 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
250 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
251 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
252 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
253 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
254 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
255 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
256 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
257 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
258 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
259 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
260 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
261 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
262 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
263 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
264 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
265 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
266 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
267 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
268 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
269 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
270 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
271 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
272 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
273 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
274 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
275 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
276 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
277 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
278 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
279 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
280 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
281 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
282 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
283 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
284 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
285 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
286 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
287 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
288 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
289 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
290 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
291 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
292 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
293 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
294 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
295 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
296 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
297 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
298 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
299 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
300 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
301 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
302 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
303 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
304 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
305 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
306 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
307 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
308 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
309 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
310 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
311 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
312 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
313 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
314 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
315 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
316 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
317 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
318 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
319 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
320 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
321 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
322 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
323 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
324 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
325 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
326 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
327 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
328 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
329 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
330 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
331 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
332 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
333 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
334 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
335 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
336 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
337 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
338 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
339 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
340 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
341 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
342 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
343 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
344 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
345 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
346 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
347 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
348 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
349 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
350 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
351 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
352 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
353 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
354 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
355 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
356 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
357 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
358 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
359 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
360 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
361 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
362 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
363 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
364 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
365 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
366 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
367 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
368 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
369 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
370 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
371 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
372 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
373 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
374 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
375 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
376 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
377 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
378 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
379 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
380 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
381 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
382 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
383 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
384 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
385 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
386 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
387 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
388 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
389 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
390 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
391 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
392 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
393 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
394 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
395 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
396 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
397 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
398 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
399 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
400 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
401 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
402 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
403 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
404 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
405 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
406 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
407 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
408 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
409 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
410 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
411 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
412 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
413 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
414 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
415 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
416 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
417 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
418 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
419 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
420 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
421 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
422 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
423 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
424 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
425 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
426 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
427 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
428 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
429 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
430 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
431 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
432 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
433 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
434 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
435 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
436 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
437 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
438 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
439 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
440 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
441 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
442 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
443 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
444 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
445 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
446 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
447 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
448 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
449 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
450 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
451 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
452 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
453 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
454 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
455 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
456 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
457 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
458 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
459 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
460 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
461 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
462 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
463 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
464 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
465 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
466 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
467 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
468 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
469 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
470 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
471 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
472 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
473 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
474 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
475 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
476 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
477 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
478 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
479 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
480 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
481 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
482 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
483 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
484 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
485 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
486 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
487 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
488 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
489 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
490 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
491 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
492 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
493 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
494 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
495 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
496 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
497 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
498 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
499 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
500 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
501 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
502 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
503 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
504 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
505 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
506 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
507 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
508 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
509 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
510 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
511 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
512 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
513 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
514 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
515 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
516 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
517 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
518 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
519 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
520 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
521 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
522 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
523 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
524 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
525 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
526 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
527 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
528 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
529 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
530 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
531 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
532 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
533 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
534 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
535 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
536 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
537 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
538 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
539 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
540 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
541 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
542 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
543 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
544 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
545 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
546 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
547 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
548 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
549 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
550 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
551 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
552 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
553 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
554 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
555 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
556 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
557 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
558 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
559 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
560 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
561 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
571 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
572 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
573 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
574 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
575 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
576 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
577 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
578 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
588 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
589 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
599 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
600 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
610 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
611 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
612 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
613 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
614 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
615 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
616 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
617 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
618 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
619 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
620 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
621 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
622 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
623 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
624 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
625 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
626 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
627 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
628 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
629 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
630 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
631 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
632 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
633 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
634 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
635 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
636 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
637 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
638 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
639 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
640 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
641 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
651 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
652 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
653 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
654 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
655 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
656 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
657 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
658 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
659 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
660 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
661 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
662 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
672 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
673 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_0_WIDTH },
674 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
675 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_1_WIDTH },
676 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
677 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_2_WIDTH },
678 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
679 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_3_WIDTH },
680 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
681 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_4_WIDTH },
682 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
683 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_5_WIDTH },
684 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
685 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_6_WIDTH },
686 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
687 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_7_WIDTH },
688 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
689 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_8_WIDTH },
690 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
691 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_9_WIDTH },
692 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
693 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_10_WIDTH },
694 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
695 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_11_WIDTH },
696 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
697 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_12_WIDTH },
698 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
699 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_13_WIDTH },
700 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
701 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_14_WIDTH },
702 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
703 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_15_WIDTH },
704 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
705 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_16_WIDTH },
706 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
707 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_17_WIDTH },
708 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
709 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_18_WIDTH },
710 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
711 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_19_WIDTH },
712 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
713 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_20_WIDTH },
714 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
715 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_21_WIDTH },
716 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
717 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_22_WIDTH },
718 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
719 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_23_WIDTH },
720 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
721 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_24_WIDTH },
722 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
723 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_25_WIDTH },
724 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
725 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_26_WIDTH },
726 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
727 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_27_WIDTH },
728 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
729 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_28_WIDTH },
730 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
731 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_29_WIDTH },
732 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
733 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_30_WIDTH },
734 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
735 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_31_WIDTH },
736 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
737 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_32_WIDTH },
738 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
739 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_33_WIDTH },
740 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
741 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_34_WIDTH },
742 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
743 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_35_WIDTH },
744 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
745 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_36_WIDTH },
746 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
747 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_37_WIDTH },
748 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
749 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_38_WIDTH },
750 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
751 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_39_WIDTH },
752 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
753 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_40_WIDTH },
754 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
755 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_41_WIDTH },
756 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
757 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_42_WIDTH },
758 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
759 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_43_WIDTH },
760 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
761 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_44_WIDTH },
762 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
763 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_45_WIDTH },
764 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
765 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_46_WIDTH },
766 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
767 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_47_WIDTH },
768 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
769 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_48_WIDTH },
770 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
771 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_49_WIDTH },
772 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
773 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_50_WIDTH },
774 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
775 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_51_WIDTH },
776 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
777 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_52_WIDTH },
778 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
779 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_53_WIDTH },
780 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
781 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_54_WIDTH },
782 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
783 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_55_WIDTH },
784 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
785 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_56_WIDTH },
786 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
787 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_57_WIDTH },
788 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
789 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_58_WIDTH },
790 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
791 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_59_WIDTH },
792 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
793 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_60_WIDTH },
794 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
795 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_61_WIDTH },
796 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
797 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_62_WIDTH },
798 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
799 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_63_WIDTH },
800 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
801 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_64_WIDTH },
802 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
803 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_65_WIDTH },
804 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
805 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_66_WIDTH },
806 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
807 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_67_WIDTH },
808 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
809 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_68_WIDTH },
810 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
811 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_69_WIDTH },
812 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
813 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_70_WIDTH },
814 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
815 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_71_WIDTH },
816 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
817 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_72_WIDTH },
818 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
819 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_73_WIDTH },
820 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
821 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_74_WIDTH },
822 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
823 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_75_WIDTH },
824 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
825 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_76_WIDTH },
826 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
827 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_77_WIDTH },
828 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
829 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_78_WIDTH },
830 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
831 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_79_WIDTH },
832 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
833 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_80_WIDTH },
834 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
835 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_81_WIDTH },
836 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
837 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_82_WIDTH },
838 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
839 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_83_WIDTH },
840 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
841 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_84_WIDTH },
842 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
843 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_85_WIDTH },
844 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
845 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_86_WIDTH },
846 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
847 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_87_WIDTH },
848 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
849 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_88_WIDTH },
850 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
851 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_89_WIDTH },
852 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
853 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_90_WIDTH },
854 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
855 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_91_WIDTH },
856 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
857 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_92_WIDTH },
858 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
859 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_93_WIDTH },
860 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
861 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_94_WIDTH },
862 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
863 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_95_WIDTH },
864 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
865 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_96_WIDTH },
866 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
867 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_97_WIDTH },
868 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
869 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_98_WIDTH },
870 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
871 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_99_WIDTH },
872 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
873 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_100_WIDTH },
874 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
875 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_101_WIDTH },
876 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
877 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_102_WIDTH },
878 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
879 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_103_WIDTH },
880 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
881 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_104_WIDTH },
882 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
883 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_105_WIDTH },
884 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
885 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_106_WIDTH },
886 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
887 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_107_WIDTH },
888 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
889 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_108_WIDTH },
890 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
891 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_109_WIDTH },
892 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
893 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_110_WIDTH },
894 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
895 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_111_WIDTH },
896 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
897 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_112_WIDTH },
898 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
899 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_113_WIDTH },
900 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
901 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_114_WIDTH },
902 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
903 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_115_WIDTH },
904 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
905 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_116_WIDTH },
906 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
907 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_117_WIDTH },
908 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
909 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_118_WIDTH },
910 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
911 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_119_WIDTH },
912 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
913 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_120_WIDTH },
914 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
915 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_121_WIDTH },
916 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
917 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_122_WIDTH },
918 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
919 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_123_WIDTH },
920 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
921 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_124_WIDTH },
922 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
923 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_125_WIDTH },
924 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
925 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_126_WIDTH },
926 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
927 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_127_WIDTH },
928 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
929 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_128_WIDTH },
930 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
931 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_129_WIDTH },
932 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
933 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_130_WIDTH },
934 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
935 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_131_WIDTH },
936 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
937 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_132_WIDTH },
938 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
939 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_133_WIDTH },
940 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
941 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_134_WIDTH },
942 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
943 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_135_WIDTH },
944 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
945 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_136_WIDTH },
946 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
947 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_137_WIDTH },
948 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
949 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_138_WIDTH },
950 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
951 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_139_WIDTH },
952 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
953 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_140_WIDTH },
954 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
955 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_141_WIDTH },
956 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
957 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_142_WIDTH },
958 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
959 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_143_WIDTH },
960 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
961 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_144_WIDTH },
962 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
963 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_145_WIDTH },
964 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
965 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_146_WIDTH },
966 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
967 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_147_WIDTH },
968 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
969 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_148_WIDTH },
970 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
971 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_149_WIDTH },
972 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
973 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_150_WIDTH },
974 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
975 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_151_WIDTH },
976 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
977 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_152_WIDTH },
978 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
979 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_153_WIDTH },
980 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
981 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_154_WIDTH },
982 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
983 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_155_WIDTH },
984 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
985 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_156_WIDTH },
986 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
987 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_157_WIDTH },
988 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
989 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_158_WIDTH },
990 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
991 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_159_WIDTH },
992 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
993 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_160_WIDTH },
994 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
995 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_161_WIDTH },
996 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
997 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_162_WIDTH },
998 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
999 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_163_WIDTH },
1000 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
1001 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_164_WIDTH },
1002 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
1003 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_165_WIDTH },
1004 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
1005 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_166_WIDTH },
1006 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
1007 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_167_WIDTH },
1008 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
1009 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_168_WIDTH },
1010 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
1011 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_169_WIDTH },
1012 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
1013 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_GROUP_170_WIDTH },
1023 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1024 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
1025 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1026 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
1027 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1028 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
1038 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
1039 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
1040 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
1041 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
1042 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
1043 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
1044 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
1045 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
1046 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
1047 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
1048 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
1049 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
1050 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
1051 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
1052 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
1053 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
1054 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
1055 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
1056 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
1057 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
1058 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
1059 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
1060 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
1061 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
1062 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
1063 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
1064 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
1065 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
1066 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
1067 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
1068 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
1069 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
1070 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
1071 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
1072 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
1073 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
1074 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
1075 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
1076 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
1077 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
1078 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
1079 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
1080 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
1081 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
1082 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
1083 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
1084 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
1085 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
1086 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
1087 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
1088 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
1089 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
1090 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
1091 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
1092 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
1093 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
1094 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
1095 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
1096 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
1097 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
1098 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
1099 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
1100 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
1101 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
1102 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
1103 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
1104 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
1105 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
1106 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
1107 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
1108 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
1109 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
1110 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
1111 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
1112 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
1113 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
1114 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
1115 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
1116 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
1117 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
1118 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
1119 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
1120 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
1121 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
1122 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
1123 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
1124 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
1125 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
1126 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
1127 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
1128 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
1129 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
1130 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
1131 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
1132 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
1133 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
1134 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
1135 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
1136 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
1137 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
1146 { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID, 0x00000000u,
1147 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_SIZE, 4u,
1148 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ROW_WIDTH, ((bool)
true) },
1157 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
1158 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
1159 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)
false) },
1169 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1170 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1171 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1172 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1173 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1174 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1175 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1176 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1177 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1178 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1179 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1180 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1181 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1182 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1183 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1184 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1185 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1186 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1187 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1188 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1189 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1190 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1191 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1192 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1193 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1194 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1195 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1196 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1197 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1198 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1199 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1200 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1201 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1202 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1203 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1204 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1205 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1206 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1207 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1208 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1209 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1210 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1211 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1212 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1213 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1214 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1215 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1216 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1217 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1218 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1219 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1220 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1221 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1222 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1223 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1224 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1225 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1226 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1227 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1228 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1229 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1230 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1231 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1232 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1233 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1234 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1235 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1236 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1237 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1238 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1239 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1240 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1241 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1242 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1243 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1244 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1245 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1246 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1247 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1248 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1249 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1250 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1251 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1252 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1253 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1254 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1255 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1256 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1257 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1258 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1259 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1260 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1261 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1262 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1263 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1264 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1265 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1266 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1267 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1268 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1269 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1270 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1271 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1272 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1273 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1274 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1275 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1276 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1277 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1278 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1279 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1280 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1281 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1282 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1283 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1284 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1285 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1286 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1287 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1288 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1289 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1290 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1291 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1292 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1293 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1294 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1295 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1296 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1297 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1298 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1308 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1309 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1310 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1311 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1312 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1313 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1314 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1315 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1316 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1317 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1318 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1319 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1320 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1321 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1322 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1323 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1324 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1325 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1326 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1327 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1328 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1329 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1330 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1331 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1332 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1333 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1334 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1335 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1336 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1337 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1347 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1348 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1349 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1350 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1351 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1352 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1353 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1354 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1355 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1356 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1357 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1358 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1359 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1360 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1361 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1362 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1363 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1364 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1365 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1366 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1367 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1368 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1369 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1370 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1371 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1372 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1373 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1374 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1375 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1376 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1377 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1378 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1379 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1380 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1381 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1382 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1383 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1384 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1385 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1386 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1387 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1388 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1389 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1390 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1391 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1392 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1393 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1394 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1395 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1396 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1397 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1398 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1399 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1400 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1401 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1402 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1403 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1404 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1405 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1406 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1407 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1408 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1409 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1410 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1411 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1412 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1413 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1414 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1415 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1416 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1417 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1418 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1419 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1420 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1421 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1422 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1423 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1424 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1425 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1426 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1427 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1428 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1429 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1430 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1431 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1432 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1433 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1434 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1435 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1436 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1437 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1438 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1439 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1440 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1441 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1442 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1443 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1444 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1445 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1446 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1447 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1448 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1449 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1450 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1451 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1452 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1453 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1454 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1455 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1456 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1457 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1458 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1459 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1460 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1461 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1462 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1463 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1464 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1465 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1466 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1467 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1468 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1469 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1470 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1471 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1472 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1473 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1474 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1475 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1476 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1477 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1478 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1479 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1480 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1481 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1482 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1483 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1484 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1485 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1486 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1487 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1488 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1489 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1490 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1491 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1492 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1493 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1494 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1495 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1496 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1497 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1498 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1499 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1500 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
1501 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
1502 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
1512 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1513 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1514 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1515 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1516 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1517 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1518 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1519 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1520 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1521 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1522 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1523 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1524 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1525 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1526 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1527 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1528 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1529 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1530 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1531 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1532 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1533 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1534 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1535 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1536 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1537 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1538 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1539 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1540 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1541 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1542 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1543 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1544 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1545 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1546 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1547 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1548 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1549 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1550 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1551 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1552 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1553 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1554 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1555 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1556 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1557 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1558 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1559 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1560 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1561 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1562 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1563 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1564 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1565 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1566 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1567 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1568 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1569 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1570 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1571 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1572 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1573 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1574 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1575 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1576 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1577 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1578 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1579 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1580 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1581 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1582 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1583 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1584 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1585 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1586 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1587 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1588 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1589 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1590 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1591 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1592 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1593 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1594 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1595 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1596 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1597 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1598 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1599 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1600 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1601 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1602 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1603 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1604 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1605 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1606 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1607 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1608 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1609 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1610 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1611 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1612 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1613 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1614 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1615 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1616 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1617 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1618 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1619 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1620 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1621 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1622 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1623 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1624 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1625 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1626 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1627 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1628 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1629 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1630 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1631 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1632 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1633 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1634 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1635 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1636 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1637 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1638 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1639 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1640 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1641 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1642 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1643 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1644 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1645 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1646 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1647 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1648 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1649 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1650 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1651 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1652 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1653 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1654 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1655 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1656 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1657 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1658 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1659 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1660 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1661 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1662 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1663 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1664 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1665 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
1675 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1676 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1677 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1678 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1679 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1680 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1681 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1682 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1683 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1684 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1685 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1686 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1687 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1688 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1689 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1690 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1691 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1692 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1693 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1694 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1695 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1696 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1697 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1698 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1699 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1700 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1701 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1702 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1703 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1704 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1705 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1706 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1707 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1708 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1709 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1710 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1711 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1712 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1713 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1714 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1715 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1716 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1717 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1718 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1719 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1720 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1721 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1722 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1723 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1724 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1725 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1726 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1727 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1728 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1729 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1730 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1731 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1732 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1733 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1734 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1735 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1736 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1737 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1738 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1739 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1740 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1741 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1742 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1743 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1744 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1745 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1746 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1747 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1748 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1749 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1750 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1751 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1752 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1753 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1754 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1755 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1756 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1757 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1758 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1759 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1760 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1761 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1762 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1763 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1764 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1765 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1766 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1767 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1768 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1769 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1770 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1771 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1772 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1773 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1774 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1775 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1776 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1777 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1778 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1779 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1780 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1781 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1782 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1783 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1784 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1785 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1786 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1787 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1788 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1789 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1790 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1791 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1792 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1793 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1794 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1795 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1796 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1797 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1798 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1799 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1800 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1801 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1802 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1803 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1804 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1805 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1806 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1807 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1808 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1809 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1810 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1811 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1812 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1813 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1814 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1815 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1816 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1817 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1818 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1819 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1820 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1821 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1822 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1823 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1824 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1825 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1826 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1827 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1828 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
1829 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
1830 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
1840 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
1841 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
1842 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
1843 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
1844 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
1845 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
1846 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
1847 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
1848 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
1849 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
1850 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
1851 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
1852 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
1853 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
1854 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
1855 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
1856 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
1857 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
1858 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
1859 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
1860 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
1861 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
1862 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
1863 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
1864 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
1865 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
1866 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
1867 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
1868 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
1869 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
1870 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
1871 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
1872 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
1873 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
1874 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
1875 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
1876 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
1877 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
1878 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
1879 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
1880 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
1881 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
1882 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
1883 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
1884 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
1885 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
1886 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
1887 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
1888 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
1889 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
1890 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
1891 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
1892 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
1893 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
1894 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
1895 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
1896 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
1897 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
1898 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
1899 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
1900 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
1901 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
1902 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
1903 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
1904 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
1905 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
1906 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
1907 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
1908 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
1909 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
1910 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
1911 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
1912 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
1913 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
1914 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
1915 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
1916 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
1917 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
1918 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
1919 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
1920 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
1921 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
1922 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
1923 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
1924 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
1925 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
1926 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
1927 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
1928 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
1929 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
1930 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
1931 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
1932 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
1933 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
1934 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
1935 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
1936 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
1937 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
1938 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
1939 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
1940 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
1941 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
1942 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
1943 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
1944 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
1945 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
1946 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
1947 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
1948 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
1949 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
1950 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
1951 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
1952 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
1953 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
1954 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
1955 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
1956 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
1957 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
1958 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
1959 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
1960 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
1961 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
1962 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
1963 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
1964 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
1965 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
1966 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
1967 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
1968 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
1969 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
1970 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
1971 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
1972 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
1973 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
1974 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
1975 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
1976 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
1977 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
1978 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
1979 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
1980 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
1981 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
1982 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
1983 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
1984 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
1985 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
1986 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
1987 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
1988 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
1989 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
1990 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
1991 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
1992 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
1993 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2002 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
2003 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
2004 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)
false) },
2014 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2015 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2016 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2017 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2018 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2019 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2020 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2021 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2022 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2023 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2024 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2025 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2026 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2027 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2028 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2029 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2030 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2031 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2032 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2033 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2034 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2035 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2036 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2037 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2038 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2039 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2040 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2041 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2042 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2043 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2044 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2045 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2046 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2047 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2048 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2049 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2050 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2051 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2052 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2053 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2054 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2055 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2056 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2057 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2058 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2059 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2060 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2061 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2062 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2063 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2064 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2065 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2066 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2067 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2068 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2069 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2070 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2071 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2072 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2073 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2074 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2075 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2076 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2077 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2078 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2079 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2080 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2081 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2082 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2083 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2084 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2085 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2086 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2087 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2088 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2089 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2090 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2091 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2092 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2093 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2094 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2095 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2096 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2097 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2098 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2099 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2100 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2101 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2102 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2103 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2104 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2105 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2106 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2107 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2108 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2109 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2110 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
2111 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
2112 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
2113 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
2114 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
2115 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
2116 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
2117 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
2118 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
2119 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
2120 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
2121 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
2122 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
2123 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
2124 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
2125 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
2126 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
2127 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
2128 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
2129 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
2130 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
2131 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
2132 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
2133 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
2134 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
2135 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
2136 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
2137 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
2138 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
2139 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
2140 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
2141 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
2142 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
2143 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
2153 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2154 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2155 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2156 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2157 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2158 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2159 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2160 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2161 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2162 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2163 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2164 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2165 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2166 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2167 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2168 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2169 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2170 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2171 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2172 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2173 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2174 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2175 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2176 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2177 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2178 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2179 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2180 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2181 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2182 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2192 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2193 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2194 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2195 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2196 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2197 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2198 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2199 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2200 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2201 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2202 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2203 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2204 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2205 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2206 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2207 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2208 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2209 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2210 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2211 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2212 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2213 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2214 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2215 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2216 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2217 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2218 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2219 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2220 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2221 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2222 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2223 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2224 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2225 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2226 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2227 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2228 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2229 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2230 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2231 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2232 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2233 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2234 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2235 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2236 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2237 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2238 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2239 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2240 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2241 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2242 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2243 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2244 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2245 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2246 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2247 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2248 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2249 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2250 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2251 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2252 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2253 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2254 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2255 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2256 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2257 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2258 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2259 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2260 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2261 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2262 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2263 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2264 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2265 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2266 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2267 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2268 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2269 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2270 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2271 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2272 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2273 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2274 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2275 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2276 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2277 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2278 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2279 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2280 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2281 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2282 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2283 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2284 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2285 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2286 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2287 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2288 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
2289 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
2290 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
2291 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
2292 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
2293 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
2294 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
2295 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
2296 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
2297 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
2298 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
2299 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
2300 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
2301 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
2302 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
2303 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
2304 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
2305 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
2306 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
2307 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
2308 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
2309 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
2310 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
2311 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
2312 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
2313 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
2314 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
2315 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
2316 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
2317 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
2318 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
2319 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
2320 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
2321 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
2322 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
2323 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
2324 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
2325 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
2326 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
2327 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
2328 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
2329 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
2330 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
2331 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
2332 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
2333 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
2334 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
2335 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
2336 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
2337 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
2338 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
2339 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
2340 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
2341 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
2342 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
2343 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
2344 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
2345 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2346 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
2347 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
2357 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2358 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2359 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2360 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2361 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2362 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2363 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2364 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2365 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2366 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2367 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2368 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2369 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2370 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2371 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2372 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2373 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2374 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2375 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2376 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2377 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2378 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2379 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2380 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2381 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2382 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2383 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2384 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2385 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2386 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2387 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2388 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2389 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2390 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2391 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2392 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2393 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2394 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2395 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2396 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2397 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2398 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2399 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2400 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2401 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2402 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2403 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2404 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2405 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2406 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2407 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2408 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2409 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2410 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2411 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2412 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2413 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2414 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2415 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2416 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2417 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2418 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2419 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2420 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2421 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2422 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2423 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2424 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2425 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2426 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2427 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2428 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2429 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2430 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2431 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2432 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2433 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2434 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2435 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2436 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2437 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2438 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2439 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2440 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2441 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2442 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2443 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2444 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2445 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2446 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2447 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2448 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2449 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2450 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2451 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2452 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2453 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
2454 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
2455 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
2456 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
2457 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
2458 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
2459 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
2460 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
2461 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
2462 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
2463 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
2464 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
2465 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
2466 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
2467 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
2468 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
2469 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
2470 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
2471 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
2472 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
2473 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
2474 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
2475 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
2476 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
2477 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
2478 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
2479 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
2480 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
2481 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
2482 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
2483 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
2484 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
2485 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
2486 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
2487 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
2488 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
2489 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
2490 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
2491 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
2492 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
2493 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
2494 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
2495 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
2496 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
2497 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
2498 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
2499 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
2500 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
2501 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
2502 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
2503 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
2504 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
2505 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
2506 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
2507 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
2508 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
2509 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
2510 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2520 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2521 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2522 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2523 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2524 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2525 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2526 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2527 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2528 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2529 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2530 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2531 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2532 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2533 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2534 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2535 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2536 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2537 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2538 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2539 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2540 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2541 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2542 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2543 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2544 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2545 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2546 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2547 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2548 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2549 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2550 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2551 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2552 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2553 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2554 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2555 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2556 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2557 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2558 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2559 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2560 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2561 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2562 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2563 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2564 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2565 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2566 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2567 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2568 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2569 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2570 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2571 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2572 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2573 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2574 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2575 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2576 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2577 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2578 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2579 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2580 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2581 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2582 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2583 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2584 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2585 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2586 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2587 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2588 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2589 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2590 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2591 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2592 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2593 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2594 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2595 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2596 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2597 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2598 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2599 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2600 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2601 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2602 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2603 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2604 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2605 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2606 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2607 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2608 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2609 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2610 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2611 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2612 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2613 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2614 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2615 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2616 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
2617 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
2618 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
2619 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
2620 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
2621 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
2622 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
2623 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
2624 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
2625 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
2626 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
2627 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
2628 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
2629 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
2630 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
2631 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
2632 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
2633 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
2634 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
2635 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
2636 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
2637 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
2638 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
2639 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
2640 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
2641 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
2642 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
2643 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
2644 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
2645 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
2646 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
2647 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
2648 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
2649 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
2650 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
2651 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
2652 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
2653 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
2654 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
2655 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
2656 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
2657 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
2658 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
2659 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
2660 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
2661 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
2662 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
2663 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
2664 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
2665 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
2666 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
2667 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
2668 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
2669 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
2670 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
2671 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
2672 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
2673 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2674 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
2675 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
2685 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
2686 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
2687 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
2688 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
2689 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
2690 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
2691 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
2692 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
2693 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
2694 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
2695 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
2696 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
2697 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
2698 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
2699 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
2700 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
2701 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
2702 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
2703 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
2704 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
2705 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
2706 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
2707 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
2708 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
2709 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
2710 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
2711 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
2712 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
2713 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
2714 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
2715 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
2716 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
2717 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
2718 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
2719 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
2720 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
2721 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
2722 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
2723 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
2724 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
2725 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
2726 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
2727 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
2728 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
2729 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
2730 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
2731 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
2732 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
2733 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
2734 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
2735 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
2736 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
2737 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
2738 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
2739 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
2740 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
2741 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
2742 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
2743 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
2744 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
2745 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
2746 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
2747 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
2748 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
2749 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
2750 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
2751 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
2752 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
2753 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
2754 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
2755 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
2756 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
2757 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
2758 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
2759 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
2760 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
2761 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
2762 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
2763 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
2764 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
2765 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
2766 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
2767 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
2768 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
2769 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
2770 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
2771 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
2772 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
2773 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
2774 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
2775 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
2776 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
2777 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
2778 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
2779 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
2780 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
2781 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
2782 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
2783 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
2784 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
2785 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
2786 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
2787 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
2788 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
2789 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
2790 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
2791 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
2792 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
2793 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
2794 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
2795 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
2796 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
2797 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
2798 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
2799 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
2800 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
2801 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
2802 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
2803 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
2804 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
2805 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
2806 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
2807 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
2808 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
2809 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
2810 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
2811 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
2812 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
2813 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
2814 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
2815 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
2816 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
2817 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
2818 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
2819 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
2820 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
2821 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
2822 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
2823 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
2824 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
2825 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
2826 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
2827 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
2828 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
2829 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
2830 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
2831 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
2832 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
2833 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
2834 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
2835 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
2836 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
2837 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
2838 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
2847 { SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
2848 SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
2849 SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
2858 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
2859 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
2860 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
2861 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
2862 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
2863 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
2864 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
2865 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
2866 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
2867 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
2868 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
2869 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
2870 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
2871 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
2872 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)
true) },
2873 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
2874 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
2875 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)
true) },
2876 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
2877 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
2878 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)
true) },
2879 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
2880 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
2881 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)
true) },
2882 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
2883 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
2884 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
2885 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
2886 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
2887 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
2888 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
2889 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
2890 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
2891 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
2892 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
2893 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
2894 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
2895 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
2896 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
2897 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
2898 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
2899 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)
true) },
2900 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
2901 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
2902 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)
true) },
2903 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
2904 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
2905 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)
true) },
2906 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
2907 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
2908 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)
true) },
2909 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
2910 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
2911 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)
true) },
2912 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
2913 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
2914 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)
true) },
2915 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
2916 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
2917 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)
true) },
2918 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
2919 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
2920 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)
true) },
2921 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID, 0u,
2922 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_SIZE, 4u,
2923 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ROW_WIDTH, ((bool)
true) },
2924 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID, 0u,
2925 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_SIZE, 4u,
2926 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ROW_WIDTH, ((bool)
true) },
2927 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID, 0u,
2928 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_SIZE, 4u,
2929 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
2930 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID, 0u,
2931 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_SIZE, 4u,
2932 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
2933 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID, 0u,
2934 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_SIZE, 4u,
2935 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
2936 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID, 0u,
2937 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_SIZE, 4u,
2938 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
2939 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID, 0u,
2940 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_SIZE, 4u,
2941 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ROW_WIDTH, ((bool)
false) },
2942 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
2943 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
2944 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)
false) },
2953 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_ID, 0u,
2954 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_SIZE, 4u,
2955 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_ROW_WIDTH, ((bool)
false) },
2956 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_ID, 0u,
2957 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_SIZE, 4u,
2958 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_ROW_WIDTH, ((bool)
false) },
2959 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_ID, 0u,
2960 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_SIZE, 4u,
2961 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_ROW_WIDTH, ((bool)
false) },
2962 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_ID, 0u,
2963 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_SIZE, 4u,
2964 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_ROW_WIDTH, ((bool)
false) },
2965 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_ID, 0u,
2966 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_SIZE, 4u,
2967 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_ROW_WIDTH, ((bool)
false) },
2968 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_ID, 0u,
2969 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_SIZE, 4u,
2970 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_ROW_WIDTH, ((bool)
false) },
2971 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_ID, 0u,
2972 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_SIZE, 4u,
2973 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_ROW_WIDTH, ((bool)
false) },
2974 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_ID, 0u,
2975 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_SIZE, 4u,
2976 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_ROW_WIDTH, ((bool)
false) },
2977 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_ID, 0u,
2978 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_SIZE, 4u,
2979 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_ROW_WIDTH, ((bool)
false) },
2980 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_ID, 0u,
2981 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_SIZE, 4u,
2982 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_ROW_WIDTH, ((bool)
false) },
2983 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_ID, 0u,
2984 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_SIZE, 4u,
2985 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_ROW_WIDTH, ((bool)
false) },
2986 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_ID, 0u,
2987 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_SIZE, 4u,
2988 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_ROW_WIDTH, ((bool)
false) },
2989 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_ID, 0u,
2990 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_SIZE, 4u,
2991 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_ROW_WIDTH, ((bool)
false) },
2992 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_ID, 0u,
2993 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_SIZE, 4u,
2994 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_ROW_WIDTH, ((bool)
false) },
2995 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_ID, 0u,
2996 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_SIZE, 4u,
2997 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_ROW_WIDTH, ((bool)
false) },
3006 { SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
3007 SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
3008 SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)
false) },
3017 { SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
3018 SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
3019 SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)
false) },
3029 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
3030 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_0_WIDTH },
3031 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
3032 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_1_WIDTH },
3033 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
3034 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_2_WIDTH },
3035 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
3036 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_3_WIDTH },
3037 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
3038 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_4_WIDTH },
3039 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
3040 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_5_WIDTH },
3041 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
3042 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_6_WIDTH },
3043 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
3044 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_7_WIDTH },
3045 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
3046 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_8_WIDTH },
3047 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
3048 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_9_WIDTH },
3049 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
3050 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_10_WIDTH },
3051 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
3052 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_11_WIDTH },
3053 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
3054 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_12_WIDTH },
3055 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
3056 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_13_WIDTH },
3057 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
3058 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_14_WIDTH },
3059 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
3060 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_15_WIDTH },
3061 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
3062 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_16_WIDTH },
3063 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
3064 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_17_WIDTH },
3065 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
3066 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_18_WIDTH },
3067 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
3068 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_19_WIDTH },
3069 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
3070 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_20_WIDTH },
3071 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
3072 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_21_WIDTH },
3073 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
3074 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_22_WIDTH },
3075 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
3076 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_23_WIDTH },
3077 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
3078 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_24_WIDTH },
3079 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
3080 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_25_WIDTH },
3081 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_26_CHECKER_TYPE,
3082 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_26_WIDTH },
3083 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_27_CHECKER_TYPE,
3084 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_27_WIDTH },
3085 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_28_CHECKER_TYPE,
3086 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_28_WIDTH },
3087 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_29_CHECKER_TYPE,
3088 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_29_WIDTH },
3089 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_30_CHECKER_TYPE,
3090 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_30_WIDTH },
3091 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_31_CHECKER_TYPE,
3092 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_31_WIDTH },
3093 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_32_CHECKER_TYPE,
3094 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_32_WIDTH },
3095 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_33_CHECKER_TYPE,
3096 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_33_WIDTH },
3097 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_34_CHECKER_TYPE,
3098 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_34_WIDTH },
3099 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_35_CHECKER_TYPE,
3100 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_35_WIDTH },
3101 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_36_CHECKER_TYPE,
3102 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_36_WIDTH },
3103 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_37_CHECKER_TYPE,
3104 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_37_WIDTH },
3105 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_38_CHECKER_TYPE,
3106 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_38_WIDTH },
3107 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_39_CHECKER_TYPE,
3108 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_39_WIDTH },
3109 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_40_CHECKER_TYPE,
3110 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_40_WIDTH },
3111 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_41_CHECKER_TYPE,
3112 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_41_WIDTH },
3113 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_42_CHECKER_TYPE,
3114 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_42_WIDTH },
3115 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_43_CHECKER_TYPE,
3116 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_43_WIDTH },
3117 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_44_CHECKER_TYPE,
3118 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_44_WIDTH },
3119 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_45_CHECKER_TYPE,
3120 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_45_WIDTH },
3121 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_46_CHECKER_TYPE,
3122 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_46_WIDTH },
3123 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_47_CHECKER_TYPE,
3124 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_47_WIDTH },
3125 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_48_CHECKER_TYPE,
3126 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_48_WIDTH },
3127 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_49_CHECKER_TYPE,
3128 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_49_WIDTH },
3129 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_50_CHECKER_TYPE,
3130 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_50_WIDTH },
3131 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_51_CHECKER_TYPE,
3132 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_51_WIDTH },
3133 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_52_CHECKER_TYPE,
3134 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_52_WIDTH },
3135 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_53_CHECKER_TYPE,
3136 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_53_WIDTH },
3137 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_54_CHECKER_TYPE,
3138 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_54_WIDTH },
3139 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_55_CHECKER_TYPE,
3140 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_55_WIDTH },
3141 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_56_CHECKER_TYPE,
3142 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_56_WIDTH },
3143 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_57_CHECKER_TYPE,
3144 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_57_WIDTH },
3145 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_58_CHECKER_TYPE,
3146 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_58_WIDTH },
3147 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_59_CHECKER_TYPE,
3148 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_59_WIDTH },
3149 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_60_CHECKER_TYPE,
3150 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_60_WIDTH },
3151 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_61_CHECKER_TYPE,
3152 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_61_WIDTH },
3153 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_62_CHECKER_TYPE,
3154 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_62_WIDTH },
3155 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_63_CHECKER_TYPE,
3156 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_63_WIDTH },
3157 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_64_CHECKER_TYPE,
3158 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_64_WIDTH },
3159 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_65_CHECKER_TYPE,
3160 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_65_WIDTH },
3161 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_66_CHECKER_TYPE,
3162 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_66_WIDTH },
3163 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_67_CHECKER_TYPE,
3164 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_67_WIDTH },
3165 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_68_CHECKER_TYPE,
3166 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_68_WIDTH },
3167 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_69_CHECKER_TYPE,
3168 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_69_WIDTH },
3169 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_70_CHECKER_TYPE,
3170 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_70_WIDTH },
3171 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_71_CHECKER_TYPE,
3172 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_71_WIDTH },
3173 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_72_CHECKER_TYPE,
3174 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_72_WIDTH },
3175 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_73_CHECKER_TYPE,
3176 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_73_WIDTH },
3177 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_74_CHECKER_TYPE,
3178 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_74_WIDTH },
3179 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_75_CHECKER_TYPE,
3180 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_75_WIDTH },
3181 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_76_CHECKER_TYPE,
3182 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_76_WIDTH },
3183 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_77_CHECKER_TYPE,
3184 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_77_WIDTH },
3185 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_78_CHECKER_TYPE,
3186 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_78_WIDTH },
3187 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_79_CHECKER_TYPE,
3188 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_79_WIDTH },
3189 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_80_CHECKER_TYPE,
3190 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_80_WIDTH },
3191 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_81_CHECKER_TYPE,
3192 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_81_WIDTH },
3193 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_82_CHECKER_TYPE,
3194 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_82_WIDTH },
3195 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_83_CHECKER_TYPE,
3196 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_83_WIDTH },
3197 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_84_CHECKER_TYPE,
3198 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_84_WIDTH },
3199 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_85_CHECKER_TYPE,
3200 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_85_WIDTH },
3201 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_86_CHECKER_TYPE,
3202 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_86_WIDTH },
3203 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_87_CHECKER_TYPE,
3204 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_87_WIDTH },
3205 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_88_CHECKER_TYPE,
3206 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_88_WIDTH },
3207 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_89_CHECKER_TYPE,
3208 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_89_WIDTH },
3209 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_90_CHECKER_TYPE,
3210 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_90_WIDTH },
3211 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_91_CHECKER_TYPE,
3212 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_91_WIDTH },
3213 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_92_CHECKER_TYPE,
3214 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_92_WIDTH },
3215 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_93_CHECKER_TYPE,
3216 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_93_WIDTH },
3217 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_94_CHECKER_TYPE,
3218 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_94_WIDTH },
3219 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_95_CHECKER_TYPE,
3220 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_95_WIDTH },
3221 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_96_CHECKER_TYPE,
3222 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_96_WIDTH },
3223 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_97_CHECKER_TYPE,
3224 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_97_WIDTH },
3225 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_98_CHECKER_TYPE,
3226 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_98_WIDTH },
3227 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_99_CHECKER_TYPE,
3228 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_99_WIDTH },
3229 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_100_CHECKER_TYPE,
3230 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_100_WIDTH },
3231 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_101_CHECKER_TYPE,
3232 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_101_WIDTH },
3233 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_102_CHECKER_TYPE,
3234 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_102_WIDTH },
3235 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_103_CHECKER_TYPE,
3236 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_103_WIDTH },
3237 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_104_CHECKER_TYPE,
3238 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_104_WIDTH },
3239 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_105_CHECKER_TYPE,
3240 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_105_WIDTH },
3241 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_106_CHECKER_TYPE,
3242 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_106_WIDTH },
3243 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_107_CHECKER_TYPE,
3244 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_107_WIDTH },
3245 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_108_CHECKER_TYPE,
3246 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_108_WIDTH },
3247 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_109_CHECKER_TYPE,
3248 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_109_WIDTH },
3249 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_110_CHECKER_TYPE,
3250 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_110_WIDTH },
3251 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_111_CHECKER_TYPE,
3252 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_111_WIDTH },
3253 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_112_CHECKER_TYPE,
3254 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_112_WIDTH },
3255 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_113_CHECKER_TYPE,
3256 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_113_WIDTH },
3257 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_114_CHECKER_TYPE,
3258 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_114_WIDTH },
3259 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_115_CHECKER_TYPE,
3260 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_115_WIDTH },
3261 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_116_CHECKER_TYPE,
3262 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_116_WIDTH },
3263 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_117_CHECKER_TYPE,
3264 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_117_WIDTH },
3265 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_118_CHECKER_TYPE,
3266 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_118_WIDTH },
3267 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_119_CHECKER_TYPE,
3268 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_119_WIDTH },
3269 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_120_CHECKER_TYPE,
3270 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_120_WIDTH },
3271 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_121_CHECKER_TYPE,
3272 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_121_WIDTH },
3273 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_122_CHECKER_TYPE,
3274 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_122_WIDTH },
3275 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_123_CHECKER_TYPE,
3276 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_123_WIDTH },
3277 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_124_CHECKER_TYPE,
3278 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_124_WIDTH },
3279 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_125_CHECKER_TYPE,
3280 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_125_WIDTH },
3281 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_126_CHECKER_TYPE,
3282 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_126_WIDTH },
3283 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_127_CHECKER_TYPE,
3284 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_127_WIDTH },
3285 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_128_CHECKER_TYPE,
3286 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_128_WIDTH },
3287 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_129_CHECKER_TYPE,
3288 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_129_WIDTH },
3289 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_130_CHECKER_TYPE,
3290 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_130_WIDTH },
3291 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_131_CHECKER_TYPE,
3292 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_131_WIDTH },
3293 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_132_CHECKER_TYPE,
3294 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_132_WIDTH },
3295 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_133_CHECKER_TYPE,
3296 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_133_WIDTH },
3297 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_134_CHECKER_TYPE,
3298 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_134_WIDTH },
3299 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_135_CHECKER_TYPE,
3300 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_135_WIDTH },
3301 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_136_CHECKER_TYPE,
3302 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_136_WIDTH },
3303 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_137_CHECKER_TYPE,
3304 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_137_WIDTH },
3305 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_138_CHECKER_TYPE,
3306 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_138_WIDTH },
3307 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_139_CHECKER_TYPE,
3308 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_139_WIDTH },
3309 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_140_CHECKER_TYPE,
3310 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_140_WIDTH },
3311 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_141_CHECKER_TYPE,
3312 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_141_WIDTH },
3313 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_142_CHECKER_TYPE,
3314 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_142_WIDTH },
3315 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_143_CHECKER_TYPE,
3316 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_143_WIDTH },
3317 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_144_CHECKER_TYPE,
3318 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_144_WIDTH },
3319 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_145_CHECKER_TYPE,
3320 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_145_WIDTH },
3321 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_146_CHECKER_TYPE,
3322 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_146_WIDTH },
3323 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_147_CHECKER_TYPE,
3324 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_147_WIDTH },
3325 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_148_CHECKER_TYPE,
3326 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_148_WIDTH },
3327 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_149_CHECKER_TYPE,
3328 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_149_WIDTH },
3329 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_150_CHECKER_TYPE,
3330 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_150_WIDTH },
3331 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_151_CHECKER_TYPE,
3332 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_151_WIDTH },
3333 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_152_CHECKER_TYPE,
3334 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_152_WIDTH },
3335 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_153_CHECKER_TYPE,
3336 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_153_WIDTH },
3337 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_154_CHECKER_TYPE,
3338 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_154_WIDTH },
3339 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_155_CHECKER_TYPE,
3340 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_155_WIDTH },
3341 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_156_CHECKER_TYPE,
3342 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_156_WIDTH },
3343 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_157_CHECKER_TYPE,
3344 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_157_WIDTH },
3345 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_158_CHECKER_TYPE,
3346 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_158_WIDTH },
3347 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_159_CHECKER_TYPE,
3348 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_159_WIDTH },
3349 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_160_CHECKER_TYPE,
3350 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_160_WIDTH },
3351 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_161_CHECKER_TYPE,
3352 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_161_WIDTH },
3353 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_162_CHECKER_TYPE,
3354 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_162_WIDTH },
3355 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_163_CHECKER_TYPE,
3356 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_163_WIDTH },
3357 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_164_CHECKER_TYPE,
3358 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_164_WIDTH },
3359 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_165_CHECKER_TYPE,
3360 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_165_WIDTH },
3361 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_166_CHECKER_TYPE,
3362 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_166_WIDTH },
3363 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_167_CHECKER_TYPE,
3364 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_167_WIDTH },
3365 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_168_CHECKER_TYPE,
3366 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_168_WIDTH },
3367 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_169_CHECKER_TYPE,
3368 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_169_WIDTH },
3369 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_170_CHECKER_TYPE,
3370 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_170_WIDTH },
3371 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_171_CHECKER_TYPE,
3372 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_171_WIDTH },
3373 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_172_CHECKER_TYPE,
3374 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_172_WIDTH },
3375 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_173_CHECKER_TYPE,
3376 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_173_WIDTH },
3377 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_174_CHECKER_TYPE,
3378 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_174_WIDTH },
3379 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_175_CHECKER_TYPE,
3380 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_175_WIDTH },
3381 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_176_CHECKER_TYPE,
3382 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_176_WIDTH },
3383 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_177_CHECKER_TYPE,
3384 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_177_WIDTH },
3385 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_178_CHECKER_TYPE,
3386 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_178_WIDTH },
3387 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_179_CHECKER_TYPE,
3388 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_179_WIDTH },
3389 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_180_CHECKER_TYPE,
3390 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_180_WIDTH },
3391 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_181_CHECKER_TYPE,
3392 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_181_WIDTH },
3393 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_182_CHECKER_TYPE,
3394 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_182_WIDTH },
3395 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_183_CHECKER_TYPE,
3396 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_GROUP_183_WIDTH },
3406 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
3407 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
3408 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
3409 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
3410 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
3411 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
3412 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
3413 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
3414 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
3415 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
3416 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
3417 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
3418 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
3419 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
3429 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
3430 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
3431 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
3432 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
3433 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
3434 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
3435 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
3436 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
3437 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
3438 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
3439 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
3440 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
3449 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
3450 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
3451 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)
false) },
3452 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID, 0u,
3453 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
3454 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)
false) },
3455 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
3456 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
3457 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
3458 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
3459 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
3460 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
3461 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
3462 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
3463 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
3464 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
3465 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
3466 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
3467 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
3468 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
3469 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)
false) },
3470 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID, 0u,
3471 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
3472 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)
false) },
3473 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID, 0u,
3474 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
3475 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)
false) },
3476 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
3477 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
3478 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)
false) },
3479 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID, 0u,
3480 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_SIZE, 4u,
3481 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ROW_WIDTH, ((bool)
false) },
3482 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID, 0u,
3483 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_SIZE, 4u,
3484 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ROW_WIDTH, ((bool)
false) },
3485 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
3486 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
3487 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)
false) },
3488 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
3489 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
3490 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)
false) },
3491 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
3492 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
3493 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)
false) },
3494 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
3495 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
3496 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)
false) },
3506 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
3507 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_0_WIDTH },
3508 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
3509 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_1_WIDTH },
3510 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
3511 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_2_WIDTH },
3512 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
3513 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_3_WIDTH },
3514 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
3515 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_4_WIDTH },
3516 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
3517 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_GROUP_5_WIDTH },
3527 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
3528 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_0_WIDTH },
3529 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
3530 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_1_WIDTH },
3531 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
3532 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_2_WIDTH },
3533 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
3534 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_3_WIDTH },
3535 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
3536 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_4_WIDTH },
3537 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
3538 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_5_WIDTH },
3539 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
3540 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_6_WIDTH },
3541 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
3542 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_7_WIDTH },
3543 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
3544 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_8_WIDTH },
3545 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
3546 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_9_WIDTH },
3547 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
3548 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_10_WIDTH },
3549 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
3550 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_11_WIDTH },
3551 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
3552 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_12_WIDTH },
3553 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
3554 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_13_WIDTH },
3555 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
3556 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_14_WIDTH },
3557 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
3558 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_15_WIDTH },
3559 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
3560 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_16_WIDTH },
3561 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
3562 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_17_WIDTH },
3563 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
3564 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_18_WIDTH },
3565 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
3566 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_19_WIDTH },
3567 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
3568 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_20_WIDTH },
3569 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
3570 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_21_WIDTH },
3571 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
3572 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_22_WIDTH },
3573 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
3574 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_23_WIDTH },
3575 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
3576 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_24_WIDTH },
3577 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
3578 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_25_WIDTH },
3579 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
3580 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_26_WIDTH },
3581 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
3582 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_27_WIDTH },
3583 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
3584 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_28_WIDTH },
3585 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
3586 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_29_WIDTH },
3587 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
3588 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_30_WIDTH },
3589 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
3590 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_31_WIDTH },
3591 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
3592 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_32_WIDTH },
3593 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
3594 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_33_WIDTH },
3595 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
3596 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_34_WIDTH },
3597 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
3598 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_35_WIDTH },
3599 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
3600 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_36_WIDTH },
3601 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
3602 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_37_WIDTH },
3603 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
3604 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_38_WIDTH },
3605 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
3606 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_39_WIDTH },
3607 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
3608 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_40_WIDTH },
3609 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
3610 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_41_WIDTH },
3611 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
3612 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_42_WIDTH },
3613 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
3614 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_43_WIDTH },
3615 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
3616 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_44_WIDTH },
3617 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
3618 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_45_WIDTH },
3619 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
3620 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_46_WIDTH },
3621 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
3622 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_47_WIDTH },
3623 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
3624 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_48_WIDTH },
3625 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
3626 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_49_WIDTH },
3627 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
3628 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_50_WIDTH },
3629 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
3630 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_51_WIDTH },
3631 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
3632 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_52_WIDTH },
3633 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
3634 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_53_WIDTH },
3635 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
3636 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_54_WIDTH },
3637 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
3638 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_55_WIDTH },
3639 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
3640 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_56_WIDTH },
3641 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
3642 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_57_WIDTH },
3643 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
3644 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_58_WIDTH },
3645 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
3646 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_59_WIDTH },
3647 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
3648 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_60_WIDTH },
3649 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
3650 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_61_WIDTH },
3651 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
3652 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_62_WIDTH },
3653 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
3654 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_63_WIDTH },
3655 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
3656 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_64_WIDTH },
3657 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
3658 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_65_WIDTH },
3659 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
3660 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_66_WIDTH },
3661 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
3662 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_67_WIDTH },
3663 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
3664 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_68_WIDTH },
3665 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
3666 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_69_WIDTH },
3667 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
3668 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_70_WIDTH },
3669 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
3670 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_GROUP_71_WIDTH },
3680 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
3681 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_0_WIDTH },
3682 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
3683 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_1_WIDTH },
3684 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
3685 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_2_WIDTH },
3686 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
3687 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_3_WIDTH },
3688 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
3689 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_4_WIDTH },
3690 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
3691 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_5_WIDTH },
3692 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
3693 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_6_WIDTH },
3694 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
3695 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_7_WIDTH },
3696 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
3697 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_8_WIDTH },
3698 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
3699 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_9_WIDTH },
3700 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
3701 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_10_WIDTH },
3702 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
3703 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_11_WIDTH },
3704 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
3705 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_12_WIDTH },
3706 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
3707 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_13_WIDTH },
3708 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
3709 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_14_WIDTH },
3710 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
3711 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_15_WIDTH },
3712 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
3713 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_16_WIDTH },
3714 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
3715 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_GROUP_17_WIDTH },
3725 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
3726 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_0_WIDTH },
3727 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
3728 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_1_WIDTH },
3729 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
3730 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_2_WIDTH },
3731 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
3732 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_3_WIDTH },
3733 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
3734 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_4_WIDTH },
3735 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
3736 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_5_WIDTH },
3737 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
3738 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_6_WIDTH },
3739 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
3740 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_7_WIDTH },
3741 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
3742 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_8_WIDTH },
3743 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
3744 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_9_WIDTH },
3745 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
3746 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_10_WIDTH },
3747 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
3748 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_11_WIDTH },
3749 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
3750 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_12_WIDTH },
3751 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
3752 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_13_WIDTH },
3753 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
3754 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_14_WIDTH },
3755 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
3756 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_15_WIDTH },
3757 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
3758 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_16_WIDTH },
3759 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
3760 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_17_WIDTH },
3761 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
3762 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_18_WIDTH },
3763 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
3764 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_19_WIDTH },
3765 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
3766 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_20_WIDTH },
3767 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
3768 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_21_WIDTH },
3769 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
3770 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_22_WIDTH },
3771 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
3772 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_23_WIDTH },
3773 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
3774 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_24_WIDTH },
3775 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
3776 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_25_WIDTH },
3777 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
3778 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_26_WIDTH },
3779 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
3780 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_27_WIDTH },
3781 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
3782 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_28_WIDTH },
3783 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
3784 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_29_WIDTH },
3785 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
3786 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_30_WIDTH },
3787 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
3788 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_31_WIDTH },
3789 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
3790 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_32_WIDTH },
3791 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
3792 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_33_WIDTH },
3793 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
3794 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_34_WIDTH },
3795 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
3796 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_35_WIDTH },
3797 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
3798 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_36_WIDTH },
3799 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
3800 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_37_WIDTH },
3801 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
3802 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_38_WIDTH },
3803 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
3804 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_39_WIDTH },
3805 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
3806 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_40_WIDTH },
3807 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
3808 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_41_WIDTH },
3809 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
3810 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_42_WIDTH },
3811 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
3812 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_43_WIDTH },
3813 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
3814 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_44_WIDTH },
3815 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
3816 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_45_WIDTH },
3817 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
3818 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_46_WIDTH },
3819 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
3820 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_47_WIDTH },
3821 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
3822 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_48_WIDTH },
3823 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
3824 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_49_WIDTH },
3825 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
3826 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_50_WIDTH },
3827 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
3828 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_51_WIDTH },
3829 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
3830 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_52_WIDTH },
3831 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
3832 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_53_WIDTH },
3833 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
3834 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_54_WIDTH },
3835 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
3836 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_55_WIDTH },
3837 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
3838 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_56_WIDTH },
3839 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
3840 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_57_WIDTH },
3841 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
3842 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_58_WIDTH },
3843 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
3844 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_59_WIDTH },
3845 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
3846 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_60_WIDTH },
3847 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
3848 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_61_WIDTH },
3849 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
3850 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_62_WIDTH },
3851 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
3852 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_63_WIDTH },
3853 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
3854 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_64_WIDTH },
3855 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
3856 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_65_WIDTH },
3857 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
3858 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_66_WIDTH },
3859 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
3860 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_67_WIDTH },
3861 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
3862 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_68_WIDTH },
3863 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
3864 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_69_WIDTH },
3865 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
3866 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_70_WIDTH },
3867 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
3868 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_71_WIDTH },
3869 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
3870 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_72_WIDTH },
3871 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
3872 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_73_WIDTH },
3873 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
3874 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_74_WIDTH },
3875 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
3876 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_75_WIDTH },
3877 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
3878 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_76_WIDTH },
3879 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
3880 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_77_WIDTH },
3881 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
3882 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_78_WIDTH },
3883 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
3884 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_79_WIDTH },
3885 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
3886 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_80_WIDTH },
3887 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
3888 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_81_WIDTH },
3889 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
3890 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_82_WIDTH },
3891 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
3892 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_83_WIDTH },
3893 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
3894 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_84_WIDTH },
3895 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
3896 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_85_WIDTH },
3897 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
3898 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_86_WIDTH },
3899 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
3900 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_87_WIDTH },
3901 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
3902 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_88_WIDTH },
3903 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
3904 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_89_WIDTH },
3905 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
3906 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_90_WIDTH },
3907 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
3908 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_91_WIDTH },
3909 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
3910 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_92_WIDTH },
3911 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
3912 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_93_WIDTH },
3913 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
3914 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_94_WIDTH },
3915 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
3916 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_95_WIDTH },
3917 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
3918 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_96_WIDTH },
3919 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
3920 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_97_WIDTH },
3921 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
3922 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_98_WIDTH },
3923 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
3924 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_99_WIDTH },
3925 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
3926 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_100_WIDTH },
3927 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
3928 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_101_WIDTH },
3929 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
3930 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_102_WIDTH },
3931 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
3932 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_103_WIDTH },
3933 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
3934 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_104_WIDTH },
3935 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
3936 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_105_WIDTH },
3937 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
3938 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_106_WIDTH },
3939 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
3940 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_107_WIDTH },
3941 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
3942 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_108_WIDTH },
3943 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
3944 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_109_WIDTH },
3945 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
3946 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_110_WIDTH },
3947 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
3948 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_111_WIDTH },
3949 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
3950 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_112_WIDTH },
3951 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
3952 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_113_WIDTH },
3953 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
3954 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_114_WIDTH },
3955 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
3956 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_115_WIDTH },
3957 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
3958 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_116_WIDTH },
3959 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
3960 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_117_WIDTH },
3961 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
3962 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_118_WIDTH },
3963 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
3964 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_119_WIDTH },
3965 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
3966 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_120_WIDTH },
3967 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
3968 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_121_WIDTH },
3969 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
3970 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_122_WIDTH },
3971 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
3972 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_123_WIDTH },
3973 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
3974 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_124_WIDTH },
3975 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
3976 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_125_WIDTH },
3977 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
3978 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_126_WIDTH },
3979 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
3980 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_127_WIDTH },
3981 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
3982 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_128_WIDTH },
3983 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
3984 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_129_WIDTH },
3985 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
3986 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_130_WIDTH },
3987 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
3988 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_131_WIDTH },
3989 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
3990 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_132_WIDTH },
3991 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
3992 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_133_WIDTH },
3993 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
3994 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_134_WIDTH },
3995 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
3996 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_135_WIDTH },
3997 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
3998 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_136_WIDTH },
3999 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
4000 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_137_WIDTH },
4001 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
4002 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_138_WIDTH },
4003 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
4004 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_139_WIDTH },
4005 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
4006 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_140_WIDTH },
4007 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
4008 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_141_WIDTH },
4009 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
4010 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_142_WIDTH },
4011 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
4012 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_143_WIDTH },
4013 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
4014 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_144_WIDTH },
4015 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
4016 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_145_WIDTH },
4017 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
4018 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_146_WIDTH },
4019 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
4020 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_147_WIDTH },
4021 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
4022 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_148_WIDTH },
4023 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
4024 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_149_WIDTH },
4025 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
4026 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_150_WIDTH },
4027 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
4028 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_151_WIDTH },
4029 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
4030 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_152_WIDTH },
4031 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
4032 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_153_WIDTH },
4033 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
4034 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_154_WIDTH },
4035 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
4036 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_155_WIDTH },
4037 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
4038 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_156_WIDTH },
4039 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
4040 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_157_WIDTH },
4041 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
4042 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_158_WIDTH },
4043 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
4044 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_159_WIDTH },
4045 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
4046 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_160_WIDTH },
4047 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
4048 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_161_WIDTH },
4049 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
4050 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_162_WIDTH },
4051 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
4052 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_163_WIDTH },
4053 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
4054 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_164_WIDTH },
4055 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
4056 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_165_WIDTH },
4057 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
4058 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_166_WIDTH },
4059 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
4060 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_167_WIDTH },
4061 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_CHECKER_TYPE,
4062 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_168_WIDTH },
4063 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_CHECKER_TYPE,
4064 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_169_WIDTH },
4065 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_CHECKER_TYPE,
4066 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_170_WIDTH },
4067 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_CHECKER_TYPE,
4068 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_171_WIDTH },
4069 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_CHECKER_TYPE,
4070 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_172_WIDTH },
4071 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_CHECKER_TYPE,
4072 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_173_WIDTH },
4073 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_CHECKER_TYPE,
4074 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_174_WIDTH },
4075 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_CHECKER_TYPE,
4076 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_175_WIDTH },
4077 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_CHECKER_TYPE,
4078 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_176_WIDTH },
4079 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_CHECKER_TYPE,
4080 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_177_WIDTH },
4081 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_CHECKER_TYPE,
4082 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_178_WIDTH },
4083 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_CHECKER_TYPE,
4084 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_179_WIDTH },
4085 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_CHECKER_TYPE,
4086 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_180_WIDTH },
4087 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_CHECKER_TYPE,
4088 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_181_WIDTH },
4089 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_CHECKER_TYPE,
4090 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_182_WIDTH },
4091 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_CHECKER_TYPE,
4092 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_183_WIDTH },
4093 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_CHECKER_TYPE,
4094 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_184_WIDTH },
4095 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_CHECKER_TYPE,
4096 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_185_WIDTH },
4097 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_CHECKER_TYPE,
4098 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_186_WIDTH },
4099 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_CHECKER_TYPE,
4100 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_187_WIDTH },
4101 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_CHECKER_TYPE,
4102 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_188_WIDTH },
4103 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_CHECKER_TYPE,
4104 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_189_WIDTH },
4105 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_CHECKER_TYPE,
4106 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_190_WIDTH },
4107 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_CHECKER_TYPE,
4108 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_191_WIDTH },
4109 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_CHECKER_TYPE,
4110 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_192_WIDTH },
4111 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_CHECKER_TYPE,
4112 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_193_WIDTH },
4113 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_CHECKER_TYPE,
4114 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_194_WIDTH },
4115 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_CHECKER_TYPE,
4116 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_195_WIDTH },
4117 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_CHECKER_TYPE,
4118 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_196_WIDTH },
4119 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_CHECKER_TYPE,
4120 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_197_WIDTH },
4121 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_CHECKER_TYPE,
4122 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_198_WIDTH },
4123 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_CHECKER_TYPE,
4124 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_199_WIDTH },
4125 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_CHECKER_TYPE,
4126 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_200_WIDTH },
4127 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_CHECKER_TYPE,
4128 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_201_WIDTH },
4129 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_CHECKER_TYPE,
4130 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_202_WIDTH },
4131 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_CHECKER_TYPE,
4132 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_203_WIDTH },
4133 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_CHECKER_TYPE,
4134 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_204_WIDTH },
4135 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_CHECKER_TYPE,
4136 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_205_WIDTH },
4137 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_CHECKER_TYPE,
4138 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_206_WIDTH },
4139 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_CHECKER_TYPE,
4140 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_207_WIDTH },
4141 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_CHECKER_TYPE,
4142 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_208_WIDTH },
4143 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_CHECKER_TYPE,
4144 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_209_WIDTH },
4145 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_CHECKER_TYPE,
4146 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_210_WIDTH },
4147 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_CHECKER_TYPE,
4148 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_211_WIDTH },
4149 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_CHECKER_TYPE,
4150 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_212_WIDTH },
4151 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_CHECKER_TYPE,
4152 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_213_WIDTH },
4153 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_CHECKER_TYPE,
4154 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_214_WIDTH },
4155 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_CHECKER_TYPE,
4156 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_215_WIDTH },
4157 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_CHECKER_TYPE,
4158 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_216_WIDTH },
4159 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_CHECKER_TYPE,
4160 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_217_WIDTH },
4161 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_CHECKER_TYPE,
4162 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_218_WIDTH },
4163 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_CHECKER_TYPE,
4164 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_219_WIDTH },
4165 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_CHECKER_TYPE,
4166 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_220_WIDTH },
4167 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_CHECKER_TYPE,
4168 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_221_WIDTH },
4169 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_CHECKER_TYPE,
4170 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_222_WIDTH },
4171 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_CHECKER_TYPE,
4172 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_223_WIDTH },
4173 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_CHECKER_TYPE,
4174 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_224_WIDTH },
4175 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_CHECKER_TYPE,
4176 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_225_WIDTH },
4177 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_CHECKER_TYPE,
4178 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_226_WIDTH },
4179 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_CHECKER_TYPE,
4180 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_227_WIDTH },
4181 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_CHECKER_TYPE,
4182 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_228_WIDTH },
4183 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_CHECKER_TYPE,
4184 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_229_WIDTH },
4185 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_CHECKER_TYPE,
4186 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_230_WIDTH },
4187 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_CHECKER_TYPE,
4188 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_231_WIDTH },
4189 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_CHECKER_TYPE,
4190 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_232_WIDTH },
4191 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_CHECKER_TYPE,
4192 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_233_WIDTH },
4193 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_CHECKER_TYPE,
4194 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_234_WIDTH },
4195 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_CHECKER_TYPE,
4196 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_235_WIDTH },
4197 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_CHECKER_TYPE,
4198 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_236_WIDTH },
4199 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_CHECKER_TYPE,
4200 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_237_WIDTH },
4201 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_CHECKER_TYPE,
4202 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_238_WIDTH },
4203 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_CHECKER_TYPE,
4204 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_239_WIDTH },
4205 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_CHECKER_TYPE,
4206 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_240_WIDTH },
4207 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_CHECKER_TYPE,
4208 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_241_WIDTH },
4209 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_CHECKER_TYPE,
4210 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_242_WIDTH },
4211 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_CHECKER_TYPE,
4212 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_243_WIDTH },
4213 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_CHECKER_TYPE,
4214 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_244_WIDTH },
4215 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_CHECKER_TYPE,
4216 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_245_WIDTH },
4217 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_CHECKER_TYPE,
4218 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_246_WIDTH },
4219 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_CHECKER_TYPE,
4220 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_247_WIDTH },
4221 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_CHECKER_TYPE,
4222 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_248_WIDTH },
4223 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_CHECKER_TYPE,
4224 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_249_WIDTH },
4225 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_CHECKER_TYPE,
4226 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_250_WIDTH },
4227 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_CHECKER_TYPE,
4228 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_251_WIDTH },
4229 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_CHECKER_TYPE,
4230 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_252_WIDTH },
4231 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_CHECKER_TYPE,
4232 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_253_WIDTH },
4233 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_CHECKER_TYPE,
4234 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_254_WIDTH },
4235 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_CHECKER_TYPE,
4236 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_GROUP_255_WIDTH },
4246 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_CHECKER_TYPE,
4247 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_0_WIDTH },
4248 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_CHECKER_TYPE,
4249 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_1_WIDTH },
4250 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_CHECKER_TYPE,
4251 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_2_WIDTH },
4252 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_CHECKER_TYPE,
4253 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_3_WIDTH },
4254 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_CHECKER_TYPE,
4255 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_4_WIDTH },
4256 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_CHECKER_TYPE,
4257 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_5_WIDTH },
4258 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_CHECKER_TYPE,
4259 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_6_WIDTH },
4260 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_CHECKER_TYPE,
4261 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_7_WIDTH },
4262 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_CHECKER_TYPE,
4263 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_8_WIDTH },
4264 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_CHECKER_TYPE,
4265 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_9_WIDTH },
4266 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_CHECKER_TYPE,
4267 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_10_WIDTH },
4268 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_CHECKER_TYPE,
4269 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_11_WIDTH },
4270 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_CHECKER_TYPE,
4271 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_12_WIDTH },
4272 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_CHECKER_TYPE,
4273 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_13_WIDTH },
4274 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_CHECKER_TYPE,
4275 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_14_WIDTH },
4276 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_CHECKER_TYPE,
4277 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_15_WIDTH },
4278 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_CHECKER_TYPE,
4279 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_16_WIDTH },
4280 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_CHECKER_TYPE,
4281 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_17_WIDTH },
4282 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_CHECKER_TYPE,
4283 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_18_WIDTH },
4284 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_CHECKER_TYPE,
4285 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_19_WIDTH },
4286 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_CHECKER_TYPE,
4287 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_20_WIDTH },
4288 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_CHECKER_TYPE,
4289 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_21_WIDTH },
4290 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_CHECKER_TYPE,
4291 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_22_WIDTH },
4292 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_CHECKER_TYPE,
4293 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_23_WIDTH },
4294 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_CHECKER_TYPE,
4295 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_24_WIDTH },
4296 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_CHECKER_TYPE,
4297 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_25_WIDTH },
4298 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_CHECKER_TYPE,
4299 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_26_WIDTH },
4300 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_CHECKER_TYPE,
4301 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_27_WIDTH },
4302 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_CHECKER_TYPE,
4303 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_28_WIDTH },
4304 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_CHECKER_TYPE,
4305 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_29_WIDTH },
4306 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_CHECKER_TYPE,
4307 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_30_WIDTH },
4308 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_CHECKER_TYPE,
4309 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_31_WIDTH },
4310 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_CHECKER_TYPE,
4311 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_32_WIDTH },
4312 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_CHECKER_TYPE,
4313 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_33_WIDTH },
4314 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_CHECKER_TYPE,
4315 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_34_WIDTH },
4316 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_CHECKER_TYPE,
4317 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_35_WIDTH },
4318 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_CHECKER_TYPE,
4319 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_36_WIDTH },
4320 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_CHECKER_TYPE,
4321 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_37_WIDTH },
4322 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_CHECKER_TYPE,
4323 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_38_WIDTH },
4324 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_CHECKER_TYPE,
4325 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_39_WIDTH },
4326 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_CHECKER_TYPE,
4327 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_40_WIDTH },
4328 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_CHECKER_TYPE,
4329 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_41_WIDTH },
4330 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_CHECKER_TYPE,
4331 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_42_WIDTH },
4332 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_CHECKER_TYPE,
4333 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_43_WIDTH },
4334 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_CHECKER_TYPE,
4335 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_44_WIDTH },
4336 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_CHECKER_TYPE,
4337 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_45_WIDTH },
4338 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_CHECKER_TYPE,
4339 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_46_WIDTH },
4340 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_CHECKER_TYPE,
4341 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_47_WIDTH },
4342 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_CHECKER_TYPE,
4343 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_48_WIDTH },
4344 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_CHECKER_TYPE,
4345 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_49_WIDTH },
4346 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_CHECKER_TYPE,
4347 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_50_WIDTH },
4348 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_CHECKER_TYPE,
4349 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_51_WIDTH },
4350 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_CHECKER_TYPE,
4351 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_52_WIDTH },
4352 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_CHECKER_TYPE,
4353 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_53_WIDTH },
4354 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_CHECKER_TYPE,
4355 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_54_WIDTH },
4356 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_CHECKER_TYPE,
4357 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_55_WIDTH },
4358 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_CHECKER_TYPE,
4359 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_GROUP_56_WIDTH },
4369 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4370 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_0_WIDTH },
4371 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4372 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_1_WIDTH },
4373 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4374 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_2_WIDTH },
4375 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4376 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_3_WIDTH },
4377 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4378 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_4_WIDTH },
4379 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4380 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_5_WIDTH },
4381 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4382 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_6_WIDTH },
4383 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4384 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_7_WIDTH },
4385 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4386 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_8_WIDTH },
4387 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4388 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_9_WIDTH },
4389 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4390 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_10_WIDTH },
4391 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4392 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_11_WIDTH },
4393 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4394 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_12_WIDTH },
4395 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4396 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_13_WIDTH },
4397 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4398 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_14_WIDTH },
4399 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4400 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_15_WIDTH },
4401 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4402 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_16_WIDTH },
4403 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4404 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_17_WIDTH },
4405 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4406 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_18_WIDTH },
4407 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4408 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_19_WIDTH },
4409 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4410 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_20_WIDTH },
4411 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4412 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_21_WIDTH },
4413 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4414 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_22_WIDTH },
4415 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4416 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_23_WIDTH },
4417 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4418 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_24_WIDTH },
4419 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4420 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_25_WIDTH },
4421 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4422 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_26_WIDTH },
4423 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4424 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_27_WIDTH },
4425 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4426 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_28_WIDTH },
4427 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
4428 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_29_WIDTH },
4429 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
4430 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_30_WIDTH },
4431 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
4432 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_31_WIDTH },
4433 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
4434 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_32_WIDTH },
4435 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
4436 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_33_WIDTH },
4437 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
4438 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_34_WIDTH },
4439 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
4440 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_35_WIDTH },
4441 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
4442 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_36_WIDTH },
4443 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
4444 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_37_WIDTH },
4445 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
4446 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_38_WIDTH },
4447 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
4448 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_39_WIDTH },
4449 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
4450 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_40_WIDTH },
4451 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
4452 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_41_WIDTH },
4453 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
4454 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_42_WIDTH },
4455 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
4456 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_43_WIDTH },
4457 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
4458 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_44_WIDTH },
4459 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
4460 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_45_WIDTH },
4461 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
4462 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_46_WIDTH },
4463 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
4464 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_47_WIDTH },
4465 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
4466 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_48_WIDTH },
4467 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
4468 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_49_WIDTH },
4469 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
4470 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_50_WIDTH },
4471 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
4472 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_51_WIDTH },
4473 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
4474 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_52_WIDTH },
4475 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
4476 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_53_WIDTH },
4477 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
4478 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_54_WIDTH },
4479 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
4480 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_55_WIDTH },
4481 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
4482 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_56_WIDTH },
4483 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
4484 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_57_WIDTH },
4485 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
4486 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_58_WIDTH },
4487 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
4488 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_59_WIDTH },
4489 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
4490 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_60_WIDTH },
4491 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
4492 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_61_WIDTH },
4493 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
4494 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_62_WIDTH },
4495 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
4496 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_63_WIDTH },
4497 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
4498 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_64_WIDTH },
4499 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
4500 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_65_WIDTH },
4501 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
4502 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_GROUP_66_WIDTH },
4512 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4513 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_0_WIDTH },
4514 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4515 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_1_WIDTH },
4516 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4517 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_2_WIDTH },
4518 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4519 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_3_WIDTH },
4520 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4521 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_4_WIDTH },
4522 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4523 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_5_WIDTH },
4524 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4525 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_6_WIDTH },
4526 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4527 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_7_WIDTH },
4528 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4529 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_8_WIDTH },
4530 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4531 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_9_WIDTH },
4532 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4533 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_10_WIDTH },
4534 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4535 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_11_WIDTH },
4536 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4537 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_12_WIDTH },
4538 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4539 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_13_WIDTH },
4540 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4541 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_14_WIDTH },
4542 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4543 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_15_WIDTH },
4544 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4545 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_16_WIDTH },
4546 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4547 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_17_WIDTH },
4548 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4549 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_18_WIDTH },
4550 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4551 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_19_WIDTH },
4552 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4553 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_20_WIDTH },
4554 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4555 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_21_WIDTH },
4556 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4557 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_22_WIDTH },
4558 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4559 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_23_WIDTH },
4560 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4561 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_24_WIDTH },
4562 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4563 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_25_WIDTH },
4564 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4565 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_26_WIDTH },
4566 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4567 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_27_WIDTH },
4568 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4569 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_28_WIDTH },
4570 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
4571 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_29_WIDTH },
4572 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
4573 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_30_WIDTH },
4574 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
4575 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_31_WIDTH },
4576 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
4577 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_32_WIDTH },
4578 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
4579 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_33_WIDTH },
4580 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
4581 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_34_WIDTH },
4582 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
4583 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_35_WIDTH },
4584 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
4585 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_36_WIDTH },
4586 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
4587 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_37_WIDTH },
4588 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
4589 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_38_WIDTH },
4590 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
4591 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_39_WIDTH },
4592 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
4593 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_40_WIDTH },
4594 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
4595 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_41_WIDTH },
4596 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
4597 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_42_WIDTH },
4598 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
4599 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_43_WIDTH },
4600 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
4601 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_44_WIDTH },
4602 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
4603 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_45_WIDTH },
4604 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
4605 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_46_WIDTH },
4606 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
4607 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_47_WIDTH },
4608 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
4609 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_48_WIDTH },
4610 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
4611 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_49_WIDTH },
4612 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
4613 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_50_WIDTH },
4614 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
4615 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_51_WIDTH },
4616 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
4617 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_52_WIDTH },
4618 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
4619 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_53_WIDTH },
4620 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
4621 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_54_WIDTH },
4622 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
4623 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_55_WIDTH },
4624 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
4625 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_56_WIDTH },
4626 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
4627 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_57_WIDTH },
4628 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
4629 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_58_WIDTH },
4630 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
4631 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_59_WIDTH },
4632 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
4633 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_60_WIDTH },
4634 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
4635 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_61_WIDTH },
4636 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
4637 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_62_WIDTH },
4638 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
4639 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_63_WIDTH },
4640 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
4641 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_64_WIDTH },
4642 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
4643 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_65_WIDTH },
4644 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
4645 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_66_WIDTH },
4646 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
4647 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_67_WIDTH },
4648 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
4649 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_68_WIDTH },
4650 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
4651 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_69_WIDTH },
4652 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
4653 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_70_WIDTH },
4654 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
4655 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_GROUP_71_WIDTH },
4665 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4666 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
4667 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4668 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
4669 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4670 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
4671 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4672 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
4673 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4674 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
4675 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4676 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
4677 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4678 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
4679 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4680 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
4681 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4682 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
4683 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4684 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
4685 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4686 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
4687 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4688 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
4689 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4690 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
4691 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4692 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
4693 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4694 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
4695 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4696 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
4697 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4698 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
4699 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4700 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
4701 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4702 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
4703 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4704 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
4705 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4706 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
4707 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4708 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
4709 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4710 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
4711 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
4712 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
4713 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
4714 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
4715 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
4716 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
4717 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
4718 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
4719 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
4720 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
4721 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
4722 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
4723 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
4724 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
4725 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
4726 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
4727 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
4728 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
4729 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
4730 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
4731 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
4732 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
4733 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
4734 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
4735 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
4736 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
4737 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
4738 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
4739 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
4740 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
4741 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
4742 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
4743 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
4744 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
4745 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
4746 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
4747 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
4748 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
4749 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
4750 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
4751 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
4752 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
4753 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
4754 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
4755 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
4756 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
4757 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
4758 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
4759 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
4760 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
4761 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
4762 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
4763 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
4764 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
4765 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
4766 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
4767 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
4768 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
4769 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
4770 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
4771 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
4772 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
4773 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
4774 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
4775 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
4776 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
4777 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
4778 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
4779 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
4780 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
4781 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
4782 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
4783 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
4784 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
4785 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
4786 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
4787 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
4788 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
4789 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
4790 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
4791 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
4792 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
4793 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
4794 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
4795 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
4796 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
4797 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
4798 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
4799 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
4800 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
4801 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
4802 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
4803 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
4804 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
4805 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
4806 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
4807 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
4808 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
4809 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
4810 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
4811 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
4812 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
4813 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
4814 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
4815 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
4816 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
4817 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
4818 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
4819 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
4820 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
4821 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
4822 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
4823 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
4824 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
4825 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
4826 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
4827 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
4828 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
4829 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
4830 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
4831 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
4832 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
4833 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
4834 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
4835 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
4836 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
4837 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
4838 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
4839 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
4840 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
4841 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
4842 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
4843 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
4844 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
4845 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
4846 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
4847 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
4848 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
4849 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
4850 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
4851 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
4852 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
4853 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
4854 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
4855 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
4856 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
4857 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
4858 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
4859 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
4860 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
4861 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
4862 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
4863 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
4864 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
4865 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
4866 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
4867 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
4868 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
4869 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
4870 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
4871 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
4872 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
4873 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
4874 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
4875 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
4876 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
4877 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
4878 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
4879 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
4880 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
4881 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
4882 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
4883 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
4884 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
4885 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
4886 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
4887 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
4888 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
4889 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
4890 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
4891 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
4892 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
4893 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
4894 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
4895 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
4896 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
4897 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
4898 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
4899 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
4900 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
4901 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
4902 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
4903 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
4904 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
4905 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
4906 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
4907 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
4908 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
4909 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
4910 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
4911 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
4912 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
4913 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
4914 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
4915 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
4916 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
4917 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
4918 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
4919 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
4920 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
4921 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
4922 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
4923 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
4924 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
4925 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
4926 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
4927 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
4928 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_131_WIDTH },
4938 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4939 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
4940 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4941 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
4942 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4943 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
4953 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
4954 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_0_WIDTH },
4955 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
4956 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_1_WIDTH },
4957 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
4958 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_2_WIDTH },
4959 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
4960 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_3_WIDTH },
4961 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
4962 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_4_WIDTH },
4963 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
4964 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_5_WIDTH },
4965 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
4966 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_6_WIDTH },
4967 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
4968 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_7_WIDTH },
4969 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
4970 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_8_WIDTH },
4971 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
4972 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_9_WIDTH },
4973 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
4974 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_10_WIDTH },
4975 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
4976 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_11_WIDTH },
4977 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
4978 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_12_WIDTH },
4979 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
4980 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_13_WIDTH },
4981 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
4982 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_14_WIDTH },
4983 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
4984 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_15_WIDTH },
4985 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
4986 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_16_WIDTH },
4987 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
4988 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_17_WIDTH },
4989 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
4990 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_18_WIDTH },
4991 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
4992 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_19_WIDTH },
4993 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
4994 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_20_WIDTH },
4995 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
4996 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_21_WIDTH },
4997 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
4998 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_22_WIDTH },
4999 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5000 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_23_WIDTH },
5001 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5002 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_24_WIDTH },
5003 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5004 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_25_WIDTH },
5005 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5006 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_26_WIDTH },
5007 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5008 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_27_WIDTH },
5009 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5010 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_28_WIDTH },
5011 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5012 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_29_WIDTH },
5013 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5014 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_30_WIDTH },
5015 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5016 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_31_WIDTH },
5017 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5018 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_32_WIDTH },
5019 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5020 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_33_WIDTH },
5021 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5022 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_34_WIDTH },
5023 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5024 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_35_WIDTH },
5025 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5026 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_36_WIDTH },
5027 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5028 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_37_WIDTH },
5029 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5030 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_38_WIDTH },
5031 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5032 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_39_WIDTH },
5033 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5034 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_40_WIDTH },
5035 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5036 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_41_WIDTH },
5037 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5038 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_42_WIDTH },
5039 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5040 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_43_WIDTH },
5041 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5042 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_44_WIDTH },
5043 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5044 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_45_WIDTH },
5045 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5046 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_46_WIDTH },
5047 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5048 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_47_WIDTH },
5049 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5050 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_48_WIDTH },
5051 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5052 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_49_WIDTH },
5053 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5054 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_50_WIDTH },
5055 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5056 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_51_WIDTH },
5057 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5058 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_52_WIDTH },
5059 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5060 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_53_WIDTH },
5061 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5062 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_54_WIDTH },
5063 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5064 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_55_WIDTH },
5065 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5066 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_56_WIDTH },
5067 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5068 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_57_WIDTH },
5069 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5070 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_58_WIDTH },
5071 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5072 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_59_WIDTH },
5073 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5074 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_60_WIDTH },
5075 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5076 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_61_WIDTH },
5077 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5078 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_GROUP_62_WIDTH },
5088 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5089 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
5090 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5091 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
5092 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5093 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
5094 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5095 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
5096 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5097 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
5098 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5099 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
5100 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5101 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
5102 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5103 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
5104 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5105 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
5106 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5107 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
5108 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5109 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
5110 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5111 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
5112 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5113 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
5114 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5115 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
5116 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5117 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
5118 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5119 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
5120 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5121 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
5122 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5123 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
5124 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5125 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
5126 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5127 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
5128 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5129 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
5130 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5131 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
5132 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5133 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
5134 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5135 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
5136 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5137 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
5138 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5139 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
5140 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5141 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
5142 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5143 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
5144 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5145 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
5146 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5147 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
5148 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5149 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
5150 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5151 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
5152 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5153 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
5163 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5164 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
5165 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5166 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
5167 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5168 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
5169 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5170 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
5171 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5172 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
5173 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5174 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
5175 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5176 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
5177 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5178 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
5179 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5180 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
5181 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5182 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
5183 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5184 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
5185 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5186 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
5187 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5188 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
5189 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5190 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
5191 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5192 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
5193 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5194 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
5195 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5196 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
5197 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5198 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
5199 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5200 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
5201 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5202 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
5203 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5204 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
5205 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5206 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
5207 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5208 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
5209 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5210 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
5211 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5212 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
5213 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5214 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
5215 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5216 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
5217 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5218 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
5219 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5220 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
5221 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5222 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
5223 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5224 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_30_WIDTH },
5225 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5226 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_31_WIDTH },
5227 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5228 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_GROUP_32_WIDTH },
5238 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5239 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
5240 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5241 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
5242 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5243 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
5244 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5245 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
5246 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5247 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
5248 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5249 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
5250 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5251 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
5252 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5253 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
5254 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5255 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
5256 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5257 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
5258 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5259 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
5260 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5261 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
5262 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5263 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
5264 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5265 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
5266 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5267 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
5268 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5269 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
5270 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5271 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
5272 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5273 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
5274 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5275 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
5276 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5277 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
5278 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5279 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
5280 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5281 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
5282 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5283 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
5284 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5285 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
5286 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5287 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
5288 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5289 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
5290 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5291 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
5292 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5293 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
5294 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5295 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
5296 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5297 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
5307 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5308 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_0_WIDTH },
5309 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5310 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_1_WIDTH },
5311 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5312 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_2_WIDTH },
5313 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5314 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_3_WIDTH },
5315 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5316 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_4_WIDTH },
5317 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5318 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_5_WIDTH },
5319 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5320 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_6_WIDTH },
5321 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5322 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_7_WIDTH },
5323 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5324 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_8_WIDTH },
5325 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5326 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_9_WIDTH },
5327 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5328 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_10_WIDTH },
5329 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5330 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_11_WIDTH },
5331 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5332 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_12_WIDTH },
5333 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5334 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_13_WIDTH },
5335 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5336 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_14_WIDTH },
5337 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5338 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_15_WIDTH },
5339 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5340 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_16_WIDTH },
5341 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5342 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_17_WIDTH },
5343 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5344 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_18_WIDTH },
5345 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5346 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_19_WIDTH },
5347 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5348 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_20_WIDTH },
5349 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5350 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_21_WIDTH },
5351 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5352 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_22_WIDTH },
5353 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5354 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_23_WIDTH },
5355 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5356 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_24_WIDTH },
5357 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5358 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_25_WIDTH },
5359 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5360 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_26_WIDTH },
5361 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5362 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_27_WIDTH },
5363 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5364 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_28_WIDTH },
5365 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5366 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_GROUP_29_WIDTH },
5376 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5377 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
5378 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5379 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
5380 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5381 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
5382 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5383 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
5384 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5385 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
5386 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5387 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
5388 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5389 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
5390 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5391 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
5392 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5393 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
5394 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5395 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
5396 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5397 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
5398 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5399 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
5400 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5401 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
5402 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5403 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
5404 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5405 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
5406 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5407 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
5408 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5409 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
5410 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5411 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
5412 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5413 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
5414 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5415 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
5416 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5417 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
5418 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5419 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
5420 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5421 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
5422 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5423 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
5424 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5425 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
5426 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5427 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
5428 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5429 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
5430 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5431 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
5432 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5433 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
5434 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5435 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
5436 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5437 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
5438 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5439 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
5440 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5441 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
5442 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5443 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
5444 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5445 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
5446 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5447 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
5448 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5449 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
5450 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5451 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
5452 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5453 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
5454 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5455 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
5456 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5457 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
5458 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5459 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
5460 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5461 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
5462 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5463 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
5464 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5465 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
5466 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5467 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
5468 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5469 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
5470 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5471 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
5472 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5473 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
5474 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5475 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
5476 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5477 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
5478 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5479 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
5480 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5481 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
5482 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5483 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
5484 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5485 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
5486 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5487 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
5488 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5489 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
5490 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5491 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
5492 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5493 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
5494 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5495 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
5496 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5497 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
5498 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5499 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
5500 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5501 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
5502 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
5503 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
5504 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
5505 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
5506 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
5507 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
5508 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
5509 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
5510 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
5511 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
5512 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
5513 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
5514 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
5515 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
5516 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
5517 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
5518 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
5519 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
5520 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
5521 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
5522 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
5523 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
5524 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
5525 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
5526 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
5527 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
5528 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
5529 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
5530 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
5531 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
5532 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
5533 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
5534 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
5535 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
5536 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
5537 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
5538 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
5539 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
5540 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
5541 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
5542 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
5543 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
5544 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
5545 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
5546 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
5547 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
5548 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
5549 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
5550 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
5551 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
5552 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
5553 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
5554 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
5555 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
5556 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
5557 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
5558 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
5559 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
5560 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
5561 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
5562 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
5563 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
5564 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
5565 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
5566 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
5567 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
5568 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
5569 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
5570 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
5571 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
5572 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
5573 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
5574 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
5575 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
5576 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
5577 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
5587 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5588 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
5589 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5590 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
5591 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5592 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
5593 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5594 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
5595 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5596 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
5597 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5598 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
5599 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5600 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
5601 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5602 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_7_WIDTH },
5603 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5604 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_8_WIDTH },
5605 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5606 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_9_WIDTH },
5607 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5608 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_10_WIDTH },
5609 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5610 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_11_WIDTH },
5611 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5612 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_12_WIDTH },
5613 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5614 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_13_WIDTH },
5615 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5616 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_14_WIDTH },
5617 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5618 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_15_WIDTH },
5619 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5620 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_16_WIDTH },
5621 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5622 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_17_WIDTH },
5623 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5624 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_18_WIDTH },
5625 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5626 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_19_WIDTH },
5627 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5628 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_20_WIDTH },
5629 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5630 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_21_WIDTH },
5631 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5632 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_22_WIDTH },
5633 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5634 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_23_WIDTH },
5635 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5636 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_24_WIDTH },
5637 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5638 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_25_WIDTH },
5639 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5640 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_26_WIDTH },
5641 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5642 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_27_WIDTH },
5643 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5644 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_28_WIDTH },
5645 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5646 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_29_WIDTH },
5647 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5648 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_30_WIDTH },
5649 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5650 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_31_WIDTH },
5651 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5652 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_32_WIDTH },
5653 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5654 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_33_WIDTH },
5655 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5656 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_34_WIDTH },
5657 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
5658 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_35_WIDTH },
5659 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
5660 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_36_WIDTH },
5661 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
5662 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_37_WIDTH },
5663 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
5664 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_38_WIDTH },
5665 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
5666 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_39_WIDTH },
5667 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
5668 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_40_WIDTH },
5669 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
5670 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_41_WIDTH },
5671 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
5672 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_42_WIDTH },
5673 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
5674 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_43_WIDTH },
5675 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
5676 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_44_WIDTH },
5677 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
5678 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_45_WIDTH },
5679 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
5680 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_46_WIDTH },
5681 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
5682 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_47_WIDTH },
5683 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
5684 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_48_WIDTH },
5685 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
5686 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_49_WIDTH },
5687 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
5688 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_50_WIDTH },
5689 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
5690 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_51_WIDTH },
5691 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
5692 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_52_WIDTH },
5693 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
5694 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_53_WIDTH },
5695 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
5696 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_54_WIDTH },
5697 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
5698 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_55_WIDTH },
5699 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
5700 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_56_WIDTH },
5701 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
5702 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_57_WIDTH },
5703 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
5704 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_58_WIDTH },
5705 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
5706 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_59_WIDTH },
5707 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
5708 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_60_WIDTH },
5709 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
5710 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_61_WIDTH },
5711 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
5712 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_62_WIDTH },
5713 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
5714 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_63_WIDTH },
5715 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
5716 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_64_WIDTH },
5717 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
5718 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_65_WIDTH },
5719 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
5720 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_66_WIDTH },
5721 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
5722 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_67_WIDTH },
5723 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
5724 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_68_WIDTH },
5725 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
5726 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_69_WIDTH },
5727 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
5728 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_70_WIDTH },
5729 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
5730 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_71_WIDTH },
5731 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
5732 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_72_WIDTH },
5733 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
5734 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_73_WIDTH },
5735 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
5736 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_74_WIDTH },
5737 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
5738 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_75_WIDTH },
5739 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
5740 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_76_WIDTH },
5741 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
5742 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_77_WIDTH },
5743 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
5744 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_78_WIDTH },
5745 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
5746 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_79_WIDTH },
5747 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
5748 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_80_WIDTH },
5749 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
5750 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_81_WIDTH },
5751 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
5752 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_82_WIDTH },
5753 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
5754 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_83_WIDTH },
5755 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
5756 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_84_WIDTH },
5757 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
5758 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_85_WIDTH },
5759 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
5760 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_86_WIDTH },
5761 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
5762 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_87_WIDTH },
5763 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
5764 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_88_WIDTH },
5765 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
5766 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_89_WIDTH },
5767 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
5768 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_90_WIDTH },
5769 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
5770 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_91_WIDTH },
5771 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
5772 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_92_WIDTH },
5773 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
5774 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_93_WIDTH },
5775 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
5776 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_94_WIDTH },
5777 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
5778 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_95_WIDTH },
5779 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
5780 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_96_WIDTH },
5781 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
5782 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_97_WIDTH },
5783 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
5784 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_98_WIDTH },
5785 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
5786 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_99_WIDTH },
5787 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
5788 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_GROUP_100_WIDTH },
5798 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5799 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_0_WIDTH },
5800 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5801 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_1_WIDTH },
5802 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5803 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_2_WIDTH },
5804 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5805 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_3_WIDTH },
5806 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5807 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_4_WIDTH },
5808 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5809 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_5_WIDTH },
5810 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5811 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_6_WIDTH },
5812 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5813 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_7_WIDTH },
5814 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5815 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_8_WIDTH },
5816 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5817 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_9_WIDTH },
5818 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5819 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_10_WIDTH },
5820 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5821 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_11_WIDTH },
5822 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5823 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_12_WIDTH },
5824 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5825 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_13_WIDTH },
5826 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5827 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_14_WIDTH },
5828 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5829 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_15_WIDTH },
5830 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5831 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_16_WIDTH },
5832 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5833 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_17_WIDTH },
5834 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5835 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_18_WIDTH },
5836 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5837 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_19_WIDTH },
5838 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5839 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_20_WIDTH },
5840 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5841 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_21_WIDTH },
5842 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5843 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_22_WIDTH },
5844 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5845 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_23_WIDTH },
5846 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5847 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_24_WIDTH },
5848 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5849 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_25_WIDTH },
5850 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5851 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_26_WIDTH },
5852 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5853 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_27_WIDTH },
5854 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5855 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_28_WIDTH },
5856 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5857 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_29_WIDTH },
5858 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5859 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_30_WIDTH },
5860 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5861 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_31_WIDTH },
5862 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5863 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_32_WIDTH },
5864 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5865 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_33_WIDTH },
5866 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5867 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_GROUP_34_WIDTH },
5877 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5878 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_0_WIDTH },
5879 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5880 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_1_WIDTH },
5881 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5882 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_2_WIDTH },
5883 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5884 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_3_WIDTH },
5885 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5886 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_4_WIDTH },
5887 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5888 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_5_WIDTH },
5889 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5890 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_6_WIDTH },
5891 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5892 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_7_WIDTH },
5893 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5894 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_8_WIDTH },
5895 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5896 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_9_WIDTH },
5897 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5898 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_10_WIDTH },
5899 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5900 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_11_WIDTH },
5901 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5902 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_12_WIDTH },
5903 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5904 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_13_WIDTH },
5905 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5906 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_14_WIDTH },
5907 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5908 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_15_WIDTH },
5909 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5910 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_16_WIDTH },
5911 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5912 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_17_WIDTH },
5913 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5914 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_18_WIDTH },
5915 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5916 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_19_WIDTH },
5917 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5918 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_20_WIDTH },
5919 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5920 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_21_WIDTH },
5921 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
5922 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_22_WIDTH },
5923 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
5924 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_23_WIDTH },
5925 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
5926 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_24_WIDTH },
5927 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
5928 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_25_WIDTH },
5929 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
5930 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_26_WIDTH },
5931 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
5932 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_27_WIDTH },
5933 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
5934 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_28_WIDTH },
5935 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
5936 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_29_WIDTH },
5937 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
5938 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_30_WIDTH },
5939 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
5940 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_31_WIDTH },
5941 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
5942 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_32_WIDTH },
5943 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
5944 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_33_WIDTH },
5945 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
5946 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_GROUP_34_WIDTH },
5956 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
5957 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
5958 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
5959 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
5960 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
5961 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
5962 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
5963 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
5964 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
5965 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
5966 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
5967 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
5968 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
5969 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
5970 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
5971 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
5972 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
5973 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
5974 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
5975 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
5976 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
5977 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
5978 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
5979 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
5980 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
5981 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
5982 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
5983 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
5984 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
5985 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
5986 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
5987 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
5988 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
5989 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
5990 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
5991 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
5992 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
5993 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
5994 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
5995 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
5996 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
5997 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
5998 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
5999 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
6000 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6001 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
6002 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6003 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
6004 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6005 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
6006 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6007 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
6008 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6009 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
6010 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6011 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
6012 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6013 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
6014 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6015 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
6016 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6017 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
6018 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6019 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
6020 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6021 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
6022 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6023 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
6024 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6025 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
6035 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6036 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_0_WIDTH },
6037 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6038 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_GROUP_1_WIDTH },
6048 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6049 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_0_WIDTH },
6050 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6051 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_GROUP_1_WIDTH },
6061 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6062 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_0_WIDTH },
6063 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6064 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_GROUP_1_WIDTH },
6074 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6075 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_0_WIDTH },
6076 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6077 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_1_WIDTH },
6078 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6079 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_2_WIDTH },
6080 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6081 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_3_WIDTH },
6082 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6083 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_4_WIDTH },
6084 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6085 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_5_WIDTH },
6086 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6087 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_6_WIDTH },
6088 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6089 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_7_WIDTH },
6090 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6091 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_8_WIDTH },
6092 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6093 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_9_WIDTH },
6094 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6095 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_10_WIDTH },
6096 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6097 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_11_WIDTH },
6098 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6099 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_12_WIDTH },
6100 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6101 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_13_WIDTH },
6102 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6103 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_14_WIDTH },
6104 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6105 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_15_WIDTH },
6106 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6107 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_16_WIDTH },
6108 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6109 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_17_WIDTH },
6110 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6111 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_18_WIDTH },
6112 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6113 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_19_WIDTH },
6114 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6115 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_20_WIDTH },
6116 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6117 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_21_WIDTH },
6118 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6119 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_22_WIDTH },
6120 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6121 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_23_WIDTH },
6122 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6123 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_24_WIDTH },
6124 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6125 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_25_WIDTH },
6126 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6127 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_26_WIDTH },
6128 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6129 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_27_WIDTH },
6130 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6131 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_28_WIDTH },
6132 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6133 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_29_WIDTH },
6134 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6135 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_30_WIDTH },
6136 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6137 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_31_WIDTH },
6138 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6139 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_32_WIDTH },
6140 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6141 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_33_WIDTH },
6142 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6143 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_GROUP_34_WIDTH },
6153 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6154 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_0_WIDTH },
6155 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6156 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_1_WIDTH },
6157 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6158 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_GROUP_2_WIDTH },
6168 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6169 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
6170 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6171 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
6172 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6173 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
6174 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6175 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
6176 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6177 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
6178 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6179 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
6180 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6181 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
6182 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6183 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
6184 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6185 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
6186 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6187 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
6188 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6189 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
6190 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6191 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
6192 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6193 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
6194 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6195 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
6196 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6197 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
6198 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6199 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
6200 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6201 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
6202 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6203 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
6204 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6205 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
6206 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6207 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
6208 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6209 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
6210 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6211 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
6212 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6213 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
6214 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6215 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
6216 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6217 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
6218 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6219 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
6220 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6221 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
6222 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6223 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
6224 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6225 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
6226 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6227 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
6228 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6229 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
6230 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6231 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
6232 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6233 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
6234 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6235 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
6236 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6237 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
6238 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6239 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
6240 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6241 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
6242 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6243 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
6244 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6245 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
6246 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6247 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
6248 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6249 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
6250 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6251 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
6252 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6253 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
6254 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6255 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
6256 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6257 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
6258 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6259 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
6260 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6261 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
6262 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6263 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
6264 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6265 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
6266 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6267 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
6268 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6269 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
6270 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6271 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
6272 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6273 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
6274 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6275 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
6276 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6277 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
6278 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6279 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
6280 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6281 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
6282 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6283 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
6284 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6285 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
6286 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6287 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
6288 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6289 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
6290 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6291 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
6292 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6293 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
6294 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6295 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
6296 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6297 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
6298 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6299 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
6300 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6301 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
6302 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6303 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
6304 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6305 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
6306 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6307 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
6308 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6309 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
6310 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6311 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
6312 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
6313 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
6314 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
6315 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
6316 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
6317 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
6318 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
6319 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
6320 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
6321 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
6322 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
6323 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
6324 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
6325 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
6326 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
6327 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
6328 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
6329 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
6330 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
6331 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
6332 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
6333 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
6334 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
6335 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
6336 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
6337 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
6338 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
6339 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
6340 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
6341 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
6342 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
6343 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
6344 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
6345 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
6346 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
6347 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
6348 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
6349 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
6350 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
6351 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
6352 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
6353 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
6354 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
6355 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
6356 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
6357 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
6358 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
6359 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
6360 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
6361 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
6362 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
6363 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
6364 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
6365 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
6366 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
6367 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
6368 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
6369 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
6370 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
6371 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
6372 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
6373 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
6374 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
6375 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
6376 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
6377 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
6378 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
6379 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
6389 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6390 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
6391 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6392 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
6393 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6394 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
6395 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6396 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
6397 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6398 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
6399 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6400 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
6401 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6402 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
6403 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6404 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
6405 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6406 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
6407 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6408 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
6409 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6410 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
6411 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6412 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
6413 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6414 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
6415 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6416 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
6417 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6418 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
6419 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6420 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
6421 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6422 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
6423 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6424 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
6425 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6426 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
6427 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6428 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
6429 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6430 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
6431 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6432 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
6433 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6434 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
6435 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6436 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
6437 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6438 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
6439 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6440 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
6441 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6442 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
6443 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6444 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
6445 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6446 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
6447 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6448 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
6449 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6450 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
6451 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6452 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
6453 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6454 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
6455 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6456 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
6457 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6458 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
6459 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6460 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
6461 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6462 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
6463 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6464 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
6465 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6466 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
6467 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6468 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
6469 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6470 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
6471 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6472 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
6473 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6474 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
6475 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6476 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
6477 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6478 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
6479 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6480 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
6481 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6482 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
6483 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6484 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
6485 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6486 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
6487 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6488 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
6489 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6490 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
6491 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6492 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
6493 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6494 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
6495 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6496 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
6497 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6498 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
6499 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6500 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
6501 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6502 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
6503 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6504 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
6505 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6506 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
6507 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6508 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
6509 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6510 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
6511 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6512 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
6513 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6514 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
6515 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6516 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
6517 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6518 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
6519 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6520 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
6521 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6522 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
6523 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6524 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
6525 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6526 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
6527 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6528 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
6529 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6530 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
6531 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6532 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
6533 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
6534 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
6535 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
6536 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
6537 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
6538 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
6539 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
6540 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
6541 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
6542 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
6543 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
6544 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
6545 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
6546 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
6547 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
6548 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
6549 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
6550 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
6551 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
6552 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
6553 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
6554 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
6555 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
6556 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
6557 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
6558 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
6559 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
6560 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
6561 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
6562 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
6563 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
6564 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
6565 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
6566 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
6567 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
6568 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
6569 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
6570 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
6571 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
6572 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
6573 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
6574 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
6575 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
6576 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
6577 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
6578 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
6579 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
6580 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
6581 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
6582 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
6583 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
6584 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
6585 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
6586 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
6587 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
6588 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
6589 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
6590 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
6591 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
6592 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
6593 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
6594 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
6604 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6605 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
6606 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6607 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
6608 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6609 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
6610 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6611 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
6612 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6613 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
6614 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6615 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
6616 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6617 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
6618 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6619 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
6620 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6621 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
6622 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6623 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
6624 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6625 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
6626 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6627 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
6628 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6629 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
6630 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6631 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
6632 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6633 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
6634 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6635 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
6636 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6637 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
6638 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6639 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
6640 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6641 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
6642 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6643 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
6644 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6645 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
6646 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6647 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
6648 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6649 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
6650 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6651 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
6652 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6653 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
6654 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6655 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
6656 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6657 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
6658 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6659 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
6660 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6661 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
6662 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6663 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
6664 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6665 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
6666 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6667 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
6668 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6669 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
6670 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6671 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
6672 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6673 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
6674 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6675 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
6676 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
6677 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
6678 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
6679 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
6680 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
6681 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
6682 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
6683 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
6684 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
6685 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
6686 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
6687 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
6688 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
6689 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
6690 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
6691 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
6692 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
6693 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
6694 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
6695 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
6696 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
6697 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
6698 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
6699 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
6700 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
6701 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
6702 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
6703 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
6704 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
6705 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
6706 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
6707 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
6708 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
6709 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
6710 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
6711 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
6712 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
6713 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
6714 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
6715 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
6716 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
6717 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
6718 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
6719 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
6720 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
6721 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
6722 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
6723 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
6724 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
6725 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
6726 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
6727 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
6728 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
6729 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
6730 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
6731 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
6732 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
6733 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
6734 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
6735 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
6736 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
6737 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
6738 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
6739 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
6740 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
6741 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
6742 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
6743 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
6744 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
6745 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
6746 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
6747 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
6748 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
6749 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
6750 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
6751 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
6752 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
6753 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
6754 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
6755 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
6756 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
6757 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
6758 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
6759 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
6760 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
6761 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
6762 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
6763 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
6764 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
6765 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
6766 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
6767 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
6768 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
6769 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
6770 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
6771 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
6772 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
6773 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
6774 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
6775 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
6776 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
6777 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
6778 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
6779 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
6780 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
6781 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
6782 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
6783 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
6784 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
6785 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
6786 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
6787 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_91_WIDTH },
6788 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
6789 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_92_WIDTH },
6790 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
6791 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_93_WIDTH },
6792 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
6793 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_94_WIDTH },
6794 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
6795 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_95_WIDTH },
6796 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
6797 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_96_WIDTH },
6798 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
6799 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_97_WIDTH },
6800 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
6801 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_98_WIDTH },
6802 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
6803 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_99_WIDTH },
6804 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
6805 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_100_WIDTH },
6806 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
6807 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_101_WIDTH },
6808 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
6809 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_102_WIDTH },
6810 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
6811 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_103_WIDTH },
6812 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
6813 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_104_WIDTH },
6814 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
6815 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_105_WIDTH },
6816 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
6817 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_106_WIDTH },
6818 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
6819 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_107_WIDTH },
6820 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
6821 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_108_WIDTH },
6822 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
6823 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_109_WIDTH },
6824 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
6825 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_110_WIDTH },
6826 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
6827 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_111_WIDTH },
6828 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
6829 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_112_WIDTH },
6830 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
6831 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_113_WIDTH },
6832 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
6833 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_114_WIDTH },
6834 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
6835 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_115_WIDTH },
6836 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
6837 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_116_WIDTH },
6838 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
6839 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_117_WIDTH },
6840 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
6841 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_118_WIDTH },
6842 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
6843 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_119_WIDTH },
6844 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
6845 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_120_WIDTH },
6846 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
6847 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_121_WIDTH },
6848 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
6849 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_122_WIDTH },
6850 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
6851 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_123_WIDTH },
6852 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
6853 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_124_WIDTH },
6854 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
6855 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_125_WIDTH },
6856 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
6857 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_126_WIDTH },
6858 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
6859 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_127_WIDTH },
6860 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
6861 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_128_WIDTH },
6862 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
6863 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_129_WIDTH },
6864 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
6865 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_GROUP_130_WIDTH },
6875 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6876 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
6877 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6878 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
6879 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6880 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
6881 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6882 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
6883 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6884 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
6885 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6886 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
6887 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6888 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
6889 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6890 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
6891 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6892 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
6893 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6894 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
6904 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6905 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_0_WIDTH },
6906 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6907 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_1_WIDTH },
6908 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6909 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_2_WIDTH },
6910 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6911 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_3_WIDTH },
6912 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6913 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_4_WIDTH },
6914 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6915 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_5_WIDTH },
6916 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6917 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_GROUP_6_WIDTH },
6927 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
6928 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_0_WIDTH },
6929 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
6930 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_1_WIDTH },
6931 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
6932 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_2_WIDTH },
6933 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
6934 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_3_WIDTH },
6935 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
6936 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_4_WIDTH },
6937 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
6938 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_5_WIDTH },
6939 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
6940 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_6_WIDTH },
6941 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
6942 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_7_WIDTH },
6943 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
6944 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_8_WIDTH },
6945 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
6946 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_9_WIDTH },
6947 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
6948 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_10_WIDTH },
6949 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
6950 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_11_WIDTH },
6951 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
6952 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_12_WIDTH },
6953 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
6954 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_13_WIDTH },
6955 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
6956 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_14_WIDTH },
6957 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
6958 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_15_WIDTH },
6959 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
6960 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_16_WIDTH },
6961 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
6962 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_17_WIDTH },
6963 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
6964 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_18_WIDTH },
6965 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
6966 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_19_WIDTH },
6967 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
6968 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_20_WIDTH },
6969 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
6970 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_21_WIDTH },
6971 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
6972 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_22_WIDTH },
6973 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
6974 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_23_WIDTH },
6975 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
6976 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_24_WIDTH },
6977 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
6978 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_25_WIDTH },
6979 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
6980 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_26_WIDTH },
6981 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
6982 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_27_WIDTH },
6983 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
6984 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_28_WIDTH },
6985 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
6986 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_29_WIDTH },
6987 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
6988 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_30_WIDTH },
6989 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
6990 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_31_WIDTH },
6991 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
6992 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_32_WIDTH },
6993 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
6994 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_33_WIDTH },
6995 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
6996 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_34_WIDTH },
6997 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
6998 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_35_WIDTH },
6999 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7000 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_36_WIDTH },
7001 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7002 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_37_WIDTH },
7003 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7004 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_38_WIDTH },
7005 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7006 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_39_WIDTH },
7007 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7008 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_40_WIDTH },
7009 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7010 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_41_WIDTH },
7011 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7012 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_42_WIDTH },
7013 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7014 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_43_WIDTH },
7015 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7016 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_44_WIDTH },
7017 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7018 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_45_WIDTH },
7019 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7020 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_46_WIDTH },
7021 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7022 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_47_WIDTH },
7023 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7024 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_48_WIDTH },
7025 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7026 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_49_WIDTH },
7027 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7028 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_50_WIDTH },
7029 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7030 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_51_WIDTH },
7031 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7032 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_52_WIDTH },
7033 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7034 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_53_WIDTH },
7035 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7036 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_54_WIDTH },
7037 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7038 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_55_WIDTH },
7039 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7040 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_56_WIDTH },
7041 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7042 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_57_WIDTH },
7043 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7044 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_58_WIDTH },
7045 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7046 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_59_WIDTH },
7047 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7048 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_60_WIDTH },
7049 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7050 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_61_WIDTH },
7051 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7052 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_62_WIDTH },
7053 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7054 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_63_WIDTH },
7055 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7056 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_64_WIDTH },
7057 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7058 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_65_WIDTH },
7059 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7060 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_66_WIDTH },
7061 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7062 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_67_WIDTH },
7063 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7064 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_68_WIDTH },
7065 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7066 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_69_WIDTH },
7067 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7068 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_70_WIDTH },
7069 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7070 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_71_WIDTH },
7071 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7072 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_72_WIDTH },
7073 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7074 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_73_WIDTH },
7075 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7076 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_74_WIDTH },
7077 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7078 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_75_WIDTH },
7079 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7080 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_76_WIDTH },
7081 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7082 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_77_WIDTH },
7083 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7084 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_78_WIDTH },
7085 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7086 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_79_WIDTH },
7087 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7088 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_80_WIDTH },
7089 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7090 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_81_WIDTH },
7091 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7092 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_82_WIDTH },
7093 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7094 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_83_WIDTH },
7095 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7096 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_84_WIDTH },
7097 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7098 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_85_WIDTH },
7099 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7100 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_86_WIDTH },
7101 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7102 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_87_WIDTH },
7103 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7104 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_88_WIDTH },
7105 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7106 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_89_WIDTH },
7107 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7108 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_GROUP_90_WIDTH },
7118 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7119 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_0_WIDTH },
7120 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7121 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_1_WIDTH },
7122 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7123 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_2_WIDTH },
7124 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7125 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_3_WIDTH },
7126 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7127 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_4_WIDTH },
7128 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7129 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_5_WIDTH },
7130 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7131 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_6_WIDTH },
7132 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7133 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_7_WIDTH },
7134 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7135 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_8_WIDTH },
7136 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7137 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_9_WIDTH },
7138 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7139 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_10_WIDTH },
7140 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7141 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_11_WIDTH },
7142 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7143 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_12_WIDTH },
7144 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7145 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_13_WIDTH },
7146 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7147 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_14_WIDTH },
7148 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7149 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_15_WIDTH },
7150 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7151 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_16_WIDTH },
7152 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7153 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_17_WIDTH },
7154 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7155 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_18_WIDTH },
7156 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7157 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_19_WIDTH },
7158 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7159 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_20_WIDTH },
7160 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7161 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_21_WIDTH },
7162 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7163 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_22_WIDTH },
7164 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7165 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_23_WIDTH },
7166 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7167 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_24_WIDTH },
7168 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7169 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_25_WIDTH },
7170 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7171 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_26_WIDTH },
7172 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7173 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_27_WIDTH },
7174 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7175 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_28_WIDTH },
7176 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7177 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_29_WIDTH },
7178 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7179 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_30_WIDTH },
7180 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7181 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_31_WIDTH },
7182 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7183 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_32_WIDTH },
7184 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7185 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_33_WIDTH },
7186 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7187 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_34_WIDTH },
7188 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7189 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_35_WIDTH },
7190 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7191 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_36_WIDTH },
7192 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7193 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_37_WIDTH },
7194 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7195 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_38_WIDTH },
7196 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7197 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_39_WIDTH },
7198 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7199 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_40_WIDTH },
7200 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7201 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_41_WIDTH },
7202 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7203 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_42_WIDTH },
7204 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7205 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_43_WIDTH },
7206 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7207 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_44_WIDTH },
7208 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7209 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_45_WIDTH },
7210 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7211 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_46_WIDTH },
7212 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7213 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_47_WIDTH },
7214 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7215 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_48_WIDTH },
7216 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7217 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_49_WIDTH },
7218 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7219 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_50_WIDTH },
7220 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7221 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_51_WIDTH },
7222 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7223 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_52_WIDTH },
7224 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7225 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_53_WIDTH },
7226 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7227 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_54_WIDTH },
7228 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7229 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_55_WIDTH },
7230 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7231 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_56_WIDTH },
7232 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7233 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_57_WIDTH },
7234 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7235 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_58_WIDTH },
7236 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7237 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_59_WIDTH },
7238 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7239 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_60_WIDTH },
7240 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7241 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_GROUP_61_WIDTH },
7250 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID, 0u,
7251 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_SIZE, 4u,
7252 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ROW_WIDTH, ((bool)
false) },
7253 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID, 0u,
7254 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_SIZE, 4u,
7255 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ROW_WIDTH, ((bool)
false) },
7256 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID, 0u,
7257 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_SIZE, 4u,
7258 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ROW_WIDTH, ((bool)
false) },
7259 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID, 0u,
7260 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
7261 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)
false) },
7262 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID, 0u,
7263 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
7264 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)
false) },
7265 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID, 0u,
7266 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_SIZE, 4u,
7267 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ROW_WIDTH, ((bool)
false) },
7268 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID, 0u,
7269 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_SIZE, 4u,
7270 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ROW_WIDTH, ((bool)
false) },
7271 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID, 0u,
7272 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_SIZE, 4u,
7273 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ROW_WIDTH, ((bool)
false) },
7274 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID, 0u,
7275 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_SIZE, 4u,
7276 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ROW_WIDTH, ((bool)
false) },
7277 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID, 0u,
7278 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_SIZE, 4u,
7279 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ROW_WIDTH, ((bool)
false) },
7280 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID, 0u,
7281 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_SIZE, 4u,
7282 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ROW_WIDTH, ((bool)
false) },
7283 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID, 0u,
7284 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_SIZE, 4u,
7285 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ROW_WIDTH, ((bool)
false) },
7294 { SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
7295 SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
7296 SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
7305 { SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
7306 SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
7307 SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
7316 { SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID, 0u,
7317 SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_SIZE, 4u,
7318 SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ROW_WIDTH, ((bool)
false) },
7328 { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_CHECKER_TYPE,
7329 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_0_WIDTH },
7330 { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_CHECKER_TYPE,
7331 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_1_WIDTH },
7332 { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_CHECKER_TYPE,
7333 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_2_WIDTH },
7334 { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_CHECKER_TYPE,
7335 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_GROUP_3_WIDTH },
7345 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7346 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_0_WIDTH },
7347 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7348 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_1_WIDTH },
7349 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7350 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_GROUP_2_WIDTH },
7360 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7361 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_0_WIDTH },
7362 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7363 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_1_WIDTH },
7364 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7365 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_2_WIDTH },
7366 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7367 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_3_WIDTH },
7368 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
7369 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_4_WIDTH },
7370 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
7371 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_5_WIDTH },
7372 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
7373 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_6_WIDTH },
7374 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
7375 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_7_WIDTH },
7376 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
7377 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_8_WIDTH },
7378 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
7379 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_9_WIDTH },
7380 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
7381 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_10_WIDTH },
7382 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
7383 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_11_WIDTH },
7384 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
7385 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_12_WIDTH },
7386 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
7387 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_13_WIDTH },
7388 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
7389 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_14_WIDTH },
7390 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
7391 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_15_WIDTH },
7392 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
7393 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_16_WIDTH },
7394 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
7395 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_17_WIDTH },
7396 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
7397 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_18_WIDTH },
7398 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
7399 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_19_WIDTH },
7400 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
7401 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_20_WIDTH },
7402 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
7403 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_21_WIDTH },
7404 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
7405 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_22_WIDTH },
7406 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
7407 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_23_WIDTH },
7408 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
7409 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_24_WIDTH },
7410 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
7411 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_25_WIDTH },
7412 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
7413 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_26_WIDTH },
7414 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
7415 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_27_WIDTH },
7416 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
7417 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_28_WIDTH },
7418 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
7419 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_29_WIDTH },
7420 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
7421 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_30_WIDTH },
7422 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
7423 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_31_WIDTH },
7424 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
7425 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_32_WIDTH },
7426 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
7427 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_33_WIDTH },
7428 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
7429 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_34_WIDTH },
7430 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
7431 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_35_WIDTH },
7432 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
7433 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_36_WIDTH },
7434 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
7435 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_37_WIDTH },
7436 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_CHECKER_TYPE,
7437 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_38_WIDTH },
7438 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_CHECKER_TYPE,
7439 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_39_WIDTH },
7440 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_CHECKER_TYPE,
7441 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_40_WIDTH },
7442 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_CHECKER_TYPE,
7443 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_41_WIDTH },
7444 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_CHECKER_TYPE,
7445 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_42_WIDTH },
7446 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_CHECKER_TYPE,
7447 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_43_WIDTH },
7448 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_CHECKER_TYPE,
7449 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_44_WIDTH },
7450 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_CHECKER_TYPE,
7451 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_45_WIDTH },
7452 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_CHECKER_TYPE,
7453 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_46_WIDTH },
7454 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_CHECKER_TYPE,
7455 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_47_WIDTH },
7456 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_CHECKER_TYPE,
7457 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_48_WIDTH },
7458 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_CHECKER_TYPE,
7459 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_49_WIDTH },
7460 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_CHECKER_TYPE,
7461 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_50_WIDTH },
7462 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_CHECKER_TYPE,
7463 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_51_WIDTH },
7464 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_CHECKER_TYPE,
7465 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_52_WIDTH },
7466 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_CHECKER_TYPE,
7467 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_53_WIDTH },
7468 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_CHECKER_TYPE,
7469 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_54_WIDTH },
7470 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_CHECKER_TYPE,
7471 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_55_WIDTH },
7472 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_CHECKER_TYPE,
7473 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_56_WIDTH },
7474 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_CHECKER_TYPE,
7475 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_57_WIDTH },
7476 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_CHECKER_TYPE,
7477 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_58_WIDTH },
7478 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_CHECKER_TYPE,
7479 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_59_WIDTH },
7480 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_CHECKER_TYPE,
7481 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_60_WIDTH },
7482 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_CHECKER_TYPE,
7483 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_61_WIDTH },
7484 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_CHECKER_TYPE,
7485 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_62_WIDTH },
7486 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_CHECKER_TYPE,
7487 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_63_WIDTH },
7488 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_CHECKER_TYPE,
7489 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_64_WIDTH },
7490 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_CHECKER_TYPE,
7491 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_65_WIDTH },
7492 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_CHECKER_TYPE,
7493 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_66_WIDTH },
7494 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_CHECKER_TYPE,
7495 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_67_WIDTH },
7496 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_CHECKER_TYPE,
7497 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_68_WIDTH },
7498 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_CHECKER_TYPE,
7499 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_69_WIDTH },
7500 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_CHECKER_TYPE,
7501 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_70_WIDTH },
7502 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_CHECKER_TYPE,
7503 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_71_WIDTH },
7504 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_CHECKER_TYPE,
7505 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_72_WIDTH },
7506 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_CHECKER_TYPE,
7507 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_73_WIDTH },
7508 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_CHECKER_TYPE,
7509 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_74_WIDTH },
7510 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_CHECKER_TYPE,
7511 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_75_WIDTH },
7512 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_CHECKER_TYPE,
7513 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_76_WIDTH },
7514 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_CHECKER_TYPE,
7515 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_77_WIDTH },
7516 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_CHECKER_TYPE,
7517 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_78_WIDTH },
7518 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_CHECKER_TYPE,
7519 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_79_WIDTH },
7520 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_CHECKER_TYPE,
7521 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_80_WIDTH },
7522 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_CHECKER_TYPE,
7523 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_81_WIDTH },
7524 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_CHECKER_TYPE,
7525 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_82_WIDTH },
7526 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_CHECKER_TYPE,
7527 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_83_WIDTH },
7528 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_CHECKER_TYPE,
7529 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_84_WIDTH },
7530 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_CHECKER_TYPE,
7531 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_85_WIDTH },
7532 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_CHECKER_TYPE,
7533 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_86_WIDTH },
7534 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_CHECKER_TYPE,
7535 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_87_WIDTH },
7536 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_CHECKER_TYPE,
7537 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_88_WIDTH },
7538 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_CHECKER_TYPE,
7539 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_89_WIDTH },
7540 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_CHECKER_TYPE,
7541 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_90_WIDTH },
7542 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_CHECKER_TYPE,
7543 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_91_WIDTH },
7544 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_CHECKER_TYPE,
7545 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_92_WIDTH },
7546 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_CHECKER_TYPE,
7547 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_93_WIDTH },
7548 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_CHECKER_TYPE,
7549 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_94_WIDTH },
7550 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_CHECKER_TYPE,
7551 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_95_WIDTH },
7552 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_CHECKER_TYPE,
7553 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_96_WIDTH },
7554 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_CHECKER_TYPE,
7555 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_97_WIDTH },
7556 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_CHECKER_TYPE,
7557 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_98_WIDTH },
7558 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_CHECKER_TYPE,
7559 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_99_WIDTH },
7560 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_CHECKER_TYPE,
7561 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_100_WIDTH },
7562 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_CHECKER_TYPE,
7563 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_101_WIDTH },
7564 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_CHECKER_TYPE,
7565 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_102_WIDTH },
7566 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_CHECKER_TYPE,
7567 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_103_WIDTH },
7568 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_CHECKER_TYPE,
7569 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_104_WIDTH },
7570 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_CHECKER_TYPE,
7571 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_105_WIDTH },
7572 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_CHECKER_TYPE,
7573 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_106_WIDTH },
7574 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_CHECKER_TYPE,
7575 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_107_WIDTH },
7576 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_CHECKER_TYPE,
7577 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_108_WIDTH },
7578 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_CHECKER_TYPE,
7579 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_109_WIDTH },
7580 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_CHECKER_TYPE,
7581 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_110_WIDTH },
7582 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_CHECKER_TYPE,
7583 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_111_WIDTH },
7584 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_CHECKER_TYPE,
7585 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_112_WIDTH },
7586 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_CHECKER_TYPE,
7587 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_113_WIDTH },
7588 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_CHECKER_TYPE,
7589 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_114_WIDTH },
7590 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_CHECKER_TYPE,
7591 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_115_WIDTH },
7592 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_CHECKER_TYPE,
7593 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_116_WIDTH },
7594 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_CHECKER_TYPE,
7595 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_117_WIDTH },
7596 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_CHECKER_TYPE,
7597 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_118_WIDTH },
7598 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_CHECKER_TYPE,
7599 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_119_WIDTH },
7600 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_CHECKER_TYPE,
7601 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_120_WIDTH },
7602 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_CHECKER_TYPE,
7603 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_121_WIDTH },
7604 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_CHECKER_TYPE,
7605 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_122_WIDTH },
7606 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_CHECKER_TYPE,
7607 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_123_WIDTH },
7608 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_CHECKER_TYPE,
7609 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_124_WIDTH },
7610 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_CHECKER_TYPE,
7611 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_125_WIDTH },
7612 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_CHECKER_TYPE,
7613 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_126_WIDTH },
7614 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_CHECKER_TYPE,
7615 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_127_WIDTH },
7616 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_CHECKER_TYPE,
7617 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_128_WIDTH },
7618 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_CHECKER_TYPE,
7619 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_129_WIDTH },
7620 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_CHECKER_TYPE,
7621 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_130_WIDTH },
7622 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_CHECKER_TYPE,
7623 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_131_WIDTH },
7624 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_CHECKER_TYPE,
7625 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_132_WIDTH },
7626 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_CHECKER_TYPE,
7627 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_133_WIDTH },
7628 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_CHECKER_TYPE,
7629 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_134_WIDTH },
7630 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_CHECKER_TYPE,
7631 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_135_WIDTH },
7632 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_CHECKER_TYPE,
7633 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_136_WIDTH },
7634 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_CHECKER_TYPE,
7635 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_137_WIDTH },
7636 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_CHECKER_TYPE,
7637 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_138_WIDTH },
7638 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_CHECKER_TYPE,
7639 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_139_WIDTH },
7640 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_CHECKER_TYPE,
7641 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_140_WIDTH },
7642 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_CHECKER_TYPE,
7643 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_141_WIDTH },
7644 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_CHECKER_TYPE,
7645 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_142_WIDTH },
7646 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_CHECKER_TYPE,
7647 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_143_WIDTH },
7648 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_CHECKER_TYPE,
7649 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_144_WIDTH },
7650 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_CHECKER_TYPE,
7651 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_145_WIDTH },
7652 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_CHECKER_TYPE,
7653 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_146_WIDTH },
7654 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_CHECKER_TYPE,
7655 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_147_WIDTH },
7656 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_CHECKER_TYPE,
7657 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_148_WIDTH },
7658 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_CHECKER_TYPE,
7659 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_149_WIDTH },
7660 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_CHECKER_TYPE,
7661 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_150_WIDTH },
7662 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_CHECKER_TYPE,
7663 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_151_WIDTH },
7664 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_CHECKER_TYPE,
7665 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_152_WIDTH },
7666 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_CHECKER_TYPE,
7667 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_153_WIDTH },
7668 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_CHECKER_TYPE,
7669 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_154_WIDTH },
7670 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_CHECKER_TYPE,
7671 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_155_WIDTH },
7672 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_CHECKER_TYPE,
7673 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_156_WIDTH },
7674 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_CHECKER_TYPE,
7675 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_157_WIDTH },
7676 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_CHECKER_TYPE,
7677 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_158_WIDTH },
7678 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_CHECKER_TYPE,
7679 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_159_WIDTH },
7680 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_CHECKER_TYPE,
7681 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_160_WIDTH },
7682 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_CHECKER_TYPE,
7683 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_161_WIDTH },
7684 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_CHECKER_TYPE,
7685 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_162_WIDTH },
7686 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_CHECKER_TYPE,
7687 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_163_WIDTH },
7688 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_CHECKER_TYPE,
7689 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_164_WIDTH },
7690 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_CHECKER_TYPE,
7691 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_165_WIDTH },
7692 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_CHECKER_TYPE,
7693 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_166_WIDTH },
7694 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_CHECKER_TYPE,
7695 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_GROUP_167_WIDTH },
7705 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7706 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
7707 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
7708 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_1_WIDTH },
7709 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
7710 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_2_WIDTH },
7711 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
7712 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_GROUP_3_WIDTH },
7722 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7723 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_GROUP_0_WIDTH },
7733 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
7734 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_GROUP_0_WIDTH },
7744 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_CHECKER_TYPE,
7745 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_0_WIDTH },
7746 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_CHECKER_TYPE,
7747 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_1_WIDTH },
7748 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_CHECKER_TYPE,
7749 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_2_WIDTH },
7750 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_CHECKER_TYPE,
7751 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_3_WIDTH },
7752 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_CHECKER_TYPE,
7753 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_4_WIDTH },
7754 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_CHECKER_TYPE,
7755 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_5_WIDTH },
7756 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_CHECKER_TYPE,
7757 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_6_WIDTH },
7758 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_CHECKER_TYPE,
7759 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_7_WIDTH },
7760 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_CHECKER_TYPE,
7761 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_8_WIDTH },
7762 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_CHECKER_TYPE,
7763 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_9_WIDTH },
7764 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_CHECKER_TYPE,
7765 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_10_WIDTH },
7766 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_CHECKER_TYPE,
7767 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_11_WIDTH },
7768 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_CHECKER_TYPE,
7769 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_12_WIDTH },
7770 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_CHECKER_TYPE,
7771 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_13_WIDTH },
7772 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_CHECKER_TYPE,
7773 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_14_WIDTH },
7774 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_CHECKER_TYPE,
7775 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_GROUP_15_WIDTH },
7784 { SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
7785 SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
7786 SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
7795 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID, 0u,
7796 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_SIZE, 4u,
7797 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ROW_WIDTH, ((bool)
false) },
7798 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_RAM_ID, 0u,
7799 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_RAM_SIZE, 4u,
7800 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_ROW_WIDTH, ((bool)
false) },
7801 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_RAM_ID, 0u,
7802 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_RAM_SIZE, 4u,
7803 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_ROW_WIDTH, ((bool)
false) },
7804 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_RAM_ID, 0u,
7805 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_RAM_SIZE, 4u,
7806 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_ROW_WIDTH, ((bool)
false) },
7807 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_RAM_ID, 0u,
7808 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_RAM_SIZE, 4u,
7809 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_ROW_WIDTH, ((bool)
false) },
7810 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_RAM_ID, 0u,
7811 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_RAM_SIZE, 4u,
7812 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_ROW_WIDTH, ((bool)
false) },
7813 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_RAM_ID, 0u,
7814 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_RAM_SIZE, 4u,
7815 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_ROW_WIDTH, ((bool)
false) },
7816 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID, 0u,
7817 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_SIZE, 4u,
7818 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ROW_WIDTH, ((bool)
false) },
7827 { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID, 0u,
7828 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_SIZE, 4u,
7829 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ROW_WIDTH, ((bool)
false) },
7838 { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID, 0u,
7839 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_SIZE, 4u,
7840 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ROW_WIDTH, ((bool)
false) },
7849 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_ID, 0u,
7850 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_SIZE, 4u,
7851 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
7852 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_ID, 0u,
7853 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_SIZE, 4u,
7854 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
7855 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
7856 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
7857 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
7858 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID, 0u,
7859 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_SIZE, 4u,
7860 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
7869 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID, 0u,
7870 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_SIZE, 4u,
7871 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ROW_WIDTH, ((bool)
false) },
7881 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
7882 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
7883 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
7884 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
7894 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
7895 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
7896 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
7897 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
7907 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
7908 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_0_WIDTH },
7909 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
7910 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_1_WIDTH },
7911 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
7912 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_2_WIDTH },
7913 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
7914 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_3_WIDTH },
7915 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
7916 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_4_WIDTH },
7917 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
7918 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_5_WIDTH },
7919 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
7920 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_6_WIDTH },
7921 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
7922 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_7_WIDTH },
7923 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
7924 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_8_WIDTH },
7925 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
7926 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_9_WIDTH },
7927 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
7928 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_10_WIDTH },
7929 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
7930 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_11_WIDTH },
7931 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
7932 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_12_WIDTH },
7933 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
7934 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_13_WIDTH },
7935 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
7936 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_14_WIDTH },
7937 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
7938 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_15_WIDTH },
7939 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
7940 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_16_WIDTH },
7941 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
7942 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_17_WIDTH },
7943 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
7944 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_18_WIDTH },
7945 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
7946 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_19_WIDTH },
7947 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
7948 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_20_WIDTH },
7949 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
7950 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_21_WIDTH },
7951 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
7952 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_22_WIDTH },
7953 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
7954 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_23_WIDTH },
7955 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
7956 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_24_WIDTH },
7957 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
7958 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_25_WIDTH },
7959 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
7960 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_26_WIDTH },
7961 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
7962 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_27_WIDTH },
7963 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
7964 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_28_WIDTH },
7965 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
7966 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_29_WIDTH },
7967 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
7968 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_30_WIDTH },
7969 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
7970 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_31_WIDTH },
7971 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
7972 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_32_WIDTH },
7973 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
7974 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_33_WIDTH },
7975 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
7976 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_34_WIDTH },
7977 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
7978 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_35_WIDTH },
7979 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
7980 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_36_WIDTH },
7981 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
7982 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_37_WIDTH },
7983 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
7984 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_38_WIDTH },
7985 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
7986 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_39_WIDTH },
7987 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
7988 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_40_WIDTH },
7989 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
7990 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_41_WIDTH },
7991 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
7992 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_42_WIDTH },
7993 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
7994 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_43_WIDTH },
7995 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
7996 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_44_WIDTH },
7997 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
7998 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_45_WIDTH },
7999 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
8000 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_46_WIDTH },
8001 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
8002 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_47_WIDTH },
8003 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
8004 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_48_WIDTH },
8005 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
8006 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_49_WIDTH },
8007 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
8008 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_50_WIDTH },
8009 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
8010 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_51_WIDTH },
8011 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_CHECKER_TYPE,
8012 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_52_WIDTH },
8013 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_CHECKER_TYPE,
8014 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_53_WIDTH },
8015 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_CHECKER_TYPE,
8016 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_54_WIDTH },
8017 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_CHECKER_TYPE,
8018 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_55_WIDTH },
8019 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_CHECKER_TYPE,
8020 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_56_WIDTH },
8021 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_CHECKER_TYPE,
8022 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_57_WIDTH },
8023 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_CHECKER_TYPE,
8024 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_58_WIDTH },
8025 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_CHECKER_TYPE,
8026 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_59_WIDTH },
8027 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_CHECKER_TYPE,
8028 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_60_WIDTH },
8029 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_CHECKER_TYPE,
8030 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_GROUP_61_WIDTH },
8040 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8041 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8042 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8043 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8044 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8045 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8046 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8047 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8048 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
8049 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
8050 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
8051 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
8052 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
8053 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
8054 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
8055 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
8056 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
8057 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
8058 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
8059 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
8060 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
8061 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
8062 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
8063 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
8064 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
8065 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
8066 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
8067 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
8068 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
8069 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
8070 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
8071 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
8072 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
8073 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
8074 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
8075 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
8076 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
8077 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
8078 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
8079 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
8080 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
8081 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
8082 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
8083 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
8084 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
8085 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
8086 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
8087 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
8088 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
8089 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
8090 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
8091 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
8092 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
8093 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
8094 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
8095 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
8096 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
8097 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
8098 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
8099 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
8100 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
8101 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
8102 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
8103 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
8104 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
8105 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
8106 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
8107 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
8108 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
8109 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
8110 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
8111 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
8112 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
8113 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
8114 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
8115 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
8116 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
8117 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
8118 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
8119 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
8120 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
8121 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
8122 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
8123 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
8124 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
8125 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
8126 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
8127 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
8128 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
8129 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
8130 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
8131 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
8132 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
8133 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
8134 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
8135 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
8136 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
8137 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
8138 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
8139 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
8140 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
8141 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
8142 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
8143 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
8144 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
8145 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
8146 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
8147 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
8148 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
8149 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
8150 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
8151 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
8152 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
8153 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
8154 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
8155 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
8156 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
8157 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
8158 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
8159 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
8160 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
8161 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
8162 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
8163 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
8164 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
8165 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
8166 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
8167 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
8168 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
8169 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
8170 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
8171 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
8172 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
8173 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
8174 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
8175 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
8176 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
8177 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
8178 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
8179 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
8180 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
8181 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
8182 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
8183 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
8184 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
8185 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
8186 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
8187 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
8197 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8198 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8199 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8200 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8201 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8202 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8203 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8204 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8205 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
8206 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
8207 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
8208 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
8209 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
8210 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
8211 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
8212 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
8213 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
8214 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
8215 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
8216 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
8217 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
8218 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
8219 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
8220 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
8221 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
8222 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
8223 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
8224 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
8225 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
8226 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
8227 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
8228 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
8229 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
8230 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
8231 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
8232 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
8233 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
8234 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
8235 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
8236 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
8237 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
8238 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
8239 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
8240 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
8241 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
8242 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
8243 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
8244 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
8245 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
8246 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
8247 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
8248 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
8249 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
8250 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
8251 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
8252 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
8253 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
8254 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
8255 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
8256 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
8257 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
8258 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
8259 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
8260 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
8261 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
8262 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
8263 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
8264 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
8265 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
8266 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
8267 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
8268 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
8269 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
8270 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
8271 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
8272 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
8273 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
8274 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
8275 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
8276 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
8277 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
8278 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
8279 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
8280 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
8281 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
8282 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
8283 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
8284 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
8285 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
8286 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
8287 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
8288 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
8289 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
8290 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
8291 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
8292 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
8293 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
8294 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
8295 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
8296 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
8297 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
8298 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
8299 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
8300 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
8301 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
8302 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
8303 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
8304 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
8305 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
8306 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
8307 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
8308 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
8309 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
8310 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
8311 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
8312 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
8313 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
8314 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
8315 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
8316 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
8317 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
8318 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
8319 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
8320 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
8321 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
8322 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
8323 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
8324 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
8325 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
8326 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
8327 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
8328 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
8329 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
8330 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
8331 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
8332 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
8333 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
8334 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
8335 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
8336 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
8337 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
8338 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
8339 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
8340 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
8341 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
8342 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
8343 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
8344 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
8345 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
8346 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
8347 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
8348 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
8358 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
8359 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
8360 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
8361 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
8362 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
8363 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
8364 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
8365 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
8366 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
8367 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
8368 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
8369 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
8370 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
8371 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
8372 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
8373 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
8374 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
8375 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
8376 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
8377 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
8378 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
8379 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
8380 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
8381 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
8382 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_CHECKER_TYPE,
8383 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_12_WIDTH },
8384 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_CHECKER_TYPE,
8385 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_13_WIDTH },
8386 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_CHECKER_TYPE,
8387 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_14_WIDTH },
8388 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_CHECKER_TYPE,
8389 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_15_WIDTH },
8390 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_CHECKER_TYPE,
8391 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_16_WIDTH },
8392 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_CHECKER_TYPE,
8393 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_17_WIDTH },
8394 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_CHECKER_TYPE,
8395 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_18_WIDTH },
8396 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_CHECKER_TYPE,
8397 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_19_WIDTH },
8398 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_CHECKER_TYPE,
8399 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_20_WIDTH },
8400 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_CHECKER_TYPE,
8401 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_21_WIDTH },
8402 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_CHECKER_TYPE,
8403 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_22_WIDTH },
8404 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_CHECKER_TYPE,
8405 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_23_WIDTH },
8406 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_CHECKER_TYPE,
8407 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_24_WIDTH },
8408 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_CHECKER_TYPE,
8409 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_25_WIDTH },
8419 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
8420 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
8421 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
8422 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
8423 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
8424 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
8425 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
8426 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
8427 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
8428 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
8429 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
8430 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
8431 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
8432 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
8433 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
8434 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
8435 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
8436 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
8437 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
8438 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
8439 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
8440 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
8441 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
8442 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
8443 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
8444 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
8445 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
8446 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
8447 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
8448 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
8458 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
8459 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
8460 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
8461 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
8462 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
8463 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
8464 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
8465 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
8475 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_CHECKER_TYPE,
8476 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_0_WIDTH },
8477 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_CHECKER_TYPE,
8478 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_1_WIDTH },
8479 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_CHECKER_TYPE,
8480 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_2_WIDTH },
8481 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_CHECKER_TYPE,
8482 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_3_WIDTH },
8483 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_CHECKER_TYPE,
8484 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_4_WIDTH },
8485 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_CHECKER_TYPE,
8486 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_5_WIDTH },
8487 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_CHECKER_TYPE,
8488 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_6_WIDTH },
8489 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_CHECKER_TYPE,
8490 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_7_WIDTH },
8491 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_CHECKER_TYPE,
8492 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_8_WIDTH },
8493 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_CHECKER_TYPE,
8494 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_9_WIDTH },
8495 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_CHECKER_TYPE,
8496 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_10_WIDTH },
8497 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_CHECKER_TYPE,
8498 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_GROUP_11_WIDTH },
8508 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8509 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8510 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8511 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8512 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8513 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8514 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8515 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8516 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
8517 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
8518 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
8519 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
8520 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
8521 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
8522 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
8523 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
8524 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
8525 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
8526 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
8527 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
8528 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
8529 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
8530 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
8531 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
8532 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
8533 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
8534 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
8535 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
8536 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
8537 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
8538 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
8539 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
8540 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
8541 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
8542 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
8543 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
8544 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
8545 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
8546 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
8547 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
8548 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
8549 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
8550 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
8551 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
8552 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
8553 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
8554 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
8555 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
8556 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
8557 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
8558 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
8559 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
8560 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
8561 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
8562 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
8563 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
8564 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
8565 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
8566 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
8567 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
8568 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
8569 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
8570 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
8571 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
8572 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
8573 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
8574 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
8575 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
8576 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
8577 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
8578 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
8579 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
8580 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
8581 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
8582 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
8583 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
8584 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
8585 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
8586 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
8587 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
8588 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
8589 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
8590 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
8591 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
8592 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
8593 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
8594 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
8595 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
8596 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
8597 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
8598 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
8599 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
8600 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
8601 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
8602 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
8603 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
8604 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
8605 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
8606 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
8607 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
8608 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
8609 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
8610 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
8611 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
8612 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
8613 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
8614 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
8615 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
8616 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
8617 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
8618 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
8619 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
8620 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
8621 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
8622 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
8623 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
8624 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
8625 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
8626 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
8627 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
8628 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
8629 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
8630 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
8631 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
8632 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
8633 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
8634 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
8635 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
8636 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
8637 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
8647 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8648 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8649 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8650 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8651 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8652 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8653 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8654 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8664 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8665 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8666 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8667 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8668 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8669 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8670 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8671 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8672 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
8673 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
8674 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
8675 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
8676 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
8677 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
8678 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
8679 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
8680 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
8681 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
8682 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
8683 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
8684 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
8685 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
8686 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
8687 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
8688 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
8689 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
8690 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
8691 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
8692 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
8693 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
8694 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
8695 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
8696 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
8697 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
8698 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
8699 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
8700 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
8701 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
8702 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
8703 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
8704 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
8705 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
8706 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
8707 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
8708 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
8709 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
8710 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
8711 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
8712 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
8713 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
8714 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
8715 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
8716 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
8717 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
8718 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
8719 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
8720 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
8721 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
8722 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
8723 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
8724 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
8725 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
8726 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
8727 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
8728 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
8729 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
8730 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
8731 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
8732 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
8733 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
8734 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
8735 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
8736 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
8737 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
8738 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
8739 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
8740 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
8741 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
8742 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
8743 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
8744 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
8745 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
8746 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
8747 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
8748 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
8749 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
8750 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
8751 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
8752 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
8753 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
8754 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
8755 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
8756 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
8757 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
8758 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
8759 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
8760 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
8761 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
8762 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
8763 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
8764 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
8765 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
8766 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
8767 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
8768 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
8769 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
8770 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
8771 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
8772 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
8773 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
8774 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
8775 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
8776 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
8777 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
8778 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
8779 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
8780 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
8781 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
8782 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
8783 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
8784 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
8785 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
8786 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
8787 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
8788 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
8789 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
8790 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
8791 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
8792 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
8793 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
8803 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
8804 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
8805 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
8806 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
8807 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
8808 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
8809 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
8810 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
8819 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
8820 SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
8821 SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)
false) },
8822 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
8823 SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
8824 SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)
false) },
8834 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
8835 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
8836 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
8837 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
8838 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
8839 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
8840 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
8841 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
8842 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
8843 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
8844 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
8845 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
8846 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
8847 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
8848 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
8849 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
8850 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
8851 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
8852 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
8853 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
8854 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
8855 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
8856 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
8857 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
8858 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
8859 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
8860 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
8861 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
8862 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
8863 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
8864 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
8865 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
8866 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
8867 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
8868 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
8869 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
8870 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
8871 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
8872 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
8873 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
8883 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
8884 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
8885 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
8886 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
8887 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
8888 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
8889 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
8890 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
8891 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
8892 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
8893 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
8894 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
8895 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
8896 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
8897 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
8898 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
8899 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
8900 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
8901 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
8902 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
8903 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
8904 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
8905 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
8906 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
8907 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
8908 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
8909 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
8910 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
8911 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
8912 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
8913 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
8914 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
8915 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
8916 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
8917 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
8918 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
8919 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
8920 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
8921 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
8922 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
8932 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_CHECKER_TYPE,
8933 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_0_WIDTH },
8934 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_CHECKER_TYPE,
8935 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_1_WIDTH },
8936 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_CHECKER_TYPE,
8937 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_2_WIDTH },
8938 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_CHECKER_TYPE,
8939 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_3_WIDTH },
8940 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_CHECKER_TYPE,
8941 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_4_WIDTH },
8942 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_CHECKER_TYPE,
8943 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_5_WIDTH },
8944 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_CHECKER_TYPE,
8945 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_6_WIDTH },
8946 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_CHECKER_TYPE,
8947 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_7_WIDTH },
8948 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_CHECKER_TYPE,
8949 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_8_WIDTH },
8950 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_CHECKER_TYPE,
8951 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_9_WIDTH },
8952 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_CHECKER_TYPE,
8953 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_10_WIDTH },
8954 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_CHECKER_TYPE,
8955 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_11_WIDTH },
8956 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_CHECKER_TYPE,
8957 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_12_WIDTH },
8958 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_CHECKER_TYPE,
8959 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_13_WIDTH },
8960 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_CHECKER_TYPE,
8961 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_14_WIDTH },
8962 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_CHECKER_TYPE,
8963 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_15_WIDTH },
8964 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_CHECKER_TYPE,
8965 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_16_WIDTH },
8966 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_CHECKER_TYPE,
8967 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_17_WIDTH },
8968 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_CHECKER_TYPE,
8969 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_18_WIDTH },
8970 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_CHECKER_TYPE,
8971 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_19_WIDTH },
8972 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_CHECKER_TYPE,
8973 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_20_WIDTH },
8974 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_CHECKER_TYPE,
8975 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_21_WIDTH },
8976 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_CHECKER_TYPE,
8977 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_22_WIDTH },
8978 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_CHECKER_TYPE,
8979 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_23_WIDTH },
8980 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_CHECKER_TYPE,
8981 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_24_WIDTH },
8982 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_CHECKER_TYPE,
8983 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_25_WIDTH },
8984 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_CHECKER_TYPE,
8985 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_26_WIDTH },
8986 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_CHECKER_TYPE,
8987 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_27_WIDTH },
8988 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_CHECKER_TYPE,
8989 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_28_WIDTH },
8990 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_CHECKER_TYPE,
8991 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_29_WIDTH },
8992 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_CHECKER_TYPE,
8993 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_30_WIDTH },
8994 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_CHECKER_TYPE,
8995 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_31_WIDTH },
8996 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_CHECKER_TYPE,
8997 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_32_WIDTH },
8998 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_CHECKER_TYPE,
8999 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_33_WIDTH },
9000 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_CHECKER_TYPE,
9001 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_34_WIDTH },
9002 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_CHECKER_TYPE,
9003 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_35_WIDTH },
9004 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_CHECKER_TYPE,
9005 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_36_WIDTH },
9006 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_CHECKER_TYPE,
9007 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_37_WIDTH },
9008 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_CHECKER_TYPE,
9009 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_38_WIDTH },
9010 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_CHECKER_TYPE,
9011 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_39_WIDTH },
9012 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_CHECKER_TYPE,
9013 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_40_WIDTH },
9014 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_CHECKER_TYPE,
9015 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_41_WIDTH },
9016 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_CHECKER_TYPE,
9017 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_42_WIDTH },
9018 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_CHECKER_TYPE,
9019 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_43_WIDTH },
9020 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_CHECKER_TYPE,
9021 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_44_WIDTH },
9022 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_CHECKER_TYPE,
9023 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_45_WIDTH },
9024 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_CHECKER_TYPE,
9025 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_46_WIDTH },
9026 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_CHECKER_TYPE,
9027 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_47_WIDTH },
9028 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_CHECKER_TYPE,
9029 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_48_WIDTH },
9030 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_CHECKER_TYPE,
9031 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_49_WIDTH },
9032 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_CHECKER_TYPE,
9033 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_50_WIDTH },
9034 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_CHECKER_TYPE,
9035 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_51_WIDTH },
9036 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_CHECKER_TYPE,
9037 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_52_WIDTH },
9038 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_CHECKER_TYPE,
9039 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_53_WIDTH },
9040 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_CHECKER_TYPE,
9041 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_54_WIDTH },
9042 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_CHECKER_TYPE,
9043 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_55_WIDTH },
9044 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_CHECKER_TYPE,
9045 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_56_WIDTH },
9046 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_CHECKER_TYPE,
9047 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_57_WIDTH },
9048 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_CHECKER_TYPE,
9049 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_58_WIDTH },
9050 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_CHECKER_TYPE,
9051 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_59_WIDTH },
9052 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_CHECKER_TYPE,
9053 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_60_WIDTH },
9054 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_CHECKER_TYPE,
9055 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_61_WIDTH },
9056 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_CHECKER_TYPE,
9057 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_62_WIDTH },
9058 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_CHECKER_TYPE,
9059 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_63_WIDTH },
9060 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_CHECKER_TYPE,
9061 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_64_WIDTH },
9062 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_CHECKER_TYPE,
9063 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_65_WIDTH },
9064 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_CHECKER_TYPE,
9065 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_66_WIDTH },
9066 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_CHECKER_TYPE,
9067 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_67_WIDTH },
9068 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_CHECKER_TYPE,
9069 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_68_WIDTH },
9070 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_CHECKER_TYPE,
9071 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_69_WIDTH },
9072 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_CHECKER_TYPE,
9073 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_70_WIDTH },
9074 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_CHECKER_TYPE,
9075 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_71_WIDTH },
9076 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_CHECKER_TYPE,
9077 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_72_WIDTH },
9078 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_CHECKER_TYPE,
9079 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_73_WIDTH },
9080 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_CHECKER_TYPE,
9081 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_74_WIDTH },
9082 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_CHECKER_TYPE,
9083 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_75_WIDTH },
9084 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_CHECKER_TYPE,
9085 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_76_WIDTH },
9086 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_CHECKER_TYPE,
9087 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_77_WIDTH },
9088 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_CHECKER_TYPE,
9089 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_78_WIDTH },
9090 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_CHECKER_TYPE,
9091 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_79_WIDTH },
9092 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_CHECKER_TYPE,
9093 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_80_WIDTH },
9094 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_CHECKER_TYPE,
9095 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_81_WIDTH },
9096 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_CHECKER_TYPE,
9097 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_82_WIDTH },
9098 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_CHECKER_TYPE,
9099 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_83_WIDTH },
9100 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_CHECKER_TYPE,
9101 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_84_WIDTH },
9102 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_CHECKER_TYPE,
9103 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_85_WIDTH },
9104 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_CHECKER_TYPE,
9105 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_86_WIDTH },
9106 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_CHECKER_TYPE,
9107 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_87_WIDTH },
9108 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_CHECKER_TYPE,
9109 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_88_WIDTH },
9110 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_CHECKER_TYPE,
9111 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_89_WIDTH },
9112 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_CHECKER_TYPE,
9113 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_90_WIDTH },
9114 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_CHECKER_TYPE,
9115 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_91_WIDTH },
9116 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_CHECKER_TYPE,
9117 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_92_WIDTH },
9118 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_CHECKER_TYPE,
9119 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_93_WIDTH },
9120 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_CHECKER_TYPE,
9121 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_94_WIDTH },
9122 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_CHECKER_TYPE,
9123 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_95_WIDTH },
9124 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_CHECKER_TYPE,
9125 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_96_WIDTH },
9126 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_CHECKER_TYPE,
9127 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_97_WIDTH },
9128 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_CHECKER_TYPE,
9129 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_98_WIDTH },
9130 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_CHECKER_TYPE,
9131 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_99_WIDTH },
9132 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_CHECKER_TYPE,
9133 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_100_WIDTH },
9134 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_CHECKER_TYPE,
9135 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_101_WIDTH },
9136 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_CHECKER_TYPE,
9137 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_102_WIDTH },
9138 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_CHECKER_TYPE,
9139 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_103_WIDTH },
9140 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_CHECKER_TYPE,
9141 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_104_WIDTH },
9142 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_CHECKER_TYPE,
9143 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_105_WIDTH },
9144 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_CHECKER_TYPE,
9145 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_106_WIDTH },
9146 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_CHECKER_TYPE,
9147 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_107_WIDTH },
9148 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_CHECKER_TYPE,
9149 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_108_WIDTH },
9150 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_CHECKER_TYPE,
9151 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_109_WIDTH },
9152 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_CHECKER_TYPE,
9153 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_110_WIDTH },
9154 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_CHECKER_TYPE,
9155 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_111_WIDTH },
9156 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_CHECKER_TYPE,
9157 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_112_WIDTH },
9158 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_CHECKER_TYPE,
9159 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_113_WIDTH },
9160 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_CHECKER_TYPE,
9161 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_114_WIDTH },
9162 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_CHECKER_TYPE,
9163 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_115_WIDTH },
9164 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_CHECKER_TYPE,
9165 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_116_WIDTH },
9166 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_CHECKER_TYPE,
9167 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_117_WIDTH },
9168 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_CHECKER_TYPE,
9169 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_118_WIDTH },
9170 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_CHECKER_TYPE,
9171 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_119_WIDTH },
9172 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_CHECKER_TYPE,
9173 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_120_WIDTH },
9174 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_CHECKER_TYPE,
9175 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_121_WIDTH },
9176 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_CHECKER_TYPE,
9177 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_122_WIDTH },
9178 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_CHECKER_TYPE,
9179 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_123_WIDTH },
9180 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_CHECKER_TYPE,
9181 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_124_WIDTH },
9182 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_CHECKER_TYPE,
9183 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_125_WIDTH },
9184 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_CHECKER_TYPE,
9185 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_126_WIDTH },
9186 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_CHECKER_TYPE,
9187 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_127_WIDTH },
9188 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_CHECKER_TYPE,
9189 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_128_WIDTH },
9190 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_CHECKER_TYPE,
9191 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_129_WIDTH },
9192 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_CHECKER_TYPE,
9193 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_130_WIDTH },
9194 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_CHECKER_TYPE,
9195 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_131_WIDTH },
9196 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_CHECKER_TYPE,
9197 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_132_WIDTH },
9198 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_CHECKER_TYPE,
9199 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_133_WIDTH },
9200 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_CHECKER_TYPE,
9201 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_134_WIDTH },
9202 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_CHECKER_TYPE,
9203 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_135_WIDTH },
9204 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_CHECKER_TYPE,
9205 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_136_WIDTH },
9206 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_CHECKER_TYPE,
9207 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_137_WIDTH },
9208 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_CHECKER_TYPE,
9209 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_138_WIDTH },
9210 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_CHECKER_TYPE,
9211 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_139_WIDTH },
9212 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_CHECKER_TYPE,
9213 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_140_WIDTH },
9214 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_CHECKER_TYPE,
9215 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_141_WIDTH },
9216 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_CHECKER_TYPE,
9217 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_142_WIDTH },
9218 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_CHECKER_TYPE,
9219 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_143_WIDTH },
9220 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_CHECKER_TYPE,
9221 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_144_WIDTH },
9222 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_CHECKER_TYPE,
9223 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_145_WIDTH },
9224 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_CHECKER_TYPE,
9225 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_146_WIDTH },
9226 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_CHECKER_TYPE,
9227 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_147_WIDTH },
9228 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_CHECKER_TYPE,
9229 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_148_WIDTH },
9230 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_CHECKER_TYPE,
9231 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_149_WIDTH },
9232 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_CHECKER_TYPE,
9233 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_150_WIDTH },
9234 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_CHECKER_TYPE,
9235 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_151_WIDTH },
9236 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_CHECKER_TYPE,
9237 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_152_WIDTH },
9238 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_CHECKER_TYPE,
9239 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_153_WIDTH },
9240 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_CHECKER_TYPE,
9241 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_154_WIDTH },
9242 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_CHECKER_TYPE,
9243 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_155_WIDTH },
9244 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_CHECKER_TYPE,
9245 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_156_WIDTH },
9246 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_CHECKER_TYPE,
9247 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_157_WIDTH },
9248 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_CHECKER_TYPE,
9249 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_158_WIDTH },
9250 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_CHECKER_TYPE,
9251 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_159_WIDTH },
9252 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_CHECKER_TYPE,
9253 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_160_WIDTH },
9254 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_CHECKER_TYPE,
9255 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_161_WIDTH },
9256 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_CHECKER_TYPE,
9257 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_162_WIDTH },
9258 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_CHECKER_TYPE,
9259 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_163_WIDTH },
9260 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_CHECKER_TYPE,
9261 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_164_WIDTH },
9262 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_CHECKER_TYPE,
9263 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_165_WIDTH },
9264 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_CHECKER_TYPE,
9265 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_166_WIDTH },
9266 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_CHECKER_TYPE,
9267 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_167_WIDTH },
9268 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_CHECKER_TYPE,
9269 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_168_WIDTH },
9270 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_CHECKER_TYPE,
9271 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_169_WIDTH },
9272 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_CHECKER_TYPE,
9273 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_170_WIDTH },
9274 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_CHECKER_TYPE,
9275 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_171_WIDTH },
9276 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_CHECKER_TYPE,
9277 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_172_WIDTH },
9278 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_CHECKER_TYPE,
9279 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_173_WIDTH },
9280 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_CHECKER_TYPE,
9281 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_174_WIDTH },
9282 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_CHECKER_TYPE,
9283 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_175_WIDTH },
9284 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_CHECKER_TYPE,
9285 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_176_WIDTH },
9286 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_CHECKER_TYPE,
9287 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_177_WIDTH },
9288 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_CHECKER_TYPE,
9289 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_178_WIDTH },
9290 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_CHECKER_TYPE,
9291 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_179_WIDTH },
9292 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_CHECKER_TYPE,
9293 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_180_WIDTH },
9294 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_CHECKER_TYPE,
9295 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_181_WIDTH },
9296 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_CHECKER_TYPE,
9297 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_182_WIDTH },
9298 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_CHECKER_TYPE,
9299 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_183_WIDTH },
9300 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_CHECKER_TYPE,
9301 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_184_WIDTH },
9302 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_CHECKER_TYPE,
9303 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_GROUP_185_WIDTH },
9313 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
9314 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
9315 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
9316 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
9317 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
9318 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
9319 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
9320 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
9321 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
9322 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
9323 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
9324 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
9325 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
9326 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
9327 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
9328 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
9329 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
9330 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
9331 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
9332 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
9333 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
9334 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
9335 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
9336 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
9337 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
9338 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
9348 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
9349 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
9350 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
9351 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
9352 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
9353 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
9354 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
9355 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
9356 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
9357 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
9358 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
9359 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
9360 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
9361 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
9362 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
9363 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
9364 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
9365 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
9366 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
9367 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
9368 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
9369 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
9370 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
9371 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
9372 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
9373 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
9374 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
9375 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
9376 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
9377 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
9378 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
9379 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
9380 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
9381 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
9382 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
9383 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
9384 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
9385 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
9386 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
9387 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
9388 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
9389 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
9390 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
9391 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
9392 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
9393 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
9394 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
9395 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
9396 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
9397 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
9398 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
9399 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
9400 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
9401 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
9402 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
9403 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
9404 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
9405 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
9406 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
9407 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
9408 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
9409 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
9410 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
9411 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
9412 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
9413 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
9414 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
9415 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
9416 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
9417 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
9418 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
9419 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
9420 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
9421 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
9422 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
9423 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
9424 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
9425 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
9426 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
9427 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
9428 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
9429 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
9430 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
9431 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
9432 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
9433 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
9434 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
9435 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
9436 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
9437 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
9438 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
9439 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
9440 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
9441 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
9442 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
9443 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
9444 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
9445 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
9446 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
9447 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
9448 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
9449 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
9450 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
9451 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
9452 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
9453 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
9454 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
9455 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
9456 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
9457 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
9458 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
9459 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
9460 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
9461 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
9462 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
9463 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
9464 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
9465 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
9466 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
9467 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
9468 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
9469 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
9470 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
9471 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
9472 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
9473 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
9474 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
9475 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
9476 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
9477 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
9478 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
9479 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
9480 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
9481 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
9482 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
9483 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
9484 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
9485 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
9486 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
9487 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
9488 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
9489 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
9490 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
9491 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
9492 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
9493 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
9494 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
9495 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
9496 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
9497 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
9498 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
9499 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
9500 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
9501 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
9502 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
9503 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
9504 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
9505 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
9506 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
9507 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
9508 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
9509 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
9510 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
9511 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
9512 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
9513 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
9514 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
9515 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
9516 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
9517 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
9518 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
9519 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
9520 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
9521 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
9522 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
9523 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
9524 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
9525 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
9526 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
9527 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
9528 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
9529 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
9530 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
9531 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
9532 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
9533 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
9534 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
9535 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
9536 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
9537 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
9538 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
9539 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
9540 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
9541 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
9542 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
9543 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
9544 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
9545 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
9546 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
9547 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
9548 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
9549 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
9550 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
9551 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
9552 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
9553 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
9554 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
9555 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
9556 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
9557 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
9558 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
9559 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
9560 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
9561 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
9562 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
9563 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
9564 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
9565 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
9566 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
9567 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
9568 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
9569 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
9570 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
9571 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
9572 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
9573 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
9574 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
9575 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
9576 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
9577 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
9578 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
9579 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
9580 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
9581 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
9582 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
9583 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
9584 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
9585 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
9586 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
9587 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
9588 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
9589 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
9590 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
9591 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
9592 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
9593 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
9594 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
9595 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
9596 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
9597 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
9598 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
9599 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
9600 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
9601 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
9602 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
9603 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
9604 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
9605 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
9606 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
9607 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
9608 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
9609 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
9610 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
9611 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
9612 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
9613 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
9614 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
9615 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
9616 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
9617 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
9618 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
9619 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
9620 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
9621 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
9622 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
9623 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
9624 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
9625 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
9626 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
9627 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
9628 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
9629 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
9630 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
9631 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
9632 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
9633 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
9634 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
9635 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
9636 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
9637 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
9638 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
9639 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
9640 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
9641 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
9642 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
9643 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
9644 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
9645 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
9646 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
9647 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
9648 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
9649 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
9650 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
9651 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
9652 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
9653 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
9654 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
9655 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
9656 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
9657 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
9658 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
9659 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
9660 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
9661 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
9662 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
9663 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
9664 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
9665 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
9666 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
9667 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
9668 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
9669 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
9670 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
9671 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
9672 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
9673 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
9674 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
9675 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
9676 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
9677 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
9678 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
9679 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
9689 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
9690 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
9691 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
9692 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
9693 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
9694 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
9695 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
9696 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
9697 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
9698 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
9699 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
9700 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
9701 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
9702 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
9703 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
9704 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
9705 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
9706 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
9707 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
9708 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
9709 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
9710 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
9711 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
9712 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
9713 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
9714 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
9715 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
9716 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
9717 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
9718 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
9719 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
9720 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
9721 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
9722 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
9723 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
9724 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
9725 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
9726 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
9727 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
9728 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
9729 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
9730 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
9731 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
9732 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
9733 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
9734 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
9735 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
9736 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
9737 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
9738 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
9739 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
9740 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
9741 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
9742 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
9743 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
9744 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
9745 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
9746 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
9747 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
9748 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
9749 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
9750 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
9751 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
9752 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
9753 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
9754 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
9755 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
9756 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
9757 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
9758 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
9759 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
9760 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
9761 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
9762 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
9763 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
9764 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
9765 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
9766 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
9767 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
9768 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
9769 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
9770 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
9771 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
9772 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
9773 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
9774 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
9775 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
9776 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
9777 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
9778 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
9779 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
9780 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
9781 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
9782 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
9783 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
9784 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
9785 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
9786 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
9787 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
9788 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
9789 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
9790 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
9791 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
9792 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
9793 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
9794 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
9795 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
9796 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
9797 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
9798 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
9799 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
9800 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
9801 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
9802 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
9803 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
9804 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
9805 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
9806 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
9807 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
9808 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
9809 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
9810 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
9811 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
9812 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
9813 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
9814 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
9824 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
9825 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
9826 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
9827 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
9828 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
9829 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
9830 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
9831 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
9832 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
9833 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
9834 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
9835 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
9836 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
9837 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
9838 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
9839 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
9849 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
9850 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
9851 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
9852 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
9853 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
9854 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
9855 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
9856 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
9857 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
9858 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
9859 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
9860 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
9861 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
9862 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
9863 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
9864 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
9865 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
9866 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
9867 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
9868 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
9869 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
9870 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
9871 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
9872 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
9873 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
9874 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
9875 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
9876 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
9877 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
9878 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
9879 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
9880 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
9881 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
9882 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
9883 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
9884 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
9885 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
9886 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
9887 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
9888 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
9889 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
9890 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
9891 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
9892 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
9893 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
9894 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
9895 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
9896 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
9897 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
9898 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
9899 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
9900 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
9901 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
9902 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
9903 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
9904 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
9905 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
9906 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
9907 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
9908 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
9909 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
9910 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
9911 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
9912 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
9913 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
9914 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
9915 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
9916 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
9917 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
9918 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
9919 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
9920 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
9921 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
9922 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
9923 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
9924 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
9925 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
9926 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
9927 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
9928 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
9929 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
9930 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
9931 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
9932 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
9942 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
9943 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
9944 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
9945 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
9946 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
9947 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
9948 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
9949 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
9950 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
9951 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
9952 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
9953 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
9954 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
9955 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
9956 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
9957 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
9958 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
9959 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
9960 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
9961 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
9962 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
9963 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
9964 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
9965 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
9966 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
9967 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
9968 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
9969 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
9970 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
9971 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
9972 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
9973 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
9974 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
9975 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
9976 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
9977 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
9978 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
9979 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
9989 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
9990 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
9991 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
9992 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
9993 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
9994 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
9995 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
9996 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
9997 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
9998 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
9999 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
10000 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
10001 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
10002 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
10003 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
10004 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
10005 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
10006 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
10007 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
10008 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
10009 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
10010 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
10011 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
10012 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
10013 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
10014 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
10015 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
10016 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
10017 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
10018 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
10019 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
10020 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
10030 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
10031 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_0_WIDTH },
10032 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
10033 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_1_WIDTH },
10034 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
10035 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_2_WIDTH },
10036 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
10037 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_3_WIDTH },
10038 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
10039 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_4_WIDTH },
10040 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
10041 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_GROUP_5_WIDTH },
10050 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID, 0u,
10051 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_SIZE, 4u,
10052 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ROW_WIDTH, ((bool)
false) },
10053 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID, 0u,
10054 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_SIZE, 4u,
10055 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ROW_WIDTH, ((bool)
false) },
10065 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_CHECKER_TYPE,
10066 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_0_WIDTH },
10067 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_CHECKER_TYPE,
10068 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_1_WIDTH },
10069 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_CHECKER_TYPE,
10070 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_2_WIDTH },
10071 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_CHECKER_TYPE,
10072 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_3_WIDTH },
10073 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_CHECKER_TYPE,
10074 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_4_WIDTH },
10075 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_CHECKER_TYPE,
10076 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_5_WIDTH },
10077 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_CHECKER_TYPE,
10078 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_6_WIDTH },
10079 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_CHECKER_TYPE,
10080 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_7_WIDTH },
10081 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_CHECKER_TYPE,
10082 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_8_WIDTH },
10083 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_CHECKER_TYPE,
10084 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_9_WIDTH },
10085 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_CHECKER_TYPE,
10086 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_10_WIDTH },
10087 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_CHECKER_TYPE,
10088 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_11_WIDTH },
10089 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_CHECKER_TYPE,
10090 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_12_WIDTH },
10091 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_CHECKER_TYPE,
10092 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_13_WIDTH },
10093 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_CHECKER_TYPE,
10094 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_14_WIDTH },
10095 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_CHECKER_TYPE,
10096 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_15_WIDTH },
10097 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_CHECKER_TYPE,
10098 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_16_WIDTH },
10099 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_CHECKER_TYPE,
10100 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_17_WIDTH },
10101 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_CHECKER_TYPE,
10102 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_18_WIDTH },
10103 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_CHECKER_TYPE,
10104 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_GROUP_19_WIDTH },
10114 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_CHECKER_TYPE,
10115 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_0_WIDTH },
10116 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_CHECKER_TYPE,
10117 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_1_WIDTH },
10118 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_CHECKER_TYPE,
10119 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_2_WIDTH },
10120 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_CHECKER_TYPE,
10121 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_3_WIDTH },
10122 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_CHECKER_TYPE,
10123 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_4_WIDTH },
10124 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_CHECKER_TYPE,
10125 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_5_WIDTH },
10126 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_CHECKER_TYPE,
10127 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_6_WIDTH },
10128 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_CHECKER_TYPE,
10129 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_7_WIDTH },
10130 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_CHECKER_TYPE,
10131 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_8_WIDTH },
10132 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_CHECKER_TYPE,
10133 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_9_WIDTH },
10134 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_CHECKER_TYPE,
10135 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_10_WIDTH },
10136 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_CHECKER_TYPE,
10137 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_11_WIDTH },
10138 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_CHECKER_TYPE,
10139 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_12_WIDTH },
10140 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_CHECKER_TYPE,
10141 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_13_WIDTH },
10142 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_CHECKER_TYPE,
10143 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_14_WIDTH },
10144 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_CHECKER_TYPE,
10145 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_15_WIDTH },
10146 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_CHECKER_TYPE,
10147 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_16_WIDTH },
10148 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_CHECKER_TYPE,
10149 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_17_WIDTH },
10150 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_CHECKER_TYPE,
10151 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_18_WIDTH },
10152 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_CHECKER_TYPE,
10153 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_GROUP_19_WIDTH },
10163 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_CHECKER_TYPE,
10164 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_0_WIDTH },
10165 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_CHECKER_TYPE,
10166 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_1_WIDTH },
10167 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_CHECKER_TYPE,
10168 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_2_WIDTH },
10169 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_CHECKER_TYPE,
10170 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_3_WIDTH },
10171 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_CHECKER_TYPE,
10172 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_4_WIDTH },
10173 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_CHECKER_TYPE,
10174 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_5_WIDTH },
10175 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_CHECKER_TYPE,
10176 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_6_WIDTH },
10177 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_CHECKER_TYPE,
10178 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_7_WIDTH },
10179 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_CHECKER_TYPE,
10180 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_8_WIDTH },
10181 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_CHECKER_TYPE,
10182 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_9_WIDTH },
10183 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_CHECKER_TYPE,
10184 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_10_WIDTH },
10185 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_CHECKER_TYPE,
10186 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_11_WIDTH },
10187 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_CHECKER_TYPE,
10188 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_12_WIDTH },
10189 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_CHECKER_TYPE,
10190 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_13_WIDTH },
10191 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_CHECKER_TYPE,
10192 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_14_WIDTH },
10193 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_CHECKER_TYPE,
10194 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_15_WIDTH },
10195 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_CHECKER_TYPE,
10196 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_16_WIDTH },
10197 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_CHECKER_TYPE,
10198 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_17_WIDTH },
10199 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_CHECKER_TYPE,
10200 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_18_WIDTH },
10201 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_CHECKER_TYPE,
10202 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_19_WIDTH },
10203 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_CHECKER_TYPE,
10204 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_20_WIDTH },
10205 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_CHECKER_TYPE,
10206 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_21_WIDTH },
10207 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_CHECKER_TYPE,
10208 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_22_WIDTH },
10209 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_CHECKER_TYPE,
10210 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_23_WIDTH },
10211 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_CHECKER_TYPE,
10212 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_24_WIDTH },
10213 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_CHECKER_TYPE,
10214 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_25_WIDTH },
10215 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_CHECKER_TYPE,
10216 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_26_WIDTH },
10217 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_CHECKER_TYPE,
10218 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_27_WIDTH },
10219 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_CHECKER_TYPE,
10220 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_28_WIDTH },
10221 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_CHECKER_TYPE,
10222 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_29_WIDTH },
10223 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_CHECKER_TYPE,
10224 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_30_WIDTH },
10225 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_CHECKER_TYPE,
10226 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_31_WIDTH },
10227 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_CHECKER_TYPE,
10228 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_32_WIDTH },
10229 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_CHECKER_TYPE,
10230 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_33_WIDTH },
10231 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_CHECKER_TYPE,
10232 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_34_WIDTH },
10233 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_CHECKER_TYPE,
10234 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_35_WIDTH },
10235 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_CHECKER_TYPE,
10236 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_36_WIDTH },
10237 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_CHECKER_TYPE,
10238 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_37_WIDTH },
10239 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_CHECKER_TYPE,
10240 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_38_WIDTH },
10241 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_CHECKER_TYPE,
10242 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_39_WIDTH },
10243 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_CHECKER_TYPE,
10244 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_40_WIDTH },
10245 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_CHECKER_TYPE,
10246 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_41_WIDTH },
10247 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_CHECKER_TYPE,
10248 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_42_WIDTH },
10249 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_CHECKER_TYPE,
10250 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_43_WIDTH },
10251 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_CHECKER_TYPE,
10252 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_44_WIDTH },
10253 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_CHECKER_TYPE,
10254 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_45_WIDTH },
10255 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_CHECKER_TYPE,
10256 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_46_WIDTH },
10257 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_CHECKER_TYPE,
10258 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_47_WIDTH },
10259 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_CHECKER_TYPE,
10260 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_48_WIDTH },
10261 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_CHECKER_TYPE,
10262 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_49_WIDTH },
10263 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_CHECKER_TYPE,
10264 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_50_WIDTH },
10265 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_CHECKER_TYPE,
10266 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_51_WIDTH },
10267 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_CHECKER_TYPE,
10268 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_52_WIDTH },
10269 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_CHECKER_TYPE,
10270 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_53_WIDTH },
10271 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_CHECKER_TYPE,
10272 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_54_WIDTH },
10273 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_CHECKER_TYPE,
10274 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_55_WIDTH },
10275 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_CHECKER_TYPE,
10276 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_56_WIDTH },
10277 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_CHECKER_TYPE,
10278 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_57_WIDTH },
10279 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_CHECKER_TYPE,
10280 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_58_WIDTH },
10281 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_CHECKER_TYPE,
10282 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_59_WIDTH },
10283 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_CHECKER_TYPE,
10284 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_60_WIDTH },
10285 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_CHECKER_TYPE,
10286 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_61_WIDTH },
10287 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_CHECKER_TYPE,
10288 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_62_WIDTH },
10289 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_CHECKER_TYPE,
10290 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_63_WIDTH },
10291 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_CHECKER_TYPE,
10292 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_64_WIDTH },
10293 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_CHECKER_TYPE,
10294 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_65_WIDTH },
10295 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_CHECKER_TYPE,
10296 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_66_WIDTH },
10297 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_CHECKER_TYPE,
10298 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_67_WIDTH },
10299 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_CHECKER_TYPE,
10300 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_68_WIDTH },
10301 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_CHECKER_TYPE,
10302 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_69_WIDTH },
10303 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_CHECKER_TYPE,
10304 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_70_WIDTH },
10305 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_CHECKER_TYPE,
10306 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_71_WIDTH },
10307 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_CHECKER_TYPE,
10308 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_72_WIDTH },
10309 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_CHECKER_TYPE,
10310 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_73_WIDTH },
10311 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_CHECKER_TYPE,
10312 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_74_WIDTH },
10313 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_CHECKER_TYPE,
10314 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_75_WIDTH },
10315 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_CHECKER_TYPE,
10316 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_76_WIDTH },
10317 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_CHECKER_TYPE,
10318 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_77_WIDTH },
10319 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_CHECKER_TYPE,
10320 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_78_WIDTH },
10321 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_CHECKER_TYPE,
10322 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_79_WIDTH },
10323 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_CHECKER_TYPE,
10324 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_80_WIDTH },
10325 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_CHECKER_TYPE,
10326 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_81_WIDTH },
10327 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_CHECKER_TYPE,
10328 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_82_WIDTH },
10329 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_CHECKER_TYPE,
10330 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_83_WIDTH },
10331 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_CHECKER_TYPE,
10332 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_84_WIDTH },
10333 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_CHECKER_TYPE,
10334 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_85_WIDTH },
10335 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_CHECKER_TYPE,
10336 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_86_WIDTH },
10337 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_CHECKER_TYPE,
10338 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_87_WIDTH },
10339 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_CHECKER_TYPE,
10340 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_88_WIDTH },
10341 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_CHECKER_TYPE,
10342 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_89_WIDTH },
10343 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_CHECKER_TYPE,
10344 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_90_WIDTH },
10345 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_CHECKER_TYPE,
10346 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_91_WIDTH },
10347 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_CHECKER_TYPE,
10348 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_92_WIDTH },
10349 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_CHECKER_TYPE,
10350 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_93_WIDTH },
10351 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_CHECKER_TYPE,
10352 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_94_WIDTH },
10353 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_CHECKER_TYPE,
10354 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_95_WIDTH },
10355 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_CHECKER_TYPE,
10356 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_96_WIDTH },
10357 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_CHECKER_TYPE,
10358 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_97_WIDTH },
10359 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_CHECKER_TYPE,
10360 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_98_WIDTH },
10361 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_CHECKER_TYPE,
10362 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_99_WIDTH },
10363 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_CHECKER_TYPE,
10364 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_100_WIDTH },
10365 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_CHECKER_TYPE,
10366 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_101_WIDTH },
10367 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_CHECKER_TYPE,
10368 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_102_WIDTH },
10369 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_CHECKER_TYPE,
10370 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_103_WIDTH },
10371 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_CHECKER_TYPE,
10372 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_104_WIDTH },
10373 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_CHECKER_TYPE,
10374 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_105_WIDTH },
10375 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_CHECKER_TYPE,
10376 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_106_WIDTH },
10377 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_CHECKER_TYPE,
10378 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_107_WIDTH },
10379 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_CHECKER_TYPE,
10380 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_108_WIDTH },
10381 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_CHECKER_TYPE,
10382 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_109_WIDTH },
10383 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_CHECKER_TYPE,
10384 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_110_WIDTH },
10385 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_CHECKER_TYPE,
10386 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_111_WIDTH },
10387 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_CHECKER_TYPE,
10388 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_112_WIDTH },
10389 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_CHECKER_TYPE,
10390 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_113_WIDTH },
10391 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_CHECKER_TYPE,
10392 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_114_WIDTH },
10393 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_CHECKER_TYPE,
10394 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_115_WIDTH },
10395 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_CHECKER_TYPE,
10396 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_116_WIDTH },
10397 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_CHECKER_TYPE,
10398 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_117_WIDTH },
10399 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_CHECKER_TYPE,
10400 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_118_WIDTH },
10401 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_CHECKER_TYPE,
10402 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_119_WIDTH },
10403 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_CHECKER_TYPE,
10404 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_120_WIDTH },
10405 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_CHECKER_TYPE,
10406 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_121_WIDTH },
10407 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_CHECKER_TYPE,
10408 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_122_WIDTH },
10409 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_CHECKER_TYPE,
10410 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_123_WIDTH },
10411 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_CHECKER_TYPE,
10412 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_124_WIDTH },
10413 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_CHECKER_TYPE,
10414 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_125_WIDTH },
10415 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_CHECKER_TYPE,
10416 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_126_WIDTH },
10417 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_CHECKER_TYPE,
10418 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_127_WIDTH },
10419 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_CHECKER_TYPE,
10420 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_128_WIDTH },
10421 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_CHECKER_TYPE,
10422 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_129_WIDTH },
10423 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_CHECKER_TYPE,
10424 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_130_WIDTH },
10425 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_CHECKER_TYPE,
10426 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_131_WIDTH },
10427 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_CHECKER_TYPE,
10428 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_132_WIDTH },
10429 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_CHECKER_TYPE,
10430 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_133_WIDTH },
10431 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_CHECKER_TYPE,
10432 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_134_WIDTH },
10433 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_CHECKER_TYPE,
10434 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_135_WIDTH },
10435 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_CHECKER_TYPE,
10436 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_136_WIDTH },
10437 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_CHECKER_TYPE,
10438 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_137_WIDTH },
10439 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_CHECKER_TYPE,
10440 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_138_WIDTH },
10441 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_CHECKER_TYPE,
10442 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_139_WIDTH },
10443 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_CHECKER_TYPE,
10444 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_140_WIDTH },
10445 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_CHECKER_TYPE,
10446 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_141_WIDTH },
10447 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_CHECKER_TYPE,
10448 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_142_WIDTH },
10449 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_CHECKER_TYPE,
10450 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_143_WIDTH },
10451 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_CHECKER_TYPE,
10452 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_144_WIDTH },
10453 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_CHECKER_TYPE,
10454 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_145_WIDTH },
10455 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_CHECKER_TYPE,
10456 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_146_WIDTH },
10457 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_CHECKER_TYPE,
10458 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_147_WIDTH },
10459 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_CHECKER_TYPE,
10460 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_148_WIDTH },
10461 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_CHECKER_TYPE,
10462 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_149_WIDTH },
10463 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_CHECKER_TYPE,
10464 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_150_WIDTH },
10465 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_CHECKER_TYPE,
10466 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_151_WIDTH },
10467 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_CHECKER_TYPE,
10468 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_152_WIDTH },
10469 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_CHECKER_TYPE,
10470 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_153_WIDTH },
10471 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_CHECKER_TYPE,
10472 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_154_WIDTH },
10473 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_CHECKER_TYPE,
10474 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_155_WIDTH },
10475 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_CHECKER_TYPE,
10476 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_156_WIDTH },
10477 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_CHECKER_TYPE,
10478 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_157_WIDTH },
10479 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_CHECKER_TYPE,
10480 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_158_WIDTH },
10481 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_CHECKER_TYPE,
10482 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_159_WIDTH },
10483 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_CHECKER_TYPE,
10484 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_160_WIDTH },
10485 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_CHECKER_TYPE,
10486 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_161_WIDTH },
10487 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_CHECKER_TYPE,
10488 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_162_WIDTH },
10489 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_CHECKER_TYPE,
10490 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_163_WIDTH },
10491 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_CHECKER_TYPE,
10492 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_164_WIDTH },
10493 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_CHECKER_TYPE,
10494 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_165_WIDTH },
10495 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_CHECKER_TYPE,
10496 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_166_WIDTH },
10497 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_CHECKER_TYPE,
10498 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_167_WIDTH },
10499 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_CHECKER_TYPE,
10500 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_168_WIDTH },
10501 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_CHECKER_TYPE,
10502 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_169_WIDTH },
10503 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_CHECKER_TYPE,
10504 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_170_WIDTH },
10505 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_CHECKER_TYPE,
10506 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_171_WIDTH },
10507 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_CHECKER_TYPE,
10508 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_172_WIDTH },
10509 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_CHECKER_TYPE,
10510 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_173_WIDTH },
10511 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_CHECKER_TYPE,
10512 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_174_WIDTH },
10513 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_CHECKER_TYPE,
10514 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_175_WIDTH },
10515 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_CHECKER_TYPE,
10516 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_176_WIDTH },
10517 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_CHECKER_TYPE,
10518 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_177_WIDTH },
10519 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_CHECKER_TYPE,
10520 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_178_WIDTH },
10521 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_CHECKER_TYPE,
10522 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_179_WIDTH },
10523 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_CHECKER_TYPE,
10524 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_180_WIDTH },
10525 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_CHECKER_TYPE,
10526 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_181_WIDTH },
10527 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_CHECKER_TYPE,
10528 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_182_WIDTH },
10529 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_CHECKER_TYPE,
10530 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_183_WIDTH },
10531 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_CHECKER_TYPE,
10532 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_184_WIDTH },
10533 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_CHECKER_TYPE,
10534 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_185_WIDTH },
10535 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_CHECKER_TYPE,
10536 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_186_WIDTH },
10537 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_CHECKER_TYPE,
10538 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_187_WIDTH },
10539 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_CHECKER_TYPE,
10540 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_188_WIDTH },
10541 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_CHECKER_TYPE,
10542 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_189_WIDTH },
10543 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_CHECKER_TYPE,
10544 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_190_WIDTH },
10545 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_CHECKER_TYPE,
10546 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_191_WIDTH },
10547 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_CHECKER_TYPE,
10548 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_192_WIDTH },
10549 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_CHECKER_TYPE,
10550 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_193_WIDTH },
10551 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_CHECKER_TYPE,
10552 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_194_WIDTH },
10553 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_CHECKER_TYPE,
10554 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_195_WIDTH },
10555 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_CHECKER_TYPE,
10556 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_196_WIDTH },
10557 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_CHECKER_TYPE,
10558 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_197_WIDTH },
10559 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_CHECKER_TYPE,
10560 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_198_WIDTH },
10561 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_CHECKER_TYPE,
10562 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_199_WIDTH },
10563 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_CHECKER_TYPE,
10564 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_200_WIDTH },
10565 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_CHECKER_TYPE,
10566 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_201_WIDTH },
10567 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_CHECKER_TYPE,
10568 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_202_WIDTH },
10569 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_CHECKER_TYPE,
10570 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_203_WIDTH },
10571 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_CHECKER_TYPE,
10572 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_204_WIDTH },
10573 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_CHECKER_TYPE,
10574 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_205_WIDTH },
10575 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_CHECKER_TYPE,
10576 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_206_WIDTH },
10577 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_CHECKER_TYPE,
10578 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_207_WIDTH },
10579 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_CHECKER_TYPE,
10580 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_208_WIDTH },
10581 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_CHECKER_TYPE,
10582 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_209_WIDTH },
10583 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_CHECKER_TYPE,
10584 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_210_WIDTH },
10585 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_CHECKER_TYPE,
10586 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_211_WIDTH },
10587 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_CHECKER_TYPE,
10588 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_212_WIDTH },
10589 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_CHECKER_TYPE,
10590 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_213_WIDTH },
10591 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_CHECKER_TYPE,
10592 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_214_WIDTH },
10593 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_CHECKER_TYPE,
10594 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_215_WIDTH },
10595 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_CHECKER_TYPE,
10596 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_216_WIDTH },
10597 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_CHECKER_TYPE,
10598 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_217_WIDTH },
10599 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_CHECKER_TYPE,
10600 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_218_WIDTH },
10601 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_CHECKER_TYPE,
10602 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_219_WIDTH },
10603 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_CHECKER_TYPE,
10604 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_220_WIDTH },
10605 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_CHECKER_TYPE,
10606 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_221_WIDTH },
10607 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_CHECKER_TYPE,
10608 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_222_WIDTH },
10609 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_CHECKER_TYPE,
10610 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_223_WIDTH },
10611 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_CHECKER_TYPE,
10612 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_224_WIDTH },
10613 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_CHECKER_TYPE,
10614 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_225_WIDTH },
10615 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_CHECKER_TYPE,
10616 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_226_WIDTH },
10617 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_CHECKER_TYPE,
10618 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_227_WIDTH },
10619 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_CHECKER_TYPE,
10620 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_228_WIDTH },
10621 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_CHECKER_TYPE,
10622 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_229_WIDTH },
10623 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_CHECKER_TYPE,
10624 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_230_WIDTH },
10625 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_CHECKER_TYPE,
10626 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_231_WIDTH },
10627 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_CHECKER_TYPE,
10628 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_232_WIDTH },
10629 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_CHECKER_TYPE,
10630 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_233_WIDTH },
10631 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_CHECKER_TYPE,
10632 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_234_WIDTH },
10633 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_CHECKER_TYPE,
10634 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_235_WIDTH },
10635 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_CHECKER_TYPE,
10636 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_236_WIDTH },
10637 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_CHECKER_TYPE,
10638 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_237_WIDTH },
10639 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_CHECKER_TYPE,
10640 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_238_WIDTH },
10641 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_CHECKER_TYPE,
10642 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_239_WIDTH },
10643 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_CHECKER_TYPE,
10644 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_240_WIDTH },
10645 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_CHECKER_TYPE,
10646 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_241_WIDTH },
10647 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_CHECKER_TYPE,
10648 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_242_WIDTH },
10649 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_CHECKER_TYPE,
10650 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_243_WIDTH },
10651 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_CHECKER_TYPE,
10652 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_244_WIDTH },
10653 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_CHECKER_TYPE,
10654 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_245_WIDTH },
10655 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_CHECKER_TYPE,
10656 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_246_WIDTH },
10657 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_CHECKER_TYPE,
10658 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_247_WIDTH },
10659 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_CHECKER_TYPE,
10660 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_248_WIDTH },
10661 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_CHECKER_TYPE,
10662 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_249_WIDTH },
10663 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_CHECKER_TYPE,
10664 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_250_WIDTH },
10665 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_CHECKER_TYPE,
10666 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_251_WIDTH },
10667 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_CHECKER_TYPE,
10668 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_252_WIDTH },
10669 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_CHECKER_TYPE,
10670 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_253_WIDTH },
10671 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_CHECKER_TYPE,
10672 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_254_WIDTH },
10673 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_CHECKER_TYPE,
10674 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_GROUP_255_WIDTH },
10684 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_CHECKER_TYPE,
10685 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_0_WIDTH },
10686 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_CHECKER_TYPE,
10687 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_1_WIDTH },
10688 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_CHECKER_TYPE,
10689 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_2_WIDTH },
10690 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_CHECKER_TYPE,
10691 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_3_WIDTH },
10692 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_CHECKER_TYPE,
10693 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_4_WIDTH },
10694 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_CHECKER_TYPE,
10695 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_5_WIDTH },
10696 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_CHECKER_TYPE,
10697 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_6_WIDTH },
10698 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_CHECKER_TYPE,
10699 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_7_WIDTH },
10700 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_CHECKER_TYPE,
10701 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_8_WIDTH },
10702 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_CHECKER_TYPE,
10703 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_9_WIDTH },
10704 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_CHECKER_TYPE,
10705 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_10_WIDTH },
10706 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_CHECKER_TYPE,
10707 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_11_WIDTH },
10708 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_CHECKER_TYPE,
10709 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_12_WIDTH },
10710 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_CHECKER_TYPE,
10711 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_13_WIDTH },
10712 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_CHECKER_TYPE,
10713 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_14_WIDTH },
10714 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_CHECKER_TYPE,
10715 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_15_WIDTH },
10716 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_CHECKER_TYPE,
10717 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_16_WIDTH },
10718 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_CHECKER_TYPE,
10719 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_17_WIDTH },
10720 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_CHECKER_TYPE,
10721 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_18_WIDTH },
10722 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_CHECKER_TYPE,
10723 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_19_WIDTH },
10724 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_CHECKER_TYPE,
10725 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_20_WIDTH },
10726 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_CHECKER_TYPE,
10727 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_21_WIDTH },
10728 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_CHECKER_TYPE,
10729 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_22_WIDTH },
10730 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_CHECKER_TYPE,
10731 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_23_WIDTH },
10732 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_CHECKER_TYPE,
10733 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_24_WIDTH },
10734 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_CHECKER_TYPE,
10735 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_25_WIDTH },
10736 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_CHECKER_TYPE,
10737 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_26_WIDTH },
10738 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_CHECKER_TYPE,
10739 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_27_WIDTH },
10740 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_CHECKER_TYPE,
10741 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_28_WIDTH },
10742 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_CHECKER_TYPE,
10743 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_29_WIDTH },
10744 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_CHECKER_TYPE,
10745 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_30_WIDTH },
10746 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_CHECKER_TYPE,
10747 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_31_WIDTH },
10748 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_CHECKER_TYPE,
10749 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_32_WIDTH },
10750 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_CHECKER_TYPE,
10751 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_33_WIDTH },
10752 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_CHECKER_TYPE,
10753 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_34_WIDTH },
10754 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_CHECKER_TYPE,
10755 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_35_WIDTH },
10756 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_CHECKER_TYPE,
10757 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_36_WIDTH },
10758 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_CHECKER_TYPE,
10759 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_37_WIDTH },
10760 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_CHECKER_TYPE,
10761 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_38_WIDTH },
10762 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_CHECKER_TYPE,
10763 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_39_WIDTH },
10764 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_CHECKER_TYPE,
10765 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_40_WIDTH },
10766 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_CHECKER_TYPE,
10767 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_41_WIDTH },
10768 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_CHECKER_TYPE,
10769 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_42_WIDTH },
10770 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_CHECKER_TYPE,
10771 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_43_WIDTH },
10772 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_CHECKER_TYPE,
10773 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_44_WIDTH },
10774 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_CHECKER_TYPE,
10775 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_45_WIDTH },
10776 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_CHECKER_TYPE,
10777 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_46_WIDTH },
10778 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_CHECKER_TYPE,
10779 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_47_WIDTH },
10780 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_CHECKER_TYPE,
10781 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_48_WIDTH },
10782 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_CHECKER_TYPE,
10783 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_49_WIDTH },
10784 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_CHECKER_TYPE,
10785 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_50_WIDTH },
10786 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_CHECKER_TYPE,
10787 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_51_WIDTH },
10788 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_CHECKER_TYPE,
10789 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_52_WIDTH },
10790 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_CHECKER_TYPE,
10791 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_53_WIDTH },
10792 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_CHECKER_TYPE,
10793 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_54_WIDTH },
10794 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_CHECKER_TYPE,
10795 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_55_WIDTH },
10796 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_CHECKER_TYPE,
10797 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_56_WIDTH },
10798 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_CHECKER_TYPE,
10799 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_57_WIDTH },
10800 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_CHECKER_TYPE,
10801 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_58_WIDTH },
10802 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_CHECKER_TYPE,
10803 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_59_WIDTH },
10804 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_CHECKER_TYPE,
10805 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_60_WIDTH },
10806 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_CHECKER_TYPE,
10807 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_61_WIDTH },
10808 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_CHECKER_TYPE,
10809 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_62_WIDTH },
10810 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_CHECKER_TYPE,
10811 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_63_WIDTH },
10812 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_CHECKER_TYPE,
10813 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_64_WIDTH },
10814 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_CHECKER_TYPE,
10815 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_65_WIDTH },
10816 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_CHECKER_TYPE,
10817 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_66_WIDTH },
10818 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_CHECKER_TYPE,
10819 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_67_WIDTH },
10820 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_CHECKER_TYPE,
10821 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_68_WIDTH },
10822 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_CHECKER_TYPE,
10823 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_69_WIDTH },
10824 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_CHECKER_TYPE,
10825 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_70_WIDTH },
10826 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_CHECKER_TYPE,
10827 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_71_WIDTH },
10828 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_CHECKER_TYPE,
10829 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_72_WIDTH },
10830 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_CHECKER_TYPE,
10831 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_73_WIDTH },
10832 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_CHECKER_TYPE,
10833 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_74_WIDTH },
10834 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_CHECKER_TYPE,
10835 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_75_WIDTH },
10836 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_CHECKER_TYPE,
10837 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_76_WIDTH },
10838 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_CHECKER_TYPE,
10839 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_77_WIDTH },
10840 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_CHECKER_TYPE,
10841 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_78_WIDTH },
10842 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_CHECKER_TYPE,
10843 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_79_WIDTH },
10844 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_CHECKER_TYPE,
10845 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_80_WIDTH },
10846 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_CHECKER_TYPE,
10847 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_81_WIDTH },
10848 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_CHECKER_TYPE,
10849 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_82_WIDTH },
10850 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_CHECKER_TYPE,
10851 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_83_WIDTH },
10852 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_CHECKER_TYPE,
10853 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_84_WIDTH },
10854 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_CHECKER_TYPE,
10855 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_85_WIDTH },
10856 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_CHECKER_TYPE,
10857 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_86_WIDTH },
10858 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_CHECKER_TYPE,
10859 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_87_WIDTH },
10860 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_CHECKER_TYPE,
10861 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_88_WIDTH },
10862 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_CHECKER_TYPE,
10863 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_89_WIDTH },
10864 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_CHECKER_TYPE,
10865 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_90_WIDTH },
10866 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_CHECKER_TYPE,
10867 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_91_WIDTH },
10868 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_CHECKER_TYPE,
10869 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_92_WIDTH },
10870 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_CHECKER_TYPE,
10871 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_93_WIDTH },
10872 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_CHECKER_TYPE,
10873 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_94_WIDTH },
10874 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_CHECKER_TYPE,
10875 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_95_WIDTH },
10876 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_CHECKER_TYPE,
10877 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_96_WIDTH },
10878 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_CHECKER_TYPE,
10879 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_97_WIDTH },
10880 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_CHECKER_TYPE,
10881 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_98_WIDTH },
10882 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_CHECKER_TYPE,
10883 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_99_WIDTH },
10884 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_CHECKER_TYPE,
10885 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_100_WIDTH },
10886 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_CHECKER_TYPE,
10887 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_101_WIDTH },
10888 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_CHECKER_TYPE,
10889 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_102_WIDTH },
10890 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_CHECKER_TYPE,
10891 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_103_WIDTH },
10892 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_CHECKER_TYPE,
10893 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_104_WIDTH },
10894 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_CHECKER_TYPE,
10895 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_105_WIDTH },
10896 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_CHECKER_TYPE,
10897 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_106_WIDTH },
10898 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_CHECKER_TYPE,
10899 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_107_WIDTH },
10900 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_CHECKER_TYPE,
10901 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_108_WIDTH },
10902 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_CHECKER_TYPE,
10903 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_109_WIDTH },
10904 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_CHECKER_TYPE,
10905 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_110_WIDTH },
10906 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_CHECKER_TYPE,
10907 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_111_WIDTH },
10908 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_CHECKER_TYPE,
10909 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_112_WIDTH },
10910 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_CHECKER_TYPE,
10911 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_113_WIDTH },
10912 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_CHECKER_TYPE,
10913 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_114_WIDTH },
10914 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_CHECKER_TYPE,
10915 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_115_WIDTH },
10916 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_CHECKER_TYPE,
10917 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_116_WIDTH },
10918 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_CHECKER_TYPE,
10919 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_117_WIDTH },
10920 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_CHECKER_TYPE,
10921 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_118_WIDTH },
10922 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_CHECKER_TYPE,
10923 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_119_WIDTH },
10924 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_CHECKER_TYPE,
10925 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_120_WIDTH },
10926 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_CHECKER_TYPE,
10927 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_121_WIDTH },
10928 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_CHECKER_TYPE,
10929 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_122_WIDTH },
10930 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_CHECKER_TYPE,
10931 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_123_WIDTH },
10932 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_CHECKER_TYPE,
10933 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_124_WIDTH },
10934 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_CHECKER_TYPE,
10935 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_125_WIDTH },
10936 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_CHECKER_TYPE,
10937 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_126_WIDTH },
10938 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_CHECKER_TYPE,
10939 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_127_WIDTH },
10940 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_CHECKER_TYPE,
10941 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_128_WIDTH },
10942 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_CHECKER_TYPE,
10943 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_129_WIDTH },
10944 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_CHECKER_TYPE,
10945 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_130_WIDTH },
10946 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_CHECKER_TYPE,
10947 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_131_WIDTH },
10948 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_CHECKER_TYPE,
10949 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_132_WIDTH },
10950 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_CHECKER_TYPE,
10951 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_133_WIDTH },
10952 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_CHECKER_TYPE,
10953 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_134_WIDTH },
10954 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_CHECKER_TYPE,
10955 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_135_WIDTH },
10956 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_CHECKER_TYPE,
10957 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_136_WIDTH },
10958 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_CHECKER_TYPE,
10959 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_137_WIDTH },
10960 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_CHECKER_TYPE,
10961 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_138_WIDTH },
10962 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_CHECKER_TYPE,
10963 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_139_WIDTH },
10964 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_CHECKER_TYPE,
10965 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_140_WIDTH },
10966 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_CHECKER_TYPE,
10967 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_141_WIDTH },
10968 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_CHECKER_TYPE,
10969 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_142_WIDTH },
10970 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_CHECKER_TYPE,
10971 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_143_WIDTH },
10972 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_CHECKER_TYPE,
10973 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_144_WIDTH },
10974 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_CHECKER_TYPE,
10975 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_145_WIDTH },
10976 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_CHECKER_TYPE,
10977 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_146_WIDTH },
10978 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_CHECKER_TYPE,
10979 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_147_WIDTH },
10980 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_CHECKER_TYPE,
10981 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_148_WIDTH },
10982 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_CHECKER_TYPE,
10983 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_149_WIDTH },
10984 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_CHECKER_TYPE,
10985 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_150_WIDTH },
10986 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_CHECKER_TYPE,
10987 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_151_WIDTH },
10988 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_CHECKER_TYPE,
10989 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_152_WIDTH },
10990 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_CHECKER_TYPE,
10991 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_153_WIDTH },
10992 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_CHECKER_TYPE,
10993 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_154_WIDTH },
10994 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_CHECKER_TYPE,
10995 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_155_WIDTH },
10996 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_CHECKER_TYPE,
10997 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_156_WIDTH },
10998 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_CHECKER_TYPE,
10999 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_157_WIDTH },
11000 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_CHECKER_TYPE,
11001 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_158_WIDTH },
11002 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_CHECKER_TYPE,
11003 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_159_WIDTH },
11004 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_CHECKER_TYPE,
11005 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_160_WIDTH },
11006 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_CHECKER_TYPE,
11007 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_161_WIDTH },
11008 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_CHECKER_TYPE,
11009 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_162_WIDTH },
11010 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_CHECKER_TYPE,
11011 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_163_WIDTH },
11012 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_CHECKER_TYPE,
11013 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_164_WIDTH },
11014 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_CHECKER_TYPE,
11015 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_165_WIDTH },
11016 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_CHECKER_TYPE,
11017 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_166_WIDTH },
11018 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_CHECKER_TYPE,
11019 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_167_WIDTH },
11020 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_CHECKER_TYPE,
11021 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_168_WIDTH },
11022 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_CHECKER_TYPE,
11023 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_169_WIDTH },
11024 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_CHECKER_TYPE,
11025 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_170_WIDTH },
11026 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_CHECKER_TYPE,
11027 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_171_WIDTH },
11028 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_CHECKER_TYPE,
11029 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_172_WIDTH },
11030 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_CHECKER_TYPE,
11031 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_173_WIDTH },
11032 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_CHECKER_TYPE,
11033 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_174_WIDTH },
11034 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_CHECKER_TYPE,
11035 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_175_WIDTH },
11036 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_CHECKER_TYPE,
11037 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_176_WIDTH },
11038 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_CHECKER_TYPE,
11039 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_177_WIDTH },
11040 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_CHECKER_TYPE,
11041 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_178_WIDTH },
11042 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_CHECKER_TYPE,
11043 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_179_WIDTH },
11044 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_CHECKER_TYPE,
11045 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_180_WIDTH },
11046 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_CHECKER_TYPE,
11047 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_181_WIDTH },
11048 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_CHECKER_TYPE,
11049 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_182_WIDTH },
11050 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_CHECKER_TYPE,
11051 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_183_WIDTH },
11052 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_CHECKER_TYPE,
11053 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_184_WIDTH },
11054 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_CHECKER_TYPE,
11055 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_185_WIDTH },
11056 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_CHECKER_TYPE,
11057 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_186_WIDTH },
11058 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_CHECKER_TYPE,
11059 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_187_WIDTH },
11060 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_CHECKER_TYPE,
11061 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_188_WIDTH },
11062 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_CHECKER_TYPE,
11063 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_189_WIDTH },
11064 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_CHECKER_TYPE,
11065 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_190_WIDTH },
11066 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_CHECKER_TYPE,
11067 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_191_WIDTH },
11068 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_CHECKER_TYPE,
11069 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_192_WIDTH },
11070 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_CHECKER_TYPE,
11071 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_193_WIDTH },
11072 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_CHECKER_TYPE,
11073 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_194_WIDTH },
11074 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_CHECKER_TYPE,
11075 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_195_WIDTH },
11076 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_CHECKER_TYPE,
11077 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_196_WIDTH },
11078 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_CHECKER_TYPE,
11079 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_197_WIDTH },
11080 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_CHECKER_TYPE,
11081 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_198_WIDTH },
11082 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_CHECKER_TYPE,
11083 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_199_WIDTH },
11084 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_CHECKER_TYPE,
11085 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_200_WIDTH },
11086 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_CHECKER_TYPE,
11087 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_201_WIDTH },
11088 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_CHECKER_TYPE,
11089 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_202_WIDTH },
11090 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_CHECKER_TYPE,
11091 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_203_WIDTH },
11092 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_CHECKER_TYPE,
11093 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_204_WIDTH },
11094 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_CHECKER_TYPE,
11095 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_205_WIDTH },
11096 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_CHECKER_TYPE,
11097 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_206_WIDTH },
11098 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_CHECKER_TYPE,
11099 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_207_WIDTH },
11100 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_CHECKER_TYPE,
11101 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_208_WIDTH },
11102 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_CHECKER_TYPE,
11103 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_209_WIDTH },
11104 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_CHECKER_TYPE,
11105 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_210_WIDTH },
11106 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_CHECKER_TYPE,
11107 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_211_WIDTH },
11108 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_CHECKER_TYPE,
11109 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_212_WIDTH },
11110 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_CHECKER_TYPE,
11111 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_213_WIDTH },
11112 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_CHECKER_TYPE,
11113 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_214_WIDTH },
11114 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_CHECKER_TYPE,
11115 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_215_WIDTH },
11116 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_CHECKER_TYPE,
11117 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_216_WIDTH },
11118 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_CHECKER_TYPE,
11119 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_217_WIDTH },
11120 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_CHECKER_TYPE,
11121 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_218_WIDTH },
11122 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_CHECKER_TYPE,
11123 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_219_WIDTH },
11124 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_CHECKER_TYPE,
11125 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_220_WIDTH },
11126 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_CHECKER_TYPE,
11127 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_221_WIDTH },
11128 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_CHECKER_TYPE,
11129 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_222_WIDTH },
11130 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_CHECKER_TYPE,
11131 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_223_WIDTH },
11132 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_CHECKER_TYPE,
11133 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_224_WIDTH },
11134 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_CHECKER_TYPE,
11135 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_225_WIDTH },
11136 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_CHECKER_TYPE,
11137 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_226_WIDTH },
11138 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_CHECKER_TYPE,
11139 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_227_WIDTH },
11140 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_CHECKER_TYPE,
11141 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_228_WIDTH },
11142 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_CHECKER_TYPE,
11143 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_229_WIDTH },
11144 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_CHECKER_TYPE,
11145 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_230_WIDTH },
11146 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_CHECKER_TYPE,
11147 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_231_WIDTH },
11148 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_CHECKER_TYPE,
11149 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_232_WIDTH },
11150 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_CHECKER_TYPE,
11151 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_233_WIDTH },
11152 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_CHECKER_TYPE,
11153 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_234_WIDTH },
11154 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_CHECKER_TYPE,
11155 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_235_WIDTH },
11156 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_CHECKER_TYPE,
11157 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_236_WIDTH },
11158 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_CHECKER_TYPE,
11159 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_237_WIDTH },
11160 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_CHECKER_TYPE,
11161 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_238_WIDTH },
11162 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_CHECKER_TYPE,
11163 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_239_WIDTH },
11164 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_CHECKER_TYPE,
11165 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_240_WIDTH },
11166 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_CHECKER_TYPE,
11167 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_241_WIDTH },
11168 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_CHECKER_TYPE,
11169 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_242_WIDTH },
11170 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_CHECKER_TYPE,
11171 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_243_WIDTH },
11172 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_CHECKER_TYPE,
11173 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_244_WIDTH },
11174 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_CHECKER_TYPE,
11175 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_245_WIDTH },
11176 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_CHECKER_TYPE,
11177 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_246_WIDTH },
11178 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_CHECKER_TYPE,
11179 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_247_WIDTH },
11180 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_CHECKER_TYPE,
11181 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_248_WIDTH },
11182 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_CHECKER_TYPE,
11183 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_249_WIDTH },
11184 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_CHECKER_TYPE,
11185 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_250_WIDTH },
11186 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_CHECKER_TYPE,
11187 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_251_WIDTH },
11188 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_CHECKER_TYPE,
11189 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_252_WIDTH },
11190 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_CHECKER_TYPE,
11191 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_253_WIDTH },
11192 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_CHECKER_TYPE,
11193 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_254_WIDTH },
11194 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_CHECKER_TYPE,
11195 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_GROUP_255_WIDTH },
11205 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_CHECKER_TYPE,
11206 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_0_WIDTH },
11207 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_CHECKER_TYPE,
11208 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_1_WIDTH },
11209 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_CHECKER_TYPE,
11210 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_2_WIDTH },
11211 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_CHECKER_TYPE,
11212 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_3_WIDTH },
11213 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_CHECKER_TYPE,
11214 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_4_WIDTH },
11215 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_CHECKER_TYPE,
11216 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_5_WIDTH },
11217 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_CHECKER_TYPE,
11218 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_6_WIDTH },
11219 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_CHECKER_TYPE,
11220 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_7_WIDTH },
11221 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_CHECKER_TYPE,
11222 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_8_WIDTH },
11223 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_CHECKER_TYPE,
11224 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_9_WIDTH },
11225 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_CHECKER_TYPE,
11226 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_10_WIDTH },
11227 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_CHECKER_TYPE,
11228 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_11_WIDTH },
11229 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_CHECKER_TYPE,
11230 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_12_WIDTH },
11231 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_CHECKER_TYPE,
11232 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_13_WIDTH },
11233 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_CHECKER_TYPE,
11234 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_14_WIDTH },
11235 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_CHECKER_TYPE,
11236 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_15_WIDTH },
11237 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_CHECKER_TYPE,
11238 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_16_WIDTH },
11239 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_CHECKER_TYPE,
11240 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_17_WIDTH },
11241 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_CHECKER_TYPE,
11242 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_18_WIDTH },
11243 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_CHECKER_TYPE,
11244 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_19_WIDTH },
11245 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_CHECKER_TYPE,
11246 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_20_WIDTH },
11247 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_CHECKER_TYPE,
11248 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_21_WIDTH },
11249 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_CHECKER_TYPE,
11250 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_22_WIDTH },
11251 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_CHECKER_TYPE,
11252 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_23_WIDTH },
11253 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_CHECKER_TYPE,
11254 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_24_WIDTH },
11255 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_CHECKER_TYPE,
11256 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_GROUP_25_WIDTH },
11266 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
11267 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_0_WIDTH },
11268 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
11269 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_1_WIDTH },
11270 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
11271 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_2_WIDTH },
11272 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
11273 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_3_WIDTH },
11274 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
11275 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_4_WIDTH },
11276 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
11277 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_5_WIDTH },
11278 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
11279 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_6_WIDTH },
11280 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
11281 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_7_WIDTH },
11282 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
11283 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_8_WIDTH },
11284 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
11285 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_9_WIDTH },
11286 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
11287 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_10_WIDTH },
11288 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
11289 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_11_WIDTH },
11290 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
11291 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_GROUP_12_WIDTH },
11301 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
11302 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_0_WIDTH },
11303 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
11304 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_1_WIDTH },
11305 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
11306 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_2_WIDTH },
11307 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
11308 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_3_WIDTH },
11309 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
11310 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_4_WIDTH },
11311 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
11312 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_5_WIDTH },
11313 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
11314 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_6_WIDTH },
11315 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
11316 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_7_WIDTH },
11317 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
11318 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_8_WIDTH },
11319 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
11320 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_9_WIDTH },
11321 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
11322 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_10_WIDTH },
11323 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
11324 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_11_WIDTH },
11325 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
11326 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_GROUP_12_WIDTH },
11336 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
11337 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
11338 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
11339 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
11340 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
11341 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
11342 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
11343 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
11344 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
11345 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
11346 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
11347 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
11348 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
11349 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
11350 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
11351 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
11352 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
11353 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
11354 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
11355 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
11356 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
11357 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
11358 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
11359 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
11360 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
11361 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
11362 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
11363 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
11364 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
11365 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
11366 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
11367 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
11368 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
11369 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
11370 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
11371 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
11372 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
11373 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
11374 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
11375 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
11376 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
11377 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
11378 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
11379 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
11380 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
11381 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
11382 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
11383 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
11384 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
11385 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
11386 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
11387 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
11388 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
11389 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
11390 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
11391 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
11392 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
11393 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
11394 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
11395 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
11396 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
11397 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
11398 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
11399 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
11400 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
11401 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
11402 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
11403 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
11404 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
11405 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
11406 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
11407 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
11408 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
11409 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
11410 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
11411 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
11412 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
11413 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
11414 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
11415 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
11416 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
11417 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
11418 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
11419 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
11420 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
11421 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
11422 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
11423 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
11424 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
11425 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
11426 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
11427 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
11428 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
11429 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
11430 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
11431 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
11432 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
11433 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
11434 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
11435 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
11436 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
11437 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
11438 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
11439 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
11440 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
11441 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
11442 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
11443 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
11444 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
11445 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
11446 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
11447 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
11448 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
11449 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
11450 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
11451 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
11452 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
11453 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
11454 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
11455 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
11456 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
11457 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
11458 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
11459 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
11460 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
11461 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
11462 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
11463 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
11464 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
11465 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
11466 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
11467 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
11468 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
11469 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
11470 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
11471 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
11472 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
11473 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
11474 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
11475 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
11476 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
11477 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
11478 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
11479 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
11480 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
11481 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
11482 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
11483 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
11484 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
11485 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
11486 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
11487 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
11488 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
11489 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
11490 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
11491 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
11492 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
11493 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
11494 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
11495 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
11496 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
11497 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
11498 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
11499 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
11500 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
11501 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
11502 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
11503 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
11504 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
11505 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
11506 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
11507 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
11508 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
11509 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
11510 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
11511 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
11512 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
11513 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
11514 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
11515 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
11516 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
11517 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
11518 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
11519 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
11520 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
11521 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
11522 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
11523 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
11524 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
11525 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
11526 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
11527 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
11528 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
11529 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
11530 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
11531 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
11532 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
11533 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
11534 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
11535 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
11536 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
11537 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
11538 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
11539 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
11540 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
11541 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
11542 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
11543 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
11544 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
11545 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
11546 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
11547 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
11548 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
11549 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
11550 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
11551 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
11552 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
11553 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
11554 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
11555 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
11556 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
11557 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
11558 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
11559 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
11560 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
11561 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
11562 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
11563 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
11564 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
11565 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
11566 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
11567 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
11568 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
11569 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
11570 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
11571 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
11572 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
11573 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
11574 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
11575 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
11576 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
11577 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
11578 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
11579 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
11580 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
11581 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
11582 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
11583 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
11584 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
11585 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
11586 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
11587 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
11588 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
11589 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
11590 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
11591 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
11592 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
11593 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
11594 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
11595 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
11596 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
11597 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
11598 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
11599 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
11600 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
11601 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
11602 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
11603 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
11604 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
11605 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
11606 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
11607 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
11608 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
11609 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
11610 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
11611 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
11612 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
11613 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
11614 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
11615 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
11616 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
11617 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
11618 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
11619 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
11620 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
11621 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
11622 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
11623 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
11624 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
11625 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
11626 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
11627 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
11628 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
11629 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
11630 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
11631 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
11632 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
11633 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
11634 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
11635 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
11636 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
11637 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
11638 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
11639 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
11640 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
11641 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
11642 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
11643 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
11644 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
11645 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
11646 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
11647 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
11648 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
11649 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
11650 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
11651 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
11652 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
11653 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
11654 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
11655 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
11656 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
11657 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
11658 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
11659 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
11660 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
11661 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
11662 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
11663 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
11664 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
11665 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
11666 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
11667 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
11668 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
11669 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
11670 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
11671 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
11672 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
11673 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
11674 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
11675 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
11676 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
11677 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
11678 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
11679 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
11680 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
11681 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
11682 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
11683 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
11684 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
11685 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
11686 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
11687 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
11688 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
11689 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
11690 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
11691 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
11692 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
11693 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
11694 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
11695 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
11696 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
11697 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
11698 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
11699 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
11700 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
11701 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
11702 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
11703 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
11704 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
11705 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
11706 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
11707 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
11708 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
11709 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
11710 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
11711 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
11712 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
11713 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
11714 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
11715 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
11716 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
11717 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
11718 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
11719 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
11720 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
11721 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
11722 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
11723 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
11724 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
11725 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
11726 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
11727 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
11728 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
11729 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
11730 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
11731 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
11732 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
11733 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
11734 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
11735 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
11736 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
11737 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
11738 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
11739 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
11740 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
11741 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
11742 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
11743 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
11744 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
11745 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
11746 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
11747 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
11748 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
11749 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
11750 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
11751 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
11752 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
11753 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
11754 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
11755 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
11756 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
11757 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
11758 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
11759 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
11760 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
11761 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
11762 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
11763 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
11764 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
11765 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
11766 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
11767 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
11768 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
11769 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
11770 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
11771 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
11772 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
11773 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
11774 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
11775 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
11776 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
11777 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
11778 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
11779 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
11780 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
11781 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
11782 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
11783 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
11784 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
11785 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
11786 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
11787 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
11788 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
11789 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
11790 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
11791 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
11792 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
11793 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
11794 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
11795 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
11796 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
11797 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
11798 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
11799 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
11800 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
11801 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
11802 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
11803 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
11804 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
11805 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
11806 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
11807 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
11808 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
11809 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
11810 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
11811 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
11812 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
11813 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
11814 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
11815 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
11816 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
11817 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
11818 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
11819 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
11820 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
11821 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
11822 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
11823 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
11824 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
11825 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
11826 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
11827 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
11828 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
11829 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
11830 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
11831 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
11832 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
11833 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
11834 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
11835 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
11836 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
11837 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
11838 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
11839 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
11840 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
11841 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
11842 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
11843 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
11844 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
11845 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
11846 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
11847 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
11857 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
11858 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
11859 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
11860 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
11861 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
11862 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
11863 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
11864 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
11865 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
11866 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
11867 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
11868 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
11869 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
11870 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
11871 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
11872 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
11873 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
11874 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
11875 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
11876 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
11877 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
11878 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
11879 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
11880 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
11881 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
11882 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
11883 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
11884 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
11885 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
11886 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
11887 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
11888 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
11889 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
11890 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
11891 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
11892 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
11893 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
11894 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
11895 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
11896 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
11897 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
11898 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
11899 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
11900 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
11901 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
11902 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
11903 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
11904 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
11905 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
11906 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
11907 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
11908 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
11909 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
11910 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
11911 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
11912 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
11913 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
11914 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
11915 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
11916 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
11917 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
11918 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
11919 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
11920 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
11921 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
11922 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
11923 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
11924 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
11925 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
11926 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
11927 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
11928 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
11929 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
11930 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
11931 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
11932 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
11933 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
11934 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
11935 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
11936 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
11937 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
11938 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
11939 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
11940 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
11941 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
11942 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
11952 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
11953 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
11954 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
11955 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
11956 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
11957 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
11958 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
11959 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
11960 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
11961 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
11962 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
11963 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
11964 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
11965 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
11966 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
11967 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
11968 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
11969 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
11970 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
11971 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
11972 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
11973 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
11974 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
11975 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
11976 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
11977 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
11978 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
11979 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
11980 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
11981 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
11982 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
11983 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
11984 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
11985 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
11986 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
11987 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
11988 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
11989 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
11990 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
11991 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
11992 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
11993 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
11994 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
11995 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
11996 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
11997 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
11998 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
11999 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12000 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12001 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12002 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12003 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12004 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12005 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12006 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12007 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12008 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12009 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12010 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12011 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12012 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12013 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12014 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12015 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12016 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12017 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12018 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12019 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12020 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12021 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12022 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12023 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12024 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
12025 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
12026 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
12027 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
12028 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
12029 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
12030 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
12031 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
12032 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
12033 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
12034 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
12035 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
12036 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
12037 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
12038 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
12039 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
12040 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
12041 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
12042 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
12043 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
12044 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
12045 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
12046 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
12047 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
12048 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
12049 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
12050 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
12051 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
12052 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
12053 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
12054 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
12055 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
12056 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
12057 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
12058 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
12059 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
12060 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
12061 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
12062 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
12063 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
12064 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
12065 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
12066 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
12067 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
12068 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
12069 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
12070 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
12071 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
12072 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
12073 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
12074 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
12075 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
12076 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
12077 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
12087 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12088 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12089 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12090 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12091 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12092 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12093 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12094 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12095 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12096 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12097 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12098 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12099 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12100 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12101 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12102 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12112 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12113 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12114 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12115 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12116 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12117 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12118 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12119 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12120 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12121 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12122 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12123 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12124 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12125 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12126 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12127 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12128 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
12129 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
12130 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
12131 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
12132 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
12133 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
12134 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
12135 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
12136 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
12137 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
12138 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
12139 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
12140 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
12141 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
12142 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
12143 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
12144 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
12145 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
12146 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
12147 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
12148 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
12149 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
12150 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
12151 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
12152 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
12153 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
12154 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
12155 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
12156 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
12157 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
12158 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
12159 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12160 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12161 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12162 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12163 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12164 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12165 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12166 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12167 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12168 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12169 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12170 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12171 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12172 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12173 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12174 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12175 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12176 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12177 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12178 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12179 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12180 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12181 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12182 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12183 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12184 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
12185 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
12186 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
12187 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
12188 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
12189 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
12190 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
12191 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
12192 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
12193 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
12194 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
12195 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
12205 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
12206 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
12207 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
12208 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
12209 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
12210 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
12211 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
12212 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
12213 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
12214 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
12215 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
12216 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
12217 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
12218 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
12219 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
12220 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
12221 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
12222 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
12223 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
12224 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
12225 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
12226 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
12227 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
12228 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
12229 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
12230 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
12231 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
12232 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
12233 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
12234 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
12235 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
12236 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
12237 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
12238 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
12239 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
12240 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
12241 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
12242 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
12252 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12253 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12254 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12255 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12256 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12257 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12258 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12259 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12260 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12261 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12262 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12263 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12264 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12265 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12266 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12267 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12268 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
12269 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
12270 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
12271 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
12272 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
12273 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
12274 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
12275 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
12276 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
12277 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
12278 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
12279 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
12280 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
12281 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
12282 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
12283 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
12284 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
12285 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
12286 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
12287 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
12288 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
12289 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
12290 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
12291 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
12292 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
12293 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
12294 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
12295 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
12296 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
12297 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
12298 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
12299 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12300 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12301 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12302 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12303 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12304 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12305 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12306 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12307 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12308 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12309 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12310 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12311 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12312 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12313 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12314 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12315 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12316 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12317 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12318 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12319 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12320 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12321 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12322 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12323 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12324 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
12325 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
12326 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
12327 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
12328 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
12329 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
12330 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
12331 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
12332 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
12333 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
12334 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
12335 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
12336 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
12337 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
12338 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
12339 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
12340 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
12341 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
12342 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
12343 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
12344 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
12345 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
12346 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
12347 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
12348 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
12349 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
12350 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
12351 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
12352 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
12353 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
12354 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
12355 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
12356 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
12357 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
12358 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
12359 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
12360 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
12361 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
12362 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
12363 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
12364 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
12365 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
12366 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
12367 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
12368 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
12369 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
12370 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
12371 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
12372 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
12373 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
12374 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
12375 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
12376 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
12377 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
12378 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
12379 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
12380 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
12381 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
12382 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
12383 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
12393 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
12394 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_0_WIDTH },
12395 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
12396 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_1_WIDTH },
12397 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
12398 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_2_WIDTH },
12399 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
12400 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_3_WIDTH },
12401 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
12402 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_4_WIDTH },
12403 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
12404 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_5_WIDTH },
12405 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
12406 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_6_WIDTH },
12407 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
12408 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_7_WIDTH },
12409 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
12410 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_8_WIDTH },
12411 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
12412 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_9_WIDTH },
12413 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
12414 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_10_WIDTH },
12415 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
12416 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_11_WIDTH },
12417 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
12418 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_GROUP_12_WIDTH },
12428 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12429 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12430 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12431 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12432 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12433 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12434 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12435 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12436 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12437 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12438 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12439 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12449 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12450 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12451 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12452 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12453 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12454 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12455 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12456 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12457 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12458 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12459 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12460 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12461 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12462 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12463 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12464 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12465 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
12466 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
12467 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
12468 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
12469 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
12470 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
12471 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
12472 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
12473 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
12474 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
12475 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
12476 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
12477 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
12478 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
12479 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
12480 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
12481 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
12482 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
12483 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
12484 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
12485 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
12486 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
12487 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
12488 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
12489 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
12490 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
12491 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
12492 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
12493 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
12494 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
12495 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
12496 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12497 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12498 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12499 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12500 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12501 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12502 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12503 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12504 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12505 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12506 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12507 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12508 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12509 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12510 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12511 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12512 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12513 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12514 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12515 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12516 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12517 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12518 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12519 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12520 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12530 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
12531 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
12532 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
12533 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
12534 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
12535 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
12536 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
12537 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
12538 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
12539 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
12540 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
12541 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
12542 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
12543 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
12544 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
12545 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
12546 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
12547 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
12548 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
12549 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
12550 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
12551 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
12552 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
12553 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
12554 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
12555 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
12556 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
12557 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
12558 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
12559 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
12560 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
12561 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
12562 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
12563 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
12564 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
12565 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
12566 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
12567 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
12568 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
12569 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
12570 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
12571 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
12572 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
12573 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
12574 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
12575 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
12576 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
12577 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
12578 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
12579 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
12580 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
12581 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
12582 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
12583 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
12584 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
12585 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
12586 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
12587 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
12588 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
12589 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
12590 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
12591 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
12592 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
12593 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
12594 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
12595 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
12596 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
12597 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
12598 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
12599 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
12600 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
12601 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
12602 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
12603 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
12613 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_CHECKER_TYPE,
12614 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_0_WIDTH },
12615 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_CHECKER_TYPE,
12616 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_1_WIDTH },
12617 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_CHECKER_TYPE,
12618 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_2_WIDTH },
12619 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_CHECKER_TYPE,
12620 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_3_WIDTH },
12621 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_CHECKER_TYPE,
12622 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_4_WIDTH },
12623 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_CHECKER_TYPE,
12624 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_GROUP_5_WIDTH },
12633 { SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_ID, 0u,
12634 SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_SIZE, 4u,
12635 SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_ROW_WIDTH, ((bool)
false) },
12644 { SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID, 0u,
12645 SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_SIZE, 4u,
12646 SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ROW_WIDTH, ((bool)
false) },
12655 { SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
12656 SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
12657 SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
12666 { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID, 0u,
12667 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_SIZE, 4u,
12668 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ROW_WIDTH, ((bool)
false) },
12669 { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID, 0u,
12670 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_SIZE, 4u,
12671 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ROW_WIDTH, ((bool)
false) },
12680 { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID, 0x41880000u,
12681 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
12682 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)
true) },
12691 { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID, 0u,
12692 SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_SIZE, 4u,
12693 SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ROW_WIDTH, ((bool)
false) },
12702 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0u,
12703 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
12704 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
12714 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
12715 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
12724 { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID, 0u,
12725 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_SIZE, 4u,
12726 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ROW_WIDTH, ((bool)
false) },
12727 { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID, 0u,
12728 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_SIZE, 4u,
12729 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ROW_WIDTH, ((bool)
false) },
12738 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
12739 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
12740 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
12741 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
12742 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
12743 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
12744 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
12745 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
12746 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
12747 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
12748 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
12749 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
12750 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
12751 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
12752 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)
true) },
12753 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
12754 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
12755 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)
true) },
12756 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
12757 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
12758 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)
true) },
12759 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
12760 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
12761 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)
true) },
12762 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
12763 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
12764 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
12765 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
12766 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
12767 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
12768 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
12769 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
12770 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
12771 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
12772 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
12773 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
12774 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
12775 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
12776 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
12777 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
12778 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
12779 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)
true) },
12780 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
12781 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
12782 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)
true) },
12783 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
12784 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
12785 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)
true) },
12786 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
12787 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
12788 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)
true) },
12789 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
12790 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
12791 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)
true) },
12792 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
12793 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
12794 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)
true) },
12795 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
12796 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
12797 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)
true) },
12798 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
12799 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
12800 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)
true) },
12801 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x00000000u,
12802 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
12803 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)
true) },
12804 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x00000000u,
12805 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
12806 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)
true) },
12807 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x41010000u,
12808 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
12809 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
12810 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x41010000u,
12811 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
12812 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
12813 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x41010000u,
12814 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
12815 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
12816 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x41010000u,
12817 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
12818 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
12819 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
12820 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
12821 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
12822 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
12823 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
12824 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
12825 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID, 0u,
12826 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_SIZE, 4u,
12827 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
12837 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12838 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_0_WIDTH },
12839 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12840 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_1_WIDTH },
12841 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12842 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_2_WIDTH },
12843 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12844 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_3_WIDTH },
12845 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12846 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_4_WIDTH },
12847 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12848 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_5_WIDTH },
12849 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12850 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_6_WIDTH },
12851 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12852 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_7_WIDTH },
12853 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12854 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_8_WIDTH },
12855 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12856 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_9_WIDTH },
12857 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12858 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_10_WIDTH },
12859 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12860 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_11_WIDTH },
12861 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12862 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_12_WIDTH },
12863 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12864 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_13_WIDTH },
12865 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12866 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_14_WIDTH },
12867 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12868 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_15_WIDTH },
12869 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12870 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_16_WIDTH },
12871 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12872 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_17_WIDTH },
12873 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12874 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_18_WIDTH },
12875 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12876 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_19_WIDTH },
12877 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12878 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_20_WIDTH },
12879 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12880 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_21_WIDTH },
12881 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12882 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_22_WIDTH },
12883 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12884 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_23_WIDTH },
12885 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12886 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_24_WIDTH },
12887 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12888 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_25_WIDTH },
12889 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12890 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_26_WIDTH },
12891 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12892 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_27_WIDTH },
12893 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12894 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_28_WIDTH },
12895 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12896 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_29_WIDTH },
12897 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12898 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_30_WIDTH },
12899 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12900 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_31_WIDTH },
12901 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12902 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_32_WIDTH },
12903 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12904 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_33_WIDTH },
12905 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12906 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_34_WIDTH },
12907 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12908 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_35_WIDTH },
12918 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
12919 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
12920 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
12921 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
12922 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
12923 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
12924 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
12925 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
12926 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
12927 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
12928 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
12929 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
12930 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
12931 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
12932 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
12933 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
12934 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
12935 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
12936 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
12937 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
12938 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
12939 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
12940 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
12941 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
12942 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
12943 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
12944 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
12945 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
12946 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
12947 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
12948 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
12949 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
12950 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
12951 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
12952 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
12953 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
12954 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
12955 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
12956 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
12957 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
12958 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
12959 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
12960 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
12961 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
12962 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
12963 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
12964 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
12965 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
12966 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
12967 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
12968 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
12969 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
12970 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
12971 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
12972 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
12973 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
12974 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
12975 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
12976 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
12977 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
12978 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
12979 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
12980 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
12981 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
12982 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
12983 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
12984 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
12985 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
12986 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
12987 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
12988 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
12989 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
12990 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
12991 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
12992 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
12993 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_37_WIDTH },
13003 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13004 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
13005 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13006 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
13007 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13008 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
13009 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13010 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
13011 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13012 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
13013 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13014 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
13015 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13016 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
13017 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13018 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
13019 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13020 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
13021 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13022 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
13023 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13024 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
13025 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13026 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
13027 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13028 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
13029 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13030 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
13031 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13032 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
13033 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13034 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
13035 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13036 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
13037 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13038 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
13039 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13040 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
13041 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13042 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
13043 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13044 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
13045 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13046 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
13047 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13048 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
13049 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13050 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
13051 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13052 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
13053 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13054 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
13055 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13056 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
13057 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13058 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
13059 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13060 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
13061 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13062 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
13063 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13064 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
13065 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13066 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
13067 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13068 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
13078 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_0_CHECKER_TYPE,
13079 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_0_WIDTH },
13080 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_1_CHECKER_TYPE,
13081 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_1_WIDTH },
13082 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_2_CHECKER_TYPE,
13083 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_2_WIDTH },
13084 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_3_CHECKER_TYPE,
13085 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_3_WIDTH },
13086 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_4_CHECKER_TYPE,
13087 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_4_WIDTH },
13088 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_5_CHECKER_TYPE,
13089 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_5_WIDTH },
13090 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_6_CHECKER_TYPE,
13091 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_6_WIDTH },
13092 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_7_CHECKER_TYPE,
13093 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_7_WIDTH },
13094 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_8_CHECKER_TYPE,
13095 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_8_WIDTH },
13096 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_9_CHECKER_TYPE,
13097 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_9_WIDTH },
13098 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_10_CHECKER_TYPE,
13099 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_10_WIDTH },
13100 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_11_CHECKER_TYPE,
13101 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_11_WIDTH },
13102 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_12_CHECKER_TYPE,
13103 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_12_WIDTH },
13104 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_13_CHECKER_TYPE,
13105 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_13_WIDTH },
13106 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_14_CHECKER_TYPE,
13107 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_14_WIDTH },
13117 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13118 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
13119 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
13120 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
13121 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
13122 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
13132 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13133 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
13134 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
13135 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
13136 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
13137 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
13138 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
13139 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
13140 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
13141 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
13142 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
13143 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
13152 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
13153 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
13154 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
13155 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
13156 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
13157 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
13158 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
13159 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
13160 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
13161 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
13162 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
13163 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
13164 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
13165 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
13166 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)
true) },
13167 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
13168 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
13169 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)
true) },
13170 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
13171 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
13172 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)
true) },
13173 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
13174 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
13175 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)
true) },
13176 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
13177 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
13178 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
13179 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
13180 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
13181 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
13182 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
13183 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
13184 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
13185 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
13186 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
13187 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
13188 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
13189 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
13190 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
13191 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
13192 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
13193 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)
true) },
13194 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
13195 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
13196 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)
true) },
13197 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
13198 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
13199 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)
true) },
13200 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
13201 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
13202 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)
true) },
13203 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
13204 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
13205 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)
true) },
13206 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
13207 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
13208 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)
true) },
13209 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
13210 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
13211 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)
true) },
13212 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
13213 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
13214 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)
true) },
13215 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
13216 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
13217 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)
true) },
13218 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0u,
13219 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
13220 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)
true) },
13221 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0u,
13222 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
13223 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)
true) },
13224 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0u,
13225 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
13226 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)
true) },
13227 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0u,
13228 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
13229 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)
true) },
13230 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0u,
13231 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
13232 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)
true) },
13233 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
13234 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
13235 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
13236 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
13237 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
13238 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
13239 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID, 0u,
13240 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_SIZE, 4u,
13241 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
13251 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13252 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_0_WIDTH },
13253 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13254 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_1_WIDTH },
13255 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13256 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_2_WIDTH },
13257 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13258 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_3_WIDTH },
13259 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13260 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_4_WIDTH },
13261 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13262 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_5_WIDTH },
13263 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13264 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_6_WIDTH },
13265 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13266 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_7_WIDTH },
13267 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13268 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_8_WIDTH },
13269 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13270 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_9_WIDTH },
13271 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13272 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_10_WIDTH },
13273 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13274 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_11_WIDTH },
13275 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13276 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_12_WIDTH },
13277 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13278 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_13_WIDTH },
13279 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13280 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_14_WIDTH },
13281 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13282 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_15_WIDTH },
13283 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13284 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_16_WIDTH },
13285 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13286 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_17_WIDTH },
13287 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13288 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_18_WIDTH },
13289 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13290 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_19_WIDTH },
13291 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13292 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_20_WIDTH },
13293 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13294 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_21_WIDTH },
13295 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13296 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_22_WIDTH },
13297 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13298 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_23_WIDTH },
13299 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13300 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_24_WIDTH },
13301 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13302 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_25_WIDTH },
13303 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13304 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_26_WIDTH },
13305 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13306 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_27_WIDTH },
13307 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13308 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_28_WIDTH },
13309 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13310 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_29_WIDTH },
13311 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13312 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_30_WIDTH },
13313 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13314 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_31_WIDTH },
13315 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13316 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_32_WIDTH },
13317 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13318 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_33_WIDTH },
13319 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13320 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_34_WIDTH },
13321 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13322 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_35_WIDTH },
13332 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13333 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_0_WIDTH },
13334 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13335 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_1_WIDTH },
13336 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13337 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_2_WIDTH },
13338 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13339 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_3_WIDTH },
13340 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13341 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_4_WIDTH },
13342 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13343 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_5_WIDTH },
13344 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13345 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_6_WIDTH },
13346 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13347 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_7_WIDTH },
13348 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13349 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_8_WIDTH },
13350 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13351 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_9_WIDTH },
13352 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13353 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_10_WIDTH },
13354 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13355 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_11_WIDTH },
13356 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13357 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_12_WIDTH },
13358 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13359 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_13_WIDTH },
13360 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13361 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_14_WIDTH },
13362 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13363 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_15_WIDTH },
13364 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13365 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_16_WIDTH },
13366 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13367 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_17_WIDTH },
13368 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13369 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_18_WIDTH },
13370 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13371 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_19_WIDTH },
13372 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13373 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_20_WIDTH },
13374 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13375 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_21_WIDTH },
13376 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13377 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_22_WIDTH },
13378 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13379 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_23_WIDTH },
13380 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13381 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_24_WIDTH },
13382 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13383 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_25_WIDTH },
13384 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13385 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_26_WIDTH },
13386 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13387 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_27_WIDTH },
13388 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13389 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_28_WIDTH },
13390 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13391 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_29_WIDTH },
13392 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13393 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_30_WIDTH },
13394 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13395 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_31_WIDTH },
13396 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13397 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_32_WIDTH },
13398 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13399 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_33_WIDTH },
13400 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13401 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_34_WIDTH },
13402 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13403 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_35_WIDTH },
13404 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13405 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_36_WIDTH },
13406 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13407 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_37_WIDTH },
13417 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13418 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_0_WIDTH },
13419 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13420 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_1_WIDTH },
13421 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13422 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_2_WIDTH },
13423 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13424 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_3_WIDTH },
13425 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13426 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_4_WIDTH },
13427 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13428 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_5_WIDTH },
13429 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13430 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_6_WIDTH },
13431 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13432 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_7_WIDTH },
13433 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13434 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_8_WIDTH },
13435 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13436 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_9_WIDTH },
13437 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13438 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_10_WIDTH },
13439 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13440 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_11_WIDTH },
13441 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13442 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_12_WIDTH },
13443 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13444 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_13_WIDTH },
13445 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13446 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_14_WIDTH },
13447 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13448 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_15_WIDTH },
13449 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13450 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_16_WIDTH },
13451 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13452 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_17_WIDTH },
13453 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13454 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_18_WIDTH },
13455 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13456 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_19_WIDTH },
13457 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13458 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_20_WIDTH },
13459 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13460 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_21_WIDTH },
13461 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13462 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_22_WIDTH },
13463 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13464 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_23_WIDTH },
13465 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13466 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_24_WIDTH },
13467 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13468 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_25_WIDTH },
13469 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13470 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_26_WIDTH },
13471 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13472 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_27_WIDTH },
13473 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13474 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_28_WIDTH },
13475 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13476 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_29_WIDTH },
13477 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13478 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_30_WIDTH },
13479 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13480 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_31_WIDTH },
13481 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13482 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_32_WIDTH },
13492 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_0_CHECKER_TYPE,
13493 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_0_WIDTH },
13494 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_1_CHECKER_TYPE,
13495 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_1_WIDTH },
13496 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_2_CHECKER_TYPE,
13497 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_2_WIDTH },
13498 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_3_CHECKER_TYPE,
13499 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_3_WIDTH },
13500 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_4_CHECKER_TYPE,
13501 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_4_WIDTH },
13502 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_5_CHECKER_TYPE,
13503 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_5_WIDTH },
13504 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_6_CHECKER_TYPE,
13505 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_6_WIDTH },
13506 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_7_CHECKER_TYPE,
13507 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_7_WIDTH },
13508 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_8_CHECKER_TYPE,
13509 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_8_WIDTH },
13510 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_9_CHECKER_TYPE,
13511 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_9_WIDTH },
13512 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_10_CHECKER_TYPE,
13513 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_10_WIDTH },
13514 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_11_CHECKER_TYPE,
13515 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_11_WIDTH },
13516 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_12_CHECKER_TYPE,
13517 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_12_WIDTH },
13518 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_13_CHECKER_TYPE,
13519 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_13_WIDTH },
13520 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_14_CHECKER_TYPE,
13521 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_14_WIDTH },
13531 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13532 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
13533 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
13534 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
13535 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
13536 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
13537 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
13538 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
13539 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
13540 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
13541 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
13542 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
13551 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
13552 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
13553 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
13554 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
13555 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
13556 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
13557 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
13558 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
13559 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
13560 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
13561 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
13562 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
13563 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
13564 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 4u,
13565 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)
true) },
13566 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
13567 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 4u,
13568 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)
true) },
13569 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
13570 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 4u,
13571 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)
true) },
13572 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
13573 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 4u,
13574 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)
true) },
13575 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
13576 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
13577 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
13578 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
13579 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
13580 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
13581 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
13582 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
13583 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
13584 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
13585 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
13586 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
13587 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
13588 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
13589 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
13590 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
13591 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
13592 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)
true) },
13593 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
13594 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
13595 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)
true) },
13596 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
13597 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
13598 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)
true) },
13599 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
13600 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
13601 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)
true) },
13602 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
13603 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
13604 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)
true) },
13605 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
13606 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
13607 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)
true) },
13608 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
13609 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
13610 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)
true) },
13611 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
13612 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
13613 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)
true) },
13614 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0u,
13615 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
13616 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)
true) },
13617 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0u,
13618 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
13619 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)
true) },
13620 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0u,
13621 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
13622 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
13623 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0u,
13624 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
13625 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
13626 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0u,
13627 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
13628 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)
true) },
13629 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0u,
13630 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
13631 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)
true) },
13632 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0u,
13633 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
13634 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
13635 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
13636 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
13637 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
13638 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID, 0u,
13639 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_SIZE, 4u,
13640 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
13650 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13651 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_0_WIDTH },
13652 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13653 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_1_WIDTH },
13654 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13655 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_2_WIDTH },
13656 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13657 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_3_WIDTH },
13658 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13659 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_4_WIDTH },
13660 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13661 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_5_WIDTH },
13662 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13663 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_6_WIDTH },
13664 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13665 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_7_WIDTH },
13666 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13667 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_8_WIDTH },
13668 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13669 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_9_WIDTH },
13670 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13671 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_10_WIDTH },
13672 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13673 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_11_WIDTH },
13674 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13675 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_12_WIDTH },
13676 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13677 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_13_WIDTH },
13678 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13679 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_14_WIDTH },
13680 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13681 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_15_WIDTH },
13682 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13683 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_16_WIDTH },
13684 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13685 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_17_WIDTH },
13686 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13687 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_18_WIDTH },
13688 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13689 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_19_WIDTH },
13690 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13691 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_20_WIDTH },
13692 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13693 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_21_WIDTH },
13694 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13695 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_22_WIDTH },
13696 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13697 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_23_WIDTH },
13698 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13699 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_24_WIDTH },
13700 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13701 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_25_WIDTH },
13702 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13703 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_26_WIDTH },
13704 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13705 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_27_WIDTH },
13706 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13707 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_28_WIDTH },
13708 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13709 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_29_WIDTH },
13710 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13711 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_30_WIDTH },
13712 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13713 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_31_WIDTH },
13714 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13715 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_32_WIDTH },
13716 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13717 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_33_WIDTH },
13718 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13719 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_34_WIDTH },
13720 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13721 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_GROUP_35_WIDTH },
13731 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13732 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
13733 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13734 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
13735 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13736 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
13737 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13738 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
13739 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13740 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
13741 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13742 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
13743 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13744 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
13745 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13746 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
13747 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13748 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
13749 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13750 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
13751 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13752 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
13753 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13754 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
13755 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13756 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
13757 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13758 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
13759 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13760 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
13761 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13762 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
13763 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13764 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
13765 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13766 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
13767 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13768 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
13769 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13770 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
13771 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13772 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
13773 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13774 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
13775 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13776 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
13777 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13778 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
13779 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13780 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
13781 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13782 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
13783 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13784 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
13785 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13786 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
13787 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13788 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
13789 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13790 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
13791 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13792 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
13793 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13794 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
13795 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13796 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
13797 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
13798 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_33_WIDTH },
13799 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
13800 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_34_WIDTH },
13801 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
13802 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_35_WIDTH },
13803 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
13804 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_36_WIDTH },
13805 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
13806 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_GROUP_37_WIDTH },
13816 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
13817 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_0_WIDTH },
13818 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
13819 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_1_WIDTH },
13820 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
13821 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_2_WIDTH },
13822 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
13823 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_3_WIDTH },
13824 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
13825 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_4_WIDTH },
13826 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
13827 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_5_WIDTH },
13828 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
13829 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_6_WIDTH },
13830 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
13831 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_7_WIDTH },
13832 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
13833 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_8_WIDTH },
13834 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
13835 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_9_WIDTH },
13836 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
13837 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_10_WIDTH },
13838 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
13839 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_11_WIDTH },
13840 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
13841 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_12_WIDTH },
13842 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
13843 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_13_WIDTH },
13844 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
13845 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_14_WIDTH },
13846 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
13847 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_15_WIDTH },
13848 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
13849 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_16_WIDTH },
13850 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
13851 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_17_WIDTH },
13852 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
13853 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_18_WIDTH },
13854 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
13855 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_19_WIDTH },
13856 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
13857 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_20_WIDTH },
13858 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
13859 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_21_WIDTH },
13860 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
13861 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_22_WIDTH },
13862 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
13863 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_23_WIDTH },
13864 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
13865 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_24_WIDTH },
13866 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
13867 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_25_WIDTH },
13868 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
13869 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_26_WIDTH },
13870 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
13871 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_27_WIDTH },
13872 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
13873 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_28_WIDTH },
13874 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
13875 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_29_WIDTH },
13876 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
13877 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_30_WIDTH },
13878 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
13879 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_31_WIDTH },
13880 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
13881 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_GROUP_32_WIDTH },
13891 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_0_CHECKER_TYPE,
13892 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_0_WIDTH },
13893 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_1_CHECKER_TYPE,
13894 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_1_WIDTH },
13895 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_2_CHECKER_TYPE,
13896 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_2_WIDTH },
13897 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_3_CHECKER_TYPE,
13898 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_3_WIDTH },
13899 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_4_CHECKER_TYPE,
13900 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_4_WIDTH },
13901 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_5_CHECKER_TYPE,
13902 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_5_WIDTH },
13903 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_6_CHECKER_TYPE,
13904 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_6_WIDTH },
13905 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_7_CHECKER_TYPE,
13906 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_7_WIDTH },
13907 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_8_CHECKER_TYPE,
13908 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_8_WIDTH },
13909 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_9_CHECKER_TYPE,
13910 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_9_WIDTH },
13911 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_10_CHECKER_TYPE,
13912 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_10_WIDTH },
13913 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_11_CHECKER_TYPE,
13914 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_11_WIDTH },
13915 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_12_CHECKER_TYPE,
13916 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_12_WIDTH },
13917 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_13_CHECKER_TYPE,
13918 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_13_WIDTH },
13919 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_14_CHECKER_TYPE,
13920 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_GROUP_14_WIDTH },
13930 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13931 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_0_WIDTH },
13932 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_CHECKER_TYPE,
13933 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_1_WIDTH },
13934 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_CHECKER_TYPE,
13935 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_GROUP_2_WIDTH },
13945 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
13946 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
13947 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
13948 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
13949 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
13950 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
13951 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
13952 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
13953 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
13954 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
13955 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
13956 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
13965 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
13966 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
13967 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)
false) },
13968 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
13969 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
13970 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)
false) },
13971 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
13972 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
13973 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)
false) },
13974 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
13975 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
13976 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)
false) },
13977 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
13978 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 4u,
13979 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)
true) },
13980 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
13981 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 4u,
13982 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)
true) },
13983 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
13984 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 4u,
13985 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)
true) },
13986 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
13987 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 4u,
13988 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)
true) },
13989 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
13990 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
13991 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)
false) },
13992 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
13993 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
13994 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)
false) },
13995 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
13996 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
13997 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)
false) },
13998 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
13999 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
14000 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)
false) },
14001 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
14002 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
14003 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)
false) },
14004 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
14005 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
14006 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)
true) },
14007 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
14008 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
14009 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)
true) },
14010 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
14011 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
14012 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)
true) },
14013 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
14014 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
14015 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)
true) },
14016 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
14017 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
14018 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)
true) },
14019 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
14020 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
14021 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)
true) },
14022 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
14023 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
14024 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)
true) },
14025 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
14026 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
14027 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)
true) },
14028 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0u,
14029 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
14030 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)
true) },
14031 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0u,
14032 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
14033 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)
true) },
14034 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0u,
14035 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
14036 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)
true) },
14037 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0u,
14038 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
14039 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)
true) },
14040 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0u,
14041 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
14042 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)
true) },
14043 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0u,
14044 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
14045 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)
true) },
14046 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0u,
14047 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
14048 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)
false) },
14049 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID, 0u,
14050 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_SIZE, 4u,
14051 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
14052 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID, 0u,
14053 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_SIZE, 4u,
14054 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ROW_WIDTH, ((bool)
false) },
14064 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14065 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_0_WIDTH },
14066 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14067 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_1_WIDTH },
14068 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14069 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_2_WIDTH },
14070 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14071 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_3_WIDTH },
14072 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14073 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_4_WIDTH },
14074 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14075 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_5_WIDTH },
14076 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14077 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_6_WIDTH },
14078 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14079 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_7_WIDTH },
14080 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14081 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_8_WIDTH },
14082 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14083 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_9_WIDTH },
14084 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14085 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_10_WIDTH },
14086 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14087 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_11_WIDTH },
14088 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14089 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_12_WIDTH },
14090 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14091 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_13_WIDTH },
14092 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14093 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_14_WIDTH },
14094 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14095 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_15_WIDTH },
14096 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14097 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_16_WIDTH },
14098 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14099 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_17_WIDTH },
14100 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14101 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_18_WIDTH },
14102 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14103 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_19_WIDTH },
14104 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14105 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_20_WIDTH },
14106 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14107 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_21_WIDTH },
14108 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14109 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_22_WIDTH },
14110 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14111 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_23_WIDTH },
14112 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14113 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_24_WIDTH },
14114 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14115 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_25_WIDTH },
14116 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14117 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_26_WIDTH },
14118 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14119 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_27_WIDTH },
14120 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14121 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_28_WIDTH },
14122 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14123 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_29_WIDTH },
14124 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14125 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_30_WIDTH },
14126 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14127 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_31_WIDTH },
14128 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14129 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_32_WIDTH },
14130 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14131 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_33_WIDTH },
14132 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14133 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_34_WIDTH },
14134 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14135 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_GROUP_35_WIDTH },
14145 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14146 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_0_WIDTH },
14147 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14148 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_1_WIDTH },
14149 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14150 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_2_WIDTH },
14151 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14152 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_3_WIDTH },
14153 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14154 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_4_WIDTH },
14155 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14156 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_5_WIDTH },
14157 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14158 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_6_WIDTH },
14159 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14160 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_7_WIDTH },
14161 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14162 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_8_WIDTH },
14163 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14164 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_9_WIDTH },
14165 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14166 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_10_WIDTH },
14167 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14168 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_11_WIDTH },
14169 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14170 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_12_WIDTH },
14171 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14172 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_13_WIDTH },
14173 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14174 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_14_WIDTH },
14175 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14176 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_15_WIDTH },
14177 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14178 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_16_WIDTH },
14179 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14180 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_17_WIDTH },
14181 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14182 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_18_WIDTH },
14183 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14184 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_19_WIDTH },
14185 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14186 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_20_WIDTH },
14187 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14188 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_21_WIDTH },
14189 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14190 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_22_WIDTH },
14191 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14192 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_23_WIDTH },
14193 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14194 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_24_WIDTH },
14195 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14196 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_25_WIDTH },
14197 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14198 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_26_WIDTH },
14199 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14200 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_27_WIDTH },
14201 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14202 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_28_WIDTH },
14203 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14204 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_29_WIDTH },
14205 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14206 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_30_WIDTH },
14207 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14208 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_31_WIDTH },
14209 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14210 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_32_WIDTH },
14211 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_33_CHECKER_TYPE,
14212 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_33_WIDTH },
14213 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_34_CHECKER_TYPE,
14214 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_34_WIDTH },
14215 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_35_CHECKER_TYPE,
14216 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_35_WIDTH },
14217 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_36_CHECKER_TYPE,
14218 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_36_WIDTH },
14219 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_37_CHECKER_TYPE,
14220 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_GROUP_37_WIDTH },
14230 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_0_CHECKER_TYPE,
14231 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_0_WIDTH },
14232 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_1_CHECKER_TYPE,
14233 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_1_WIDTH },
14234 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_2_CHECKER_TYPE,
14235 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_2_WIDTH },
14236 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_3_CHECKER_TYPE,
14237 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_3_WIDTH },
14238 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_4_CHECKER_TYPE,
14239 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_4_WIDTH },
14240 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_5_CHECKER_TYPE,
14241 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_5_WIDTH },
14242 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_6_CHECKER_TYPE,
14243 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_6_WIDTH },
14244 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_7_CHECKER_TYPE,
14245 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_7_WIDTH },
14246 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_8_CHECKER_TYPE,
14247 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_8_WIDTH },
14248 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_9_CHECKER_TYPE,
14249 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_9_WIDTH },
14250 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_10_CHECKER_TYPE,
14251 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_10_WIDTH },
14252 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_11_CHECKER_TYPE,
14253 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_11_WIDTH },
14254 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_12_CHECKER_TYPE,
14255 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_12_WIDTH },
14256 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_13_CHECKER_TYPE,
14257 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_13_WIDTH },
14258 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_14_CHECKER_TYPE,
14259 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_14_WIDTH },
14260 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_15_CHECKER_TYPE,
14261 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_15_WIDTH },
14262 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_16_CHECKER_TYPE,
14263 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_16_WIDTH },
14264 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_17_CHECKER_TYPE,
14265 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_17_WIDTH },
14266 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_18_CHECKER_TYPE,
14267 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_18_WIDTH },
14268 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_19_CHECKER_TYPE,
14269 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_19_WIDTH },
14270 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_20_CHECKER_TYPE,
14271 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_20_WIDTH },
14272 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_21_CHECKER_TYPE,
14273 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_21_WIDTH },
14274 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_22_CHECKER_TYPE,
14275 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_22_WIDTH },
14276 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_23_CHECKER_TYPE,
14277 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_23_WIDTH },
14278 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_24_CHECKER_TYPE,
14279 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_24_WIDTH },
14280 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_25_CHECKER_TYPE,
14281 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_25_WIDTH },
14282 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_26_CHECKER_TYPE,
14283 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_26_WIDTH },
14284 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_27_CHECKER_TYPE,
14285 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_27_WIDTH },
14286 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_28_CHECKER_TYPE,
14287 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_28_WIDTH },
14288 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_29_CHECKER_TYPE,
14289 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_29_WIDTH },
14290 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_30_CHECKER_TYPE,
14291 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_30_WIDTH },
14292 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_31_CHECKER_TYPE,
14293 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_31_WIDTH },
14294 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_32_CHECKER_TYPE,
14295 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_GROUP_32_WIDTH },
14305 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_0_CHECKER_TYPE,
14306 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_0_WIDTH },
14307 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_1_CHECKER_TYPE,
14308 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_1_WIDTH },
14309 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_2_CHECKER_TYPE,
14310 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_2_WIDTH },
14311 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_3_CHECKER_TYPE,
14312 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_3_WIDTH },
14313 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_4_CHECKER_TYPE,
14314 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_4_WIDTH },
14315 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_5_CHECKER_TYPE,
14316 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_5_WIDTH },
14317 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_6_CHECKER_TYPE,
14318 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_6_WIDTH },
14319 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_7_CHECKER_TYPE,
14320 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_7_WIDTH },
14321 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_8_CHECKER_TYPE,
14322 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_8_WIDTH },
14323 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_9_CHECKER_TYPE,
14324 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_9_WIDTH },
14325 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_10_CHECKER_TYPE,
14326 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_10_WIDTH },
14327 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_11_CHECKER_TYPE,
14328 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_11_WIDTH },
14329 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_12_CHECKER_TYPE,
14330 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_12_WIDTH },
14331 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_13_CHECKER_TYPE,
14332 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_13_WIDTH },
14333 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_14_CHECKER_TYPE,
14334 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_GROUP_14_WIDTH },
14344 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14345 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
14346 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
14347 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
14348 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
14349 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
14350 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
14351 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
14352 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
14353 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
14354 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
14355 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
14365 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14366 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14367 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14368 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14369 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14370 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14371 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14372 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14373 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
14374 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
14375 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
14376 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
14377 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
14378 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
14388 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14389 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14390 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14391 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14392 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14393 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14394 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14395 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14396 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14397 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14398 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
14399 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
14400 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
14401 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
14402 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
14403 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
14404 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
14405 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
14406 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
14407 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
14408 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
14409 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
14410 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
14411 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
14412 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
14413 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
14414 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
14415 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
14416 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
14417 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
14418 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
14419 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
14420 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
14421 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
14422 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
14423 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
14424 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
14425 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
14426 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
14427 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
14428 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
14429 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
14430 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
14431 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
14432 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
14433 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
14434 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
14435 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
14436 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
14437 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
14438 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
14439 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
14440 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
14441 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
14442 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
14443 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
14444 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
14445 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
14446 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
14447 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
14448 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
14449 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
14450 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
14451 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
14452 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
14453 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
14454 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
14455 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
14456 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
14457 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
14458 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
14459 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
14460 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
14461 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
14462 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
14463 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
14464 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
14465 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
14466 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
14467 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
14468 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
14469 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
14470 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
14471 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
14472 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
14473 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
14474 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
14475 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
14476 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
14477 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
14478 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
14479 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
14480 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
14481 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
14482 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
14483 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
14484 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
14485 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
14486 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
14487 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
14488 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
14489 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
14490 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
14491 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
14492 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
14493 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
14494 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
14495 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
14496 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
14497 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
14498 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
14499 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
14500 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
14501 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
14502 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
14503 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
14504 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
14505 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
14506 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
14507 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
14508 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
14509 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
14510 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
14511 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
14512 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
14513 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
14514 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
14515 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
14516 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
14517 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
14518 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
14519 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
14520 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
14521 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
14522 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
14523 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
14524 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
14525 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
14535 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
14536 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
14537 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
14538 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
14539 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
14540 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
14541 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
14542 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
14543 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
14544 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
14545 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
14546 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
14556 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14557 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14558 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14559 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14560 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14561 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14562 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14563 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14564 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14565 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14566 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
14567 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
14568 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
14569 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
14570 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
14571 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
14572 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
14573 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
14574 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
14575 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
14576 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
14577 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
14578 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
14579 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
14580 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
14581 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
14582 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
14583 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
14584 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
14585 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
14586 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
14587 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
14588 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
14589 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
14590 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
14591 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
14592 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
14593 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
14594 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
14595 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
14596 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
14597 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
14598 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
14599 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
14600 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
14601 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
14602 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
14603 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
14604 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
14605 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
14606 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
14607 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
14608 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
14609 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
14610 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
14611 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
14612 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
14613 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
14614 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
14615 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
14616 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
14617 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
14618 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
14619 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
14620 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
14621 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
14622 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
14623 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
14624 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
14625 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
14626 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
14627 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
14628 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
14629 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
14630 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
14631 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
14632 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
14633 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
14634 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
14635 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
14636 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
14637 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
14638 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
14639 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
14640 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
14641 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
14642 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
14643 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
14644 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
14645 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
14646 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
14647 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
14648 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
14649 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
14650 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
14651 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
14652 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
14653 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
14654 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
14655 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
14656 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
14657 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
14658 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
14659 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
14660 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
14661 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
14662 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
14663 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
14664 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
14665 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
14666 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
14667 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
14668 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
14669 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
14670 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
14671 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
14672 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
14673 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
14674 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
14675 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
14676 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
14677 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
14678 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
14679 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
14680 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
14681 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
14682 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
14683 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
14684 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
14685 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
14686 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
14687 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
14688 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
14689 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
14690 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
14691 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
14692 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
14693 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
14694 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
14695 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
14696 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
14697 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
14698 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
14699 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
14700 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
14701 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
14702 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
14703 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
14704 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
14705 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
14706 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
14707 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
14708 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
14709 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
14710 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
14711 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
14721 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
14722 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
14723 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
14724 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
14725 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
14726 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
14727 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
14728 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
14729 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
14730 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
14731 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
14732 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
14733 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
14734 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
14735 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
14736 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
14737 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
14738 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
14739 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
14740 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
14741 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
14742 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
14743 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
14744 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
14745 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
14746 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
14747 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
14748 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
14749 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
14750 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
14751 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
14752 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
14753 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
14754 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
14755 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
14756 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
14757 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
14758 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
14759 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
14760 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
14761 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
14762 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
14763 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
14764 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
14765 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
14766 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
14767 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
14768 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
14769 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
14770 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
14771 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
14772 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
14773 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
14774 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
14775 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
14776 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
14777 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
14778 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
14779 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
14780 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
14781 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
14782 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
14783 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
14784 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
14785 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
14786 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
14787 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
14788 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
14789 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
14790 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
14791 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
14792 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
14793 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
14794 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
14795 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
14796 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
14797 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
14798 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
14799 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
14800 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
14801 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
14802 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
14803 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
14804 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
14805 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
14806 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
14807 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
14808 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
14809 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
14810 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
14811 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
14812 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
14813 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
14814 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
14815 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
14816 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
14817 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
14818 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
14819 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
14820 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
14821 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
14822 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
14823 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
14824 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
14825 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
14826 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
14827 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
14828 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
14829 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
14830 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
14831 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
14832 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
14833 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
14834 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
14835 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
14836 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
14837 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
14838 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
14839 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
14840 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
14841 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
14842 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
14843 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
14844 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
14845 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
14846 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
14847 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
14848 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
14849 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
14850 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
14851 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
14852 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
14853 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
14854 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
14855 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
14856 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
14857 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
14858 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
14859 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
14860 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
14861 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
14862 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
14863 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
14864 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
14865 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
14866 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
14867 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
14868 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
14869 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
14870 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
14871 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
14872 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
14873 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
14874 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
14875 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
14876 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
14877 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
14878 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
14879 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
14880 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
14881 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
14882 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
14892 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
14893 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
14894 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
14895 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
14905 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14906 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14907 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14908 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14909 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14910 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14911 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14912 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14913 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14914 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14915 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14916 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14917 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14918 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14919 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14920 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14921 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14922 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14923 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14924 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14925 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14926 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14927 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14928 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14929 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14930 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14931 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14932 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14933 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14934 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14935 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14936 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14937 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14938 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14948 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
14949 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
14950 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
14951 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
14952 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
14953 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
14954 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
14955 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
14956 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
14957 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
14958 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
14959 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
14960 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
14961 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
14962 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
14963 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
14964 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
14965 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
14966 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
14967 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
14968 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
14969 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
14970 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
14971 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
14972 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
14973 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
14974 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
14975 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
14976 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
14977 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
14978 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
14979 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
14980 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
14981 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
14991 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_CHECKER_TYPE,
14992 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_0_WIDTH },
14993 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_CHECKER_TYPE,
14994 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_1_WIDTH },
14995 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_CHECKER_TYPE,
14996 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_2_WIDTH },
14997 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_CHECKER_TYPE,
14998 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_3_WIDTH },
14999 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_CHECKER_TYPE,
15000 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_4_WIDTH },
15001 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_CHECKER_TYPE,
15002 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_5_WIDTH },
15003 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_CHECKER_TYPE,
15004 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_GROUP_6_WIDTH },
15014 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15015 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15016 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15017 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15018 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15019 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15020 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15021 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15022 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15023 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15024 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15025 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15026 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15027 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15028 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15029 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15030 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15031 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15032 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15033 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15034 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15035 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15036 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15037 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15038 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15039 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15040 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15041 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15042 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15043 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15044 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15045 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15046 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15047 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15048 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15049 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15050 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15051 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15052 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15053 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15054 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15055 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15056 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15057 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15058 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15059 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15060 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15061 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15062 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15063 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15064 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15065 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15066 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15067 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15068 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15069 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15070 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15071 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15072 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15073 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15074 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15075 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15076 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15077 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15078 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15079 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15080 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15081 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15082 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15083 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15084 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15085 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15086 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15087 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15088 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15089 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15090 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15091 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15092 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15093 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15094 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15095 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15096 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15097 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15098 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15099 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15100 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15101 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15102 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15103 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15104 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15105 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15106 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15107 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15108 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15109 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15110 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15111 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15112 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15113 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15114 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15115 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15116 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15117 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15118 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15119 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15120 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15121 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15122 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15123 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15124 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15125 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15126 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15127 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15128 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15129 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15130 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15131 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15132 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15133 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15134 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15135 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15136 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15137 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15138 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15139 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15140 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
15141 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
15142 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
15143 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
15144 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
15145 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
15146 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
15147 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
15148 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
15149 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
15159 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_CHECKER_TYPE,
15160 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_0_WIDTH },
15161 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_CHECKER_TYPE,
15162 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_1_WIDTH },
15163 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_CHECKER_TYPE,
15164 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_2_WIDTH },
15165 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_CHECKER_TYPE,
15166 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_3_WIDTH },
15167 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_CHECKER_TYPE,
15168 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_4_WIDTH },
15169 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_CHECKER_TYPE,
15170 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_5_WIDTH },
15171 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_CHECKER_TYPE,
15172 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_6_WIDTH },
15173 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_CHECKER_TYPE,
15174 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_7_WIDTH },
15175 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_CHECKER_TYPE,
15176 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_8_WIDTH },
15177 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_CHECKER_TYPE,
15178 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_9_WIDTH },
15179 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_CHECKER_TYPE,
15180 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_10_WIDTH },
15181 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_CHECKER_TYPE,
15182 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_11_WIDTH },
15183 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_CHECKER_TYPE,
15184 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_12_WIDTH },
15185 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_CHECKER_TYPE,
15186 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_13_WIDTH },
15187 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_CHECKER_TYPE,
15188 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_14_WIDTH },
15189 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_CHECKER_TYPE,
15190 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_15_WIDTH },
15191 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_CHECKER_TYPE,
15192 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_16_WIDTH },
15193 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_CHECKER_TYPE,
15194 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_17_WIDTH },
15195 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_CHECKER_TYPE,
15196 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_18_WIDTH },
15197 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_CHECKER_TYPE,
15198 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_19_WIDTH },
15199 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_CHECKER_TYPE,
15200 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_20_WIDTH },
15201 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_CHECKER_TYPE,
15202 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_21_WIDTH },
15203 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_CHECKER_TYPE,
15204 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_22_WIDTH },
15205 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_CHECKER_TYPE,
15206 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_23_WIDTH },
15207 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_CHECKER_TYPE,
15208 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_24_WIDTH },
15209 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_CHECKER_TYPE,
15210 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_25_WIDTH },
15211 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_CHECKER_TYPE,
15212 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_26_WIDTH },
15213 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_CHECKER_TYPE,
15214 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_27_WIDTH },
15215 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_CHECKER_TYPE,
15216 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_28_WIDTH },
15217 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_CHECKER_TYPE,
15218 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_29_WIDTH },
15219 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_CHECKER_TYPE,
15220 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_30_WIDTH },
15221 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_CHECKER_TYPE,
15222 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_31_WIDTH },
15223 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_CHECKER_TYPE,
15224 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_32_WIDTH },
15225 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_CHECKER_TYPE,
15226 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_33_WIDTH },
15227 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_CHECKER_TYPE,
15228 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_34_WIDTH },
15229 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_CHECKER_TYPE,
15230 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_35_WIDTH },
15231 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_CHECKER_TYPE,
15232 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_36_WIDTH },
15233 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_CHECKER_TYPE,
15234 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_37_WIDTH },
15235 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_CHECKER_TYPE,
15236 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_38_WIDTH },
15237 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_CHECKER_TYPE,
15238 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_39_WIDTH },
15239 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_CHECKER_TYPE,
15240 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_40_WIDTH },
15241 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_CHECKER_TYPE,
15242 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_41_WIDTH },
15243 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_CHECKER_TYPE,
15244 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_42_WIDTH },
15245 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_CHECKER_TYPE,
15246 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_43_WIDTH },
15247 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_CHECKER_TYPE,
15248 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_44_WIDTH },
15249 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_CHECKER_TYPE,
15250 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_45_WIDTH },
15251 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_CHECKER_TYPE,
15252 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_46_WIDTH },
15253 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_CHECKER_TYPE,
15254 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_47_WIDTH },
15255 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_CHECKER_TYPE,
15256 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_48_WIDTH },
15257 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_CHECKER_TYPE,
15258 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_49_WIDTH },
15259 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_CHECKER_TYPE,
15260 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_50_WIDTH },
15261 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_CHECKER_TYPE,
15262 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_GROUP_51_WIDTH },
15272 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_CHECKER_TYPE,
15273 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_0_WIDTH },
15274 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_CHECKER_TYPE,
15275 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_1_WIDTH },
15276 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_CHECKER_TYPE,
15277 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_2_WIDTH },
15278 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_CHECKER_TYPE,
15279 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_3_WIDTH },
15280 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_CHECKER_TYPE,
15281 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_4_WIDTH },
15282 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_CHECKER_TYPE,
15283 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_5_WIDTH },
15284 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_CHECKER_TYPE,
15285 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_6_WIDTH },
15286 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_CHECKER_TYPE,
15287 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_7_WIDTH },
15288 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_CHECKER_TYPE,
15289 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_8_WIDTH },
15290 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_CHECKER_TYPE,
15291 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_9_WIDTH },
15292 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_CHECKER_TYPE,
15293 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_10_WIDTH },
15294 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_CHECKER_TYPE,
15295 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_11_WIDTH },
15296 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_CHECKER_TYPE,
15297 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_12_WIDTH },
15298 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_CHECKER_TYPE,
15299 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_13_WIDTH },
15300 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_CHECKER_TYPE,
15301 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_14_WIDTH },
15302 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_CHECKER_TYPE,
15303 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_15_WIDTH },
15304 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_CHECKER_TYPE,
15305 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_16_WIDTH },
15306 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_CHECKER_TYPE,
15307 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_17_WIDTH },
15308 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_CHECKER_TYPE,
15309 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_18_WIDTH },
15310 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_CHECKER_TYPE,
15311 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_19_WIDTH },
15312 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_CHECKER_TYPE,
15313 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_20_WIDTH },
15314 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_CHECKER_TYPE,
15315 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_21_WIDTH },
15316 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_CHECKER_TYPE,
15317 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_22_WIDTH },
15318 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_CHECKER_TYPE,
15319 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_23_WIDTH },
15320 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_CHECKER_TYPE,
15321 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_24_WIDTH },
15322 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_CHECKER_TYPE,
15323 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_25_WIDTH },
15324 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_CHECKER_TYPE,
15325 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_26_WIDTH },
15326 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_CHECKER_TYPE,
15327 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_27_WIDTH },
15328 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_CHECKER_TYPE,
15329 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_28_WIDTH },
15330 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_CHECKER_TYPE,
15331 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_29_WIDTH },
15332 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_CHECKER_TYPE,
15333 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_30_WIDTH },
15334 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_CHECKER_TYPE,
15335 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_31_WIDTH },
15336 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_CHECKER_TYPE,
15337 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_32_WIDTH },
15338 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_33_CHECKER_TYPE,
15339 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_33_WIDTH },
15340 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_34_CHECKER_TYPE,
15341 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_34_WIDTH },
15342 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_35_CHECKER_TYPE,
15343 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_35_WIDTH },
15344 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_36_CHECKER_TYPE,
15345 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_36_WIDTH },
15346 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_37_CHECKER_TYPE,
15347 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_37_WIDTH },
15348 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_38_CHECKER_TYPE,
15349 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_38_WIDTH },
15350 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_39_CHECKER_TYPE,
15351 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_39_WIDTH },
15352 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_40_CHECKER_TYPE,
15353 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_40_WIDTH },
15354 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_41_CHECKER_TYPE,
15355 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_41_WIDTH },
15356 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_42_CHECKER_TYPE,
15357 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_42_WIDTH },
15358 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_43_CHECKER_TYPE,
15359 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_43_WIDTH },
15360 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_44_CHECKER_TYPE,
15361 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_44_WIDTH },
15362 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_45_CHECKER_TYPE,
15363 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_45_WIDTH },
15364 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_46_CHECKER_TYPE,
15365 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_46_WIDTH },
15366 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_47_CHECKER_TYPE,
15367 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_47_WIDTH },
15368 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_48_CHECKER_TYPE,
15369 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_48_WIDTH },
15370 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_49_CHECKER_TYPE,
15371 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_49_WIDTH },
15372 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_50_CHECKER_TYPE,
15373 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_50_WIDTH },
15374 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_51_CHECKER_TYPE,
15375 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_51_WIDTH },
15376 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_52_CHECKER_TYPE,
15377 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_52_WIDTH },
15378 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_53_CHECKER_TYPE,
15379 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_53_WIDTH },
15380 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_54_CHECKER_TYPE,
15381 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_GROUP_54_WIDTH },
15391 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
15392 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
15393 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
15394 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
15395 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
15396 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
15397 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
15398 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
15399 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
15400 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
15401 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
15402 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
15411 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
15412 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
15413 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
15414 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID, 0u,
15415 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_SIZE, 4u,
15416 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
15417 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
15418 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
15419 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
15420 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID, 0u,
15421 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_SIZE, 4u,
15422 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
15431 { SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID, 0u,
15432 SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_SIZE, 4u,
15433 SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ROW_WIDTH, ((bool)
false) },
15442 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
15443 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
15444 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
15445 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID, 0u,
15446 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_SIZE, 4u,
15447 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ROW_WIDTH, ((bool)
false) },
15448 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
15449 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
15450 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
15451 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID, 0u,
15452 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_SIZE, 4u,
15453 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ROW_WIDTH, ((bool)
false) },
15463 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15464 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15465 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15466 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15467 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15468 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15469 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15470 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15471 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15472 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15473 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15474 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15475 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15476 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15477 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15478 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15479 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15480 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15481 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15482 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15483 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15484 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15485 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15486 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15487 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15488 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15489 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15490 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15491 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15492 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15493 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15494 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15495 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15496 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15497 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15498 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15499 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15500 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15501 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15502 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15503 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15504 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15505 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15506 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15507 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15508 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15509 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15510 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15511 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15512 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15513 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15514 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15515 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15516 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15517 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15518 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15519 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15520 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15521 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15522 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15523 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15524 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15525 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15526 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15527 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15528 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15529 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15530 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15531 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15532 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15533 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15534 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15535 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15536 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15537 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15538 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15539 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15540 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15541 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15542 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15543 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15544 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15545 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15546 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15547 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15548 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15549 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15550 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15551 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15552 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15553 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15554 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15555 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15556 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15557 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15558 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15559 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15560 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15561 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15562 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15563 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15564 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15565 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15566 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15567 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15568 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15569 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15570 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15571 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15572 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15573 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15574 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15575 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15576 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15577 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15578 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15579 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15580 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15581 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15582 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15583 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15584 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15585 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15586 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15587 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15588 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15589 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
15590 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
15591 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
15592 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
15602 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15603 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15604 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15605 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15606 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15607 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15608 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15609 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15619 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15620 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15621 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15622 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15623 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15624 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15625 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15626 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15627 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15628 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15629 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15630 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15631 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15632 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15633 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15634 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15635 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15636 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15637 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15638 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15639 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15640 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15641 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15642 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15643 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15644 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15645 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15646 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15647 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15648 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15658 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15659 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15660 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15661 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15662 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15663 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15664 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15665 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15666 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15667 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15668 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15669 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15670 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15671 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15672 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15673 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15674 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15675 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15676 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15677 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15678 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15679 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15680 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15681 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15682 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15683 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15684 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15685 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15686 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15687 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15688 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
15689 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
15690 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
15691 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
15692 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
15693 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
15694 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
15695 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
15696 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
15697 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
15698 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
15699 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
15700 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
15701 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
15702 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
15703 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
15704 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
15705 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
15706 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
15707 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
15708 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
15709 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
15710 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
15711 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
15712 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
15713 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
15714 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
15715 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
15716 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
15717 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
15718 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
15719 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
15720 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
15721 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
15722 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
15723 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
15724 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
15725 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
15726 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
15727 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
15728 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
15729 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
15730 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
15731 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
15732 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
15733 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
15734 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
15735 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
15736 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
15737 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
15738 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
15739 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
15740 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
15741 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
15742 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
15743 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
15744 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
15745 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
15746 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
15747 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
15748 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
15749 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
15750 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
15751 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
15752 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
15753 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
15754 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
15755 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
15756 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
15757 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
15758 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
15759 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
15760 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
15761 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
15762 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
15763 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
15764 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
15765 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
15766 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
15767 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
15768 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
15769 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
15770 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
15771 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
15772 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
15773 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
15774 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
15775 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
15776 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
15777 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
15778 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
15779 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
15780 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
15781 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
15782 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
15783 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
15784 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
15785 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
15786 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
15787 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
15797 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15798 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15799 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15800 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15801 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15802 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15803 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15804 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15814 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
15815 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
15816 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
15817 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
15818 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
15819 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
15820 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
15821 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
15822 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
15823 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
15824 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
15825 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
15826 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
15827 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
15828 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
15829 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
15830 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
15831 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
15832 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
15833 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
15834 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
15835 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
15836 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
15837 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
15838 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
15839 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
15840 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
15841 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
15842 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
15843 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
15852 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20738000u,
15853 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
15854 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
15864 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
15865 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
15874 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20728000u,
15875 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
15876 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
15886 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
15887 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
15896 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20718000u,
15897 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
15898 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
15908 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
15909 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
15918 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_RAM_ID, 0u,
15919 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_RAM_SIZE, 4u,
15920 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_ROW_WIDTH, ((bool)
false) },
15921 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_RAM_ID, 0u,
15922 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_RAM_SIZE, 4u,
15923 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_ROW_WIDTH, ((bool)
false) },
15924 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_RAM_ID, 0u,
15925 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_RAM_SIZE, 4u,
15926 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
15927 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_RAM_ID, 0u,
15928 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_RAM_SIZE, 4u,
15929 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
15930 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_RAM_ID, 0u,
15931 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_RAM_SIZE, 4u,
15932 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
15933 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_RAM_ID, 0u,
15934 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_RAM_SIZE, 4u,
15935 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
15936 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_RAM_ID, 0u,
15937 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_RAM_SIZE, 4u,
15938 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)
false) },
15939 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_RAM_ID, 0u,
15940 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_RAM_SIZE, 4u,
15941 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_ROW_WIDTH, ((bool)
false) },
15942 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_RAM_ID, 0u,
15943 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_RAM_SIZE, 4u,
15944 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_ROW_WIDTH, ((bool)
false) },
15945 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_RAM_ID, 0u,
15946 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
15947 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)
false) },
15948 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_RAM_ID, 0u,
15949 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_RAM_SIZE, 4u,
15950 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_ROW_WIDTH, ((bool)
false) },
15951 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_RAM_ID, 0u,
15952 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_RAM_SIZE, 4u,
15953 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_ROW_WIDTH, ((bool)
false) },
15954 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_RAM_ID, 0u,
15955 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_RAM_SIZE, 4u,
15956 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_ROW_WIDTH, ((bool)
false) },
15957 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_RAM_ID, 0u,
15958 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_RAM_SIZE, 4u,
15959 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_ROW_WIDTH, ((bool)
false) },
15960 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_RAM_ID, 0u,
15961 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_RAM_SIZE, 4u,
15962 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
15963 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_RAM_ID, 0u,
15964 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_RAM_SIZE, 4u,
15965 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
15966 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_RAM_ID, 0u,
15967 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_RAM_SIZE, 4u,
15968 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_ROW_WIDTH, ((bool)
false) },
15969 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_RAM_ID, 0u,
15970 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_RAM_SIZE, 4u,
15971 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_ROW_WIDTH, ((bool)
false) },
15972 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_RAM_ID, 0u,
15973 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_RAM_SIZE, 4u,
15974 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_ROW_WIDTH, ((bool)
false) },
15975 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_RAM_ID, 0u,
15976 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_RAM_SIZE, 4u,
15977 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_ROW_WIDTH, ((bool)
false) },
15978 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_RAM_ID, 0u,
15979 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_RAM_SIZE, 4u,
15980 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_ROW_WIDTH, ((bool)
false) },
15981 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_RAM_ID, 0u,
15982 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_RAM_SIZE, 4u,
15983 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_ROW_WIDTH, ((bool)
false) },
15984 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID, 0u,
15985 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_SIZE, 4u,
15986 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ROW_WIDTH, ((bool)
false) },
15987 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_RAM_ID, 0u,
15988 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_RAM_SIZE, 4u,
15989 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_ROW_WIDTH, ((bool)
false) },
15990 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_RAM_ID, 0u,
15991 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_RAM_SIZE, 4u,
15992 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_ROW_WIDTH, ((bool)
false) },
15993 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID, 0u,
15994 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_RAM_SIZE, 4u,
15995 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_ROW_WIDTH, ((bool)
false) },
15996 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID, 0u,
15997 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_SIZE, 4u,
15998 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_ROW_WIDTH, ((bool)
false) },
15999 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_RAM_ID, 0u,
16000 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_RAM_SIZE, 4u,
16001 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_ROW_WIDTH, ((bool)
false) },
16010 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x20748000u,
16011 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
16012 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)
true) },
16022 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_CHECKER_TYPE,
16023 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_GROUP_0_WIDTH },
16032 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
16033 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
16034 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)
false) },
16044 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16045 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16046 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16047 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16048 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16049 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16050 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16051 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16052 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16053 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16054 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16055 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16056 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16057 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16058 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16059 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16060 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16061 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16062 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16063 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16064 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16065 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16066 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16067 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16068 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16069 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16070 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16071 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16072 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16073 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16074 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16075 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16076 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16077 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16078 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16079 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16080 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16081 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16082 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16083 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16084 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16085 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16086 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16087 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16088 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16089 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16090 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16091 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16092 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16093 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16094 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16095 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16096 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16097 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16098 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16099 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16100 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16101 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16102 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16103 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16104 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16105 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16106 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16107 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16108 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16109 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16110 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16111 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16112 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16113 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16114 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16115 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16116 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16117 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16118 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16119 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16120 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16121 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16122 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16123 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16124 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16125 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16126 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16127 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16128 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16129 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16130 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16131 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16132 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16133 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16134 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16135 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16136 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16137 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
16138 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
16139 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
16140 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
16141 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
16142 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
16143 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
16144 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
16145 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
16146 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
16147 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
16148 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
16149 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
16150 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
16151 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
16152 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
16153 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
16154 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
16155 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
16156 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
16157 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16158 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16159 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16160 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16161 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16162 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16163 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16164 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16165 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16166 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16167 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16168 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16169 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16170 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
16171 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
16172 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
16173 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
16183 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16184 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16185 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16186 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16187 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16188 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16189 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16190 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16191 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16192 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16193 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16194 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16195 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16196 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16197 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16198 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16199 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16200 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16201 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16202 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16203 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16204 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16205 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16206 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16207 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16208 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16209 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16210 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16211 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16212 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16222 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16223 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16224 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16225 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16226 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16227 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16228 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16229 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16230 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16231 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16232 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16233 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16234 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16235 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16236 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16237 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16238 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16239 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16240 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16241 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16242 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16243 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16244 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16245 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16246 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16247 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16248 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16249 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16250 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16251 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16252 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16253 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16254 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16255 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16256 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16257 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16258 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16259 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16260 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16261 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16262 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16263 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16264 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16265 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16266 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16267 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16268 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16269 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16270 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16271 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16272 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16273 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16274 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16275 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16276 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16277 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16278 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16279 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16280 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16281 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16282 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16283 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16284 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16285 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16286 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16287 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16288 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16289 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16290 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16291 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16292 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16293 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16294 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16295 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16296 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16297 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16298 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16299 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16300 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16301 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16302 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16303 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16304 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16305 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16306 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16307 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16308 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16309 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16310 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16311 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16312 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16313 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16314 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16315 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
16316 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
16317 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
16318 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
16319 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
16320 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
16321 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
16322 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
16323 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
16324 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
16325 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
16326 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
16327 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
16328 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
16329 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
16330 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
16331 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
16332 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
16333 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
16334 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
16335 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16336 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16337 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16338 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16339 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16340 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16341 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16342 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16343 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16344 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16345 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16346 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16347 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16348 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
16349 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
16350 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
16351 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
16352 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
16353 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
16354 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
16355 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
16356 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
16357 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
16358 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
16359 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
16360 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
16361 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
16362 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
16363 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
16364 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
16365 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
16366 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
16367 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
16368 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
16369 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
16370 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
16371 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
16372 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
16373 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
16374 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
16375 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
16376 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
16377 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
16387 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16388 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16389 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16390 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16391 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16392 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16393 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16394 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16395 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16396 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16397 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16398 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16399 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16400 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16401 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16402 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16403 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16404 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16405 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16406 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16407 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16408 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16409 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16410 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16411 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16412 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16413 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16414 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16415 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16416 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16417 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16418 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16419 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16420 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16421 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16422 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16423 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16424 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16425 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16426 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16427 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16428 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16429 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16430 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16431 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16432 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16433 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16434 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16435 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16436 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16437 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16438 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16439 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16440 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16441 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16442 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16443 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16444 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16445 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16446 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16447 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16448 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16449 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16450 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16451 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16452 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16453 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16454 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16455 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16456 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16457 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16458 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16459 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16460 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16461 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16462 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16463 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16464 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16465 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16466 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16467 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16468 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16469 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16470 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16471 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16472 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16473 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16474 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16475 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16476 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16477 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16478 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16479 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16480 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
16481 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
16482 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
16483 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
16484 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
16485 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
16486 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
16487 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
16488 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
16489 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
16490 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
16491 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
16492 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
16493 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
16494 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
16495 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
16496 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
16497 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
16498 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
16499 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
16500 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16501 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16502 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16503 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16504 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16505 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16506 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16507 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16508 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16509 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16510 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16511 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16512 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16513 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
16514 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
16515 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
16516 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
16517 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
16518 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
16519 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
16520 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
16521 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
16522 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
16523 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
16524 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
16525 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
16526 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
16527 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
16528 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
16529 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
16530 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
16531 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
16532 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
16533 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
16534 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
16535 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
16536 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
16537 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
16538 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
16539 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
16540 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
16550 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16551 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16552 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16553 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16554 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16555 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16556 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16557 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16558 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16559 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16560 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16561 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16562 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16563 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16564 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16565 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16566 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16567 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16568 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16569 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16570 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16571 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16572 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16573 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16574 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16575 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16576 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16577 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16578 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16579 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16580 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16581 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16582 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16583 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16584 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16585 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16586 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16587 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16588 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16589 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16590 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16591 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16592 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16593 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16594 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16595 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16596 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16597 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16598 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16599 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16600 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16601 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16602 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16603 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16604 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16605 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16606 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16607 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16608 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16609 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16610 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16611 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16612 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16613 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16614 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16615 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16616 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16617 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16618 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16619 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16620 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16621 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16622 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16623 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16624 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16625 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16626 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16627 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16628 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16629 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16630 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16631 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16632 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16633 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16634 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16635 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16636 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16637 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16638 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16639 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16640 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16641 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16642 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16643 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
16644 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
16645 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
16646 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
16647 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
16648 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
16649 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
16650 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
16651 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
16652 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
16653 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
16654 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
16655 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
16656 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
16657 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
16658 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
16659 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
16660 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
16661 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
16662 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
16663 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16664 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16665 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16666 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16667 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16668 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16669 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16670 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16671 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16672 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16673 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16674 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16675 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16676 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
16677 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
16678 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
16679 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
16680 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
16681 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
16682 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
16683 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
16684 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
16685 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
16686 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
16687 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
16688 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
16689 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
16690 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
16691 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
16692 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
16693 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
16694 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
16695 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
16696 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
16697 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
16698 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
16699 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
16700 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
16701 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
16702 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
16703 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
16704 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
16705 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
16715 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16716 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16717 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16718 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16719 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16720 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16721 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16722 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16723 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16724 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16725 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16726 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16727 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16728 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16729 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16730 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16731 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16732 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16733 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16734 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16735 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16736 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16737 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16738 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16739 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16740 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16741 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16742 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16743 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16744 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16745 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16746 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16747 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16748 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16749 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16750 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16751 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16752 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16753 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16754 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16755 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16756 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16757 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16758 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16759 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16760 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16761 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16762 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16763 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16764 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16765 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16766 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16767 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16768 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16769 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16770 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16771 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16772 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16773 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16774 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16775 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16776 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16777 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16778 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16779 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16780 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16781 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16782 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16783 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16784 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16785 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16786 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16787 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16788 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16789 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16790 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16791 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16792 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16793 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16794 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16795 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16796 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16797 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16798 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16799 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16800 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16801 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16802 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16803 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16804 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16805 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16806 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16807 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16808 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
16809 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
16810 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
16811 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
16812 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
16813 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
16814 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
16815 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
16816 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
16817 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
16818 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
16819 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
16820 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
16821 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
16822 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
16823 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
16824 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
16825 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
16826 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
16827 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
16828 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
16829 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
16830 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
16831 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
16832 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
16833 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
16834 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
16835 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
16836 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
16837 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
16838 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
16839 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
16840 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
16841 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
16842 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
16843 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
16844 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
16845 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
16846 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
16847 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
16848 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
16849 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
16850 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
16851 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
16852 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
16853 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
16854 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
16855 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
16856 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
16857 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
16858 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
16859 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
16860 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
16861 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
16862 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
16863 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
16864 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
16865 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
16866 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
16867 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
16868 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
16878 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16879 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16880 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16881 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16882 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16883 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16884 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16885 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16894 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID, 0u,
16895 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_SIZE, 4u,
16896 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ROW_WIDTH, ((bool)
false) },
16906 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
16907 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
16908 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
16909 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
16910 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
16911 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
16912 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
16913 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
16914 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
16915 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
16916 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
16917 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
16918 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
16919 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
16920 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
16921 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
16922 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
16923 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
16924 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
16925 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
16926 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
16927 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
16928 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
16929 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
16930 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
16931 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
16932 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
16933 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
16934 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
16935 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
16936 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
16937 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
16938 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
16939 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
16940 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
16941 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
16942 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
16943 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
16944 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
16945 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
16946 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
16947 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
16948 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
16949 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
16950 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
16951 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
16952 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
16953 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
16954 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
16955 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
16956 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
16957 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
16958 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
16959 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
16960 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
16961 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
16962 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
16963 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
16964 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
16965 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
16966 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
16967 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
16968 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
16969 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
16970 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
16971 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
16972 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
16973 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
16974 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
16975 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
16976 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
16977 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
16978 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
16979 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
16980 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
16981 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
16982 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
16983 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
16984 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
16985 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
16986 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
16987 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
16988 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
16989 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
16990 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
16991 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
16992 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
16993 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
16994 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
16995 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
16996 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
16997 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
16998 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
16999 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17000 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17001 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17002 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17003 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17004 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17005 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17006 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17007 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17008 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17009 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17010 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17011 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17012 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17013 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17014 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17015 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17016 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17017 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17018 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17019 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17020 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17021 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17022 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17023 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17024 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17025 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17026 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17027 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17028 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17029 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17030 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17031 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17032 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
17033 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
17034 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
17035 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
17045 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17046 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17047 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17048 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17049 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17050 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17051 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17052 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17053 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17054 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17055 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17056 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17057 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17058 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17059 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17060 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17061 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17062 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17063 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17064 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17065 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17066 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17067 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17068 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17069 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17070 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17071 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17072 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17073 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17074 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17084 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17085 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17086 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17087 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17088 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17089 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17090 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17091 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17092 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17093 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17094 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17095 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17096 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17097 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17098 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17099 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17100 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17101 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17102 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17103 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17104 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17105 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17106 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17107 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17108 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17109 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17110 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17111 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17112 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17113 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17114 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17115 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17116 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17117 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17118 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17119 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17120 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17121 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17122 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17123 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17124 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17125 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17126 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17127 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17128 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17129 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17130 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17131 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17132 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17133 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17134 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17135 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17136 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17137 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17138 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17139 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17140 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17141 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17142 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17143 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17144 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17145 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17146 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17147 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17148 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17149 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17150 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17151 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17152 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17153 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17154 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17155 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17156 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17157 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17158 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17159 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17160 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17161 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17162 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17163 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17164 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17165 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17166 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17167 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17168 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
17169 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
17170 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
17171 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
17172 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
17173 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
17174 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
17175 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
17176 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
17177 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17178 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17179 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17180 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17181 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17182 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17183 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17184 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17185 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17186 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17187 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17188 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17189 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17190 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17191 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17192 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17193 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17194 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17195 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17196 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17197 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17198 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17199 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17200 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17201 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17202 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17203 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17204 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17205 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17206 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17207 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17208 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17209 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17210 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
17211 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
17212 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
17213 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
17214 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
17215 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
17216 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
17217 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
17218 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
17219 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
17220 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
17221 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
17222 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
17223 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
17224 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
17225 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
17226 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
17227 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
17228 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
17229 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
17230 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
17231 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
17232 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
17233 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
17234 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
17235 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
17236 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
17237 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
17238 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
17239 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
17249 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17250 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17251 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17252 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17253 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17254 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17255 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17256 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17257 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17258 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17259 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17260 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17261 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17262 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17263 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17264 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17265 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17266 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17267 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17268 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17269 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17270 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17271 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17272 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17273 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17274 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17275 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17276 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17277 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17278 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17279 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17280 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17281 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17282 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17283 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17284 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17285 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17286 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17287 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17288 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17289 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17290 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17291 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17292 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17293 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17294 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17295 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17296 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17297 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17298 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17299 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17300 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17301 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17302 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17303 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17304 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17305 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17306 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17307 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17308 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17309 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17310 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17311 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17312 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17313 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17314 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17315 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17316 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17317 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17318 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17319 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17320 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17321 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17322 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17323 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17324 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17325 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17326 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17327 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17328 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17329 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17330 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17331 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17332 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17333 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
17334 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
17335 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
17336 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
17337 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
17338 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
17339 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
17340 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
17341 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
17342 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17343 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17344 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17345 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17346 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17347 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17348 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17349 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17350 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17351 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17352 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17353 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17354 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17355 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17356 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17357 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17358 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17359 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17360 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17361 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17362 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17363 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17364 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17365 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17366 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17367 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17368 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17369 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17370 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17371 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17372 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17373 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17374 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17375 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
17376 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
17377 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
17378 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
17379 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
17380 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
17381 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
17382 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
17383 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
17384 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
17385 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
17386 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
17387 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
17388 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
17389 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
17390 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
17391 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
17392 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
17393 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
17394 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
17395 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
17396 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
17397 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
17398 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
17399 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
17400 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
17401 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
17402 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
17412 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17413 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17414 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17415 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17416 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17417 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17418 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17419 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17420 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17421 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17422 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17423 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17424 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17425 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17426 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17427 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17428 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17429 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17430 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17431 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17432 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17433 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17434 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17435 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17436 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17437 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17438 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17439 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17440 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17441 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17442 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17443 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17444 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17445 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17446 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17447 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17448 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17449 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17450 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17451 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17452 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17453 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17454 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17455 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17456 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17457 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17458 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17459 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17460 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17461 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17462 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17463 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17464 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17465 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17466 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17467 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17468 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17469 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17470 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17471 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17472 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17473 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17474 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17475 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17476 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17477 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17478 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17479 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17480 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17481 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17482 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17483 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17484 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17485 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17486 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17487 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17488 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17489 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17490 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17491 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17492 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17493 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17494 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17495 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17496 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
17497 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
17498 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
17499 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
17500 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
17501 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
17502 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
17503 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
17504 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
17505 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17506 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17507 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17508 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17509 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17510 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17511 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17512 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17513 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17514 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17515 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17516 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17517 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17518 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17519 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17520 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17521 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17522 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17523 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17524 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17525 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17526 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17527 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17528 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17529 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17530 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17531 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17532 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17533 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17534 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17535 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17536 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17537 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17538 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
17539 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
17540 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
17541 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
17542 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
17543 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
17544 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
17545 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
17546 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
17547 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
17548 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
17549 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
17550 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
17551 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
17552 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
17553 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
17554 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
17555 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
17556 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
17557 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
17558 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
17559 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
17560 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
17561 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
17562 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
17563 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
17564 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
17565 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
17566 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
17567 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
17577 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17578 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17579 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17580 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17581 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17582 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17583 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17584 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17585 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
17586 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
17587 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
17588 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
17589 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
17590 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
17591 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
17592 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
17593 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
17594 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
17595 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
17596 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
17597 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
17598 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
17599 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
17600 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
17601 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
17602 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
17603 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
17604 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
17605 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
17606 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
17607 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
17608 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
17609 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
17610 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
17611 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
17612 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
17613 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
17614 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
17615 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
17616 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
17617 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
17618 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
17619 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
17620 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
17621 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
17622 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
17623 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
17624 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
17625 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
17626 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
17627 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
17628 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
17629 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
17630 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
17631 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
17632 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
17633 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
17634 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
17635 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
17636 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
17637 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
17638 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
17639 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
17640 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
17641 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
17642 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
17643 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
17644 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
17645 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
17646 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
17647 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
17648 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
17649 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
17650 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
17651 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
17652 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
17653 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
17654 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
17655 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
17656 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
17657 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
17658 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
17659 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
17660 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
17661 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
17662 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
17663 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
17664 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
17665 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
17666 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
17667 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
17668 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
17669 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
17670 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
17671 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
17672 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
17673 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
17674 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
17675 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
17676 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
17677 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
17678 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
17679 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
17680 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
17681 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
17682 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
17683 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
17684 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
17685 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
17686 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
17687 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
17688 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
17689 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
17690 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
17691 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
17692 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
17693 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
17694 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
17695 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
17696 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
17697 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
17698 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
17699 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
17700 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
17701 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
17702 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
17703 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
17704 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
17705 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
17706 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
17707 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
17708 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
17709 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
17710 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
17711 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
17712 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
17713 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
17714 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
17715 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
17716 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
17717 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
17718 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
17719 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
17720 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
17721 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
17722 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
17723 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
17724 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
17725 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
17726 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
17727 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
17728 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
17729 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
17730 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
17740 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
17741 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
17742 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
17743 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
17744 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
17745 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
17746 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
17747 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
17757 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
17758 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
17759 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
17760 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
17761 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
17762 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
17763 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
17764 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
17765 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
17766 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
17767 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
17768 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
17769 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
17770 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
17771 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
17772 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
17773 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
17774 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
17775 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
17776 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
17777 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
17778 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
17779 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
17780 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
17781 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
17782 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
17783 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
17784 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
17785 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
17786 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
17787 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
17788 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
17789 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
17790 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
17791 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
17792 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
17793 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
17794 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
17795 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
17796 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
17797 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
17798 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
17799 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
17800 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
17801 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
17802 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
17803 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
17804 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
17805 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
17806 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
17807 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
17808 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
17809 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
17810 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
17811 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
17812 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
17813 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
17814 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
17815 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
17816 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
17817 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
17818 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
17819 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
17820 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
17821 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
17822 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
17823 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
17824 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
17825 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
17826 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
17827 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
17828 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
17829 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
17830 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
17831 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
17832 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
17833 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
17834 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
17835 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
17836 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
17837 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
17838 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
17839 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
17840 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
17841 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
17842 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
17843 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
17844 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
17845 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
17846 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
17847 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
17848 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
17849 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
17850 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
17851 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
17852 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
17853 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
17854 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
17855 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
17856 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
17857 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
17858 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
17859 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
17860 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
17861 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
17862 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
17863 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
17864 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
17865 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
17866 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
17867 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
17868 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
17869 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
17870 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
17871 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
17872 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
17873 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
17874 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
17875 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
17876 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
17877 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
17878 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
17879 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
17880 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
17881 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
17882 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
17883 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
17884 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
17885 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
17886 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
17887 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
17888 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
17889 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
17890 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
17891 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
17892 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
17893 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
17894 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
17895 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
17896 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
17897 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
17898 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
17899 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
17900 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
17901 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
17902 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
17903 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
17904 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
17905 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
17906 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
17907 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
17908 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
17909 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
17910 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
17911 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
17912 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
17913 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
17914 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
17915 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
17916 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
17917 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
17918 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
17919 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
17920 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
17921 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
17922 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
17923 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
17924 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
17925 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
17926 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
17927 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
17928 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
17929 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
17930 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
17931 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
17932 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
17933 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
17934 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
17935 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
17936 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
17937 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
17938 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
17939 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
17940 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
17941 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
17942 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
17943 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
17944 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
17945 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
17946 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
17947 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
17948 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
17949 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
17950 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
17951 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
17952 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
17953 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
17954 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
17955 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
17956 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
17957 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
17958 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
17959 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
17960 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
17961 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
17962 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
17963 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
17964 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
17965 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
17966 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
17967 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
17968 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
17969 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
17970 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
17971 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
17972 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
17973 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
17974 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
17975 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
17976 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
17977 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
17978 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
17979 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
17980 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
17981 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
17982 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
17983 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
17984 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
17985 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
17986 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
17987 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
17988 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
17989 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
17990 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
17991 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
17992 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
17993 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
17994 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
17995 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
17996 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
17997 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
17998 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
17999 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
18000 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
18001 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
18002 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
18003 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
18004 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
18005 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
18006 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
18007 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
18008 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
18009 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
18010 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
18011 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
18012 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
18013 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
18014 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
18015 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
18016 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
18017 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
18018 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
18019 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
18020 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
18021 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
18022 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
18023 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
18024 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
18025 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
18026 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
18027 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
18028 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
18029 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
18030 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
18031 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
18032 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
18033 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
18034 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
18035 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
18036 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
18037 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
18038 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
18039 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
18040 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
18041 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
18042 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
18043 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
18044 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
18045 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
18046 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
18047 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
18048 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
18049 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
18050 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
18051 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
18052 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
18053 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
18054 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
18055 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
18056 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
18057 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
18058 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
18059 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
18060 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
18061 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
18062 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
18063 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
18064 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
18065 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
18066 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
18067 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
18068 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
18069 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
18070 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
18071 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
18072 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
18073 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
18074 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
18075 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
18076 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
18077 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
18078 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
18079 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
18080 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
18081 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
18082 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
18083 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
18084 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
18085 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
18086 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
18087 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
18088 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
18089 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
18090 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
18091 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
18092 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
18093 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
18094 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
18095 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
18096 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
18097 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
18098 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
18099 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
18100 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
18101 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
18102 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
18103 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
18104 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
18105 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
18106 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
18107 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
18108 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
18109 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
18110 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
18111 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
18112 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
18113 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
18114 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
18115 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
18116 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
18117 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
18118 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
18119 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
18120 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
18121 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
18122 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
18123 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
18124 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
18125 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
18126 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
18127 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
18128 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
18129 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
18130 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
18131 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
18132 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
18133 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
18134 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
18135 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
18136 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
18137 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
18138 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
18139 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
18140 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
18141 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
18142 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
18143 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
18144 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
18145 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
18146 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
18147 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
18148 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
18149 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
18150 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
18151 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
18152 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
18153 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
18154 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
18155 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
18156 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
18157 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
18158 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
18159 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
18160 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
18161 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
18162 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
18163 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
18164 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
18165 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
18166 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
18167 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
18168 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
18169 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
18170 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
18171 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
18172 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
18173 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
18174 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
18175 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
18176 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
18177 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
18178 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
18179 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
18180 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
18181 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
18182 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
18183 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
18184 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
18185 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
18186 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
18187 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
18188 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
18189 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
18190 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
18191 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
18192 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
18193 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
18194 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
18195 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
18196 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
18197 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
18198 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
18199 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
18200 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
18201 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
18202 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
18203 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
18204 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
18205 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
18206 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
18207 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
18208 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
18209 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
18210 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
18211 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
18212 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
18213 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
18214 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
18215 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
18216 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
18217 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
18218 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
18219 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
18220 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
18221 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
18222 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
18223 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
18224 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
18225 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
18226 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
18227 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
18228 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
18229 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
18230 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
18231 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
18232 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
18233 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
18234 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
18235 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
18236 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
18237 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
18238 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
18239 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
18240 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
18241 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
18242 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
18243 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
18244 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
18245 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
18246 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
18247 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
18248 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
18249 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
18250 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
18251 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
18252 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
18253 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
18254 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
18255 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
18256 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
18257 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
18258 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
18259 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
18260 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
18261 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
18262 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
18263 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
18264 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
18265 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
18266 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
18267 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
18268 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
18278 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
18279 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
18280 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
18281 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
18282 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
18283 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
18284 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
18285 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
18286 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
18287 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
18288 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
18289 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
18290 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
18291 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
18292 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
18293 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
18294 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
18295 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
18296 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
18297 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
18298 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
18299 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
18300 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
18301 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
18302 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
18303 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
18304 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
18305 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
18306 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
18307 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
18308 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
18309 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
18310 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
18311 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
18312 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
18313 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
18314 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
18315 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
18316 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
18317 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
18318 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
18319 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
18320 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
18321 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
18322 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
18323 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
18324 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
18325 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
18326 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
18327 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
18328 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
18329 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
18330 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
18331 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
18332 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
18333 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
18334 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
18335 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
18336 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
18337 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
18338 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
18339 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
18340 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
18341 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
18342 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
18343 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
18344 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
18345 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
18346 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
18347 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
18348 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
18349 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
18350 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
18351 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
18352 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
18353 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
18354 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
18355 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
18356 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
18357 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
18358 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
18359 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
18360 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
18361 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
18362 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
18363 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
18364 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
18365 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
18366 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
18367 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
18377 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
18378 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
18379 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
18380 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
18381 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
18382 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
18383 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
18384 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
18385 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
18386 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
18387 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
18388 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
18389 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
18390 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
18391 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
18392 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
18393 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
18394 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
18395 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
18396 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
18397 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
18398 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
18399 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
18400 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
18401 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
18402 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
18403 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
18404 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
18405 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
18406 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
18407 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
18408 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
18409 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
18410 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
18411 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
18412 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
18413 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
18414 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
18415 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
18416 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
18417 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
18418 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
18419 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
18420 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
18421 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
18422 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
18423 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
18424 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
18425 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
18426 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
18427 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
18428 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
18429 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
18430 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
18431 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
18432 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
18433 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
18434 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
18435 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
18436 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
18437 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
18438 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
18439 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
18440 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
18441 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
18442 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
18443 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
18444 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
18445 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
18446 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
18447 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
18448 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
18449 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
18450 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
18451 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
18452 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
18453 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
18454 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
18455 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
18456 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
18457 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
18458 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
18459 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
18460 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
18461 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
18462 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
18463 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
18464 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
18465 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
18466 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
18467 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
18468 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
18469 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
18470 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
18471 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
18472 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
18473 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
18474 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
18475 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
18476 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
18477 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
18478 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
18479 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
18480 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
18481 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
18482 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
18492 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_CHECKER_TYPE,
18493 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_0_WIDTH },
18494 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_CHECKER_TYPE,
18495 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_1_WIDTH },
18496 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_CHECKER_TYPE,
18497 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_2_WIDTH },
18498 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_CHECKER_TYPE,
18499 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_3_WIDTH },
18500 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_CHECKER_TYPE,
18501 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_4_WIDTH },
18502 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_CHECKER_TYPE,
18503 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_5_WIDTH },
18504 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_CHECKER_TYPE,
18505 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_6_WIDTH },
18506 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_CHECKER_TYPE,
18507 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_7_WIDTH },
18508 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_CHECKER_TYPE,
18509 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_8_WIDTH },
18510 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_CHECKER_TYPE,
18511 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_9_WIDTH },
18512 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_CHECKER_TYPE,
18513 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_10_WIDTH },
18514 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_CHECKER_TYPE,
18515 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_11_WIDTH },
18516 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_CHECKER_TYPE,
18517 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_12_WIDTH },
18518 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_CHECKER_TYPE,
18519 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_13_WIDTH },
18520 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_CHECKER_TYPE,
18521 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_14_WIDTH },
18522 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_CHECKER_TYPE,
18523 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_15_WIDTH },
18524 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_CHECKER_TYPE,
18525 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_16_WIDTH },
18526 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_CHECKER_TYPE,
18527 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_17_WIDTH },
18528 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_CHECKER_TYPE,
18529 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_18_WIDTH },
18530 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_CHECKER_TYPE,
18531 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_19_WIDTH },
18532 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_CHECKER_TYPE,
18533 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_20_WIDTH },
18534 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_CHECKER_TYPE,
18535 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_21_WIDTH },
18536 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_CHECKER_TYPE,
18537 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_22_WIDTH },
18538 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_CHECKER_TYPE,
18539 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_23_WIDTH },
18540 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_CHECKER_TYPE,
18541 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_24_WIDTH },
18542 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_CHECKER_TYPE,
18543 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_25_WIDTH },
18544 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_CHECKER_TYPE,
18545 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_26_WIDTH },
18546 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_CHECKER_TYPE,
18547 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_27_WIDTH },
18548 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_CHECKER_TYPE,
18549 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_28_WIDTH },
18550 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_CHECKER_TYPE,
18551 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_29_WIDTH },
18552 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_CHECKER_TYPE,
18553 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_30_WIDTH },
18554 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_CHECKER_TYPE,
18555 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_31_WIDTH },
18556 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_CHECKER_TYPE,
18557 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_32_WIDTH },
18558 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_CHECKER_TYPE,
18559 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_33_WIDTH },
18560 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_CHECKER_TYPE,
18561 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_34_WIDTH },
18562 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_CHECKER_TYPE,
18563 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_35_WIDTH },
18564 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_CHECKER_TYPE,
18565 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_36_WIDTH },
18566 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_CHECKER_TYPE,
18567 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_37_WIDTH },
18568 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_CHECKER_TYPE,
18569 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_38_WIDTH },
18570 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_CHECKER_TYPE,
18571 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_39_WIDTH },
18572 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_CHECKER_TYPE,
18573 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_40_WIDTH },
18574 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_CHECKER_TYPE,
18575 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_41_WIDTH },
18576 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_CHECKER_TYPE,
18577 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_42_WIDTH },
18578 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_CHECKER_TYPE,
18579 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_43_WIDTH },
18580 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_CHECKER_TYPE,
18581 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_44_WIDTH },
18582 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_CHECKER_TYPE,
18583 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_45_WIDTH },
18584 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_CHECKER_TYPE,
18585 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_46_WIDTH },
18586 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_CHECKER_TYPE,
18587 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_47_WIDTH },
18588 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_CHECKER_TYPE,
18589 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_48_WIDTH },
18590 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_CHECKER_TYPE,
18591 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_49_WIDTH },
18592 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_CHECKER_TYPE,
18593 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_50_WIDTH },
18594 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_CHECKER_TYPE,
18595 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_51_WIDTH },
18596 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_CHECKER_TYPE,
18597 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_52_WIDTH },
18598 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_CHECKER_TYPE,
18599 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_53_WIDTH },
18600 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_CHECKER_TYPE,
18601 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_54_WIDTH },
18602 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_CHECKER_TYPE,
18603 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_55_WIDTH },
18604 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_CHECKER_TYPE,
18605 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_56_WIDTH },
18606 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_CHECKER_TYPE,
18607 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_57_WIDTH },
18608 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_CHECKER_TYPE,
18609 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_58_WIDTH },
18610 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_CHECKER_TYPE,
18611 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_59_WIDTH },
18612 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_CHECKER_TYPE,
18613 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_60_WIDTH },
18614 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_CHECKER_TYPE,
18615 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_61_WIDTH },
18616 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_CHECKER_TYPE,
18617 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_62_WIDTH },
18618 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_CHECKER_TYPE,
18619 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_63_WIDTH },
18620 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_CHECKER_TYPE,
18621 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_64_WIDTH },
18622 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_CHECKER_TYPE,
18623 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_65_WIDTH },
18624 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_CHECKER_TYPE,
18625 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_66_WIDTH },
18626 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_CHECKER_TYPE,
18627 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_67_WIDTH },
18628 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_CHECKER_TYPE,
18629 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_68_WIDTH },
18630 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_CHECKER_TYPE,
18631 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_69_WIDTH },
18632 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_CHECKER_TYPE,
18633 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_70_WIDTH },
18634 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_CHECKER_TYPE,
18635 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_71_WIDTH },
18636 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_CHECKER_TYPE,
18637 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_72_WIDTH },
18638 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_CHECKER_TYPE,
18639 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_73_WIDTH },
18640 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_CHECKER_TYPE,
18641 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_74_WIDTH },
18642 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_CHECKER_TYPE,
18643 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_75_WIDTH },
18644 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_CHECKER_TYPE,
18645 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_76_WIDTH },
18646 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_CHECKER_TYPE,
18647 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_77_WIDTH },
18648 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_CHECKER_TYPE,
18649 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_78_WIDTH },
18650 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_CHECKER_TYPE,
18651 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_79_WIDTH },
18652 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_CHECKER_TYPE,
18653 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_80_WIDTH },
18654 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_CHECKER_TYPE,
18655 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_81_WIDTH },
18656 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_CHECKER_TYPE,
18657 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_82_WIDTH },
18658 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_CHECKER_TYPE,
18659 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_83_WIDTH },
18660 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_CHECKER_TYPE,
18661 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_84_WIDTH },
18662 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_CHECKER_TYPE,
18663 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_85_WIDTH },
18664 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_CHECKER_TYPE,
18665 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_86_WIDTH },
18666 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_CHECKER_TYPE,
18667 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_87_WIDTH },
18668 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_CHECKER_TYPE,
18669 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_88_WIDTH },
18670 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_CHECKER_TYPE,
18671 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_89_WIDTH },
18672 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_CHECKER_TYPE,
18673 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_90_WIDTH },
18674 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_CHECKER_TYPE,
18675 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_91_WIDTH },
18676 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_CHECKER_TYPE,
18677 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_92_WIDTH },
18678 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_CHECKER_TYPE,
18679 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_93_WIDTH },
18680 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_CHECKER_TYPE,
18681 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_94_WIDTH },
18682 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_CHECKER_TYPE,
18683 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_95_WIDTH },
18684 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_CHECKER_TYPE,
18685 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_96_WIDTH },
18686 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_CHECKER_TYPE,
18687 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_97_WIDTH },
18688 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_CHECKER_TYPE,
18689 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_98_WIDTH },
18690 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_CHECKER_TYPE,
18691 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_99_WIDTH },
18692 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_CHECKER_TYPE,
18693 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_100_WIDTH },
18694 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_CHECKER_TYPE,
18695 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_101_WIDTH },
18696 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_CHECKER_TYPE,
18697 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_102_WIDTH },
18698 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_CHECKER_TYPE,
18699 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_103_WIDTH },
18700 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_CHECKER_TYPE,
18701 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_104_WIDTH },
18702 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_CHECKER_TYPE,
18703 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_105_WIDTH },
18704 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_CHECKER_TYPE,
18705 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_106_WIDTH },
18706 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_CHECKER_TYPE,
18707 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_107_WIDTH },
18708 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_CHECKER_TYPE,
18709 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_108_WIDTH },
18710 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_CHECKER_TYPE,
18711 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_109_WIDTH },
18712 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_CHECKER_TYPE,
18713 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_110_WIDTH },
18714 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_CHECKER_TYPE,
18715 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_111_WIDTH },
18716 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_CHECKER_TYPE,
18717 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_112_WIDTH },
18718 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_CHECKER_TYPE,
18719 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_113_WIDTH },
18720 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_CHECKER_TYPE,
18721 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_114_WIDTH },
18722 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_CHECKER_TYPE,
18723 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_115_WIDTH },
18724 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_CHECKER_TYPE,
18725 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_116_WIDTH },
18726 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_CHECKER_TYPE,
18727 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_117_WIDTH },
18728 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_CHECKER_TYPE,
18729 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_118_WIDTH },
18730 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_CHECKER_TYPE,
18731 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_119_WIDTH },
18732 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_CHECKER_TYPE,
18733 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_120_WIDTH },
18734 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_CHECKER_TYPE,
18735 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_121_WIDTH },
18736 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_CHECKER_TYPE,
18737 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_122_WIDTH },
18738 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_CHECKER_TYPE,
18739 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_123_WIDTH },
18740 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_CHECKER_TYPE,
18741 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_124_WIDTH },
18742 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_CHECKER_TYPE,
18743 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_125_WIDTH },
18744 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_CHECKER_TYPE,
18745 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_126_WIDTH },
18746 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_CHECKER_TYPE,
18747 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_127_WIDTH },
18748 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_CHECKER_TYPE,
18749 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_128_WIDTH },
18750 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_CHECKER_TYPE,
18751 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_129_WIDTH },
18752 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_CHECKER_TYPE,
18753 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_130_WIDTH },
18754 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_CHECKER_TYPE,
18755 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_131_WIDTH },
18756 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_CHECKER_TYPE,
18757 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_132_WIDTH },
18758 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_CHECKER_TYPE,
18759 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_133_WIDTH },
18760 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_CHECKER_TYPE,
18761 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_134_WIDTH },
18762 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_CHECKER_TYPE,
18763 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_135_WIDTH },
18764 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_CHECKER_TYPE,
18765 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_136_WIDTH },
18766 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_CHECKER_TYPE,
18767 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_137_WIDTH },
18768 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_CHECKER_TYPE,
18769 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_138_WIDTH },
18770 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_CHECKER_TYPE,
18771 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_139_WIDTH },
18772 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_CHECKER_TYPE,
18773 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_140_WIDTH },
18774 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_CHECKER_TYPE,
18775 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_141_WIDTH },
18776 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_CHECKER_TYPE,
18777 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_142_WIDTH },
18778 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_CHECKER_TYPE,
18779 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_143_WIDTH },
18780 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_CHECKER_TYPE,
18781 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_144_WIDTH },
18782 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_CHECKER_TYPE,
18783 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_145_WIDTH },
18784 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_CHECKER_TYPE,
18785 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_146_WIDTH },
18786 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_CHECKER_TYPE,
18787 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_147_WIDTH },
18788 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_CHECKER_TYPE,
18789 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_148_WIDTH },
18790 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_CHECKER_TYPE,
18791 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_149_WIDTH },
18792 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_CHECKER_TYPE,
18793 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_150_WIDTH },
18794 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_CHECKER_TYPE,
18795 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_151_WIDTH },
18796 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_CHECKER_TYPE,
18797 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_152_WIDTH },
18798 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_CHECKER_TYPE,
18799 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_153_WIDTH },
18800 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_CHECKER_TYPE,
18801 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_154_WIDTH },
18802 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_CHECKER_TYPE,
18803 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_155_WIDTH },
18804 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_CHECKER_TYPE,
18805 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_156_WIDTH },
18806 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_CHECKER_TYPE,
18807 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_157_WIDTH },
18808 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_CHECKER_TYPE,
18809 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_158_WIDTH },
18810 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_CHECKER_TYPE,
18811 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_159_WIDTH },
18812 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_CHECKER_TYPE,
18813 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_160_WIDTH },
18814 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_CHECKER_TYPE,
18815 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_161_WIDTH },
18816 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_CHECKER_TYPE,
18817 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_162_WIDTH },
18818 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_CHECKER_TYPE,
18819 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_163_WIDTH },
18820 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_CHECKER_TYPE,
18821 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_164_WIDTH },
18822 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_CHECKER_TYPE,
18823 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_165_WIDTH },
18824 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_CHECKER_TYPE,
18825 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_166_WIDTH },
18826 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_CHECKER_TYPE,
18827 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_167_WIDTH },
18828 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_CHECKER_TYPE,
18829 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_168_WIDTH },
18830 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_CHECKER_TYPE,
18831 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_169_WIDTH },
18832 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_CHECKER_TYPE,
18833 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_170_WIDTH },
18834 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_CHECKER_TYPE,
18835 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_171_WIDTH },
18836 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_CHECKER_TYPE,
18837 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_172_WIDTH },
18838 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_CHECKER_TYPE,
18839 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_173_WIDTH },
18840 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_CHECKER_TYPE,
18841 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_174_WIDTH },
18842 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_CHECKER_TYPE,
18843 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_175_WIDTH },
18844 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_CHECKER_TYPE,
18845 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_176_WIDTH },
18846 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_CHECKER_TYPE,
18847 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_177_WIDTH },
18848 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_CHECKER_TYPE,
18849 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_178_WIDTH },
18850 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_CHECKER_TYPE,
18851 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_179_WIDTH },
18852 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_CHECKER_TYPE,
18853 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_180_WIDTH },
18854 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_CHECKER_TYPE,
18855 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_181_WIDTH },
18856 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_CHECKER_TYPE,
18857 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_182_WIDTH },
18858 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_CHECKER_TYPE,
18859 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_183_WIDTH },
18860 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_CHECKER_TYPE,
18861 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_184_WIDTH },
18862 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_CHECKER_TYPE,
18863 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_185_WIDTH },
18864 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_CHECKER_TYPE,
18865 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_186_WIDTH },
18866 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_CHECKER_TYPE,
18867 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_187_WIDTH },
18868 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_CHECKER_TYPE,
18869 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_188_WIDTH },
18870 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_CHECKER_TYPE,
18871 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_189_WIDTH },
18872 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_CHECKER_TYPE,
18873 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_190_WIDTH },
18874 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_CHECKER_TYPE,
18875 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_191_WIDTH },
18876 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_CHECKER_TYPE,
18877 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_192_WIDTH },
18878 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_CHECKER_TYPE,
18879 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_193_WIDTH },
18880 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_CHECKER_TYPE,
18881 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_194_WIDTH },
18882 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_CHECKER_TYPE,
18883 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_195_WIDTH },
18884 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_CHECKER_TYPE,
18885 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_196_WIDTH },
18886 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_CHECKER_TYPE,
18887 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_197_WIDTH },
18888 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_CHECKER_TYPE,
18889 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_198_WIDTH },
18890 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_CHECKER_TYPE,
18891 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_199_WIDTH },
18892 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_CHECKER_TYPE,
18893 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_200_WIDTH },
18894 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_CHECKER_TYPE,
18895 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_201_WIDTH },
18896 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_CHECKER_TYPE,
18897 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_202_WIDTH },
18898 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_CHECKER_TYPE,
18899 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_203_WIDTH },
18900 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_CHECKER_TYPE,
18901 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_204_WIDTH },
18902 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_CHECKER_TYPE,
18903 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_205_WIDTH },
18904 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_CHECKER_TYPE,
18905 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_206_WIDTH },
18906 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_CHECKER_TYPE,
18907 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_207_WIDTH },
18908 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_CHECKER_TYPE,
18909 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_208_WIDTH },
18910 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_CHECKER_TYPE,
18911 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_209_WIDTH },
18912 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_CHECKER_TYPE,
18913 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_210_WIDTH },
18914 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_CHECKER_TYPE,
18915 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_211_WIDTH },
18916 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_CHECKER_TYPE,
18917 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_212_WIDTH },
18918 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_CHECKER_TYPE,
18919 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_213_WIDTH },
18920 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_CHECKER_TYPE,
18921 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_214_WIDTH },
18922 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_CHECKER_TYPE,
18923 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_215_WIDTH },
18924 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_CHECKER_TYPE,
18925 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_216_WIDTH },
18926 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_CHECKER_TYPE,
18927 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_217_WIDTH },
18928 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_CHECKER_TYPE,
18929 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_218_WIDTH },
18930 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_CHECKER_TYPE,
18931 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_219_WIDTH },
18932 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_CHECKER_TYPE,
18933 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_220_WIDTH },
18934 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_CHECKER_TYPE,
18935 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_221_WIDTH },
18936 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_CHECKER_TYPE,
18937 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_222_WIDTH },
18938 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_CHECKER_TYPE,
18939 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_223_WIDTH },
18940 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_CHECKER_TYPE,
18941 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_224_WIDTH },
18942 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_CHECKER_TYPE,
18943 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_225_WIDTH },
18944 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_CHECKER_TYPE,
18945 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_226_WIDTH },
18946 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_CHECKER_TYPE,
18947 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_227_WIDTH },
18948 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_CHECKER_TYPE,
18949 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_228_WIDTH },
18950 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_CHECKER_TYPE,
18951 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_229_WIDTH },
18952 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_CHECKER_TYPE,
18953 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_230_WIDTH },
18954 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_CHECKER_TYPE,
18955 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_231_WIDTH },
18956 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_CHECKER_TYPE,
18957 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_232_WIDTH },
18958 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_CHECKER_TYPE,
18959 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_233_WIDTH },
18960 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_CHECKER_TYPE,
18961 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_234_WIDTH },
18962 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_CHECKER_TYPE,
18963 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_235_WIDTH },
18964 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_CHECKER_TYPE,
18965 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_236_WIDTH },
18966 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_CHECKER_TYPE,
18967 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_237_WIDTH },
18968 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_CHECKER_TYPE,
18969 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_238_WIDTH },
18970 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_CHECKER_TYPE,
18971 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_239_WIDTH },
18972 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_CHECKER_TYPE,
18973 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_240_WIDTH },
18974 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_CHECKER_TYPE,
18975 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_241_WIDTH },
18976 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_CHECKER_TYPE,
18977 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_242_WIDTH },
18978 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_CHECKER_TYPE,
18979 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_243_WIDTH },
18980 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_CHECKER_TYPE,
18981 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_244_WIDTH },
18982 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_CHECKER_TYPE,
18983 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_245_WIDTH },
18984 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_CHECKER_TYPE,
18985 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_246_WIDTH },
18986 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_CHECKER_TYPE,
18987 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_247_WIDTH },
18988 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_CHECKER_TYPE,
18989 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_248_WIDTH },
18990 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_CHECKER_TYPE,
18991 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_249_WIDTH },
18992 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_CHECKER_TYPE,
18993 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_250_WIDTH },
18994 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_CHECKER_TYPE,
18995 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_251_WIDTH },
18996 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_CHECKER_TYPE,
18997 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_252_WIDTH },
18998 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_CHECKER_TYPE,
18999 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_253_WIDTH },
19000 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_CHECKER_TYPE,
19001 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_254_WIDTH },
19002 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_CHECKER_TYPE,
19003 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_GROUP_255_WIDTH },
19013 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_CHECKER_TYPE,
19014 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_0_WIDTH },
19015 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_CHECKER_TYPE,
19016 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_1_WIDTH },
19017 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_CHECKER_TYPE,
19018 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_2_WIDTH },
19019 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_CHECKER_TYPE,
19020 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_3_WIDTH },
19021 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_CHECKER_TYPE,
19022 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_4_WIDTH },
19023 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_CHECKER_TYPE,
19024 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_5_WIDTH },
19025 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_CHECKER_TYPE,
19026 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_6_WIDTH },
19027 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_CHECKER_TYPE,
19028 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_7_WIDTH },
19029 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_CHECKER_TYPE,
19030 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_8_WIDTH },
19031 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_CHECKER_TYPE,
19032 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_9_WIDTH },
19033 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_CHECKER_TYPE,
19034 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_10_WIDTH },
19035 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_CHECKER_TYPE,
19036 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_11_WIDTH },
19037 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_CHECKER_TYPE,
19038 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_12_WIDTH },
19039 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_CHECKER_TYPE,
19040 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_13_WIDTH },
19041 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_CHECKER_TYPE,
19042 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_14_WIDTH },
19043 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_CHECKER_TYPE,
19044 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_15_WIDTH },
19045 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_CHECKER_TYPE,
19046 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_16_WIDTH },
19047 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_CHECKER_TYPE,
19048 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_17_WIDTH },
19049 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_CHECKER_TYPE,
19050 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_18_WIDTH },
19051 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_CHECKER_TYPE,
19052 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_19_WIDTH },
19053 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_CHECKER_TYPE,
19054 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_20_WIDTH },
19055 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_CHECKER_TYPE,
19056 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_21_WIDTH },
19057 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_CHECKER_TYPE,
19058 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_22_WIDTH },
19059 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_CHECKER_TYPE,
19060 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_23_WIDTH },
19061 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_CHECKER_TYPE,
19062 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_24_WIDTH },
19063 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_CHECKER_TYPE,
19064 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_25_WIDTH },
19065 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_CHECKER_TYPE,
19066 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_26_WIDTH },
19067 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_CHECKER_TYPE,
19068 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_27_WIDTH },
19069 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_CHECKER_TYPE,
19070 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_28_WIDTH },
19071 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_CHECKER_TYPE,
19072 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_29_WIDTH },
19073 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_CHECKER_TYPE,
19074 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_30_WIDTH },
19075 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_CHECKER_TYPE,
19076 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_31_WIDTH },
19077 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_CHECKER_TYPE,
19078 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_32_WIDTH },
19079 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_CHECKER_TYPE,
19080 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_33_WIDTH },
19081 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_CHECKER_TYPE,
19082 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_34_WIDTH },
19083 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_CHECKER_TYPE,
19084 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_35_WIDTH },
19085 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_CHECKER_TYPE,
19086 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_36_WIDTH },
19087 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_CHECKER_TYPE,
19088 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_37_WIDTH },
19089 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_CHECKER_TYPE,
19090 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_38_WIDTH },
19091 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_CHECKER_TYPE,
19092 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_39_WIDTH },
19093 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_CHECKER_TYPE,
19094 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_40_WIDTH },
19095 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_CHECKER_TYPE,
19096 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_41_WIDTH },
19097 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_CHECKER_TYPE,
19098 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_42_WIDTH },
19099 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_CHECKER_TYPE,
19100 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_43_WIDTH },
19101 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_CHECKER_TYPE,
19102 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_44_WIDTH },
19103 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_CHECKER_TYPE,
19104 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_45_WIDTH },
19105 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_CHECKER_TYPE,
19106 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_46_WIDTH },
19107 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_CHECKER_TYPE,
19108 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_47_WIDTH },
19109 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_CHECKER_TYPE,
19110 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_48_WIDTH },
19111 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_CHECKER_TYPE,
19112 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_49_WIDTH },
19113 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_CHECKER_TYPE,
19114 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_50_WIDTH },
19115 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_CHECKER_TYPE,
19116 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_51_WIDTH },
19117 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_CHECKER_TYPE,
19118 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_52_WIDTH },
19119 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_CHECKER_TYPE,
19120 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_53_WIDTH },
19121 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_CHECKER_TYPE,
19122 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_54_WIDTH },
19123 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_CHECKER_TYPE,
19124 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_55_WIDTH },
19125 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_CHECKER_TYPE,
19126 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_56_WIDTH },
19127 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_CHECKER_TYPE,
19128 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_57_WIDTH },
19129 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_CHECKER_TYPE,
19130 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_58_WIDTH },
19131 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_CHECKER_TYPE,
19132 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_59_WIDTH },
19133 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_CHECKER_TYPE,
19134 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_60_WIDTH },
19135 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_CHECKER_TYPE,
19136 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_61_WIDTH },
19137 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_CHECKER_TYPE,
19138 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_62_WIDTH },
19139 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_CHECKER_TYPE,
19140 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_63_WIDTH },
19141 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_CHECKER_TYPE,
19142 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_64_WIDTH },
19143 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_CHECKER_TYPE,
19144 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_65_WIDTH },
19145 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_CHECKER_TYPE,
19146 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_66_WIDTH },
19147 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_CHECKER_TYPE,
19148 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_67_WIDTH },
19149 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_CHECKER_TYPE,
19150 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_68_WIDTH },
19151 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_CHECKER_TYPE,
19152 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_69_WIDTH },
19153 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_CHECKER_TYPE,
19154 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_70_WIDTH },
19155 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_CHECKER_TYPE,
19156 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_71_WIDTH },
19157 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_CHECKER_TYPE,
19158 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_72_WIDTH },
19159 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_CHECKER_TYPE,
19160 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_73_WIDTH },
19161 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_CHECKER_TYPE,
19162 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_74_WIDTH },
19163 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_CHECKER_TYPE,
19164 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_75_WIDTH },
19165 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_CHECKER_TYPE,
19166 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_76_WIDTH },
19167 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_CHECKER_TYPE,
19168 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_77_WIDTH },
19169 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_CHECKER_TYPE,
19170 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_78_WIDTH },
19171 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_CHECKER_TYPE,
19172 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_79_WIDTH },
19173 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_CHECKER_TYPE,
19174 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_80_WIDTH },
19175 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_CHECKER_TYPE,
19176 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_81_WIDTH },
19177 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_CHECKER_TYPE,
19178 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_82_WIDTH },
19179 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_CHECKER_TYPE,
19180 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_83_WIDTH },
19181 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_CHECKER_TYPE,
19182 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_84_WIDTH },
19183 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_CHECKER_TYPE,
19184 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_85_WIDTH },
19185 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_CHECKER_TYPE,
19186 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_86_WIDTH },
19187 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_CHECKER_TYPE,
19188 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_87_WIDTH },
19189 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_CHECKER_TYPE,
19190 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_88_WIDTH },
19191 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_CHECKER_TYPE,
19192 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_89_WIDTH },
19193 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_CHECKER_TYPE,
19194 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_90_WIDTH },
19195 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_CHECKER_TYPE,
19196 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_91_WIDTH },
19197 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_CHECKER_TYPE,
19198 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_92_WIDTH },
19199 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_CHECKER_TYPE,
19200 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_93_WIDTH },
19201 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_CHECKER_TYPE,
19202 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_94_WIDTH },
19203 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_CHECKER_TYPE,
19204 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_95_WIDTH },
19205 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_CHECKER_TYPE,
19206 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_96_WIDTH },
19207 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_CHECKER_TYPE,
19208 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_97_WIDTH },
19209 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_CHECKER_TYPE,
19210 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_98_WIDTH },
19211 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_CHECKER_TYPE,
19212 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_99_WIDTH },
19213 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_CHECKER_TYPE,
19214 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_100_WIDTH },
19215 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_CHECKER_TYPE,
19216 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_101_WIDTH },
19217 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_CHECKER_TYPE,
19218 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_102_WIDTH },
19219 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_CHECKER_TYPE,
19220 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_103_WIDTH },
19221 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_CHECKER_TYPE,
19222 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_104_WIDTH },
19223 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_CHECKER_TYPE,
19224 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_105_WIDTH },
19225 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_CHECKER_TYPE,
19226 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_106_WIDTH },
19227 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_CHECKER_TYPE,
19228 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_107_WIDTH },
19229 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_CHECKER_TYPE,
19230 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_108_WIDTH },
19231 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_CHECKER_TYPE,
19232 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_109_WIDTH },
19233 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_CHECKER_TYPE,
19234 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_110_WIDTH },
19235 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_CHECKER_TYPE,
19236 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_111_WIDTH },
19237 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_CHECKER_TYPE,
19238 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_112_WIDTH },
19239 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_CHECKER_TYPE,
19240 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_113_WIDTH },
19241 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_CHECKER_TYPE,
19242 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_114_WIDTH },
19243 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_CHECKER_TYPE,
19244 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_115_WIDTH },
19245 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_CHECKER_TYPE,
19246 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_116_WIDTH },
19247 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_CHECKER_TYPE,
19248 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_117_WIDTH },
19249 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_CHECKER_TYPE,
19250 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_118_WIDTH },
19251 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_CHECKER_TYPE,
19252 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_119_WIDTH },
19253 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_CHECKER_TYPE,
19254 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_120_WIDTH },
19255 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_CHECKER_TYPE,
19256 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_121_WIDTH },
19257 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_CHECKER_TYPE,
19258 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_122_WIDTH },
19259 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_CHECKER_TYPE,
19260 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_123_WIDTH },
19261 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_CHECKER_TYPE,
19262 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_124_WIDTH },
19263 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_CHECKER_TYPE,
19264 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_125_WIDTH },
19265 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_CHECKER_TYPE,
19266 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_126_WIDTH },
19267 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_CHECKER_TYPE,
19268 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_127_WIDTH },
19269 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_CHECKER_TYPE,
19270 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_128_WIDTH },
19271 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_CHECKER_TYPE,
19272 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_129_WIDTH },
19273 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_CHECKER_TYPE,
19274 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_130_WIDTH },
19275 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_CHECKER_TYPE,
19276 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_131_WIDTH },
19277 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_CHECKER_TYPE,
19278 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_132_WIDTH },
19279 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_CHECKER_TYPE,
19280 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_133_WIDTH },
19281 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_CHECKER_TYPE,
19282 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_134_WIDTH },
19283 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_CHECKER_TYPE,
19284 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_135_WIDTH },
19285 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_CHECKER_TYPE,
19286 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_136_WIDTH },
19287 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_CHECKER_TYPE,
19288 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_137_WIDTH },
19289 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_CHECKER_TYPE,
19290 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_138_WIDTH },
19291 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_CHECKER_TYPE,
19292 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_139_WIDTH },
19293 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_CHECKER_TYPE,
19294 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_140_WIDTH },
19295 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_CHECKER_TYPE,
19296 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_141_WIDTH },
19297 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_CHECKER_TYPE,
19298 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_142_WIDTH },
19299 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_CHECKER_TYPE,
19300 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_143_WIDTH },
19301 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_CHECKER_TYPE,
19302 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_144_WIDTH },
19303 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_CHECKER_TYPE,
19304 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_145_WIDTH },
19305 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_CHECKER_TYPE,
19306 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_146_WIDTH },
19307 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_CHECKER_TYPE,
19308 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_147_WIDTH },
19309 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_CHECKER_TYPE,
19310 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_148_WIDTH },
19311 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_CHECKER_TYPE,
19312 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_149_WIDTH },
19313 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_CHECKER_TYPE,
19314 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_150_WIDTH },
19315 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_CHECKER_TYPE,
19316 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_151_WIDTH },
19317 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_CHECKER_TYPE,
19318 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_152_WIDTH },
19319 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_CHECKER_TYPE,
19320 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_153_WIDTH },
19321 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_CHECKER_TYPE,
19322 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_154_WIDTH },
19323 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_CHECKER_TYPE,
19324 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_155_WIDTH },
19325 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_CHECKER_TYPE,
19326 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_156_WIDTH },
19327 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_CHECKER_TYPE,
19328 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_157_WIDTH },
19329 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_CHECKER_TYPE,
19330 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_158_WIDTH },
19331 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_CHECKER_TYPE,
19332 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_159_WIDTH },
19333 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_CHECKER_TYPE,
19334 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_160_WIDTH },
19335 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_CHECKER_TYPE,
19336 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_161_WIDTH },
19337 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_CHECKER_TYPE,
19338 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_162_WIDTH },
19339 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_CHECKER_TYPE,
19340 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_163_WIDTH },
19341 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_CHECKER_TYPE,
19342 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_164_WIDTH },
19343 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_CHECKER_TYPE,
19344 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_165_WIDTH },
19345 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_CHECKER_TYPE,
19346 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_166_WIDTH },
19347 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_CHECKER_TYPE,
19348 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_167_WIDTH },
19349 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_CHECKER_TYPE,
19350 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_168_WIDTH },
19351 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_CHECKER_TYPE,
19352 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_169_WIDTH },
19353 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_CHECKER_TYPE,
19354 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_170_WIDTH },
19355 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_CHECKER_TYPE,
19356 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_171_WIDTH },
19357 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_CHECKER_TYPE,
19358 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_172_WIDTH },
19359 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_CHECKER_TYPE,
19360 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_173_WIDTH },
19361 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_CHECKER_TYPE,
19362 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_174_WIDTH },
19363 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_CHECKER_TYPE,
19364 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_175_WIDTH },
19365 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_CHECKER_TYPE,
19366 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_176_WIDTH },
19367 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_CHECKER_TYPE,
19368 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_177_WIDTH },
19369 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_CHECKER_TYPE,
19370 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_178_WIDTH },
19371 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_CHECKER_TYPE,
19372 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_179_WIDTH },
19373 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_CHECKER_TYPE,
19374 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_180_WIDTH },
19375 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_CHECKER_TYPE,
19376 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_181_WIDTH },
19377 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_CHECKER_TYPE,
19378 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_182_WIDTH },
19379 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_CHECKER_TYPE,
19380 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_183_WIDTH },
19381 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_CHECKER_TYPE,
19382 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_184_WIDTH },
19383 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_CHECKER_TYPE,
19384 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_185_WIDTH },
19385 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_CHECKER_TYPE,
19386 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_186_WIDTH },
19387 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_CHECKER_TYPE,
19388 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_187_WIDTH },
19389 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_CHECKER_TYPE,
19390 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_188_WIDTH },
19391 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_CHECKER_TYPE,
19392 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_189_WIDTH },
19393 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_CHECKER_TYPE,
19394 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_190_WIDTH },
19395 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_CHECKER_TYPE,
19396 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_191_WIDTH },
19397 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_CHECKER_TYPE,
19398 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_192_WIDTH },
19399 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_CHECKER_TYPE,
19400 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_193_WIDTH },
19401 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_CHECKER_TYPE,
19402 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_194_WIDTH },
19403 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_CHECKER_TYPE,
19404 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_195_WIDTH },
19405 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_CHECKER_TYPE,
19406 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_196_WIDTH },
19407 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_CHECKER_TYPE,
19408 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_197_WIDTH },
19409 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_CHECKER_TYPE,
19410 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_198_WIDTH },
19411 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_CHECKER_TYPE,
19412 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_199_WIDTH },
19413 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_CHECKER_TYPE,
19414 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_200_WIDTH },
19415 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_CHECKER_TYPE,
19416 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_201_WIDTH },
19417 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_CHECKER_TYPE,
19418 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_202_WIDTH },
19419 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_CHECKER_TYPE,
19420 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_203_WIDTH },
19421 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_CHECKER_TYPE,
19422 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_204_WIDTH },
19423 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_CHECKER_TYPE,
19424 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_205_WIDTH },
19425 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_CHECKER_TYPE,
19426 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_206_WIDTH },
19427 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_CHECKER_TYPE,
19428 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_207_WIDTH },
19429 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_CHECKER_TYPE,
19430 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_208_WIDTH },
19431 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_CHECKER_TYPE,
19432 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_209_WIDTH },
19433 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_CHECKER_TYPE,
19434 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_210_WIDTH },
19435 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_CHECKER_TYPE,
19436 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_211_WIDTH },
19437 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_CHECKER_TYPE,
19438 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_212_WIDTH },
19439 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_CHECKER_TYPE,
19440 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_213_WIDTH },
19441 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_CHECKER_TYPE,
19442 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_214_WIDTH },
19443 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_CHECKER_TYPE,
19444 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_215_WIDTH },
19445 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_CHECKER_TYPE,
19446 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_216_WIDTH },
19447 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_CHECKER_TYPE,
19448 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_217_WIDTH },
19449 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_CHECKER_TYPE,
19450 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_218_WIDTH },
19451 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_CHECKER_TYPE,
19452 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_219_WIDTH },
19453 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_CHECKER_TYPE,
19454 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_220_WIDTH },
19455 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_CHECKER_TYPE,
19456 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_221_WIDTH },
19457 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_CHECKER_TYPE,
19458 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_222_WIDTH },
19459 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_CHECKER_TYPE,
19460 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_223_WIDTH },
19461 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_CHECKER_TYPE,
19462 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_224_WIDTH },
19463 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_CHECKER_TYPE,
19464 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_225_WIDTH },
19465 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_CHECKER_TYPE,
19466 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_226_WIDTH },
19467 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_CHECKER_TYPE,
19468 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_227_WIDTH },
19469 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_CHECKER_TYPE,
19470 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_228_WIDTH },
19471 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_CHECKER_TYPE,
19472 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_229_WIDTH },
19473 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_CHECKER_TYPE,
19474 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_230_WIDTH },
19475 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_CHECKER_TYPE,
19476 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_231_WIDTH },
19477 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_CHECKER_TYPE,
19478 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_232_WIDTH },
19479 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_CHECKER_TYPE,
19480 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_233_WIDTH },
19481 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_CHECKER_TYPE,
19482 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_234_WIDTH },
19483 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_CHECKER_TYPE,
19484 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_235_WIDTH },
19485 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_CHECKER_TYPE,
19486 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_236_WIDTH },
19487 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_CHECKER_TYPE,
19488 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_237_WIDTH },
19489 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_CHECKER_TYPE,
19490 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_238_WIDTH },
19491 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_CHECKER_TYPE,
19492 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_239_WIDTH },
19493 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_CHECKER_TYPE,
19494 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_240_WIDTH },
19495 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_CHECKER_TYPE,
19496 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_241_WIDTH },
19497 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_CHECKER_TYPE,
19498 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_242_WIDTH },
19499 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_CHECKER_TYPE,
19500 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_243_WIDTH },
19501 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_CHECKER_TYPE,
19502 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_244_WIDTH },
19503 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_CHECKER_TYPE,
19504 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_245_WIDTH },
19505 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_CHECKER_TYPE,
19506 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_246_WIDTH },
19507 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_CHECKER_TYPE,
19508 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_247_WIDTH },
19509 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_CHECKER_TYPE,
19510 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_248_WIDTH },
19511 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_CHECKER_TYPE,
19512 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_249_WIDTH },
19513 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_CHECKER_TYPE,
19514 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_250_WIDTH },
19515 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_CHECKER_TYPE,
19516 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_251_WIDTH },
19517 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_CHECKER_TYPE,
19518 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_252_WIDTH },
19519 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_CHECKER_TYPE,
19520 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_253_WIDTH },
19521 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_CHECKER_TYPE,
19522 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_254_WIDTH },
19523 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_CHECKER_TYPE,
19524 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_GROUP_255_WIDTH },
19534 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_CHECKER_TYPE,
19535 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_0_WIDTH },
19536 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_CHECKER_TYPE,
19537 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_1_WIDTH },
19538 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_CHECKER_TYPE,
19539 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_2_WIDTH },
19540 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_CHECKER_TYPE,
19541 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_3_WIDTH },
19542 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_CHECKER_TYPE,
19543 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_4_WIDTH },
19544 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_CHECKER_TYPE,
19545 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_5_WIDTH },
19546 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_CHECKER_TYPE,
19547 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_6_WIDTH },
19548 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_CHECKER_TYPE,
19549 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_7_WIDTH },
19550 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_CHECKER_TYPE,
19551 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_8_WIDTH },
19552 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_CHECKER_TYPE,
19553 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_9_WIDTH },
19554 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_CHECKER_TYPE,
19555 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_10_WIDTH },
19556 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_CHECKER_TYPE,
19557 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_11_WIDTH },
19558 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_CHECKER_TYPE,
19559 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_12_WIDTH },
19560 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_CHECKER_TYPE,
19561 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_13_WIDTH },
19562 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_CHECKER_TYPE,
19563 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_14_WIDTH },
19564 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_CHECKER_TYPE,
19565 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_15_WIDTH },
19566 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_CHECKER_TYPE,
19567 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_16_WIDTH },
19568 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_CHECKER_TYPE,
19569 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_17_WIDTH },
19570 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_CHECKER_TYPE,
19571 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_18_WIDTH },
19572 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_CHECKER_TYPE,
19573 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_19_WIDTH },
19574 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_CHECKER_TYPE,
19575 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_20_WIDTH },
19576 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_CHECKER_TYPE,
19577 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_21_WIDTH },
19578 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_CHECKER_TYPE,
19579 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_22_WIDTH },
19580 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_CHECKER_TYPE,
19581 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_23_WIDTH },
19582 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_CHECKER_TYPE,
19583 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_24_WIDTH },
19584 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_CHECKER_TYPE,
19585 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_25_WIDTH },
19586 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_CHECKER_TYPE,
19587 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_26_WIDTH },
19588 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_CHECKER_TYPE,
19589 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_27_WIDTH },
19590 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_CHECKER_TYPE,
19591 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_28_WIDTH },
19592 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_CHECKER_TYPE,
19593 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_29_WIDTH },
19594 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_CHECKER_TYPE,
19595 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_30_WIDTH },
19596 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_CHECKER_TYPE,
19597 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_31_WIDTH },
19598 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_CHECKER_TYPE,
19599 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_32_WIDTH },
19600 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_CHECKER_TYPE,
19601 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_33_WIDTH },
19602 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_CHECKER_TYPE,
19603 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_34_WIDTH },
19604 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_CHECKER_TYPE,
19605 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_35_WIDTH },
19606 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_CHECKER_TYPE,
19607 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_36_WIDTH },
19608 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_CHECKER_TYPE,
19609 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_37_WIDTH },
19610 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_CHECKER_TYPE,
19611 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_38_WIDTH },
19612 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_CHECKER_TYPE,
19613 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_39_WIDTH },
19614 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_CHECKER_TYPE,
19615 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_40_WIDTH },
19616 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_CHECKER_TYPE,
19617 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_41_WIDTH },
19618 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_CHECKER_TYPE,
19619 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_42_WIDTH },
19620 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_CHECKER_TYPE,
19621 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_43_WIDTH },
19622 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_CHECKER_TYPE,
19623 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_44_WIDTH },
19624 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_CHECKER_TYPE,
19625 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_45_WIDTH },
19626 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_CHECKER_TYPE,
19627 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_46_WIDTH },
19628 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_CHECKER_TYPE,
19629 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_47_WIDTH },
19630 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_CHECKER_TYPE,
19631 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_48_WIDTH },
19632 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_CHECKER_TYPE,
19633 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_49_WIDTH },
19634 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_CHECKER_TYPE,
19635 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_50_WIDTH },
19636 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_CHECKER_TYPE,
19637 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_51_WIDTH },
19638 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_CHECKER_TYPE,
19639 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_52_WIDTH },
19640 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_CHECKER_TYPE,
19641 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_53_WIDTH },
19642 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_CHECKER_TYPE,
19643 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_54_WIDTH },
19644 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_CHECKER_TYPE,
19645 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_55_WIDTH },
19646 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_CHECKER_TYPE,
19647 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_56_WIDTH },
19648 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_CHECKER_TYPE,
19649 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_57_WIDTH },
19650 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_CHECKER_TYPE,
19651 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_58_WIDTH },
19652 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_CHECKER_TYPE,
19653 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_59_WIDTH },
19654 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_CHECKER_TYPE,
19655 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_60_WIDTH },
19656 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_CHECKER_TYPE,
19657 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_61_WIDTH },
19658 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_CHECKER_TYPE,
19659 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_62_WIDTH },
19660 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_CHECKER_TYPE,
19661 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_63_WIDTH },
19662 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_CHECKER_TYPE,
19663 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_64_WIDTH },
19664 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_CHECKER_TYPE,
19665 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_65_WIDTH },
19666 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_CHECKER_TYPE,
19667 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_66_WIDTH },
19668 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_CHECKER_TYPE,
19669 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_67_WIDTH },
19670 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_CHECKER_TYPE,
19671 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_68_WIDTH },
19672 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_CHECKER_TYPE,
19673 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_69_WIDTH },
19674 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_CHECKER_TYPE,
19675 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_70_WIDTH },
19676 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_CHECKER_TYPE,
19677 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_71_WIDTH },
19678 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_CHECKER_TYPE,
19679 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_72_WIDTH },
19680 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_CHECKER_TYPE,
19681 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_73_WIDTH },
19682 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_CHECKER_TYPE,
19683 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_74_WIDTH },
19684 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_CHECKER_TYPE,
19685 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_75_WIDTH },
19686 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_CHECKER_TYPE,
19687 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_76_WIDTH },
19688 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_CHECKER_TYPE,
19689 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_77_WIDTH },
19690 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_CHECKER_TYPE,
19691 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_78_WIDTH },
19692 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_CHECKER_TYPE,
19693 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_79_WIDTH },
19694 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_CHECKER_TYPE,
19695 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_80_WIDTH },
19696 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_CHECKER_TYPE,
19697 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_81_WIDTH },
19698 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_CHECKER_TYPE,
19699 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_82_WIDTH },
19700 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_CHECKER_TYPE,
19701 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_83_WIDTH },
19702 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_CHECKER_TYPE,
19703 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_84_WIDTH },
19704 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_CHECKER_TYPE,
19705 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_85_WIDTH },
19706 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_CHECKER_TYPE,
19707 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_86_WIDTH },
19708 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_CHECKER_TYPE,
19709 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_87_WIDTH },
19710 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_CHECKER_TYPE,
19711 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_88_WIDTH },
19712 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_CHECKER_TYPE,
19713 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_89_WIDTH },
19714 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_CHECKER_TYPE,
19715 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_90_WIDTH },
19716 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_CHECKER_TYPE,
19717 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_91_WIDTH },
19718 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_CHECKER_TYPE,
19719 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_92_WIDTH },
19720 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_CHECKER_TYPE,
19721 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_93_WIDTH },
19722 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_CHECKER_TYPE,
19723 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_94_WIDTH },
19724 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_CHECKER_TYPE,
19725 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_95_WIDTH },
19726 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_CHECKER_TYPE,
19727 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_96_WIDTH },
19728 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_CHECKER_TYPE,
19729 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_97_WIDTH },
19730 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_CHECKER_TYPE,
19731 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_98_WIDTH },
19732 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_CHECKER_TYPE,
19733 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_99_WIDTH },
19734 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_CHECKER_TYPE,
19735 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_100_WIDTH },
19736 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_CHECKER_TYPE,
19737 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_101_WIDTH },
19738 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_CHECKER_TYPE,
19739 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_102_WIDTH },
19740 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_CHECKER_TYPE,
19741 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_103_WIDTH },
19742 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_CHECKER_TYPE,
19743 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_104_WIDTH },
19744 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_CHECKER_TYPE,
19745 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_105_WIDTH },
19746 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_CHECKER_TYPE,
19747 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_106_WIDTH },
19748 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_CHECKER_TYPE,
19749 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_107_WIDTH },
19750 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_CHECKER_TYPE,
19751 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_108_WIDTH },
19752 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_CHECKER_TYPE,
19753 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_109_WIDTH },
19754 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_CHECKER_TYPE,
19755 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_110_WIDTH },
19756 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_CHECKER_TYPE,
19757 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_111_WIDTH },
19758 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_CHECKER_TYPE,
19759 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_112_WIDTH },
19760 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_CHECKER_TYPE,
19761 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_113_WIDTH },
19762 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_CHECKER_TYPE,
19763 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_114_WIDTH },
19764 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_CHECKER_TYPE,
19765 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_115_WIDTH },
19766 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_CHECKER_TYPE,
19767 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_116_WIDTH },
19768 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_CHECKER_TYPE,
19769 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_117_WIDTH },
19770 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_CHECKER_TYPE,
19771 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_118_WIDTH },
19772 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_CHECKER_TYPE,
19773 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_119_WIDTH },
19774 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_CHECKER_TYPE,
19775 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_120_WIDTH },
19776 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_CHECKER_TYPE,
19777 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_121_WIDTH },
19778 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_CHECKER_TYPE,
19779 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_122_WIDTH },
19780 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_CHECKER_TYPE,
19781 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_123_WIDTH },
19782 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_CHECKER_TYPE,
19783 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_124_WIDTH },
19784 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_CHECKER_TYPE,
19785 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_125_WIDTH },
19786 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_CHECKER_TYPE,
19787 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_126_WIDTH },
19788 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_CHECKER_TYPE,
19789 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_127_WIDTH },
19790 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_CHECKER_TYPE,
19791 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_128_WIDTH },
19792 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_CHECKER_TYPE,
19793 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_129_WIDTH },
19794 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_CHECKER_TYPE,
19795 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_130_WIDTH },
19796 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_CHECKER_TYPE,
19797 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_GROUP_131_WIDTH },
19807 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
19808 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_0_WIDTH },
19809 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
19810 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_1_WIDTH },
19811 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
19812 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_2_WIDTH },
19813 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
19814 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_3_WIDTH },
19815 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
19816 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_4_WIDTH },
19817 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
19818 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_5_WIDTH },
19819 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
19820 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_6_WIDTH },
19821 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
19822 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_7_WIDTH },
19823 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
19824 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_8_WIDTH },
19825 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
19826 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_9_WIDTH },
19827 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
19828 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_10_WIDTH },
19829 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
19830 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_11_WIDTH },
19831 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
19832 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_12_WIDTH },
19833 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
19834 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_13_WIDTH },
19835 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
19836 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_14_WIDTH },
19837 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
19838 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_15_WIDTH },
19839 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
19840 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_16_WIDTH },
19841 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
19842 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_17_WIDTH },
19843 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
19844 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_18_WIDTH },
19845 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_CHECKER_TYPE,
19846 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_19_WIDTH },
19847 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_CHECKER_TYPE,
19848 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_20_WIDTH },
19849 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_CHECKER_TYPE,
19850 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_21_WIDTH },
19851 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_CHECKER_TYPE,
19852 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_22_WIDTH },
19853 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_CHECKER_TYPE,
19854 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_23_WIDTH },
19855 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_CHECKER_TYPE,
19856 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_24_WIDTH },
19857 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_CHECKER_TYPE,
19858 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_25_WIDTH },
19859 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_CHECKER_TYPE,
19860 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_26_WIDTH },
19861 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_CHECKER_TYPE,
19862 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_27_WIDTH },
19863 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_CHECKER_TYPE,
19864 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_28_WIDTH },
19865 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_CHECKER_TYPE,
19866 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_29_WIDTH },
19867 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_CHECKER_TYPE,
19868 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_GROUP_30_WIDTH },
19878 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
19879 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
19880 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
19881 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
19891 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
19892 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
19893 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
19894 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
19904 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
19905 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
19906 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
19907 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
19908 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
19909 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
19910 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
19911 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
19912 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
19913 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
19914 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
19915 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
19916 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
19917 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
19918 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
19919 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
19920 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
19921 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
19922 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
19923 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
19924 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
19925 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
19926 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
19927 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
19928 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
19929 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
19930 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
19931 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
19932 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
19933 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
19934 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
19935 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
19936 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
19937 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
19938 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
19939 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
19940 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
19941 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
19942 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
19943 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
19944 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
19945 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
19946 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
19947 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
19948 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
19949 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
19950 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
19951 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
19952 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
19953 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
19954 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
19955 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
19956 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
19957 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
19958 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
19959 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
19960 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
19961 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
19962 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
19963 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
19964 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
19965 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
19966 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
19967 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
19968 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
19969 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
19970 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
19971 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
19972 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
19973 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
19974 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
19975 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
19976 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
19977 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
19978 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
19979 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
19980 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
19981 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
19982 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
19983 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
19984 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
19985 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
19986 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
19987 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
19988 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_CHECKER_TYPE,
19989 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_42_WIDTH },
19990 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_CHECKER_TYPE,
19991 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_43_WIDTH },
19992 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_CHECKER_TYPE,
19993 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_44_WIDTH },
19994 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_CHECKER_TYPE,
19995 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_45_WIDTH },
19996 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_CHECKER_TYPE,
19997 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_46_WIDTH },
19998 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_CHECKER_TYPE,
19999 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_47_WIDTH },
20000 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_CHECKER_TYPE,
20001 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_48_WIDTH },
20002 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_CHECKER_TYPE,
20003 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_49_WIDTH },
20004 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_CHECKER_TYPE,
20005 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_50_WIDTH },
20006 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_CHECKER_TYPE,
20007 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_51_WIDTH },
20008 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_CHECKER_TYPE,
20009 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_52_WIDTH },
20010 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_CHECKER_TYPE,
20011 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_53_WIDTH },
20012 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_CHECKER_TYPE,
20013 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_54_WIDTH },
20014 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_CHECKER_TYPE,
20015 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_55_WIDTH },
20016 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_CHECKER_TYPE,
20017 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_56_WIDTH },
20018 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_CHECKER_TYPE,
20019 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_57_WIDTH },
20020 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_CHECKER_TYPE,
20021 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_58_WIDTH },
20022 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_CHECKER_TYPE,
20023 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_59_WIDTH },
20024 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_CHECKER_TYPE,
20025 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_60_WIDTH },
20026 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_CHECKER_TYPE,
20027 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_61_WIDTH },
20028 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_CHECKER_TYPE,
20029 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_62_WIDTH },
20030 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_CHECKER_TYPE,
20031 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_63_WIDTH },
20032 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_CHECKER_TYPE,
20033 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_64_WIDTH },
20034 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_CHECKER_TYPE,
20035 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_65_WIDTH },
20036 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_CHECKER_TYPE,
20037 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_66_WIDTH },
20038 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_CHECKER_TYPE,
20039 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_67_WIDTH },
20040 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_CHECKER_TYPE,
20041 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_68_WIDTH },
20042 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_CHECKER_TYPE,
20043 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_69_WIDTH },
20044 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_CHECKER_TYPE,
20045 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_70_WIDTH },
20046 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_CHECKER_TYPE,
20047 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_71_WIDTH },
20048 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_CHECKER_TYPE,
20049 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_72_WIDTH },
20050 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_CHECKER_TYPE,
20051 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_73_WIDTH },
20052 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_CHECKER_TYPE,
20053 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_74_WIDTH },
20054 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_CHECKER_TYPE,
20055 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_75_WIDTH },
20056 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_CHECKER_TYPE,
20057 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_76_WIDTH },
20058 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_CHECKER_TYPE,
20059 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_77_WIDTH },
20060 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_CHECKER_TYPE,
20061 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_78_WIDTH },
20062 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_CHECKER_TYPE,
20063 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_79_WIDTH },
20064 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_CHECKER_TYPE,
20065 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_80_WIDTH },
20066 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_CHECKER_TYPE,
20067 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_81_WIDTH },
20068 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_CHECKER_TYPE,
20069 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_82_WIDTH },
20070 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_CHECKER_TYPE,
20071 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_83_WIDTH },
20072 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_CHECKER_TYPE,
20073 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_84_WIDTH },
20074 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_CHECKER_TYPE,
20075 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_85_WIDTH },
20076 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_CHECKER_TYPE,
20077 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_86_WIDTH },
20078 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_CHECKER_TYPE,
20079 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_87_WIDTH },
20080 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_CHECKER_TYPE,
20081 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_88_WIDTH },
20082 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_CHECKER_TYPE,
20083 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_89_WIDTH },
20084 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_CHECKER_TYPE,
20085 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_90_WIDTH },
20086 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_CHECKER_TYPE,
20087 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_91_WIDTH },
20088 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_CHECKER_TYPE,
20089 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_92_WIDTH },
20090 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_CHECKER_TYPE,
20091 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_93_WIDTH },
20092 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_CHECKER_TYPE,
20093 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_94_WIDTH },
20094 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_CHECKER_TYPE,
20095 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_95_WIDTH },
20096 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_CHECKER_TYPE,
20097 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_96_WIDTH },
20098 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_CHECKER_TYPE,
20099 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_97_WIDTH },
20100 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_CHECKER_TYPE,
20101 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_98_WIDTH },
20102 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_CHECKER_TYPE,
20103 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_99_WIDTH },
20104 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_CHECKER_TYPE,
20105 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_100_WIDTH },
20106 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_CHECKER_TYPE,
20107 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_101_WIDTH },
20108 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_CHECKER_TYPE,
20109 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_102_WIDTH },
20110 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_CHECKER_TYPE,
20111 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_103_WIDTH },
20112 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_CHECKER_TYPE,
20113 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_104_WIDTH },
20114 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_CHECKER_TYPE,
20115 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_105_WIDTH },
20116 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_CHECKER_TYPE,
20117 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_106_WIDTH },
20118 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_CHECKER_TYPE,
20119 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_107_WIDTH },
20120 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_CHECKER_TYPE,
20121 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_108_WIDTH },
20122 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_CHECKER_TYPE,
20123 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_109_WIDTH },
20124 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_CHECKER_TYPE,
20125 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_110_WIDTH },
20126 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_CHECKER_TYPE,
20127 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_111_WIDTH },
20128 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_CHECKER_TYPE,
20129 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_112_WIDTH },
20130 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_CHECKER_TYPE,
20131 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_113_WIDTH },
20132 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_CHECKER_TYPE,
20133 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_114_WIDTH },
20134 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_CHECKER_TYPE,
20135 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_115_WIDTH },
20136 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_CHECKER_TYPE,
20137 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_116_WIDTH },
20138 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_CHECKER_TYPE,
20139 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_117_WIDTH },
20140 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_CHECKER_TYPE,
20141 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_118_WIDTH },
20142 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_CHECKER_TYPE,
20143 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_119_WIDTH },
20144 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_CHECKER_TYPE,
20145 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_120_WIDTH },
20146 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_CHECKER_TYPE,
20147 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_121_WIDTH },
20148 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_CHECKER_TYPE,
20149 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_122_WIDTH },
20150 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_CHECKER_TYPE,
20151 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_123_WIDTH },
20152 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_CHECKER_TYPE,
20153 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_124_WIDTH },
20154 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_CHECKER_TYPE,
20155 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_125_WIDTH },
20156 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_CHECKER_TYPE,
20157 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_126_WIDTH },
20158 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_CHECKER_TYPE,
20159 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_127_WIDTH },
20160 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_CHECKER_TYPE,
20161 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_128_WIDTH },
20162 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_CHECKER_TYPE,
20163 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_129_WIDTH },
20164 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_CHECKER_TYPE,
20165 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_130_WIDTH },
20166 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_CHECKER_TYPE,
20167 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_131_WIDTH },
20168 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_CHECKER_TYPE,
20169 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_132_WIDTH },
20170 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_133_CHECKER_TYPE,
20171 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_133_WIDTH },
20172 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_134_CHECKER_TYPE,
20173 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_134_WIDTH },
20174 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_135_CHECKER_TYPE,
20175 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_135_WIDTH },
20176 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_136_CHECKER_TYPE,
20177 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_136_WIDTH },
20178 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_137_CHECKER_TYPE,
20179 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_137_WIDTH },
20180 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_138_CHECKER_TYPE,
20181 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_138_WIDTH },
20182 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_139_CHECKER_TYPE,
20183 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_139_WIDTH },
20184 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_140_CHECKER_TYPE,
20185 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_140_WIDTH },
20186 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_141_CHECKER_TYPE,
20187 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_141_WIDTH },
20188 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_142_CHECKER_TYPE,
20189 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_142_WIDTH },
20190 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_143_CHECKER_TYPE,
20191 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_143_WIDTH },
20192 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_144_CHECKER_TYPE,
20193 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_144_WIDTH },
20194 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_145_CHECKER_TYPE,
20195 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_145_WIDTH },
20196 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_146_CHECKER_TYPE,
20197 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_146_WIDTH },
20198 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_147_CHECKER_TYPE,
20199 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_147_WIDTH },
20200 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_148_CHECKER_TYPE,
20201 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_148_WIDTH },
20202 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_149_CHECKER_TYPE,
20203 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_149_WIDTH },
20204 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_150_CHECKER_TYPE,
20205 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_150_WIDTH },
20206 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_151_CHECKER_TYPE,
20207 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_151_WIDTH },
20208 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_152_CHECKER_TYPE,
20209 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_152_WIDTH },
20210 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_153_CHECKER_TYPE,
20211 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_153_WIDTH },
20212 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_154_CHECKER_TYPE,
20213 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_154_WIDTH },
20214 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_155_CHECKER_TYPE,
20215 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_155_WIDTH },
20216 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_156_CHECKER_TYPE,
20217 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_156_WIDTH },
20218 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_157_CHECKER_TYPE,
20219 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_157_WIDTH },
20220 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_158_CHECKER_TYPE,
20221 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_158_WIDTH },
20222 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_159_CHECKER_TYPE,
20223 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_159_WIDTH },
20224 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_160_CHECKER_TYPE,
20225 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_160_WIDTH },
20226 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_161_CHECKER_TYPE,
20227 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_161_WIDTH },
20228 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_162_CHECKER_TYPE,
20229 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_162_WIDTH },
20230 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_163_CHECKER_TYPE,
20231 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_163_WIDTH },
20232 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_164_CHECKER_TYPE,
20233 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_164_WIDTH },
20234 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_165_CHECKER_TYPE,
20235 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_165_WIDTH },
20236 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_166_CHECKER_TYPE,
20237 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_166_WIDTH },
20238 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_167_CHECKER_TYPE,
20239 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_167_WIDTH },
20240 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_168_CHECKER_TYPE,
20241 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_GROUP_168_WIDTH },
20251 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20252 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20253 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20254 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20255 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20256 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20257 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20258 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20259 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20260 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20270 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_CHECKER_TYPE,
20271 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_0_WIDTH },
20272 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_CHECKER_TYPE,
20273 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_1_WIDTH },
20274 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_CHECKER_TYPE,
20275 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_2_WIDTH },
20276 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_CHECKER_TYPE,
20277 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_3_WIDTH },
20278 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_CHECKER_TYPE,
20279 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_4_WIDTH },
20280 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_CHECKER_TYPE,
20281 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_5_WIDTH },
20282 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_CHECKER_TYPE,
20283 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_6_WIDTH },
20284 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_CHECKER_TYPE,
20285 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_7_WIDTH },
20286 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_CHECKER_TYPE,
20287 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_8_WIDTH },
20288 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_CHECKER_TYPE,
20289 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_9_WIDTH },
20290 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_CHECKER_TYPE,
20291 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_10_WIDTH },
20292 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_CHECKER_TYPE,
20293 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_11_WIDTH },
20294 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_CHECKER_TYPE,
20295 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_12_WIDTH },
20296 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_CHECKER_TYPE,
20297 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_13_WIDTH },
20298 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_CHECKER_TYPE,
20299 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_14_WIDTH },
20300 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_CHECKER_TYPE,
20301 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_15_WIDTH },
20302 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_CHECKER_TYPE,
20303 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_16_WIDTH },
20304 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_CHECKER_TYPE,
20305 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_17_WIDTH },
20306 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_CHECKER_TYPE,
20307 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_GROUP_18_WIDTH },
20317 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_CHECKER_TYPE,
20318 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_0_WIDTH },
20319 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_CHECKER_TYPE,
20320 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_1_WIDTH },
20321 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_CHECKER_TYPE,
20322 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_2_WIDTH },
20323 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_CHECKER_TYPE,
20324 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_3_WIDTH },
20325 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_CHECKER_TYPE,
20326 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_4_WIDTH },
20327 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_CHECKER_TYPE,
20328 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_5_WIDTH },
20329 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_CHECKER_TYPE,
20330 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_6_WIDTH },
20331 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_CHECKER_TYPE,
20332 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_7_WIDTH },
20333 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_CHECKER_TYPE,
20334 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_8_WIDTH },
20335 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_CHECKER_TYPE,
20336 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_9_WIDTH },
20337 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_CHECKER_TYPE,
20338 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_10_WIDTH },
20339 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_CHECKER_TYPE,
20340 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_11_WIDTH },
20341 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_CHECKER_TYPE,
20342 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_12_WIDTH },
20343 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_CHECKER_TYPE,
20344 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_13_WIDTH },
20345 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_CHECKER_TYPE,
20346 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_14_WIDTH },
20347 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_CHECKER_TYPE,
20348 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_15_WIDTH },
20349 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_CHECKER_TYPE,
20350 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_16_WIDTH },
20351 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_CHECKER_TYPE,
20352 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_17_WIDTH },
20353 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_CHECKER_TYPE,
20354 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_18_WIDTH },
20355 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_CHECKER_TYPE,
20356 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_19_WIDTH },
20357 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_CHECKER_TYPE,
20358 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_20_WIDTH },
20359 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_CHECKER_TYPE,
20360 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_21_WIDTH },
20361 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_CHECKER_TYPE,
20362 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_22_WIDTH },
20363 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_CHECKER_TYPE,
20364 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_23_WIDTH },
20365 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_CHECKER_TYPE,
20366 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_24_WIDTH },
20367 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_CHECKER_TYPE,
20368 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_25_WIDTH },
20369 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_CHECKER_TYPE,
20370 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_26_WIDTH },
20371 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_CHECKER_TYPE,
20372 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_27_WIDTH },
20373 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_CHECKER_TYPE,
20374 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_28_WIDTH },
20375 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_CHECKER_TYPE,
20376 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_29_WIDTH },
20377 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_CHECKER_TYPE,
20378 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_30_WIDTH },
20379 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_CHECKER_TYPE,
20380 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_31_WIDTH },
20381 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_CHECKER_TYPE,
20382 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_32_WIDTH },
20383 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_CHECKER_TYPE,
20384 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_33_WIDTH },
20385 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_CHECKER_TYPE,
20386 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_34_WIDTH },
20387 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_CHECKER_TYPE,
20388 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_35_WIDTH },
20389 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_CHECKER_TYPE,
20390 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_36_WIDTH },
20391 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_CHECKER_TYPE,
20392 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_37_WIDTH },
20393 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_CHECKER_TYPE,
20394 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_38_WIDTH },
20395 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_CHECKER_TYPE,
20396 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_39_WIDTH },
20397 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_CHECKER_TYPE,
20398 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_40_WIDTH },
20399 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_CHECKER_TYPE,
20400 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_GROUP_41_WIDTH },
20410 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
20411 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
20412 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
20413 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
20414 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
20415 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
20416 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
20417 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
20418 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
20419 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
20420 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
20421 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
20422 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
20423 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
20424 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
20425 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
20426 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
20427 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
20428 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
20429 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
20430 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
20431 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
20432 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
20433 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
20434 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
20435 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
20436 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
20437 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
20438 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
20439 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
20440 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
20441 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
20442 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
20443 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
20444 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
20445 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
20446 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
20447 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
20448 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
20449 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
20450 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
20451 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
20452 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
20453 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
20454 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
20455 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
20456 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
20457 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
20458 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
20459 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
20460 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
20461 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
20462 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
20463 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
20464 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
20465 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
20466 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
20467 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
20468 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
20469 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
20470 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
20471 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
20472 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
20473 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
20474 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
20475 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
20476 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
20477 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
20478 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
20479 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
20480 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
20481 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
20482 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
20483 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
20484 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
20485 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
20486 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
20487 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
20488 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
20489 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
20490 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
20491 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
20492 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
20493 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
20494 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
20495 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
20496 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
20497 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
20498 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
20499 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
20500 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
20501 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
20502 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
20503 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
20504 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
20505 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
20506 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
20507 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
20508 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
20509 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
20510 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
20511 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
20512 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
20513 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
20514 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
20515 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
20516 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
20517 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
20518 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
20519 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
20520 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
20521 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
20522 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
20523 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
20524 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
20525 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
20526 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
20527 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
20528 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
20529 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
20530 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_CHECKER_TYPE,
20531 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_60_WIDTH },
20532 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_CHECKER_TYPE,
20533 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_61_WIDTH },
20534 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_CHECKER_TYPE,
20535 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_62_WIDTH },
20536 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_CHECKER_TYPE,
20537 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_63_WIDTH },
20538 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_CHECKER_TYPE,
20539 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_64_WIDTH },
20540 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_CHECKER_TYPE,
20541 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_65_WIDTH },
20542 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_CHECKER_TYPE,
20543 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_66_WIDTH },
20544 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_CHECKER_TYPE,
20545 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_67_WIDTH },
20546 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_CHECKER_TYPE,
20547 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_68_WIDTH },
20548 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_CHECKER_TYPE,
20549 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_69_WIDTH },
20550 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_CHECKER_TYPE,
20551 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_70_WIDTH },
20552 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_CHECKER_TYPE,
20553 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_71_WIDTH },
20554 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_CHECKER_TYPE,
20555 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_72_WIDTH },
20556 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_CHECKER_TYPE,
20557 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_73_WIDTH },
20558 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_CHECKER_TYPE,
20559 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_74_WIDTH },
20560 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_CHECKER_TYPE,
20561 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_75_WIDTH },
20562 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_CHECKER_TYPE,
20563 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_76_WIDTH },
20564 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_CHECKER_TYPE,
20565 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_77_WIDTH },
20566 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_CHECKER_TYPE,
20567 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_78_WIDTH },
20568 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_CHECKER_TYPE,
20569 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_79_WIDTH },
20570 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_CHECKER_TYPE,
20571 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_80_WIDTH },
20572 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_CHECKER_TYPE,
20573 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_81_WIDTH },
20574 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_CHECKER_TYPE,
20575 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_82_WIDTH },
20576 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_CHECKER_TYPE,
20577 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_83_WIDTH },
20578 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_CHECKER_TYPE,
20579 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_84_WIDTH },
20580 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_CHECKER_TYPE,
20581 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_85_WIDTH },
20582 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_CHECKER_TYPE,
20583 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_86_WIDTH },
20584 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_CHECKER_TYPE,
20585 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_87_WIDTH },
20586 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_CHECKER_TYPE,
20587 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_88_WIDTH },
20588 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_CHECKER_TYPE,
20589 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_89_WIDTH },
20590 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_CHECKER_TYPE,
20591 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_90_WIDTH },
20592 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_CHECKER_TYPE,
20593 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_91_WIDTH },
20594 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_CHECKER_TYPE,
20595 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_92_WIDTH },
20596 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_CHECKER_TYPE,
20597 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_93_WIDTH },
20598 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_CHECKER_TYPE,
20599 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_94_WIDTH },
20600 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_CHECKER_TYPE,
20601 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_95_WIDTH },
20602 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_CHECKER_TYPE,
20603 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_96_WIDTH },
20604 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_CHECKER_TYPE,
20605 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_97_WIDTH },
20606 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_CHECKER_TYPE,
20607 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_98_WIDTH },
20608 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_CHECKER_TYPE,
20609 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_99_WIDTH },
20610 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_CHECKER_TYPE,
20611 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_100_WIDTH },
20612 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_CHECKER_TYPE,
20613 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_101_WIDTH },
20614 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_CHECKER_TYPE,
20615 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_102_WIDTH },
20616 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_CHECKER_TYPE,
20617 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_103_WIDTH },
20618 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_CHECKER_TYPE,
20619 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_104_WIDTH },
20620 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_CHECKER_TYPE,
20621 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_105_WIDTH },
20622 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_CHECKER_TYPE,
20623 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_106_WIDTH },
20624 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_CHECKER_TYPE,
20625 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_107_WIDTH },
20626 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_CHECKER_TYPE,
20627 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_108_WIDTH },
20628 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_CHECKER_TYPE,
20629 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_109_WIDTH },
20630 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_CHECKER_TYPE,
20631 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_110_WIDTH },
20632 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_CHECKER_TYPE,
20633 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_111_WIDTH },
20634 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_CHECKER_TYPE,
20635 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_112_WIDTH },
20636 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_CHECKER_TYPE,
20637 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_113_WIDTH },
20638 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_CHECKER_TYPE,
20639 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_114_WIDTH },
20640 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_CHECKER_TYPE,
20641 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_115_WIDTH },
20642 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_CHECKER_TYPE,
20643 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_116_WIDTH },
20644 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_CHECKER_TYPE,
20645 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_117_WIDTH },
20646 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_CHECKER_TYPE,
20647 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_118_WIDTH },
20648 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_CHECKER_TYPE,
20649 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_119_WIDTH },
20650 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_CHECKER_TYPE,
20651 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_120_WIDTH },
20652 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_CHECKER_TYPE,
20653 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_121_WIDTH },
20654 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_CHECKER_TYPE,
20655 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_122_WIDTH },
20656 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_CHECKER_TYPE,
20657 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_123_WIDTH },
20658 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_CHECKER_TYPE,
20659 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_124_WIDTH },
20660 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_CHECKER_TYPE,
20661 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_125_WIDTH },
20662 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_CHECKER_TYPE,
20663 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_126_WIDTH },
20664 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_CHECKER_TYPE,
20665 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_127_WIDTH },
20666 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_CHECKER_TYPE,
20667 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_128_WIDTH },
20668 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_CHECKER_TYPE,
20669 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_129_WIDTH },
20670 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_CHECKER_TYPE,
20671 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_130_WIDTH },
20672 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_CHECKER_TYPE,
20673 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_131_WIDTH },
20674 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_CHECKER_TYPE,
20675 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_132_WIDTH },
20676 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_CHECKER_TYPE,
20677 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_133_WIDTH },
20678 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_CHECKER_TYPE,
20679 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_134_WIDTH },
20680 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_135_CHECKER_TYPE,
20681 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_135_WIDTH },
20682 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_136_CHECKER_TYPE,
20683 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_136_WIDTH },
20684 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_137_CHECKER_TYPE,
20685 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_137_WIDTH },
20686 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_138_CHECKER_TYPE,
20687 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_138_WIDTH },
20688 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_139_CHECKER_TYPE,
20689 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_139_WIDTH },
20690 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_140_CHECKER_TYPE,
20691 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_140_WIDTH },
20692 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_141_CHECKER_TYPE,
20693 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_141_WIDTH },
20694 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_142_CHECKER_TYPE,
20695 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_142_WIDTH },
20696 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_143_CHECKER_TYPE,
20697 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_143_WIDTH },
20698 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_144_CHECKER_TYPE,
20699 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_144_WIDTH },
20700 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_145_CHECKER_TYPE,
20701 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_145_WIDTH },
20702 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_146_CHECKER_TYPE,
20703 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_146_WIDTH },
20704 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_147_CHECKER_TYPE,
20705 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_147_WIDTH },
20706 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_148_CHECKER_TYPE,
20707 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_148_WIDTH },
20708 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_149_CHECKER_TYPE,
20709 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_149_WIDTH },
20710 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_150_CHECKER_TYPE,
20711 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_150_WIDTH },
20712 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_151_CHECKER_TYPE,
20713 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_151_WIDTH },
20714 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_152_CHECKER_TYPE,
20715 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_152_WIDTH },
20716 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_153_CHECKER_TYPE,
20717 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_153_WIDTH },
20718 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_154_CHECKER_TYPE,
20719 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_154_WIDTH },
20720 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_155_CHECKER_TYPE,
20721 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_155_WIDTH },
20722 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_156_CHECKER_TYPE,
20723 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_156_WIDTH },
20724 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_157_CHECKER_TYPE,
20725 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_157_WIDTH },
20726 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_158_CHECKER_TYPE,
20727 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_GROUP_158_WIDTH },
20737 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
20738 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
20739 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
20740 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
20741 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
20742 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
20743 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
20744 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
20745 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
20746 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
20747 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
20748 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
20757 { SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_ID, 0u,
20758 SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_SIZE, 4u,
20759 SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_ROW_WIDTH, ((bool)
false) },
20769 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_CHECKER_TYPE,
20770 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_0_WIDTH },
20771 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_CHECKER_TYPE,
20772 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_1_WIDTH },
20773 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_CHECKER_TYPE,
20774 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_2_WIDTH },
20775 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_CHECKER_TYPE,
20776 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_3_WIDTH },
20777 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_CHECKER_TYPE,
20778 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_4_WIDTH },
20779 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_CHECKER_TYPE,
20780 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_5_WIDTH },
20781 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_CHECKER_TYPE,
20782 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_6_WIDTH },
20783 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_CHECKER_TYPE,
20784 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_7_WIDTH },
20785 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_CHECKER_TYPE,
20786 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_8_WIDTH },
20787 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_CHECKER_TYPE,
20788 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_9_WIDTH },
20789 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_CHECKER_TYPE,
20790 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_10_WIDTH },
20791 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_CHECKER_TYPE,
20792 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_11_WIDTH },
20793 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_CHECKER_TYPE,
20794 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_12_WIDTH },
20795 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_CHECKER_TYPE,
20796 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_13_WIDTH },
20797 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_CHECKER_TYPE,
20798 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_14_WIDTH },
20799 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_CHECKER_TYPE,
20800 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_15_WIDTH },
20801 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_CHECKER_TYPE,
20802 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_GROUP_16_WIDTH },
20812 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
20813 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
20814 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
20815 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
20825 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
20826 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
20827 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
20828 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
20838 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_0_CHECKER_TYPE,
20839 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_0_WIDTH },
20840 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_1_CHECKER_TYPE,
20841 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_GROUP_1_WIDTH },
20851 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_0_CHECKER_TYPE,
20852 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_0_WIDTH },
20853 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_1_CHECKER_TYPE,
20854 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_1_WIDTH },
20855 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_2_CHECKER_TYPE,
20856 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_2_WIDTH },
20857 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_3_CHECKER_TYPE,
20858 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_3_WIDTH },
20859 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_4_CHECKER_TYPE,
20860 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_4_WIDTH },
20861 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_5_CHECKER_TYPE,
20862 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_5_WIDTH },
20863 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_6_CHECKER_TYPE,
20864 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_6_WIDTH },
20865 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_7_CHECKER_TYPE,
20866 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_7_WIDTH },
20867 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_8_CHECKER_TYPE,
20868 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_8_WIDTH },
20869 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_9_CHECKER_TYPE,
20870 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_9_WIDTH },
20871 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_10_CHECKER_TYPE,
20872 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_10_WIDTH },
20873 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_11_CHECKER_TYPE,
20874 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_11_WIDTH },
20875 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_12_CHECKER_TYPE,
20876 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_12_WIDTH },
20877 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_13_CHECKER_TYPE,
20878 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_13_WIDTH },
20879 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_14_CHECKER_TYPE,
20880 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_14_WIDTH },
20881 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_15_CHECKER_TYPE,
20882 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_15_WIDTH },
20883 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_16_CHECKER_TYPE,
20884 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_16_WIDTH },
20885 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_17_CHECKER_TYPE,
20886 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_17_WIDTH },
20887 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_18_CHECKER_TYPE,
20888 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_18_WIDTH },
20889 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_19_CHECKER_TYPE,
20890 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_19_WIDTH },
20891 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_20_CHECKER_TYPE,
20892 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_20_WIDTH },
20893 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_21_CHECKER_TYPE,
20894 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_21_WIDTH },
20895 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_22_CHECKER_TYPE,
20896 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_22_WIDTH },
20897 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_23_CHECKER_TYPE,
20898 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_23_WIDTH },
20899 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_24_CHECKER_TYPE,
20900 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_24_WIDTH },
20901 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_25_CHECKER_TYPE,
20902 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_25_WIDTH },
20903 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_26_CHECKER_TYPE,
20904 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_26_WIDTH },
20905 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_27_CHECKER_TYPE,
20906 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_27_WIDTH },
20907 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_28_CHECKER_TYPE,
20908 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_28_WIDTH },
20909 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_29_CHECKER_TYPE,
20910 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_29_WIDTH },
20911 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_30_CHECKER_TYPE,
20912 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_30_WIDTH },
20913 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_31_CHECKER_TYPE,
20914 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_31_WIDTH },
20915 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_32_CHECKER_TYPE,
20916 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_32_WIDTH },
20917 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_33_CHECKER_TYPE,
20918 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_33_WIDTH },
20919 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_34_CHECKER_TYPE,
20920 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_34_WIDTH },
20921 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_35_CHECKER_TYPE,
20922 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_35_WIDTH },
20923 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_36_CHECKER_TYPE,
20924 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_36_WIDTH },
20925 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_37_CHECKER_TYPE,
20926 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_37_WIDTH },
20927 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_38_CHECKER_TYPE,
20928 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_38_WIDTH },
20929 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_39_CHECKER_TYPE,
20930 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_39_WIDTH },
20931 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_40_CHECKER_TYPE,
20932 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_40_WIDTH },
20933 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_41_CHECKER_TYPE,
20934 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_41_WIDTH },
20935 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_42_CHECKER_TYPE,
20936 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_42_WIDTH },
20937 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_43_CHECKER_TYPE,
20938 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_43_WIDTH },
20939 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_44_CHECKER_TYPE,
20940 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_44_WIDTH },
20941 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_45_CHECKER_TYPE,
20942 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_45_WIDTH },
20943 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_46_CHECKER_TYPE,
20944 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_46_WIDTH },
20945 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_47_CHECKER_TYPE,
20946 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_47_WIDTH },
20947 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_48_CHECKER_TYPE,
20948 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_48_WIDTH },
20949 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_49_CHECKER_TYPE,
20950 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_49_WIDTH },
20951 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_50_CHECKER_TYPE,
20952 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_50_WIDTH },
20953 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_51_CHECKER_TYPE,
20954 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_51_WIDTH },
20955 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_52_CHECKER_TYPE,
20956 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_52_WIDTH },
20957 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_53_CHECKER_TYPE,
20958 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_53_WIDTH },
20959 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_54_CHECKER_TYPE,
20960 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_54_WIDTH },
20961 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_55_CHECKER_TYPE,
20962 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_55_WIDTH },
20963 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_56_CHECKER_TYPE,
20964 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_56_WIDTH },
20965 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_57_CHECKER_TYPE,
20966 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_57_WIDTH },
20967 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_58_CHECKER_TYPE,
20968 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_58_WIDTH },
20969 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_59_CHECKER_TYPE,
20970 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_59_WIDTH },
20971 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_60_CHECKER_TYPE,
20972 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_60_WIDTH },
20973 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_61_CHECKER_TYPE,
20974 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_61_WIDTH },
20975 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_62_CHECKER_TYPE,
20976 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_62_WIDTH },
20977 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_63_CHECKER_TYPE,
20978 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_63_WIDTH },
20979 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_64_CHECKER_TYPE,
20980 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_64_WIDTH },
20981 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_65_CHECKER_TYPE,
20982 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_65_WIDTH },
20983 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_66_CHECKER_TYPE,
20984 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_66_WIDTH },
20985 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_67_CHECKER_TYPE,
20986 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_67_WIDTH },
20987 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_68_CHECKER_TYPE,
20988 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_68_WIDTH },
20989 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_69_CHECKER_TYPE,
20990 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_69_WIDTH },
20991 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_70_CHECKER_TYPE,
20992 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_70_WIDTH },
20993 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_71_CHECKER_TYPE,
20994 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_71_WIDTH },
20995 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_72_CHECKER_TYPE,
20996 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_72_WIDTH },
20997 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_73_CHECKER_TYPE,
20998 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_73_WIDTH },
20999 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_74_CHECKER_TYPE,
21000 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_74_WIDTH },
21001 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_75_CHECKER_TYPE,
21002 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_75_WIDTH },
21003 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_76_CHECKER_TYPE,
21004 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_76_WIDTH },
21005 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_77_CHECKER_TYPE,
21006 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_77_WIDTH },
21007 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_78_CHECKER_TYPE,
21008 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_78_WIDTH },
21009 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_79_CHECKER_TYPE,
21010 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_79_WIDTH },
21011 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_80_CHECKER_TYPE,
21012 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_80_WIDTH },
21013 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_81_CHECKER_TYPE,
21014 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_81_WIDTH },
21015 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_82_CHECKER_TYPE,
21016 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_82_WIDTH },
21017 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_83_CHECKER_TYPE,
21018 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_83_WIDTH },
21019 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_84_CHECKER_TYPE,
21020 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_84_WIDTH },
21021 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_85_CHECKER_TYPE,
21022 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_85_WIDTH },
21023 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_86_CHECKER_TYPE,
21024 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_86_WIDTH },
21025 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_87_CHECKER_TYPE,
21026 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_87_WIDTH },
21027 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_88_CHECKER_TYPE,
21028 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_88_WIDTH },
21029 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_89_CHECKER_TYPE,
21030 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_89_WIDTH },
21031 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_90_CHECKER_TYPE,
21032 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_90_WIDTH },
21033 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_91_CHECKER_TYPE,
21034 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_91_WIDTH },
21035 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_92_CHECKER_TYPE,
21036 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_92_WIDTH },
21037 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_93_CHECKER_TYPE,
21038 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_93_WIDTH },
21039 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_94_CHECKER_TYPE,
21040 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_94_WIDTH },
21041 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_95_CHECKER_TYPE,
21042 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_95_WIDTH },
21043 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_96_CHECKER_TYPE,
21044 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_96_WIDTH },
21045 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_97_CHECKER_TYPE,
21046 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_97_WIDTH },
21047 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_98_CHECKER_TYPE,
21048 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_98_WIDTH },
21049 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_99_CHECKER_TYPE,
21050 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_99_WIDTH },
21051 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_100_CHECKER_TYPE,
21052 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_100_WIDTH },
21053 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_101_CHECKER_TYPE,
21054 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_101_WIDTH },
21055 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_102_CHECKER_TYPE,
21056 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_102_WIDTH },
21057 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_103_CHECKER_TYPE,
21058 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_103_WIDTH },
21059 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_104_CHECKER_TYPE,
21060 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_104_WIDTH },
21061 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_105_CHECKER_TYPE,
21062 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_105_WIDTH },
21063 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_106_CHECKER_TYPE,
21064 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_106_WIDTH },
21065 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_107_CHECKER_TYPE,
21066 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_107_WIDTH },
21067 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_108_CHECKER_TYPE,
21068 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_108_WIDTH },
21069 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_109_CHECKER_TYPE,
21070 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_109_WIDTH },
21071 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_110_CHECKER_TYPE,
21072 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_GROUP_110_WIDTH },
21082 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
21083 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
21084 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
21085 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
21086 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
21087 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
21088 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
21089 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
21090 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
21091 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
21092 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
21093 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
21094 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
21095 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
21096 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
21097 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
21098 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
21099 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
21100 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
21101 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
21102 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
21103 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
21104 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
21105 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
21106 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
21107 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
21108 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
21109 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
21110 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
21111 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
21112 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
21113 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
21114 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
21115 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
21116 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
21117 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
21118 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
21119 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
21120 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
21121 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
21122 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
21123 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
21124 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
21125 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
21126 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
21127 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
21128 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
21129 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
21130 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
21131 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
21132 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
21133 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
21134 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
21135 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
21136 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
21137 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
21138 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
21139 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
21140 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
21141 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
21142 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
21143 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
21144 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
21145 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
21146 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
21147 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
21157 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_CHECKER_TYPE,
21158 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_0_WIDTH },
21159 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_CHECKER_TYPE,
21160 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_1_WIDTH },
21161 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_CHECKER_TYPE,
21162 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_2_WIDTH },
21163 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_CHECKER_TYPE,
21164 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_3_WIDTH },
21165 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_CHECKER_TYPE,
21166 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_4_WIDTH },
21167 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_CHECKER_TYPE,
21168 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_5_WIDTH },
21169 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_CHECKER_TYPE,
21170 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_6_WIDTH },
21171 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_CHECKER_TYPE,
21172 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_7_WIDTH },
21173 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_CHECKER_TYPE,
21174 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_8_WIDTH },
21175 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_CHECKER_TYPE,
21176 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_9_WIDTH },
21177 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_CHECKER_TYPE,
21178 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_10_WIDTH },
21179 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_CHECKER_TYPE,
21180 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_11_WIDTH },
21181 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_CHECKER_TYPE,
21182 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_12_WIDTH },
21183 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_CHECKER_TYPE,
21184 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_13_WIDTH },
21185 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_CHECKER_TYPE,
21186 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_14_WIDTH },
21187 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_CHECKER_TYPE,
21188 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_15_WIDTH },
21189 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_CHECKER_TYPE,
21190 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_16_WIDTH },
21191 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_CHECKER_TYPE,
21192 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_17_WIDTH },
21193 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_CHECKER_TYPE,
21194 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_18_WIDTH },
21195 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_CHECKER_TYPE,
21196 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_19_WIDTH },
21197 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_CHECKER_TYPE,
21198 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_20_WIDTH },
21199 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_CHECKER_TYPE,
21200 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_21_WIDTH },
21201 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_CHECKER_TYPE,
21202 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_22_WIDTH },
21203 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_CHECKER_TYPE,
21204 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_23_WIDTH },
21205 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_CHECKER_TYPE,
21206 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_24_WIDTH },
21207 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_CHECKER_TYPE,
21208 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_25_WIDTH },
21209 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_CHECKER_TYPE,
21210 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_26_WIDTH },
21211 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_CHECKER_TYPE,
21212 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_27_WIDTH },
21213 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_CHECKER_TYPE,
21214 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_28_WIDTH },
21215 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_CHECKER_TYPE,
21216 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_29_WIDTH },
21217 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_CHECKER_TYPE,
21218 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_30_WIDTH },
21219 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_CHECKER_TYPE,
21220 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_31_WIDTH },
21221 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_CHECKER_TYPE,
21222 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_32_WIDTH },
21223 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_CHECKER_TYPE,
21224 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_33_WIDTH },
21225 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_CHECKER_TYPE,
21226 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_34_WIDTH },
21227 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_CHECKER_TYPE,
21228 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_35_WIDTH },
21229 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_CHECKER_TYPE,
21230 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_36_WIDTH },
21231 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_CHECKER_TYPE,
21232 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_37_WIDTH },
21233 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_CHECKER_TYPE,
21234 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_38_WIDTH },
21235 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_CHECKER_TYPE,
21236 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_39_WIDTH },
21237 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_CHECKER_TYPE,
21238 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_40_WIDTH },
21239 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_CHECKER_TYPE,
21240 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_41_WIDTH },
21241 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_CHECKER_TYPE,
21242 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_42_WIDTH },
21243 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_CHECKER_TYPE,
21244 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_43_WIDTH },
21245 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_CHECKER_TYPE,
21246 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_44_WIDTH },
21247 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_CHECKER_TYPE,
21248 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_45_WIDTH },
21249 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_CHECKER_TYPE,
21250 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_46_WIDTH },
21251 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_CHECKER_TYPE,
21252 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_47_WIDTH },
21253 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_CHECKER_TYPE,
21254 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_48_WIDTH },
21255 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_CHECKER_TYPE,
21256 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_49_WIDTH },
21257 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_CHECKER_TYPE,
21258 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_50_WIDTH },
21259 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_CHECKER_TYPE,
21260 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_51_WIDTH },
21261 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_CHECKER_TYPE,
21262 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_52_WIDTH },
21263 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_CHECKER_TYPE,
21264 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_53_WIDTH },
21265 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_CHECKER_TYPE,
21266 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_54_WIDTH },
21267 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_CHECKER_TYPE,
21268 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_55_WIDTH },
21269 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_CHECKER_TYPE,
21270 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_56_WIDTH },
21271 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_CHECKER_TYPE,
21272 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_57_WIDTH },
21273 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_CHECKER_TYPE,
21274 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_58_WIDTH },
21275 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_CHECKER_TYPE,
21276 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_GROUP_59_WIDTH },
21286 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_0_CHECKER_TYPE,
21287 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_0_WIDTH },
21288 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_1_CHECKER_TYPE,
21289 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_1_WIDTH },
21290 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_2_CHECKER_TYPE,
21291 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_2_WIDTH },
21292 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_3_CHECKER_TYPE,
21293 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_3_WIDTH },
21294 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_4_CHECKER_TYPE,
21295 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_4_WIDTH },
21296 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_5_CHECKER_TYPE,
21297 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_GROUP_5_WIDTH },
21305 { SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
21306 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
21307 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
21308 SDL_C7X256V1_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
21310 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
21311 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
21312 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
21313 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
21315 { SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
21316 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
21317 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
21318 SDL_C7X256V1_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
21320 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
21321 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
21322 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
21323 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21325 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
21326 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
21327 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
21328 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
21330 { SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
21331 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
21332 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
21333 SDL_C7X256V1_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
21335 { SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID,
21336 SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
21337 SDL_C7X256V1_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
21340 { SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
21341 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
21342 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
21343 SDL_C7X256V1_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
21353 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_RAM_ID,
21354 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_INJECT_TYPE,
21355 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_ECC_TYPE,
21356 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21358 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_RAM_ID,
21359 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_INJECT_TYPE,
21360 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_ECC_TYPE,
21361 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_MMR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21363 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
21364 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
21365 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
21366 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_VBUSP_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
21368 { SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_RAM_ID,
21369 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
21370 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
21371 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_K3VTM_N16FFC_CFG_CBASS_CFG_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21381 { SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_RAM_ID,
21382 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_INJECT_TYPE,
21383 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_PSRAM256X32E_PSRAM0_ECC_ECC_TYPE,
21394 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
21395 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21396 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21397 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21399 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21400 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21401 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21402 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21404 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21405 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21406 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21407 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21409 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_RAM_ID,
21410 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21411 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21412 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21414 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21415 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21416 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21417 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21419 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_RAM_ID,
21420 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21421 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21422 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21424 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID,
21425 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_INJECT_TYPE,
21426 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ECC_TYPE,
21437 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
21438 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21439 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21440 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21442 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21443 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21444 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21445 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_P2P_CPU0_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21447 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21448 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21449 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21450 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21452 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_RAM_ID,
21453 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21454 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21455 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21457 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
21458 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
21459 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
21460 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21462 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_RAM_ID,
21463 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
21464 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
21465 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_IDOM0_M2M_CPU0_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
21467 { SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID,
21468 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_INJECT_TYPE,
21469 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_CPU0_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ECC_TYPE,
21480 { SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
21481 SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
21482 SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
21493 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
21494 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
21495 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
21498 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
21499 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
21500 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
21503 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
21504 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
21505 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
21508 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
21509 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
21510 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
21513 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
21514 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
21515 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
21518 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
21519 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
21520 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
21523 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
21524 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
21525 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
21528 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
21529 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
21530 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
21533 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
21534 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
21535 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
21538 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
21539 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
21540 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
21543 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
21544 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
21545 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
21548 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
21549 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
21550 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
21553 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
21554 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
21555 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
21558 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
21559 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
21560 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
21563 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
21564 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
21565 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
21568 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
21569 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
21570 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
21573 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
21574 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
21575 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
21578 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
21579 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
21580 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
21583 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
21584 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
21585 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
21588 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
21589 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
21590 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
21593 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
21594 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
21595 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
21598 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_RAM_ID,
21599 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_INJECT_TYPE,
21600 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK0_ECC_TYPE,
21603 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_RAM_ID,
21604 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_INJECT_TYPE,
21605 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_ATCM0_BANK1_ECC_TYPE,
21608 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_RAM_ID,
21609 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_INJECT_TYPE,
21610 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK0_ECC_TYPE,
21613 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_RAM_ID,
21614 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_INJECT_TYPE,
21615 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B0TCM0_BANK1_ECC_TYPE,
21618 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_RAM_ID,
21619 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_INJECT_TYPE,
21620 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK0_ECC_TYPE,
21623 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_RAM_ID,
21624 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_INJECT_TYPE,
21625 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_B1TCM0_BANK1_ECC_TYPE,
21628 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_RAM_ID,
21629 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_INJECT_TYPE,
21630 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_PULSAR_KS_VIM_COMMON_CORE0_RAM_ECC_TYPE,
21633 { SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
21634 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
21635 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_PULSAR_UL_MEM_MST0_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
21646 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_RAM_ID,
21647 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_INJECT_TYPE,
21648 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ADR_FIFO_ECC_TYPE,
21651 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_RAM_ID,
21652 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_INJECT_TYPE,
21653 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT0_FIFO_ECC_TYPE,
21656 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_RAM_ID,
21657 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_INJECT_TYPE,
21658 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WDAT1_FIFO_ECC_TYPE,
21661 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_RAM_ID,
21662 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_INJECT_TYPE,
21663 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT0_FIFO_ECC_TYPE,
21666 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_RAM_ID,
21667 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_INJECT_TYPE,
21668 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_BDAT1_FIFO_ECC_TYPE,
21671 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_RAM_ID,
21672 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_INJECT_TYPE,
21673 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RDAT_FIFO_ECC_TYPE,
21676 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_RAM_ID,
21677 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_INJECT_TYPE,
21678 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_RX_FIFO_ECC_TYPE,
21681 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_RAM_ID,
21682 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_INJECT_TYPE,
21683 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW0_FIFO_ECC_TYPE,
21686 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_RAM_ID,
21687 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_INJECT_TYPE,
21688 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID0_FIFO_ECC_TYPE,
21691 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_RAM_ID,
21692 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_INJECT_TYPE,
21693 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID0_FIFO_ECC_TYPE,
21696 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_RAM_ID,
21697 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_INJECT_TYPE,
21698 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AW1_FIFO_ECC_TYPE,
21701 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_RAM_ID,
21702 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_INJECT_TYPE,
21703 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_WID1_FIFO_ECC_TYPE,
21706 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_RAM_ID,
21707 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_INJECT_TYPE,
21708 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AWID1_FIFO_ECC_TYPE,
21711 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_RAM_ID,
21712 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_INJECT_TYPE,
21713 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_AR_FIFO_ECC_TYPE,
21716 { SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_RAM_ID,
21717 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_INJECT_TYPE,
21718 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_HYPERBUS1P0_WRAP_MEM_ARID_FIFO_ECC_TYPE,
21729 { SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
21730 SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
21731 SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
21742 { SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
21743 SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
21744 SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
21755 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_RAM_ID,
21756 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_INJECT_TYPE,
21757 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_ECC_TYPE,
21758 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_MEM_CBASS_MAIN_R5SS_CLK_2_CLK_EDC_CTRL_CBASS_INT_MAIN_R5SS_CLK_2_BUSECC_MAX_NUM_CHECKERS,
21760 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
21761 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
21762 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
21763 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
21765 { SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_RAM_ID,
21766 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
21767 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_ECC_TYPE,
21768 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_AM275_R5_MAIN_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21778 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_RAM_ID,
21779 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_INJECT_TYPE,
21780 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_ECC_TYPE,
21781 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_ECCAGGR_EDC_CTRL_MAX_NUM_CHECKERS,
21783 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_RAM_ID,
21784 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_INJECT_TYPE,
21785 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_CONFIG_ECC_TYPE,
21788 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_RAM_ID,
21789 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_INJECT_TYPE,
21790 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_CFG_STATE_ECC_TYPE,
21793 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_RAM_ID,
21794 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
21795 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F0_ECC_TYPE,
21798 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_RAM_ID,
21799 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
21800 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_TPCFIFO_F1_ECC_TYPE,
21803 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_RAM_ID,
21804 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
21805 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F0_ECC_TYPE,
21808 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_RAM_ID,
21809 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
21810 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_F1_ECC_TYPE,
21813 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_RAM_ID,
21814 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
21815 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RPCFIFO_WC_ECC_TYPE,
21818 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_RAM_ID,
21819 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_INJECT_TYPE,
21820 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STST0_ECC_TYPE,
21823 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_RAM_ID,
21824 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_INJECT_TYPE,
21825 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_STATS_STSR0_ECC_TYPE,
21828 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_RAM_ID,
21829 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
21830 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
21833 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_RAM_ID,
21834 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_INJECT_TYPE,
21835 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_ECC_TYPE,
21836 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PKTDMA_EDC_CTRL_0_MAX_NUM_CHECKERS,
21838 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_RAM_ID,
21839 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_INJECT_TYPE,
21840 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_ECC_TYPE,
21841 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21843 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_RAM_ID,
21844 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_INJECT_TYPE,
21845 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_STATREG_SR_SPRAM_8X128_SWW_SR_ECC_TYPE,
21848 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_RAM_ID,
21849 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_INJECT_TYPE,
21850 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_INTAGGR_COMMON_IM_TPRAM_158X34_SWW_SR_ECC_TYPE,
21853 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_RAM_ID,
21854 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_INJECT_TYPE,
21855 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_ECC_TYPE,
21856 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_0_MAX_NUM_CHECKERS,
21858 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_RAM_ID,
21859 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_INJECT_TYPE,
21860 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_ECC_TYPE,
21861 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_EDC_CTRL_1_MAX_NUM_CHECKERS,
21863 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_RAM_ID,
21864 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_INJECT_TYPE,
21865 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_RINGACC_STRAM_ECC_TYPE,
21868 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
21869 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
21870 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
21873 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
21874 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
21875 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
21878 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_RAM_ID,
21879 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_INJECT_TYPE,
21880 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_ECC_TYPE,
21881 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_SEC_PROXY_EDC_CTRL_0_MAX_NUM_CHECKERS,
21883 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_RAM_ID,
21884 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_INJECT_TYPE,
21885 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_ECC_TYPE,
21886 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_0_MAX_NUM_CHECKERS,
21888 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
21889 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
21890 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
21891 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21893 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
21894 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
21895 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
21896 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
21898 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_RAM_ID,
21899 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_INJECT_TYPE,
21900 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_ECC0_ECC_TYPE,
21903 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_RAM_ID,
21904 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_INJECT_TYPE,
21905 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_ECC_TYPE,
21906 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_IPCSS_MSRAM_EDC_CTRL_0_MAX_NUM_CHECKERS,
21908 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_RAM_ID,
21909 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_INJECT_TYPE,
21910 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_ECC_TYPE,
21911 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_SAUL0_PSIL_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
21913 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_RAM_ID,
21914 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
21915 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
21916 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_STRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
21918 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
21919 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
21920 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
21921 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
21923 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_RAM_ID,
21924 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_INJECT_TYPE,
21925 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_ECC_TYPE,
21926 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_SAFEG_EDC_CTRL_0_MAX_NUM_CHECKERS,
21928 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
21929 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
21930 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
21931 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PKTDMA_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
21933 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_RAM_ID,
21934 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
21935 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_ECC_TYPE,
21936 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_PSILCFG_CFGSTRM_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
21938 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_RAM_ID,
21939 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_INJECT_TYPE,
21940 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_ECC_TYPE,
21941 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_SAUL0_PSIL_EDC_CTRL_0_MAX_NUM_CHECKERS,
21943 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_RAM_ID,
21944 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_INJECT_TYPE,
21945 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_ECC_TYPE,
21946 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_STRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
21948 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_RAM_ID,
21949 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
21950 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
21951 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PKTDMA_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
21953 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_RAM_ID,
21954 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_INJECT_TYPE,
21955 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_ECC_TYPE,
21956 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_EVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
21958 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_RAM_ID,
21959 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_INJECT_TYPE,
21960 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_ECC_TYPE,
21961 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_CEVT_EDC_CTRL_0_MAX_NUM_CHECKERS,
21963 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_RAM_ID,
21964 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_INJECT_TYPE,
21965 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_ECC_TYPE,
21966 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_INTAGGR_MEVT_IN_EDC_CTRL_0_MAX_NUM_CHECKERS,
21968 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_RAM_ID,
21969 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_INJECT_TYPE,
21970 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_ECC_TYPE,
21971 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_L2P_PSILCFG_CFGSTRM_EDC_CTRL_0_MAX_NUM_CHECKERS,
21973 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_RAM_ID,
21974 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_INJECT_TYPE,
21975 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_ECC_TYPE,
21976 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CFG_EDC_CTRL_0_MAX_NUM_CHECKERS,
21978 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_RAM_ID,
21979 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_INJECT_TYPE,
21980 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_ECC_TYPE,
21981 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_DATA_SCR1_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21983 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_RAM_ID,
21984 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_INJECT_TYPE,
21985 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_ECC_TYPE,
21986 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_RESP_SCR2_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21988 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_RAM_ID,
21989 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_INJECT_TYPE,
21990 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_ECC_TYPE,
21991 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_SCR3_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
21993 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_RAM_ID,
21994 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
21995 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
21996 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_PSILSS_CBASS_ETL_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
21998 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_RAM_ID,
21999 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_INJECT_TYPE,
22000 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_ECC_TYPE,
22001 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_DMSS_CFG_P2P_BRIDGE_EDC_CTRL_0_MAX_NUM_CHECKERS,
22003 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_RAM_ID,
22004 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_INJECT_TYPE,
22005 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_ECC_TYPE,
22006 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_SCR_SCR_EDC_CTRL_0_MAX_NUM_CHECKERS,
22008 { SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_RAM_ID,
22009 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_INJECT_TYPE,
22010 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_ECC_TYPE,
22011 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_DMSS_HSM_CFG_CBASS_VD2GCLK_EDC_CTRL_0_MAX_NUM_CHECKERS,
22021 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_RAM_ID,
22022 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_INJECT_TYPE,
22023 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM0_ECC_ECC_TYPE,
22026 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_RAM_ID,
22027 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_INJECT_TYPE,
22028 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKTRAM1_ECC_ECC_TYPE,
22031 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_RAM_ID,
22032 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_INJECT_TYPE,
22033 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_PKA_PROG_RAM_ECC_ECC_TYPE,
22036 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_RAM_ID,
22037 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_INJECT_TYPE,
22038 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK01_ECC_ECC_TYPE,
22041 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_RAM_ID,
22042 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_INJECT_TYPE,
22043 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK23_ECC_ECC_TYPE,
22046 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_RAM_ID,
22047 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_INJECT_TYPE,
22048 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_ENCR_CTXRAM_BANK4_ECC_ECC_TYPE,
22051 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_RAM_ID,
22052 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_INJECT_TYPE,
22053 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK01_ECC_ECC_TYPE,
22056 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_RAM_ID,
22057 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_INJECT_TYPE,
22058 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK23_ECC_ECC_TYPE,
22061 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_RAM_ID,
22062 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_INJECT_TYPE,
22063 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK45_ECC_ECC_TYPE,
22066 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_RAM_ID,
22067 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_INJECT_TYPE,
22068 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK67_ECC_ECC_TYPE,
22071 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_RAM_ID,
22072 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_INJECT_TYPE,
22073 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK89_ECC_ECC_TYPE,
22076 { SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_RAM_ID,
22077 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_INJECT_TYPE,
22078 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_SA3_UL_CM_AUTH_CTXRAM_BANK10_ECC_ECC_TYPE,
22089 { SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
22090 SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
22091 SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
22102 { SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
22103 SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
22104 SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
22115 { SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_RAM_ID,
22116 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_INJECT_TYPE,
22117 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_ECC_TYPE,
22118 SDL_C7X256V0_ECC_AGGR_AC71_PMC_WRAP_PMC_PMC_MEMWRAP_EDC_CTRL_PARITY_0_MAX_NUM_CHECKERS,
22120 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_RAM_ID,
22121 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_INJECT_TYPE,
22122 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_ECC_TYPE,
22123 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_TAG_CTL_TOP_DMC_TAG_CTL_EDC_CTRL_0_MAX_NUM_CHECKERS,
22125 { SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_RAM_ID,
22126 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_INJECT_TYPE,
22127 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_ECC_TYPE,
22128 SDL_C7X256V0_ECC_AGGR_C7XV_256_DMC_WRAP_C7XV_256_DMC_DMC_CORE_DMC_DATA_RTN_DMC_DATA_RTN_EDC_CTRL_0_MAX_NUM_CHECKERS,
22130 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_RAM_ID,
22131 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_INJECT_TYPE,
22132 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_ECC_TYPE,
22133 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_QUEUE_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
22135 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_RAM_ID,
22136 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_INJECT_TYPE,
22137 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_ECC_TYPE,
22138 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_RD_BUFFER_CMD_EDC_CTRL_0_MAX_NUM_CHECKERS,
22140 { SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_RAM_ID,
22141 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_INJECT_TYPE,
22142 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_ECC_TYPE,
22143 SDL_C7X256V0_ECC_AGGR_DRU_R30_R_CORE_CH_LOGIC_RING_MEM_RING_EDC_CTRL_0_MAX_NUM_CHECKERS,
22145 { SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_RAM_ID,
22146 SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_INJECT_TYPE,
22147 SDL_C7X256V0_ECC_AGGR_AM275_C7XV_CLEC_CLEC_SRAM_ECC_TYPE,
22150 { SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_RAM_ID,
22151 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_INJECT_TYPE,
22152 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_ECC_TYPE,
22153 SDL_C7X256V0_ECC_AGGR_C7XV_256_UMC_WRAP_C7XV_EL2_C7XV_EL2_CORE_C7XV_EL2_EDC_CTL_0_MAX_NUM_CHECKERS,
22163 { SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
22164 SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
22165 SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
22176 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_RAM_ID,
22177 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_INJECT_TYPE,
22178 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_ALE_RAM_ECC_TYPE,
22181 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_RAM_ID,
22182 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_INJECT_TYPE,
22183 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL1_ECC_TYPE,
22186 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_RAM_ID,
22187 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_INJECT_TYPE,
22188 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL2_ECC_TYPE,
22191 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_RAM_ID,
22192 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_INJECT_TYPE,
22193 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL3_ECC_TYPE,
22196 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_RAM_ID,
22197 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_INJECT_TYPE,
22198 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL4_ECC_TYPE,
22201 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_RAM_ID,
22202 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_INJECT_TYPE,
22203 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL5_ECC_TYPE,
22206 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_RAM_ID,
22207 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_INJECT_TYPE,
22208 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_CPSW_3GU_AM62L_CORE_ECC_ECC_CTRL6_ECC_TYPE,
22211 { SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_RAM_ID,
22212 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_INJECT_TYPE,
22213 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_EST_RAM_ECC_TYPE,
22224 { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_RAM_ID,
22225 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_INJECT_TYPE,
22226 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_EMMCSD8SS_SDHC_WRAP_TXMEM_ECC_TYPE,
22237 { SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_RAM_ID,
22238 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_INJECT_TYPE,
22239 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_EMMCSD8SS_SDHC_WRAP_RXMEM_ECC_TYPE,
22250 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_RAM_ID,
22251 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_INJECT_TYPE,
22252 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F0_TPRAM_68X128_SBW_SR_ECC_TYPE,
22255 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_RAM_ID,
22256 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_INJECT_TYPE,
22257 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_TF0_F1_TPRAM_68X128_SBW_SR_ECC_TYPE,
22260 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_RAM_ID,
22261 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_INJECT_TYPE,
22262 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F0_TPRAM_68X144_SBW_SR_ECC_TYPE,
22265 { SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_RAM_ID,
22266 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_INJECT_TYPE,
22267 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_AM275_PDMA_SPI1_PDMA_CORE_RF0_F1_TPRAM_68X144_SBW_SR_ECC_TYPE,
22278 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_RAM_ID,
22279 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_INJECT_TYPE,
22280 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_IMAILBOX8_MAIN_0_RAMECC_ECC_TYPE,
22283 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_RAM_ID,
22284 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_INJECT_TYPE,
22285 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_ECC_TYPE,
22286 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_TIFS_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
22288 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_RAM_ID,
22289 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_INJECT_TYPE,
22290 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_ECC_TYPE,
22291 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_ISMS_MAIN_0_HSM_VBUSP_S_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
22293 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_RAM_ID,
22294 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_INJECT_TYPE,
22295 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_ECC_TYPE,
22296 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_CENTRAL_CBASS_HSM_CLK_1_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
22298 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
22299 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
22300 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
22301 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22303 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
22304 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
22305 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
22306 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_AM275_MAIN_IPCSS_CBASS_ISA3SS_AM62A_MAIN_0_IPCSS_VBM_DST_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22308 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
22309 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
22310 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
22311 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_IPCSS_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
22313 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
22314 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
22315 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
22316 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
22318 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_RAM_ID,
22319 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
22320 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
22321 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_ISMS_MAIN_0_FWMGR_CFG_P2P_BRIDGE_ISMS_MAIN_0_FWMGR_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
22323 { SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_RAM_ID,
22324 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_INJECT_TYPE,
22325 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_ECC_TYPE,
22326 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_AM275_MAIN_FW_CBASS_HSM_CLK_2_CLK_EDC_CTRL_CBASS_INT_HSM_CLK_2_BUSECC_MAX_NUM_CHECKERS,
22336 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
22337 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
22338 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
22339 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22341 { SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
22342 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
22343 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
22344 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22354 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
22355 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
22356 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
22357 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_M2M_CPU0_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22359 { SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
22360 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
22361 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
22362 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_IDOM0_P2P_CPU0_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22372 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_RAM_ID,
22373 SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_INJECT_TYPE,
22374 SDL_SMS0_SMS_HSM_ECC_ISRAM0_RAMECC_ECC_TYPE,
22377 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_RAM_ID,
22378 SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_INJECT_TYPE,
22379 SDL_SMS0_SMS_HSM_ECC_ISRAM1_RAMECC_ECC_TYPE,
22382 { SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_RAM_ID,
22383 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_INJECT_TYPE,
22384 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_ECC_TYPE,
22385 SDL_SMS0_SMS_HSM_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
22387 { SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_RAM_ID,
22388 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_INJECT_TYPE,
22389 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_ECC_TYPE,
22390 SDL_SMS0_SMS_HSM_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
22392 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_RAM_ID,
22393 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_INJECT_TYPE,
22394 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_ECC_TYPE,
22395 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_MAX_NUM_CHECKERS,
22397 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
22398 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
22399 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
22400 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22402 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
22403 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22404 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22405 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_SMS_HSM_CBASS_SMS_HSM_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22407 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_RAM_ID,
22408 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
22409 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
22410 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22412 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
22413 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
22414 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
22415 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_SMS_HSM_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22417 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
22418 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22419 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22420 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_SMS_HSM_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22422 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
22423 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22424 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
22425 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22427 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
22428 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
22429 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
22430 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22432 { SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_RAM_ID,
22433 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_INJECT_TYPE,
22434 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_ECC_TYPE,
22435 SDL_SMS0_SMS_HSM_ECC_SMS_HSM_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
22445 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_RAM_ID,
22446 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_INJECT_TYPE,
22447 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_RAMECC_ECC_TYPE,
22450 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_RAM_ID,
22451 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_INJECT_TYPE,
22452 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_RAMECC_ECC_TYPE,
22455 { SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_RAM_ID,
22456 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_INJECT_TYPE,
22457 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_ECC_TYPE,
22458 SDL_SMS0_SMS_TIFS_ECC_ISRAM0_BUSECC_MAX_NUM_CHECKERS,
22460 { SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_RAM_ID,
22461 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_INJECT_TYPE,
22462 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_ECC_TYPE,
22463 SDL_SMS0_SMS_TIFS_ECC_ISRAM1_BUSECC_MAX_NUM_CHECKERS,
22465 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_RAM_ID,
22466 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_INJECT_TYPE,
22467 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_ECC_TYPE,
22468 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_0_MAX_NUM_CHECKERS,
22470 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_RAM_ID,
22471 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_INJECT_TYPE,
22472 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_ECC_TYPE,
22473 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_1_MAX_NUM_CHECKERS,
22475 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_RAM_ID,
22476 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_INJECT_TYPE,
22477 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_ECC_TYPE,
22478 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_VBUS_CLK_EDC_CTRL_CBASS_INT_VBUS_BUSECC_2_MAX_NUM_CHECKERS,
22480 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_RAM_ID,
22481 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_INJECT_TYPE,
22482 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_ECC_TYPE,
22483 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IECC_S_P2P_BRIDGE_IECC_S_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22485 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_RAM_ID,
22486 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_INJECT_TYPE,
22487 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_ECC_TYPE,
22488 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_IFWMGR_M_P2P_BRIDGE_IFWMGR_M_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22490 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_RAM_ID,
22491 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
22492 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_ECC_TYPE,
22493 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
22495 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_RAM_ID,
22496 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
22497 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_ECC_TYPE,
22498 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_SMS_TIFS_CBASS_SMS_TIFS_SCR_SCR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
22500 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_RAM_ID,
22501 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_INJECT_TYPE,
22502 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_ECC_TYPE,
22503 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_RAT_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22505 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_RAM_ID,
22506 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_INJECT_TYPE,
22507 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_ECC_TYPE,
22508 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_SMS_TIFS_CBASS_CBASS_DEFAULT_MMRS_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22510 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_RAM_ID,
22511 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22512 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22513 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_SMS_TIFS_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22515 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_RAM_ID,
22516 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_INJECT_TYPE,
22517 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_ECC_TYPE,
22518 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_DMSC_SLV_P2P_BRIDGE_DMSC_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22520 { SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_RAM_ID,
22521 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
22522 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
22523 SDL_SMS0_SMS_TIFS_ECC_SMS_FWMGR_CBASS_SMS_SCR_SCR_SMS_FWMGR_CBASS_SMS_SCR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22525 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_RAM_ID,
22526 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_INJECT_TYPE,
22527 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_ECC_TYPE,
22528 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CBASS_SMS_DMSS_HSM_P2P_BRIDGE_SMS_DMSS_HSM_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
22530 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_RAM_ID,
22531 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
22532 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_ECC_TYPE,
22533 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_WWRTI_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22535 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_RAM_ID,
22536 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
22537 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_ECC_TYPE,
22538 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22540 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_RAM_ID,
22541 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_INJECT_TYPE,
22542 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_ECC_TYPE,
22543 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_SEC_CM_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
22545 { SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_RAM_ID,
22546 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_INJECT_TYPE,
22547 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_ECC_TYPE,
22548 SDL_SMS0_SMS_TIFS_ECC_SMS_TIFS_ECC_EDC_CTRL_MAX_NUM_CHECKERS,
22558 { SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_RAM_ID,
22559 SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_INJECT_TYPE,
22560 SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_PDMEM_ECC_TYPE,
22571 { SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_RAM_ID,
22572 SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_INJECT_TYPE,
22573 SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_OSPI_OSPI_WRAP_SRAM_ECC_TYPE,
22584 { SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
22585 SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
22586 SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
22597 { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_RAM_ID,
22598 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_INJECT_TYPE,
22599 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_AXI2VBUSM_MST_KSBUS_AXI2VBUSM_R_RDATA_BUFFER_ECC_TYPE,
22602 { SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_RAM_ID,
22603 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_INJECT_TYPE,
22604 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_USB2SS_16FFC_USB2SS_CORE_RAMS_MEM_CTRL_RAM0_ECC_TYPE,
22615 { SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_RAM_ID,
22616 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_INJECT_TYPE,
22617 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_PSRAM8KX32E_PSRAM0_ECC_ECC_TYPE,
22628 { SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_RAM_ID,
22629 SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_INJECT_TYPE,
22630 SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_MLBSS2P0_MLBDIM_WRAP_DBMEM_ECC_TYPE,
22641 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
22642 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
22643 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
22646 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
22647 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
22648 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
22649 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
22659 { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_RAM_ID,
22660 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_INJECT_TYPE,
22661 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM0_TPRAM_ECC_ECC_TYPE,
22664 { SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_RAM_ID,
22665 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_INJECT_TYPE,
22666 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_RAM1_TPRAM_ECC_ECC_TYPE,
22677 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
22678 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
22679 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
22682 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
22683 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
22684 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
22687 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
22688 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
22689 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
22692 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
22693 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
22694 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
22697 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
22698 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
22699 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
22702 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
22703 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
22704 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
22707 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
22708 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
22709 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
22712 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
22713 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
22714 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
22717 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
22718 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
22719 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
22722 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
22723 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
22724 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
22727 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
22728 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
22729 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
22732 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
22733 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
22734 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
22737 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
22738 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
22739 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
22742 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
22743 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
22744 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
22747 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
22748 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
22749 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
22752 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
22753 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
22754 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
22757 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
22758 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
22759 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
22762 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
22763 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
22764 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
22767 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
22768 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
22769 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
22772 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
22773 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
22774 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
22777 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
22778 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
22779 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
22782 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
22783 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
22784 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
22787 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
22788 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
22789 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
22792 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
22793 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
22794 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
22797 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
22798 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
22799 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
22802 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
22803 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
22804 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
22807 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
22808 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
22809 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
22812 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
22813 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
22814 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
22817 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID,
22818 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_INJECT_TYPE,
22819 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_ECC_TYPE,
22820 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22822 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
22823 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
22824 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
22827 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_RAM_ID,
22828 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
22829 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
22830 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22832 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID,
22833 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_INJECT_TYPE,
22834 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ECC_TYPE,
22837 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_RAM_ID,
22838 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_INJECT_TYPE,
22839 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_ECC_TYPE,
22840 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
22842 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_RAM_ID,
22843 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_INJECT_TYPE,
22844 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_ECC_TYPE,
22845 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS,
22847 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
22848 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
22849 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE,
22850 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS,
22852 { SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
22853 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
22854 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
22855 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
22865 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
22866 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
22867 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
22870 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
22871 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
22872 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
22875 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
22876 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
22877 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
22880 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
22881 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
22882 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
22885 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
22886 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
22887 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
22890 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
22891 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
22892 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
22895 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
22896 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
22897 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
22900 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
22901 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
22902 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
22905 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
22906 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
22907 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
22910 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
22911 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
22912 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
22915 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
22916 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
22917 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
22920 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
22921 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
22922 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
22925 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
22926 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
22927 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
22930 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
22931 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
22932 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
22935 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
22936 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
22937 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
22940 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
22941 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
22942 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
22945 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
22946 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
22947 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
22950 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
22951 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
22952 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
22955 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
22956 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
22957 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
22960 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
22961 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
22962 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
22965 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
22966 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
22967 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
22970 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
22971 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
22972 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
22975 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
22976 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
22977 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
22980 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
22981 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
22982 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
22985 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
22986 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
22987 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
22990 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
22991 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
22992 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
22995 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
22996 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
22997 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
23000 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
23001 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
23002 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
23005 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_RAM_ID,
23006 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_INJECT_TYPE,
23007 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_ECC_TYPE,
23008 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23010 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
23011 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
23012 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
23015 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_RAM_ID,
23016 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_INJECT_TYPE,
23017 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_ECC_TYPE,
23018 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23020 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID,
23021 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_INJECT_TYPE,
23022 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ECC_TYPE,
23025 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_RAM_ID,
23026 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_INJECT_TYPE,
23027 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_ECC_TYPE,
23028 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23030 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_RAM_ID,
23031 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_INJECT_TYPE,
23032 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_ECC_TYPE,
23033 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS,
23035 { SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_RAM_ID,
23036 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23037 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23038 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23048 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
23049 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
23050 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
23053 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
23054 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
23055 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
23058 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
23059 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
23060 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
23063 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
23064 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
23065 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
23068 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
23069 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
23070 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
23073 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
23074 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
23075 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
23078 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
23079 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
23080 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
23083 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
23084 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
23085 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
23088 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
23089 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
23090 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
23093 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
23094 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
23095 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
23098 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
23099 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
23100 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
23103 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
23104 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
23105 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
23108 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
23109 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
23110 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
23113 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
23114 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
23115 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
23118 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
23119 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
23120 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
23123 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
23124 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
23125 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
23128 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
23129 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
23130 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
23133 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
23134 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
23135 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
23138 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
23139 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
23140 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
23143 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
23144 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
23145 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
23148 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
23149 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
23150 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
23153 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
23154 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
23155 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
23158 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
23159 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
23160 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
23163 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
23164 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
23165 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
23168 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
23169 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
23170 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
23173 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
23174 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
23175 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
23178 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
23179 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
23180 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
23183 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
23184 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
23185 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
23188 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_RAM_ID,
23189 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_INJECT_TYPE,
23190 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_ECC_TYPE,
23191 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI0_EDC_CTRL_0_MAX_NUM_CHECKERS,
23193 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
23194 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
23195 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
23198 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_RAM_ID,
23199 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_INJECT_TYPE,
23200 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_ECC_TYPE,
23201 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_MEM_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
23203 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID,
23204 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_INJECT_TYPE,
23205 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AXI2VBUSM_PERIPH_MST_RAMECC_ECC_TYPE,
23208 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_RAM_ID,
23209 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_INJECT_TYPE,
23210 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_ECC_TYPE,
23211 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_PERIPH_M_MST0_EDC_CTRL_0_MAX_NUM_CHECKERS,
23213 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_RAM_ID,
23214 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_INJECT_TYPE,
23215 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_ECC_TYPE,
23216 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_CPU0_AHB2VBUSP_EDC_MAX_NUM_CHECKERS,
23218 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_RAM_ID,
23219 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
23220 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE,
23221 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_MAX_NUM_CHECKERS,
23223 { SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_RAM_ID,
23224 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23225 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23226 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_PULSAR_SL_CPU0_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23236 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
23237 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
23238 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
23241 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
23242 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
23243 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
23246 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
23247 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
23248 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
23251 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
23252 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
23253 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
23256 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
23257 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
23258 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
23261 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
23262 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
23263 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
23266 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
23267 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
23268 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
23271 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
23272 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
23273 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
23276 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
23277 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
23278 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
23281 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
23282 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
23283 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
23286 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
23287 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
23288 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
23291 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
23292 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
23293 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
23296 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
23297 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
23298 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
23301 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
23302 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
23303 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
23306 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
23307 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
23308 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
23311 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
23312 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
23313 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
23316 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
23317 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
23318 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
23321 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
23322 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
23323 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
23326 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
23327 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
23328 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
23331 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
23332 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
23333 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
23336 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
23337 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
23338 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
23341 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
23342 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
23343 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
23346 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
23347 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
23348 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
23351 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
23352 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
23353 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
23356 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
23357 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
23358 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
23361 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
23362 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
23363 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
23366 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
23367 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
23368 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
23371 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
23372 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
23373 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
23376 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_RAM_ID,
23377 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_INJECT_TYPE,
23378 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_ECC_TYPE,
23379 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_KSBUS_VBUSM2AXI1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23381 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_RAM_ID,
23382 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_INJECT_TYPE,
23383 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_MEM_MST_RAMECC_ECC_TYPE,
23386 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_RAM_ID,
23387 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_INJECT_TYPE,
23388 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_ECC_TYPE,
23389 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_MEM_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23391 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_RAM_ID,
23392 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_INJECT_TYPE,
23393 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AXI2VBUSM_PERIPH_MST_RAMECC_ECC_TYPE,
23396 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_RAM_ID,
23397 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_INJECT_TYPE,
23398 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_ECC_TYPE,
23399 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_PERIPH_M_MST1_EDC_CTRL_0_MAX_NUM_CHECKERS,
23401 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_RAM_ID,
23402 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_INJECT_TYPE,
23403 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_ECC_TYPE,
23404 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_CPU1_AHB2VBUSP_EDC_MAX_NUM_CHECKERS,
23406 { SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_RAM_ID,
23407 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23408 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23409 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_PULSAR_SL_CPU1_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23419 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
23420 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
23421 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
23422 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23424 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
23425 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23426 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23427 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23429 { SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_RAM_ID,
23430 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23431 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23432 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_AM275_DM_MCU_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23442 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
23443 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23444 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23445 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23447 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_RAM_ID,
23448 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23449 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23450 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_AM275_WKUP_DM_CBASS_ISA3SS_AM62A_MAIN_0_PKTDMA_MEM_M2M_BRIDGE_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23452 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_RAM_ID,
23453 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_INJECT_TYPE,
23454 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_ECC_TYPE,
23455 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_IK3VTM_N16FFC_WKUP_0_VBUSP_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
23457 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
23458 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23459 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
23460 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_MCU_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23462 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
23463 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
23464 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
23465 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
23467 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_RAM_ID,
23468 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_INJECT_TYPE,
23469 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_ECC_TYPE,
23470 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_P2P_BRIDGE_IAM275_DM_DM_ECC_AGGR_WKUP_0_CFG_BRIDGE_DST_BUSECC_MAX_NUM_CHECKERS,
23472 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_RAM_ID,
23473 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23474 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23475 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_AM275_WKUP_DM_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2M_BRIDGE_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23477 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_RAM_ID,
23478 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_INJECT_TYPE,
23479 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_ECC_TYPE,
23480 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_1_CLK_EDC_CTRL_CBASS_INT_DM_CLK_1_BUSECC_MAX_NUM_CHECKERS,
23482 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_RAM_ID,
23483 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_INJECT_TYPE,
23484 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_ECC_TYPE,
23485 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_WKUP_DM_CBASS_DM_CLK_4_CLK_EDC_CTRL_CBASS_INT_DM_CLK_4_BUSECC_MAX_NUM_CHECKERS,
23487 { SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_RAM_ID,
23488 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
23489 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_ECC_TYPE,
23490 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_AM275_DM_DM_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
23500 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_RAM_ID,
23501 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_INJECT_TYPE,
23502 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F0_TPRAM_28X128_SBW_SR_ECC_TYPE,
23505 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_RAM_ID,
23506 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_INJECT_TYPE,
23507 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_TF0_F1_TPRAM_28X128_SBW_SR_ECC_TYPE,
23510 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_RAM_ID,
23511 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_INJECT_TYPE,
23512 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F0_TPRAM_28X144_SBW_SR_ECC_TYPE,
23515 { SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_RAM_ID,
23516 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_INJECT_TYPE,
23517 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_SAM62_PDMA_UART_PDMA_CORE_RF0_F1_TPRAM_28X144_SBW_SR_ECC_TYPE,
23528 { SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_RAM_ID,
23529 SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_INJECT_TYPE,
23530 SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_MSRAM32KX256E_MSRAM0_ECC0_ECC_TYPE,
23541 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_RAM_ID,
23542 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_INJECT_TYPE,
23543 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F0_TPRAM_72X128_SBW_SR_ECC_TYPE,
23546 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_RAM_ID,
23547 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_INJECT_TYPE,
23548 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_TF0_F1_TPRAM_72X128_SBW_SR_ECC_TYPE,
23551 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_RAM_ID,
23552 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_INJECT_TYPE,
23553 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F0_TPRAM_72X144_SBW_SR_ECC_TYPE,
23556 { SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_RAM_ID,
23557 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_INJECT_TYPE,
23558 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_SAM67_PDMA_SPI_PDMA_CORE_RF0_F1_TPRAM_72X144_SBW_SR_ECC_TYPE,
23569 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
23570 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23571 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23572 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23574 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23575 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23576 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23577 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23579 { SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
23580 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23581 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23582 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23592 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
23593 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23594 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23595 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_M2M_CPU1_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23597 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23598 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23599 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23600 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_PMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23602 { SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_RAM_ID,
23603 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23604 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23605 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_IDOM1_P2P_CPU1_CFG_SLV_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23615 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
23616 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
23617 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
23620 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
23621 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
23622 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
23623 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
23633 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
23634 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
23635 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
23638 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
23639 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
23640 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
23641 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
23651 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
23652 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
23653 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
23656 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
23657 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
23658 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
23659 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
23669 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_RAM_ID,
23670 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_INJECT_TYPE,
23671 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_CONFIG_ECC_TYPE,
23674 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_RAM_ID,
23675 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_INJECT_TYPE,
23676 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_CFG_STATE_ECC_TYPE,
23679 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_RAM_ID,
23680 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_INJECT_TYPE,
23681 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F0_ECC_TYPE,
23684 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_RAM_ID,
23685 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_INJECT_TYPE,
23686 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_TPCFIFO_F1_ECC_TYPE,
23689 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_RAM_ID,
23690 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_INJECT_TYPE,
23691 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F0_ECC_TYPE,
23694 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_RAM_ID,
23695 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_INJECT_TYPE,
23696 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_F1_ECC_TYPE,
23699 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_RAM_ID,
23700 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_INJECT_TYPE,
23701 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RPCFIFO_WC_ECC_TYPE,
23704 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_RAM_ID,
23705 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_INJECT_TYPE,
23706 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STST0_ECC_TYPE,
23709 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_RAM_ID,
23710 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_INJECT_TYPE,
23711 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_STATS_STSR0_ECC_TYPE,
23714 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_RAM_ID,
23715 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_INJECT_TYPE,
23716 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_PKTDMA_RINGOCC_CNTR_ECC_TYPE,
23719 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_RAM_ID,
23720 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_INJECT_TYPE,
23721 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_CONFIG_ECC_TYPE,
23724 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_RAM_ID,
23725 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_INJECT_TYPE,
23726 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_CFG_STATE_ECC_TYPE,
23729 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_RAM_ID,
23730 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_INJECT_TYPE,
23731 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F0_ECC_TYPE,
23734 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_RAM_ID,
23735 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_INJECT_TYPE,
23736 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_PCFIFO_DFIFO_F1_ECC_TYPE,
23739 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_RAM_ID,
23740 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_INJECT_TYPE,
23741 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F0_ECC_TYPE,
23744 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_RAM_ID,
23745 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_INJECT_TYPE,
23746 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_TPCFIFO_F1_ECC_TYPE,
23749 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_RAM_ID,
23750 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_INJECT_TYPE,
23751 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F0_ECC_TYPE,
23754 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_RAM_ID,
23755 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_INJECT_TYPE,
23756 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_F1_ECC_TYPE,
23759 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_RAM_ID,
23760 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_INJECT_TYPE,
23761 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RPCFIFO_WC_ECC_TYPE,
23764 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_RAM_ID,
23765 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_INJECT_TYPE,
23766 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STST0_ECC_TYPE,
23769 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_RAM_ID,
23770 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_INJECT_TYPE,
23771 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_STATS_STSR0_ECC_TYPE,
23774 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_RAM_ID,
23775 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_INJECT_TYPE,
23776 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_BCDMA_RINGOCC_CNTR_ECC_TYPE,
23779 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_RAM_ID,
23780 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_INJECT_TYPE,
23781 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_STATREG_SR_SPRAM_184X128_SWW_SR_ECC_TYPE,
23784 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_RAM_ID,
23785 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_INJECT_TYPE,
23786 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_INTAGGR_COMMON_IM_TPRAM_1611X34_SWW_SR_ECC_TYPE,
23789 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_RAM_ID,
23790 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_INJECT_TYPE,
23791 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_RINGACC_STRAM_ECC_TYPE,
23794 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_RAM_ID,
23795 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_INJECT_TYPE,
23796 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_STRAM_ECC_TYPE,
23799 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_RAM_ID,
23800 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_INJECT_TYPE,
23801 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_SEC_PROXY_BUF_BUFRAM_ECC_TYPE,
23804 { SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_RAM_ID,
23805 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_INJECT_TYPE,
23806 SDL_DMASS0_ECC_AGGR_0_DMSS_AM275_IPCSS_MSRAM_ECC0_ECC_TYPE,
23817 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
23818 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
23819 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
23822 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_RAM_ID,
23823 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_INJECT_TYPE,
23824 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_ECC_TYPE,
23825 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_CTRL_EDC_VBUSS_MAX_NUM_CHECKERS,
23835 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
23836 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23837 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23838 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23840 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23841 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23842 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23843 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23845 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23846 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23847 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23848 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23850 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23851 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23852 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23853 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23855 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23856 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23857 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23858 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23860 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23861 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23862 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23863 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23865 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID,
23866 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_INJECT_TYPE,
23867 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ECC_TYPE,
23870 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
23871 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23872 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23873 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23883 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
23884 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23885 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23886 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23888 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23889 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23890 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23891 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_PMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23893 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23894 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23895 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23896 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23898 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23899 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23900 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23901 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_RMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23903 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_RAM_ID,
23904 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_INJECT_TYPE,
23905 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_ECC_TYPE,
23906 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_SRC_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23908 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_RAM_ID,
23909 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23910 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23911 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_M2M_CPU1_WMST_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23913 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_RAM_ID,
23914 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_INJECT_TYPE,
23915 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_CPU1_RL2_OF_TAGRAM_EDC_CTRL_BUSECC_ECC_TYPE,
23918 { SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_RAM_ID,
23919 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_INJECT_TYPE,
23920 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_ECC_TYPE,
23921 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_IDOM1_P2P_CPU1_CFG_SLV_DST_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23931 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
23932 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23933 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23934 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23936 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
23937 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23938 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23939 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23941 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_RAM_ID,
23942 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_INJECT_TYPE,
23943 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_ECC_TYPE,
23944 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PLL_MMR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23946 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_RAM_ID,
23947 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_INJECT_TYPE,
23948 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_ECC_TYPE,
23949 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_0_MAX_NUM_CHECKERS,
23951 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_RAM_ID,
23952 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_INJECT_TYPE,
23953 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_ECC_TYPE,
23954 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_1_MAX_NUM_CHECKERS,
23956 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_RAM_ID,
23957 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_INJECT_TYPE,
23958 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_ECC_TYPE,
23959 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_MCU_PADCFG_CTRL_MMR_EDC_CTRL_BUSECC_2_MAX_NUM_CHECKERS,
23961 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_RAM_ID,
23962 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_INJECT_TYPE,
23963 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_ECC_TYPE,
23964 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_M2P_BRIDGE_EXPORT_AM275_WKUP_DM_CBASS_TO_AM275_WKUP_SAFE_CBASS_DATA_L0_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23966 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_RAM_ID,
23967 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_INJECT_TYPE,
23968 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_ECC_TYPE,
23969 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_IAM275_WKUP_SAFE_ECC_AGGR_WKUP_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
23971 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_RAM_ID,
23972 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_INJECT_TYPE,
23973 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_ECC_TYPE,
23974 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_IAM275_WKUP_SAFE_CBASS_WKUP_0_CBASS_ERR_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
23976 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_RAM_ID,
23977 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23978 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23979 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_AM275_WKUP_SAFE_CBASS_SCRP_32_SAFE_MCU_CLK4_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23981 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_RAM_ID,
23982 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_INJECT_TYPE,
23983 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_ECC_TYPE,
23984 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_AM275_WKUP_SAFE_CBASS_CBASS_DEFAULT_ERR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23986 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_RAM_ID,
23987 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_INJECT_TYPE,
23988 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_ECC_TYPE,
23989 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SLV_P2P_BRIDGE_ERR_SLV_BRIDGE_BUSECC_MAX_NUM_CHECKERS,
23991 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_RAM_ID,
23992 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_INJECT_TYPE,
23993 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_ECC_TYPE,
23994 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_ERR_SCR_AM275_WKUP_SAFE_CBASS_ERR_SCR_EDC_CTRL_BUSECC_MAX_NUM_CHECKERS,
23996 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_RAM_ID,
23997 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_INJECT_TYPE,
23998 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_ECC_TYPE,
23999 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_CBASS_MCU_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MCU_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
24001 { SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_RAM_ID,
24002 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
24003 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_ECC_TYPE,
24004 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_AM275_WKUP_SAFE_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
24014 { SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_RAM_ID,
24015 SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_INJECT_TYPE,
24016 SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_PSRAM2KX32E_PSRAM0_ECC_ECC_TYPE,
24027 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_RAM_ID,
24028 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_INJECT_TYPE,
24029 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_ECC_TYPE,
24030 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_P2P_BRIDGE_IAM275_R5_MAIN_IP_ECC_AGGR_MAIN_0_CFG_BRIDGE_SRC_BUSECC_MAX_NUM_CHECKERS,
24032 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_RAM_ID,
24033 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_INJECT_TYPE,
24034 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_ECC_TYPE,
24035 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_0_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
24037 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_RAM_ID,
24038 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_INJECT_TYPE,
24039 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_ECC_TYPE,
24040 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_IPULSAR_SL_MAIN_1_CPU1_CFG_SLV_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
24042 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_RAM_ID,
24043 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_INJECT_TYPE,
24044 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_ECC_TYPE,
24045 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_IAM275_MAIN_SYS_IP_ECC_AGGR_MAIN_0_CFG_P2P_GASKET_BUSECC_MAX_NUM_CHECKERS,
24047 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_RAM_ID,
24048 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_INJECT_TYPE,
24049 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_ECC_TYPE,
24050 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_2_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_2_BUSECC_MAX_NUM_CHECKERS,
24052 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
24053 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
24054 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
24055 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_DATA_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
24057 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_RAM_ID,
24058 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_INJECT_TYPE,
24059 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_ECC_TYPE,
24060 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_MISC_PERI_CBASS_MAIN_SYSCLK0_4_CLK_EDC_CTRL_CBASS_INT_MAIN_SYSCLK0_4_BUSECC_MAX_NUM_CHECKERS,
24062 { SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_RAM_ID,
24063 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
24064 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_ECC_TYPE,
24065 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_AM275_MAIN_SYS_IP_ECC_AGGR_EDC_CTRL_MAX_NUM_CHECKERS,
24079 SDL_C7X256V1_ECC_AGGR_NUM_RAMS,
24084 SDLR_ESM0_ESM_LVL_EVENT_C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_1,
24085 SDLR_ESM0_ESM_LVL_EVENT_C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_0
24089 SDL_WKUP_VTM0_K3VTM_N16FFC_ECCAGGR_NUM_RAMS,
24094 SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_CORR_LEVEL_0,
24095 SDLR_ESM0_ESM_LVL_EVENT_WKUP_VTM0_UNCORR_LEVEL_0
24099 SDL_PSRAMECC0_PSRAM256X32E_ECC_AGGR_NUM_RAMS,
24104 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_CORR_LEVEL_0,
24105 SDLR_ESM0_ESM_LVL_EVENT_PSRAMECC0_ECC_UNCORR_LEVEL_0
24109 SDL_IDOM0_PULSAR_PLL_ECC_AGGR10_NUM_RAMS,
24114 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_PULSAR_PLL_ECC_AGGR10_CORR_LEVEL_0,
24115 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_PULSAR_PLL_ECC_AGGR10_UNCORR_LEVEL_0
24119 SDL_IDOM0_PULSAR_PLL_ECC_AGGR8_NUM_RAMS,
24124 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_PULSAR_PLL_ECC_AGGR8_CORR_LEVEL_0,
24125 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_PULSAR_PLL_ECC_AGGR8_UNCORR_LEVEL_0
24129 SDL_MSRAM_1MB4_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24134 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB4_ECC_CORR_LEVEL_0,
24135 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB4_ECC_UNCORR_LEVEL_0
24140 SDL_WKUP_R5FSS0_PULSAR_UL_CPU0_ECC_AGGR_NUM_RAMS,
24145 SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
24146 SDLR_ESM0_ESM_LVL_EVENT_WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
24150 SDL_FSS1_FSS_HB_WRAP_ECC_AGGR_NUM_RAMS,
24155 SDLR_ESM0_ESM_LVL_EVENT_FSS1_HYPERBUS_ECC_AGGR_0_HPB_ECC_CORR_LEVEL_0,
24156 SDLR_ESM0_ESM_LVL_EVENT_FSS1_HYPERBUS_ECC_AGGR_0_HPB_ECC_UNCORR_LEVEL_0
24160 SDL_FSS1_FSS_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
24165 SDLR_ESM0_ESM_LVL_EVENT_FSS1_OSPI_ECC_AGGR_0_OSPI_ECC_CORR_LVL_INTR_0,
24166 SDLR_ESM0_ESM_LVL_EVENT_FSS1_OSPI_ECC_AGGR_0_OSPI_ECC_UNCORR_LVL_INTR_0
24170 SDL_FSS1_FSS_OSPI1_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
24175 SDLR_ESM0_ESM_LVL_EVENT_FSS1_FSAS_0_ECC_INTR_ERR_PEND_0,
24176 SDLR_ESM0_ESM_LVL_EVENT_FSS1_MISC_0_ECC_INTR_ERR_PEND_0
24180 SDL_ECC_AGGR3_AM275_R5_MAIN_IP_ECC_AGGR_NUM_RAMS,
24185 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR3_CORR_LEVEL_0,
24186 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR3_UNCORR_LEVEL_0
24190 SDL_SA3_SS0_SA3SS_AM62A_DMSS_ECCAGGR_NUM_RAMS,
24195 SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0,
24196 SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0
24200 SDL_SA3_SS0_SA3SS_AM62A_SA_UL_ECC_AGGR_NUM_RAMS,
24205 SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0,
24206 SDLR_ESM0_ESM_LVL_EVENT_SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0
24210 SDL_MSRAM_1MB2_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24215 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB2_ECC_CORR_LEVEL_0,
24216 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB2_ECC_UNCORR_LEVEL_0
24220 SDL_MSRAM_1MB1_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24225 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB1_ECC_CORR_LEVEL_0,
24226 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB1_ECC_UNCORR_LEVEL_0
24230 SDL_C7X256V0_ECC_AGGR_NUM_RAMS,
24235 SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_1,
24236 SDLR_ESM0_ESM_LVL_EVENT_C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_0
24241 SDL_MSRAM_1MB0_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24246 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB0_ECC_CORR_LEVEL_0,
24247 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB0_ECC_UNCORR_LEVEL_0
24252 SDL_CPSW0_CPSW_3GUSS_AM62L_CORE_ECC_CPSW_ECC_AGGR_NUM_RAMS,
24257 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_SEC_PEND_0,
24258 SDLR_ESM0_ESM_LVL_EVENT_CPSW0_ECC_DED_PEND_0
24262 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_TXMEM_NUM_RAMS,
24267 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_CORR_ERR_LVL_0,
24268 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0
24273 SDL_MMCSD0_EMMCSD8SS_ECC_AGGR_RXMEM_NUM_RAMS,
24278 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_CORR_ERR_LVL_0,
24279 SDLR_ESM0_ESM_LVL_EVENT_MMCSD0_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0
24283 SDL_PDMA4_AM275_PDMA_SPI1_ECCAGGR_NUM_RAMS,
24288 SDLR_ESM0_ESM_LVL_EVENT_PDMA4_ECC_SEC_PEND_0,
24289 SDLR_ESM0_ESM_LVL_EVENT_PDMA4_ECC_DED_PEND_0
24293 SDL_ECC_AGGR0_AM275_SEC_HSM_ECC_AGGR_NUM_RAMS,
24298 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_CORR_LEVEL_0,
24299 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR0_UNCORR_LEVEL_0
24303 SDL_IDOM0_MAIN_PLL_ECC_AGGR6_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS,
24308 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_MAIN_PLL_ECC_AGGR6_CORR_LEVEL_0,
24309 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_MAIN_PLL_ECC_AGGR6_UNCORR_LEVEL_0
24313 SDL_IDOM0_MAIN_PLL_ECC_AGGR4_IDOM0_MAIN_PLL_ECC_AGGR_NUM_RAMS,
24318 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_MAIN_PLL_ECC_AGGR4_CORR_LEVEL_0,
24319 SDLR_ESM0_ESM_LVL_EVENT_IDOM0_MAIN_PLL_ECC_AGGR4_UNCORR_LEVEL_0
24323 SDL_SMS0_SMS_HSM_ECC_NUM_RAMS,
24328 SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
24329 SDLR_ESM0_ESM_LVL_EVENT_SMS0_HSM_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
24333 SDL_SMS0_SMS_TIFS_ECC_NUM_RAMS,
24338 SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0,
24339 SDLR_ESM0_ESM_LVL_EVENT_SMS0_TIFS_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0
24343 SDL_FSS0_FSS_OF_UL_FSAS_FOTA_FSS_OF_UL_FOTA_ACC_ECC_AGGR_NUM_RAMS,
24348 SDLR_ESM0_ESM_LVL_EVENT_FSS0_ECC_CORR_LEVEL_0,
24349 SDLR_ESM0_ESM_LVL_EVENT_FSS0_ECC_UNCORR_LEVEL_0
24354 SDL_FSS0_FSS_OF_UL_OSPI0_OSPI_WRAP_ECC_AGGR_NUM_RAMS,
24359 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI0_ECC_CORR_LVL_INTR_0,
24360 SDLR_ESM0_ESM_LVL_EVENT_FSS0_OSPI0_ECC_UNCORR_LVL_INTR_0
24365 SDL_MSRAM_1MB3_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24370 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB3_ECC_CORR_LEVEL_0,
24371 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB3_ECC_UNCORR_LEVEL_0
24375 SDL_USB0_USB2SS_16FFC_USB2SS_CORE_ECC_AGGR_NUM_RAMS,
24380 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0,
24381 SDLR_ESM0_ESM_LVL_EVENT_USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0
24385 SDL_WKUP_PSRAMECC_8K0_PSRAM8KX32E_ECC_AGGR_NUM_RAMS,
24390 SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0,
24391 SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0
24395 SDL_MLB0_MLBSS2P0_MLBDIM_WRAP_ECC_AGGR_NUM_RAMS,
24400 SDLR_ESM0_ESM_LVL_EVENT_MLB0_MLBSS_ECC_CORR_LVL_0,
24401 SDLR_ESM0_ESM_LVL_EVENT_MLB0_MLBSS_ECC_UNCORR_LVL_0
24405 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24410 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_CORR_LVL_INT_0,
24411 SDLR_ESM0_ESM_LVL_EVENT_MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0
24416 SDL_ADC12FCC0_ADC12FC_16FFC_ADC12_CORE_FIFO_RAM_ECC_AGGR_NUM_RAMS,
24421 SDLR_ESM0_ESM_LVL_EVENT_ADC12FCC0_ECC_CORRECTED_ERR_LEVEL_0,
24422 SDLR_ESM0_ESM_LVL_EVENT_ADC12FCC0_ECC_UNCORRECTED_ERR_LEVEL_0
24426 SDL_R5FSS0_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS,
24431 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_AGGR_ECC_CORRECTED_LEVEL_0,
24432 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE0_ECC_AGGR_ECC_UNCORRECTED_LEVEL_0
24436 SDL_R5FSS0_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS,
24441 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_AGGR_ECC_CORRECTED_LEVEL_0,
24442 SDLR_ESM0_ESM_LVL_EVENT_R5FSS0_CORE1_ECC_AGGR_ECC_UNCORRECTED_LEVEL_0
24446 SDL_R5FSS1_PULSAR_SL_CPU0_ECC_AGGR_NUM_RAMS,
24451 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_AGGR_ECC_CORRECTED_LEVEL_0,
24452 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE0_ECC_AGGR_ECC_UNCORRECTED_LEVEL_0
24456 SDL_R5FSS1_PULSAR_SL_CPU1_ECC_AGGR_NUM_RAMS,
24461 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_AGGR_ECC_CORRECTED_LEVEL_0,
24462 SDLR_ESM0_ESM_LVL_EVENT_R5FSS1_CORE1_ECC_AGGR_ECC_UNCORRECTED_LEVEL_0
24467 SDL_WKUP_ECC_AGGR1_AM275_DM_MCU_ECC_AGGR_NUM_RAMS,
24472 SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_CORR_LEVEL_0,
24473 SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR1_UNCORR_LEVEL_0
24477 SDL_WKUP_ECC_AGGR0_AM275_DM_DM_ECC_AGGR_NUM_RAMS,
24482 SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_CORR_LEVEL_0,
24483 SDLR_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR0_UNCORR_LEVEL_0
24487 SDL_PDMA1_SAM62_PDMA_UART_ECCAGGR_NUM_RAMS,
24492 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_SEC_PEND_0,
24493 SDLR_ESM0_ESM_LVL_EVENT_PDMA1_ECC_DED_PEND_0
24497 SDL_MSRAM_1MB5_MSRAM32KX256E_ECC_AGGR_NUM_RAMS,
24502 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB5_ECC_CORR_LEVEL_0,
24503 SDLR_ESM0_ESM_LVL_EVENT_MSRAM_1MB5_ECC_UNCORR_LEVEL_0
24508 SDL_PDMA0_SAM67_PDMA_SPI_ECCAGGR_NUM_RAMS,
24513 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_SEC_PEND_0,
24514 SDLR_ESM0_ESM_LVL_EVENT_PDMA0_ECC_DED_PEND_0
24519 SDL_IDOM1_MAIN_PLL_ECC_AGGR5_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS,
24524 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_MAIN_PLL_ECC_AGGR5_CORR_LEVEL_0,
24525 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_MAIN_PLL_ECC_AGGR5_UNCORR_LEVEL_0
24530 SDL_IDOM1_MAIN_PLL_ECC_AGGR7_IDOM1_MAIN_PLL_ECC_AGGR_NUM_RAMS,
24535 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_MAIN_PLL_ECC_AGGR7_CORR_LEVEL_0,
24536 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_MAIN_PLL_ECC_AGGR7_UNCORR_LEVEL_0
24540 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24545 SDLR_ESM0_ESM_LVL_EVENT_MCAN3_MCANSS_ECC_CORR_LVL_INT_0,
24546 SDLR_ESM0_ESM_LVL_EVENT_MCAN3_MCANSS_ECC_UNCORR_LVL_INT_0
24550 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24555 SDLR_ESM0_ESM_LVL_EVENT_MCAN2_MCANSS_ECC_CORR_LVL_INT_0,
24556 SDLR_ESM0_ESM_LVL_EVENT_MCAN2_MCANSS_ECC_UNCORR_LVL_INT_0
24560 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24565 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_CORR_LVL_INT_0,
24566 SDLR_ESM0_ESM_LVL_EVENT_MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0
24570 SDL_DMASS0_ECC_AGGR_0_NUM_RAMS,
24575 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0,
24576 SDLR_ESM0_ESM_LVL_EVENT_DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0
24580 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
24585 SDLR_ESM0_ESM_LVL_EVENT_MCAN4_MCANSS_ECC_CORR_LVL_INT_0,
24586 SDLR_ESM0_ESM_LVL_EVENT_MCAN4_MCANSS_ECC_UNCORR_LVL_INT_0
24590 SDL_IDOM1_PULSAR_PLL_ECC_AGGR9_NUM_RAMS,
24595 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_PULSAR_PLL_ECC_AGGR9_CORR_LEVEL_0,
24596 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_PULSAR_PLL_ECC_AGGR9_UNCORR_LEVEL_0
24600 SDL_IDOM1_PULSAR_PLL_ECC_AGGR11_NUM_RAMS,
24605 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_PULSAR_PLL_ECC_AGGR11_CORR_LEVEL_0,
24606 SDLR_ESM0_ESM_LVL_EVENT_IDOM1_PULSAR_PLL_ECC_AGGR11_UNCORR_LEVEL_0
24610 SDL_WKUP_ECC_AGGR2_AM275_WKUP_SAFE_ECC_AGGR_NUM_RAMS,
24615 SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_CORR_LEVEL_0,
24616 SDLR_WKUP_ESM0_ESM_LVL_EVENT_WKUP_ECC_AGGR2_UNCORR_LEVEL_0
24620 SDL_WKUP_PSRAM2KX32E0_PSRAM2KX32E_ECC_AGGR_NUM_RAMS,
24625 SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAM2KX32E0_ECC_CORR_LEVEL_0,
24626 SDLR_ESM0_ESM_LVL_EVENT_WKUP_PSRAM2KX32E0_ECC_UNCORR_LEVEL_0
24630 SDL_ECC_AGGR2_AM275_MAIN_SYS_IP_ECC_AGGR_NUM_RAMS,
24635 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR2_CORR_LEVEL_0,
24636 SDLR_ESM0_ESM_LVL_EVENT_ECC_AGGR2_UNCORR_LEVEL_0