Files | |
file | sciclient_fmwMsgParams.h |
This file contains the definition of all the parameter IDs for PM, RM, Security. | |
Macros | |
#define | TISCI_PARAM_UNDEF (0xFFFFFFFFU) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu) |
#define | TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu) |
#define | TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu) |
#define | TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu) |
#define | TISCI_ISC_CC_ID (160U) |
Special ISC ID to refer to compute cluster privid registers. More... | |
#define | SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U) |
#define | SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U) |
#define | SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1 |
#define | SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF |
Sciclient Firmware ABI revisions | |
ABI revisions for compatibility check. | |
#define | SCICLIENT_FIRMWARE_ABI_MAJOR (4U) |
#define | SCICLIENT_FIRMWARE_ABI_MINOR (1U) |
Sciclient Context Ids | |
Context IDs for Sciclient_ConfigPrms_t . | |
#define | SCICLIENT_CONTEXT_WKUP_R5_SEC_0 (0U) |
#define | SCICLIENT_CONTEXT_WKUP_R5_NONSEC_0 (1U) |
#define | SCICLIENT_CONTEXT_MAIN_0_R5_0_SEC_0 (2U) |
#define | SCICLIENT_CONTEXT_MAIN_0_R5_0_NONSEC_0 (3U) |
#define | SCICLIENT_CONTEXT_MAIN_0_R5_1_SEC_0 (4U) |
#define | SCICLIENT_CONTEXT_MAIN_0_R5_1_NONSEC_0 (5U) |
#define | SCICLIENT_CONTEXT_MAIN_1_R5_0_SEC_0 (6U) |
#define | SCICLIENT_CONTEXT_MAIN_1_R5_1_NONSEC_0 (7U) |
#define | SCICLIENT_CONTEXT_MAIN_1_R5_1_SEC_0 (8U) |
#define | SCICLIENT_CONTEXT_MAIN_1_R5_0_NONSEC_0 (9U) |
#define | SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U) |
#define | SCICLIENT_CONTEXT_C7X_NONSEC_1 (11U) |
#define | SCICLIENT_CONTEXT_MAX_NUM (12U) |
Sciclient Processor Ids | |
Processor IDs for the Processor Boot Configuration APIs. | |
#define | PROC_ID_C7X256V0_C7XV_CORE_0 (0x03U) |
#define | PROC_ID_C7X256V1_C7XV_CORE_0 (0x04U) |
#define | PROC_ID_R5FSS0_CORE0 (0x06U) |
#define | PROC_ID_R5FSS0_CORE1 (0x07U) |
#define | PROC_ID_R5FSS1_CORE0 (0x08U) |
#define | PROC_ID_R5FSS1_CORE1 (0x09U) |
#define | PROC_ID_WKUP_R5FSS0_CORE0 (0x01U) |
#define | SOC_NUM_PROCESSORS (0x07U) |
IRQ source index start | |
Start offset of IRQ source index. | |
#define | TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U) |
#define | TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U) |
#define | TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U) |
#define | TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U) |
#define | TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U) |
#define | TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U) |
#define | TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U) |
#define | TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U) |
#define | TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U) |
#define | TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U) |
#define | TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U) |
#define | TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U) |
#define | TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U) |
#define | TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U) |
#define | TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U) |
Boot/DM R5 IDs | |
Boot Device CPU IDs. | |
#define | SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0) |
#define | SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0) |
Boot/DM Pulsar Processor IDs | |
Boot Device Processor IDs. | |
#define | SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (PROC_ID_WKUP_R5FSS0_CORE0) |
#define | SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (PROC_ID_WKUP_R5FSS0_CORE0) |
#define TISCI_PARAM_UNDEF (0xFFFFFFFFU) |
Undefined Param Undefined
#define SCICLIENT_FIRMWARE_ABI_MAJOR (4U) |
#define SCICLIENT_FIRMWARE_ABI_MINOR (1U) |
#define SCICLIENT_CONTEXT_WKUP_R5_SEC_0 (0U) |
WKUP_0_R5_0(Secure): Cortex WKUP R5 Context 0
#define SCICLIENT_CONTEXT_WKUP_R5_NONSEC_0 (1U) |
WKUP_0_R5_1(Non-Secure): Cortex WKUP R5 Context 1
#define SCICLIENT_CONTEXT_MAIN_0_R5_0_SEC_0 (2U) |
MAIN_0_R5_0(Secure): Cortex R5_0_core_0 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_0_R5_0_NONSEC_0 (3U) |
MAIN_0_R5_1(Non Secure): Cortex R5_0_core_0 context 1 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_0_R5_1_SEC_0 (4U) |
MAIN_0_R5_2(Secure): Cortex R5_0_core_1 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_0_R5_1_NONSEC_0 (5U) |
MAIN_0_R5_3(Non Secure): Cortex R5_0_core_1 context 1 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_1_R5_0_SEC_0 (6U) |
MAIN_1_R5_0(Secure): Cortex R5_1_core_0 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_1_R5_1_NONSEC_0 (7U) |
MAIN_1_R5_1(Non Secure): Cortex R5_1_core_0 context 1 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_1_R5_1_SEC_0 (8U) |
MAIN_1_R5_2(Secure): Cortex R5_1_core_1 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_MAIN_1_R5_0_NONSEC_0 (9U) |
MAIN_1_R5_3(Non Secure): Cortex R5_1_core_1 context 1 on MAIN domain
#define SCICLIENT_CONTEXT_C7X_NONSEC_0 (10U) |
C7X_0_0(Non Secure): C7x_0 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_C7X_NONSEC_1 (11U) |
C7X_1_0(Non Secure): C7x_1 context 0 on MAIN domain
#define SCICLIENT_CONTEXT_MAX_NUM (12U) |
Total number of possible contexts for application.
#define PROC_ID_C7X256V0_C7XV_CORE_0 (0x03U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 13 Processor 0)
#define PROC_ID_C7X256V1_C7XV_CORE_0 (0x04U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 14 Processor 0)
#define PROC_ID_R5FSS0_CORE0 (0x06U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 0)
#define PROC_ID_R5FSS0_CORE1 (0x07U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 0 Processor 1)
#define PROC_ID_R5FSS1_CORE0 (0x08U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 0)
#define PROC_ID_R5FSS1_CORE1 (0x09U) |
AM275_MAIN_SEC_MMR_MAIN_0: (Cluster 1 Processor 1)
#define PROC_ID_WKUP_R5FSS0_CORE0 (0x01U) |
AM275_WKUP_SEC_MMR_WKUP_0: (Cluster 28 Processor 0)
#define SOC_NUM_PROCESSORS (0x07U) |
Total Number of processors in AM275X
#define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu) |
-----------------— Resource Management Parameters ------------------—
#define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu) |
#define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu) |
#define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu) |
#define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu) |
The ring mode field of the RING_SIZE register is not modified if this value is used for: tisci_msg_rm_ring_cfg_req::mode
#define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu) |
#define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu) |
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu) |
#define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu) |
#define TISCI_ISC_CC_ID (160U) |
Special ISC ID to refer to compute cluster privid registers.
#define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U) |
#define TISCI_PKTDMA0_TX_EOES_IRQ_SRC_IDX_START (4096U) |
#define TISCI_PKTDMA0_TX_FLOW_OES_IRQ_SRC_IDX_START (4608U) |
#define TISCI_PKTDMA0_RX_EOES_IRQ_SRC_IDX_START (5120U) |
#define TISCI_PKTDMA0_RX_FLOW_OES_IRQ_SRC_IDX_START (5632U) |
#define TISCI_PKTDMA0_RX_FLOW_SOES_IRQ_SRC_IDX_START (6144U) |
#define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (8192U) |
#define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (8704U) |
#define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (9216U) |
#define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (9728U) |
#define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (10240U) |
#define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (10752U) |
#define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (11264U) |
#define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (11776U) |
#define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (12288U) |
#define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U) |
#define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U) |
#define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_WKUP_R5FSS0_CORE0) |
#define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_WKUP_R5FSS0_CORE0) |
#define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID (PROC_ID_WKUP_R5FSS0_CORE0) |
#define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID (PROC_ID_WKUP_R5FSS0_CORE0) |
#define SCICLIENT_ALLOWED_BOARDCFG_BASE_START 1 |
Board config Base start address
#define SCICLIENT_ALLOWED_BOARDCFG_BASE_END 0xFFFFFFFF |
Board config Base end address