AM64x MCU+ SDK  07.03.00
tiescbsp.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef TIESC_BSP_H_
34 #define TIESC_BSP_H_
35 
95 /* ========================================================================== */
96 /* Include Files */
97 /* ========================================================================== */
98 
99 #ifndef DISABLE_UART_PRINT
100 #include <stdio.h>
101 #endif
102 
103 #include <networking/ethercat_slave/icss_fwhal/tiesc_pruss_intc_mapping.h>
104 #include <drivers/pruicss.h>
105 #include <networking/ethercat_slave/icss_fwhal/tiesc_def.h>
106 
107 #ifdef __cplusplus
108 extern "C" {
109 #endif
110 
111 /* ========================================================================== */
112 /* Macros & Typedefs */
113 /* ========================================================================== */
114 
115 /*Single datagram accessing contiguous multiple FMMU mapped areas in a single slave for process data
116 is supported now by TI ESC firmware.
117 Process path latency in TI ESC is high when this support is active
118 For specific use cases (4SM with 3 FMMUs or multiple FMMUs (in a given ESC) are not accessed in a single datagram)
119 process path latency improvement can be achieved by disabling below define */
120 #define ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM 0
121 
122 #define MAX_SYNC_MAN 8
123 #define SIZEOF_SM_REGISTER 8
124 
125 #define TIESC_EEPROM_SIZE 0x800
126 
127 #define MAILBOX_WRITE 0
128 #define MAILBOX_READ 1
129 #define PROCESS_DATA_OUT 2
130 #define PROCESS_DATA_IN 3
131 
132 #define MBX_WRITE_EVENT ((uint16_t) 0x0100)
133 #define MBX_READ_EVENT ((uint16_t) 0x0200)
134 
135 //Below constants are not defined in esc.h
136 #define ESC_ADDR_REV_TYPE 0x000
137 #define ESC_ADDR_BUILD 0x002
138 
139 #define ESC_ADDR_CONFIG_STATION_ALIAS 0x012
140 #define ESC_ADDR_DLSTATUS 0x110
141 #define ESC_ADDR_ALCONTROL 0x120
142 #define ESC_ADDR_ALSTATUS 0x130
143 #define ESC_ADDR_PDI_CONTROL 0x140
144 #define ESC_PDI_CONTROL_ELD_ALL_PORTS_MASK (1 << 1)
145 #define ESC_ADDR_PDI_CONFIG 0x150
146 #define ESC_ADDR_AL_EVENT_MASK 0x204
147 #define ESC_ADDR_AL_EVENT_REQ 0x220
148 #define ESC_ADDR_SM_WD_STATUS 0x440
149 #define ESC_ADDR_EEPROM_CTRL 0x502
150 #define ESC_ADDR_MI_ECAT_ACCESS 0x516
151 #define ESC_ADDR_MI_PDI_ACCESS 0x517
152 
153 #define ESC_EEPROM_CMD_MASK 0x0700 //Description (0x502.8:10): Command bit mask
154 #define ESC_EEPROM_CMD_READ_MASK 0x0100 //Description (0x502.8): Currently executed read command
155 #define ESC_EEPROM_CMD_WRITE_MASK 0x0200 //Description (0x502.9): Initialize Write Command
156 #define ESC_EEPROM_CMD_RELOAD_MASK 0x0400 //Description (0x502.10): Trigger EEPROM reload
157 #define ESC_EEPROM_ERROR_MASK 0x7800 //Description : Mask all EEPROM error bits; Checksum error (0x0502.11); EEPROM not loaded (0x0502.12); Missing EEPROM Acknowledge (0x0502.13); Write Error (0x0502.14)
158 #define ESC_EEPROM_ERROR_CRC 0x0800 //Description (0x502.11): EEPROM CRC Error
159 #define ESC_EEPROM_ERROR_CMD_ACK 0x2000 //Description (0x502.13): EEPROM Busy
160 #define ESC_EEPROM_BUSY_MASK 0x8000 //Description (0x502.15): EEPROM Busy
161 
162 #define ESC_ADDR_SYNCMAN 0x800
163 
164 #define ESC_ADDR_SM1_STATUS 0x80D
165 #define SM_STATUS_MBX_FULL 0x08
166 
167 #define ESC_ADDR_SM0_STATUS 0x805
168 #define ESC_ADDR_SM0_ACTIVATE 0x806
169 #define ESC_ADDR_SM1_ACTIVATE 0x806+8
170 #define ESC_ADDR_SM2_ACTIVATE 0x806+8*2
171 #define ESC_ADDR_SM3_ACTIVATE 0x806+8*3
172 #define ESC_ADDR_SM4_ACTIVATE 0x806+8*4
173 #define ESC_ADDR_SM5_ACTIVATE 0x806+8*5
174 #define ESC_ADDR_SM6_ACTIVATE 0x806+8*6
175 #define ESC_ADDR_SM7_ACTIVATE 0x806+8*7
176 #define ESC_ADDR_SM0_PDI_CONTROL 0x807
177 #define ESC_ADDR_SM1_PDI_CONTROL 0x807+8
178 #define ESC_ADDR_SM2_PDI_CONTROL 0x807+8*2
179 #define ESC_ADDR_SM3_PDI_CONTROL 0x807+8*3
180 #define ESC_ADDR_SM4_PDI_CONTROL 0x807+8*4
181 #define ESC_ADDR_SM5_PDI_CONTROL 0x807+8*5
182 #define ESC_ADDR_SM6_PDI_CONTROL 0x807+8*6
183 #define ESC_ADDR_SM7_PDI_CONTROL 0x807+8*7
184 
185 #define SM_PDI_CONTROL_SM_DISABLE 1
186 
187 #define ESC_ADDR_SYSTIME 0x910
188 #define ESC_ADDR_SYSTIME_HIGH 0x914
189 #define ESC_ADDR_SYSTIME_OFFSET 0x920
190 #define ESC_ADDR_SYSTIME_DELAY 0x928
191 #define ESC_ADDR_SPEEDCOUNTER_START 0x930
192 #define ESC_ADDR_TIMEDIFF_FILTDEPTH 0x934
193 #define ESC_ADDR_SPEEDDIFF_FILTDEPTH 0x935
194 #define ESC_ADDR_SYNC_PULSE_LENGTH 0x982
195 #define ESC_ADDR_SYNC_STATUS 0x98E
196 #define ESC_ADDR_LATCH0_CONTROL 0x9A8
197 #define ESC_ADDR_LATCH1_CONTROL 0x9A9
198 #define ESC_ADDR_LATCH0_POS_EDGE 0x9B0
199 #define ESC_ADDR_LATCH0_NEG_EDGE 0x9B8
200 #define ESC_ADDR_LATCH1_POS_EDGE 0x9C0
201 #define ESC_ADDR_LATCH1_NEG_EDGE 0x9C8
202 #define ESC_ADDR_TI_PORT0_ACTIVITY 0xE00
203 #define ESC_ADDR_TI_PORT1_ACTIVITY 0xE04
204 #define ESC_ADDR_TI_PORT0_PHYADDR 0xE08
205 #define ESC_ADDR_TI_PORT1_PHYADDR 0xE09
206 #define ESC_ADDR_TI_PDI_ISR_PINSEL 0xE0A
207 #define ESC_ADDR_TI_PHY_LINK_POLARITY 0XE0C
208 #define ESC_ADDR_TI_PORT0_TX_START_DELAY 0xE10
209 #define ESC_ADDR_TI_PORT1_TX_START_DELAY 0xE12
210 #define ESC_ADDR_TI_ESC_RESET 0xE14
211 #define ESC_ADDR_TI_EDMA_LATENCY_ENHANCEMENT 0xE24
212 #define TI_ESC_RST_CMD_U 0x545352
213 #define TI_ESC_RST_CMD_L 0x747372
214 
215 #define ESC_ADDR_MEMORY 0x1000
216 
217 #define CMD_DL_USER_CLEAR_AL_EVENT_HIGH 0x0
218 #define CMD_DL_USER_GET_BUFFER_READ_ADDR 0x1
219 #define CMD_DL_USER_GET_BUFFER_WRITE_ADDR 0x2
220 #define CMD_DL_USER_SET_BUFFER_WRITE_DONE 0x3
221 
225 #define CMD_DL_USER_ACK_MBX_READ 0x4
226 
230 #define CMD_DL_USER_ACK_MBX_WRITE 0x5
231 
235 #define CMD_DL_USER_EEPROM_CMD_ACK 0x6
236 
240 #define CMD_DL_USER_READ_SYNC_STATUS 0x7
241 #define SYNC0 0
242 #define SYNC1 1
243 
247 #define CMD_DL_USER_READ_AL_CONTROL 0x8
248 
252 #define CMD_DL_USER_WRITE_AL_STATUS 0x9
253 
257 #define CMD_DL_USER_READ_PD_WD_STATUS 0xA
258 
262 #define CMD_DL_USER_READ_SM_ACTIVATE 0xB
263 
267 #define CMD_DL_USER_WRITE_SM_PDI_CTRL 0xC
268 
272 #define CMD_DL_USER_READ_LATCH_TIME 0xD
273 #define LATCH0_POS_EDGE 0
274 #define LATCH0_NEG_EDGE 1
275 #define LATCH1_POS_EDGE 2
276 #define LATCH1_NEG_EDGE 3
277 
282 #define CMD_DL_USER_READ_SYS_TIME 0xE
283 
287 #define CMD_DL_USER_CLEAR_AL_EVENT_LOW 0xF
288 #ifdef SYSTEM_TIME_PDI_CONTROLLED
289 
293 #define CMD_DL_USER_SYSTIME_PDI_CONTROL 0x10
294 #define WRITE_SYSTIME 0
295 #define WRITE_SYSTIME_OFFSET 1
296 #define WRITE_FILTER_CONFIG 2
297 #endif
298 
299 
302 #define SPI_APPL_BIN_OFFSET 0x20000 /* Verify from Starterware Bootloader */
303 
304 #define QSPI_APPL_BIN_OFFSET 0x80000 /* Verify from Starterware Bootloader */
305 
306 /*SPI Flash offset at which application binary downloaded over FOE will be stored*/
307 #define FOE_APPL_BIN_OFFSET (QSPI_APPL_BIN_OFFSET)
308 #define FOE_FLASH_SECTOR_SIZE (0xFFFF)
309 
310 #define SWAPWORD
311 #define SWAPDWORD
312 
313 
314 #define ICSS_MDIO_USRPHYSEL_LINKINT_ENABLE 0x40
315 #define ICSS_MDIO_USRPHYSEL_LINKSTAT_MLINK 0x80
316 
317 #define TIESC_PERM_RW 0x0
318 #define TIESC_PERM_WRITE_ONLY 0x1
319 #define TIESC_PERM_READ_ONLY 0x2
320 
321 #define TIESC_PERM_WRITE TIESC_PERM_WRITE_ONLY
322 #define TIESC_PERM_READ TIESC_PERM_READ_ONLY
323 
324 #define PDI_PERM_RW 0x0
325 #define PDI_PERM_READ_ONLY 0x1
326 
327 #define PDI_PERM_WRITE PDI_PERM_RW
328 #define PDI_PERM_READ PDI_PERM_READ_ONLY
329 
330 #define TIESC_MDIO_CLKDIV 79 //For 2.5MHz MDIO clock: 200/(TIESC_MDIO_CLKDIV+1)
331 
332 #define TIESC_MDIO_RX_LINK_DISABLE 0 //Slow MDIO state m/c based link detection
333 #define TIESC_MDIO_RX_LINK_ENABLE 1 //Fast link detect using RXLINK forward from PHY to MDIO MLINK
334 #define TIESC_LINK_POL_ACTIVE_LOW 1
335 #define TIESC_LINK_POL_ACTIVE_HIGH 0
336 
341 #define PDI_WD_TRIGGER_RX_SOF (0 << 4)
342 
347 #define PDI_WD_TRIGGER_LATCH_IN (1 << 4)
348 
353 #define PDI_WD_TRIGGER_SYNC0_OUT (2 << 4)
354 
359 #define PDI_WD_TRIGGER_SYNC1_OUT (3 << 4)
360 
361 #if ENABLE_MULTIPLE_SM_ACCESS_IN_SINGLE_DATAGRAM
362 #define TIESC_PORT0_TX_DELAY 0x98
363 #else
364 #define TIESC_PORT0_TX_DELAY 0x48
365 #endif
366 #define TIESC_PORT1_TX_DELAY TIESC_PORT0_TX_DELAY
367 
368 #define PDI_ISR_EDIO_NUM 7 //GPMC_CSN(2) -> pr1_edio_data_out7 for ICEv2.J4.Pin21
369 
370 /* PDI side register protection using register permission table (4KB) in memory - disable if you care for performance and memory foot print */
371 /* #define ENABLE_PDI_REG_PERMISSIONS */
372 
373 /* Use ESC system time instead of SYS/BIOS Timestamp_get32 for timing info */
374 #define USE_ECAT_TIMER
375 
376 #if !defined(_JAILHOUSE_INMATE)
377 /*TODO: Enable this after flash APIs are available*/
378 //#define ENABLE_ONLINE_FIRMWARE_UPGRADE
379 #endif
380 
381 /* Uncomment following to enable DC feature of system time compensation via PDI interface instead of ECAT interface
382  for synchronizing two independent EtherCAT networks */
383 //#define SYSTEM_TIME_PDI_CONTROLLED
384 /*Comment to following to enable PDI ISR and SYNC ISR in HWI context */
385 #define ENABLE_PDI_TASK
386 #define ENABLE_SYNC_TASK
387 
394 /* #define SUPPORT_CMDACK_POLL_MODE */
395 
396 #if defined (__aarch64__)
397 #define ASSERT_DMB() __asm__(" dmb ISH")
398 #define ASSERT_DSB() __asm__(" dsb ISH")
399 #else
400 #define ASSERT_DMB() __asm__(" dmb")
401 #define ASSERT_DSB() __asm__(" dsb")
402 #endif
403 
404 #ifdef USE_ECAT_TIMER
405 #define ECAT_TIMER_INC_P_MS 1000000
406 #else
407 #define ECAT_TIMER_INC_P_MS ecat_timer_inc_p_ms /* ARM frequency: Will be detected during bsp_init*/
408 extern volatile uint32_t ecat_timer_inc_p_ms;
409 #endif
410 
411 #define ESC_SYSTEMTIME_OFFSET_OFFSET 0x0920
412 #define ESC_SPEED_COUNTER_START_OFFSET 0x0930
413 #define ESC_DC_START_TIME_CYCLIC_OFFSET 0x0990
414 
415 #define DRIFTCTRL_TASK_SYNC_ZERO_CROSS_ADJUST 0xE0 //PRU_DMEM0
416 
421 #define LOCK_PD_BUF_AVAILABLE_FOR_HOST 0
422 
426 #define LOCK_PD_BUF_HOST_ACCESS_START 1
427 
431 #define LOCK_PD_BUF_HOST_ACCESS_FINISH 2
432 
433 typedef void (*bsp_function_handler)(void);
434 
435 typedef int32_t (*bsp_eeprom_read_t)(uint8_t *buf, uint32_t len);
436 typedef int32_t (*bsp_eeprom_write_t)(uint8_t *buf, uint32_t len);
437 typedef void (*bsp_init_spinlock_t)(void);
438 typedef uint32_t (*bsp_hwspinlock_lock_t)(int num);
439 typedef void (*bsp_hwspinlock_unlock_t)(int num);
440 typedef void (*bsp_ethphy_init_t)(PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable);
441 typedef int8_t (*bsp_get_phy_address_t)(uint8_t instance, uint8_t portNumber);
442 
443 /* ========================================================================== */
444 /* Structure Declarations */
445 /* ========================================================================== */
446 
450 typedef struct bsp_params_s
451 {
471  uint32_t link0_polarity;
473  uint32_t link1_polarity;
475  uint32_t phy0_address;
477  uint32_t phy1_address;
479  const unsigned char *default_tiesc_eeprom;
484 } bsp_params;
485 
487 
491 typedef struct
492 {
493  uint8_t sm_buf_index;
494  uint8_t lock_state;
495  uint16_t addr;
497 
502 typedef struct
503 {
504  uint8_t reserved1[0x90];
505  uint32_t system_time_low;
506  uint32_t system_time_high;
508  uint8_t reserved2[7];
509  uint16_t cmdlow;
510  uint16_t cmdlow_ack;
511  uint16_t param1low;
512  uint16_t param2low;
513  uint16_t resp1low;
514  uint16_t resp2low;
515 #ifndef SYSTEM_TIME_PDI_CONTROLLED
516  uint8_t reserved3[212];
517 #else
518  uint8_t reserved3[24];
519  uint32_t systime_offset_low;
520  uint32_t systime_offset_high;
521  uint8_t reserved4[180];
522 #endif
523  t_sm_processdata sm_processdata[6];
525 
529 typedef struct
530 {
531  uint8_t reserved[1024];
532  uint8_t reg_properties[4096];
534 
535 typedef struct
536 {
538  uint16_t length;
540 
544 typedef struct
545 {
546  uint16_t clkdiv;
547  uint8_t addr0;
548  uint8_t addr1;
549  uint8_t link0pol; /* LINK_MII signal polarity of PHY hooked to PRU-ICSS MII0. 1: Active lLow 0: Active High */
550  uint8_t link1pol; /* LINK_MII signal polarity of PHY hooked to PRU-ICSS MII1. 1: Active lLow 0: Active High */
552 } t_mdio_params;
553 
554 /* ========================================================================== */
555 /* Function Declarations */
556 /* ========================================================================== */
557 
567 void bsp_params_init(bsp_params *init_params);
568 
584 extern int32_t bsp_init(bsp_params *init_params);
585 
613  pruIcssHandle); //Internal API - invoked by bsp_init
614 
622 extern void bsp_start_esc_isr(PRUICSS_Handle pruIcssHandle);
623 
634 extern void bsp_exit(PRUICSS_Handle pruIcssHandle);
635 
650 extern void bsp_set_pdi_wd_trigger_mode(PRUICSS_Handle pruIcssHandle,
651  uint32_t mode);
694  uint32_t command, uint16_t param1, uint16_t param2);
709 extern void bsp_eeprom_emulation_init(void);
710 
720 extern int32_t bsp_eeprom_load_esc_registers(PRUICSS_Handle pruIcssHandle,
721  int32_t reload_flag);
722 
731 extern int32_t bsp_eeprom_emulation_reload(PRUICSS_Handle pruIcssHandle);
732 
740 
746 extern void bsp_eeprom_emulation_flush(void);
747 
753 extern void bsp_eeprom_emulation_exit(void);
754 
761 extern uint8_t *bsp_get_eeprom_cache_base(void);
762 
768 
776 
784 extern void bsp_set_eeprom_update_status(uint8_t status);
785 
793 extern uint8_t bsp_get_eeprom_update_status(void);
794 
813 extern void bsp_set_sm_properties(PRUICSS_Handle pruIcssHandle, uint8_t sm,
814  uint16_t address, uint16_t len);
826 
827 extern int16_t bsp_get_sm_index(uint16_t address, uint16_t len);
843 extern uint8_t bsp_pdi_sm_config_ongoing(PRUICSS_Handle pruIcssHandle);
856 extern void bsp_pdi_mbx_read_start(PRUICSS_Handle pruIcssHandle);
857 
863 extern void bsp_pdi_mbx_read_complete(PRUICSS_Handle pruIcssHandle);
864 
871 extern void bsp_pdi_mbx_write_start(PRUICSS_Handle pruIcssHandle);
872 
879 extern void bsp_pdi_mbx_write_complete(PRUICSS_Handle pruIcssHandle);
880 
899 extern uint16_t bsp_get_process_data_address(PRUICSS_Handle pruIcssHandle,
900  uint16_t address, uint16_t len, int16_t *p_sm_index);
901 
914  uint16_t address, uint16_t len, int16_t sm_index);
915 
932 extern uint8_t bsp_read_byte(PRUICSS_Handle pruIcssHandle, uint16_t address);
933 
944 extern uint16_t bsp_read_word(PRUICSS_Handle pruIcssHandle, uint16_t address);
945 
956 extern uint32_t bsp_read_dword(PRUICSS_Handle pruIcssHandle, uint16_t address);
957 
967 extern void bsp_read(PRUICSS_Handle pruIcssHandle, uint8_t *pdata,
968  uint16_t address,
969  uint16_t len);
970 
980 extern uint8_t bsp_read_byte_isr(PRUICSS_Handle pruIcssHandle, uint16_t address);
981 
991 extern uint16_t bsp_read_word_isr(PRUICSS_Handle pruIcssHandle,
992  uint16_t address);
993 
1003 extern uint32_t bsp_read_dword_isr(PRUICSS_Handle pruIcssHandle,
1004  uint16_t address);
1005 
1023  uint16_t address, uint16_t length);
1038 extern void bsp_pdi_write_indication(PRUICSS_Handle pruIcssHandle,
1039  uint16_t address, uint16_t length,
1040  uint16_t value);
1049 extern void bsp_write_byte(PRUICSS_Handle pruIcssHandle, uint8_t val,
1050  uint16_t address);
1051 
1060 extern void bsp_write_word(PRUICSS_Handle pruIcssHandle, uint16_t val,
1061  uint16_t address);
1062 
1071 extern void bsp_write_dword(PRUICSS_Handle pruIcssHandle, uint32_t val,
1072  uint16_t address);
1073 
1083 extern void bsp_write(PRUICSS_Handle pruIcssHandle, uint8_t *pdata,
1084  uint16_t address, uint16_t len);
1085 
1094 extern uint32_t bsp_pruss_mdioreg_read(PRUICSS_Handle pruIcssHandle,
1095  uint32_t regoffset);
1096 
1105 extern void bsp_pruss_mdioreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val,
1106  uint32_t regoffset);
1107 
1116 extern uint32_t bsp_pruss_iepreg_read(PRUICSS_Handle pruIcssHandle,
1117  uint32_t regoffset);
1118 
1127 extern void bsp_pruss_iepreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val,
1128  uint32_t regoffset);
1129 
1137 extern void bsp_pruss_cmd_intfc_write_word(uint16_t val, volatile uint16_t *ptr);
1138 
1146 extern uint16_t bsp_pruss_cmd_intfc_read_word(volatile uint16_t *ptr);
1147 
1157 extern uint8_t bsp_get_pdi_access_perm(uint16_t address, uint8_t access);
1158 
1168 extern uint8_t bsp_pdi_access_perm_word(uint16_t address, uint8_t access);
1169 
1179 extern uint8_t bsp_pdi_access_perm_dword(uint16_t address, uint8_t access);
1180 
1191 extern uint8_t bsp_pdi_access_perm_array(uint16_t address, uint8_t access,
1192  uint16_t size);
1193 
1201 extern void bsp_set_pdi_perm_read_only(uint16_t *perm_array, uint16_t address);
1202 
1210 extern void bsp_set_pdi_perm_read_write(uint16_t *perm_array, uint16_t address);
1211 
1222 extern uint8_t bsp_is_pdi_perm_read_only(uint16_t *perm_array, uint16_t address);
1223 
1231 
1239 
1257 extern int16_t bsp_pruss_mdio_init(PRUICSS_Handle pruIcssHandle,
1258  t_mdio_params *pmdio_params);
1259 
1270 extern int16_t bsp_pruss_mdio_phy_read(PRUICSS_Handle pruIcssHandle,
1271  uint8_t phyaddr, uint8_t regoffset, uint16_t *regval);
1272 
1283 extern int16_t bsp_pruss_mdio_phy_write(PRUICSS_Handle pruIcssHandle,
1284  uint8_t phyaddr, uint8_t regoffset, uint16_t regval);
1285 
1296 extern uint32_t bsp_pruss_mdio_phy_link_state(PRUICSS_Handle pruIcssHandle,
1297  uint8_t phyaddr);
1311 
1318 extern void bsp_set_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num);
1319 
1326 extern void bsp_clear_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num);
1327 
1337 extern void bsp_hwspinlock_init(void);
1338 
1345 extern uint32_t bsp_hwspinlock_lock(int num);
1346 
1352 extern void bsp_hwspinlock_unlock(int num);
1353 
1360 #ifdef SYSTEM_TIME_PDI_CONTROLLED
1361 
1368 extern void bsp_pdi_latch0_control(PRUICSS_Handle pruIcssHandle, uint8_t val);
1369 
1377 extern void bsp_pdi_latch1_control(PRUICSS_Handle pruIcssHandle, uint8_t val);
1378 
1385 extern void bsp_pdi_write_system_time(PRUICSS_Handle pruIcssHandle,
1386  uint32_t systime);
1393 extern void bsp_pdi_write_system_timeoffset(PRUICSS_Handle pruIcssHandle,
1394  unsigned long long systime);
1401 extern void bsp_pdi_write_systime_delay(PRUICSS_Handle pruIcssHandle,
1402  uint32_t systime);
1411 extern void bsp_pdi_write_filterconfig(PRUICSS_Handle pruIcssHandle,
1412  uint16_t speedcount_start,
1413  uint8_t speedcount_filtdepth, uint8_t systime_filtdepth);
1414 #endif
1415 
1427 extern uint32_t bsp_get_timer_register(void);
1428 
1433 extern void bsp_clear_timer_register(void);
1440 extern void bsp_get_local_sys_time(uint32_t *systime_low,
1441  uint32_t *systime_high);
1442 
1451  uint32_t *systime_low, uint32_t *systime_high);
1452 
1461  uint32_t *systime_low, uint32_t *systime_high);
1462 
1471  uint32_t *systime_low, uint32_t *systime_high);
1472 
1481  uint32_t *systime_low, uint32_t *systime_high);
1482 
1494 extern void bsp_global_mutex_lock(void);
1495 
1500 extern void bsp_global_mutex_unlock(void);
1510 void Sync0Isr(void *args);
1514 void Sync1Isr(void *args);
1518 void EcatIsr(void *args);
1519 
1520 #ifndef SUPPORT_CMDACK_POLL_MODE
1521 
1524 void EscCmdLowAckIsr(void *args);
1525 #endif
1526 
1543 extern void bsp_set_pru_firmware(uint32_t *frameProc, uint32_t frameProcLen,
1544  uint32_t *hostProc, uint32_t hostProcLen);
1551 #ifdef ENABLE_ONLINE_FIRMWARE_UPGRADE
1552 
1558 extern void bsp_start_fw_download(uint32_t password);
1567 extern void bsp_store_fw_data(uint16_t *pData, uint16_t Size);
1574 extern void bsp_boot_2_init_handler(void);
1575 #endif
1576 
1582 #ifdef __cplusplus
1583 }
1584 #endif
1585 
1586 #endif/*TIESC_BSP_H_ */
bsp_set_eeprom_update_status
void bsp_set_eeprom_update_status(uint8_t status)
Indicate to FWHAL whether EEPROM is written for flushing to non-volatile storage. Typically called on...
bsp_params::phy1_address
uint32_t phy1_address
Definition: tiescbsp.h:477
t_sm_processdata::sm_buf_index
uint8_t sm_buf_index
Definition: tiescbsp.h:493
bsp_get_pdi_read_access_fail_cnt
uint32_t bsp_get_pdi_read_access_fail_cnt()
Returns the count of PDI read access failures.
bsp_hwspinlock_lock
uint32_t bsp_hwspinlock_lock(int num)
Acquire selected spinlock instance.
t_host_interface::resp2low
uint16_t resp2low
Definition: tiescbsp.h:514
bsp_pdi_post_read_indication
void bsp_pdi_post_read_indication(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t length)
Invoked after reading a register or mailbox buffer from PDI side .
EscCmdLowAckIsr
void EscCmdLowAckIsr(void *args)
ESC CMD Low ACK IRQ Handler.
bsp_eeprom_emulation_exit
void bsp_eeprom_emulation_exit(void)
Call EEPROM flush on exit.
bsp_init_spinlock_t
void(* bsp_init_spinlock_t)(void)
Definition: tiescbsp.h:437
size
uint16_t size
Definition: tisci_boardcfg.h:1
bsp_get_latch0_posedge_time
void bsp_get_latch0_posedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 posedge timestamp for application use(nanosec resolution)
bsp_pdi_mbx_write_start
void bsp_pdi_mbx_write_start(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side write to read mailbox has started.
bsp_global_mutex_lock
void bsp_global_mutex_lock(void)
Critical section enter API using semaphore/mutex/interrupt disable primitives from RTOS....
bsp_pdi_access_perm_dword
uint8_t bsp_pdi_access_perm_dword(uint16_t address, uint8_t access)
Checks if the PDI register [Four bytes] has the requested access permission and returns the result.
bsp_params::eeprom_pointer_for_stack
uint8_t ** eeprom_pointer_for_stack
Definition: tiescbsp.h:481
t_host_interface::system_time_low
uint32_t system_time_low
Definition: tiescbsp.h:505
t_host_interface::cmdlow_ack
uint16_t cmdlow_ack
Definition: tiescbsp.h:510
t_sm_processdata
Struct for host to PRU-ICSS command interface.
Definition: tiescbsp.h:492
t_mdio_params::addr0
uint8_t addr0
Definition: tiescbsp.h:547
bsp_process_data_access_complete
void bsp_process_data_access_complete(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t len, int16_t sm_index)
This API is invoked after PDI side completes read/write to PD address returned by bsp_get_process_dat...
bsp_params::ethphy_init
bsp_ethphy_init_t ethphy_init
Definition: tiescbsp.h:469
bsp_read_word
uint16_t bsp_read_word(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 16-bit value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
t_sm_processdata::lock_state
uint8_t lock_state
Definition: tiescbsp.h:494
bsp_get_latch1_posedge_time
void bsp_get_latch1_posedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch1 posedge timestamp for application use(nanosec resolution)
pruicss.h
bsp_hwspinlock_unlock
void bsp_hwspinlock_unlock(int num)
Release selected spinlock instance.
bsp_is_pdi_perm_read_only
uint8_t bsp_is_pdi_perm_read_only(uint16_t *perm_array, uint16_t address)
Checks if the PDI register [byte] has read only access permission and returns the result.
bsp_send_command_to_firmware
void bsp_send_command_to_firmware(PRUICSS_Handle pruIcssHandle, uint32_t command, uint16_t param1, uint16_t param2)
Send command and parameters from stack to firmware to perform some action based on stack state or in ...
bsp_read_byte
uint8_t bsp_read_byte(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a byte value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
bsp_pdi_write_indication
void bsp_pdi_write_indication(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t length, uint16_t value)
Invoked after writing a register or mailbox buffer from PDI side .
t_sm_properties::length
uint16_t length
Definition: tiescbsp.h:538
bsp_params_init
void bsp_params_init(bsp_params *init_params)
Initialize the members of bsp_params with default values.
t_sm_properties
Definition: tiescbsp.h:536
bsp_pruss_iepreg_write
void bsp_pruss_iepreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val, uint32_t regoffset)
Write a 32-bit value from PRU-ICSS IEP register at 'regoffset'.
bsp_hwspinlock_lock_t
uint32_t(* bsp_hwspinlock_lock_t)(int num)
Definition: tiescbsp.h:438
bsp_pruss_mdioreg_read
uint32_t bsp_pruss_mdioreg_read(PRUICSS_Handle pruIcssHandle, uint32_t regoffset)
Read a 32-bit value from PRU-ICSS MDIO register at 'regoffset'.
bsp_read_dword_isr
uint32_t bsp_read_dword_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 32-bit value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
bsp_eeprom_emulation_reload
int32_t bsp_eeprom_emulation_reload(PRUICSS_Handle pruIcssHandle)
Perform reload operation after validating EEPROM CRC.
bsp_set_pdi_wd_trigger_mode
void bsp_set_pdi_wd_trigger_mode(PRUICSS_Handle pruIcssHandle, uint32_t mode)
Configure PDI WD trigger mode, PDI WD is triggered automatically by h/w on RX_SOF(port0/port1),...
bsp_eeprom_emulation_flush
void bsp_eeprom_emulation_flush(void)
Flush the EEPROM cache to non-volatile storage. Write is performed using eeprom_write callback from b...
bsp_read
void bsp_read(PRUICSS_Handle pruIcssHandle, uint8_t *pdata, uint16_t address, uint16_t len)
Read a byte array at 'address' from ESC memory.
bsp_get_process_data_address
uint16_t bsp_get_process_data_address(PRUICSS_Handle pruIcssHandle, uint16_t address, uint16_t len, int16_t *p_sm_index)
Get the actual address of the buffer for PDI side read/write from host in 3-buffer mode.
bsp_read_word_isr
uint16_t bsp_read_word_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 16-bit value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
bsp_set_sm_properties
void bsp_set_sm_properties(PRUICSS_Handle pruIcssHandle, uint8_t sm, uint16_t address, uint16_t len)
Set the address, length info from register to FWHAL layer. During INIT to PREOP transition in Mailbox...
t_host_interface::system_time_high
uint32_t system_time_high
Definition: tiescbsp.h:506
bsp_pruss_mdio_phy_write
int16_t bsp_pruss_mdio_phy_write(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr, uint8_t regoffset, uint16_t regval)
API to write PHY register via PRU-ICSS MDIO.
bsp_params::spinlock_base_address
uint32_t spinlock_base_address
Definition: tiescbsp.h:466
t_register_properties
Struct for register permission array.
Definition: tiescbsp.h:530
bsp_get_latch1_negedge_time
void bsp_get_latch1_negedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 negedge timestamp for application use(nanosec resolution)
bsp_set_pru_firmware
void bsp_set_pru_firmware(uint32_t *frameProc, uint32_t frameProcLen, uint32_t *hostProc, uint32_t hostProcLen)
This function internally sets the location from which PRU firmwares can be loaded.
bsp_eeprom_read_t
int32_t(* bsp_eeprom_read_t)(uint8_t *buf, uint32_t len)
Definition: tiescbsp.h:435
bsp_pdi_access_perm_word
uint8_t bsp_pdi_access_perm_word(uint16_t address, uint8_t access)
Checks if the PDI register [Two bytes] has the requested access permission and returns the result.
bsp_set_pdi_perm_read_only
void bsp_set_pdi_perm_read_only(uint16_t *perm_array, uint16_t address)
Set the PDI register [byte] access permission to read only.
t_mdio_params::enhancedlink_enable
uint8_t enhancedlink_enable
Definition: tiescbsp.h:551
bsp_set_eeprom_updated_time
void bsp_set_eeprom_updated_time(void)
Set EEPROM update time.
bsp_write_byte
void bsp_write_byte(PRUICSS_Handle pruIcssHandle, uint8_t val, uint16_t address)
Write a byte value at 'address' in ESC memory.
bsp_hwspinlock_unlock_t
void(* bsp_hwspinlock_unlock_t)(int num)
Definition: tiescbsp.h:439
bsp_eeprom_load_esc_registers
int32_t bsp_eeprom_load_esc_registers(PRUICSS_Handle pruIcssHandle, int32_t reload_flag)
For loading ESC registers from EEPROM during first boot/reload after validating CRC.
bsp_esc_reg_perm_init
void bsp_esc_reg_perm_init(PRUICSS_Handle pruIcssHandle)
Sets up register permissions for ECAT side access for TI ESC, if ENABLE_PDI_REG_PERMISSIONS is define...
bsp_write
void bsp_write(PRUICSS_Handle pruIcssHandle, uint8_t *pdata, uint16_t address, uint16_t len)
Write 'len' bytes from pdata to 'address' in ESC memory.
t_mdio_params::addr1
uint8_t addr1
Definition: tiescbsp.h:548
t_host_interface::resp1low
uint16_t resp1low
Definition: tiescbsp.h:513
bsp_write_word
void bsp_write_word(PRUICSS_Handle pruIcssHandle, uint16_t val, uint16_t address)
Write a 16-bit value at 'address' in ESC memory.
bsp_eeprom_emulation_command_ack
void bsp_eeprom_emulation_command_ack(PRUICSS_Handle pruIcssHandle)
Perform reload operation after validating EEPROM CRC, Wrapper API for SSC.
g_bsp_params
static bsp_params g_bsp_params
Definition: tiescbsp.h:486
bsp_pruss_mdio_phy_read
int16_t bsp_pruss_mdio_phy_read(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr, uint8_t regoffset, uint16_t *regval)
API to read PHY register via PRU-ICSS MDIO.
t_mdio_params::link1pol
uint8_t link1pol
Definition: tiescbsp.h:550
t_mdio_params
Struct for MDIO initialization parameters.
Definition: tiescbsp.h:545
bsp_set_digio_out
void bsp_set_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num)
Set selected digital output pin.
bsp_get_pdi_access_perm
uint8_t bsp_get_pdi_access_perm(uint16_t address, uint8_t access)
Checks if the PDI register [byte] has the requested access permission and returns the result.
bsp_global_mutex_unlock
void bsp_global_mutex_unlock(void)
Critical section leave API using semaphore/mutex/interrupt enable primitives from RTOS....
t_host_interface::param2low
uint16_t param2low
Definition: tiescbsp.h:512
bsp_params::interrupt_offset
int32_t interrupt_offset
Definition: tiescbsp.h:454
bsp_exit
void bsp_exit(PRUICSS_Handle pruIcssHandle)
Cleanup of EtherCAT FWHAL It does following things: .
t_host_interface
Struct for host to PRU-ICSS command interface Starts at PRU0 DMEM.
Definition: tiescbsp.h:503
bsp_params::link0_polarity
uint32_t link0_polarity
Definition: tiescbsp.h:471
bsp_init
int32_t bsp_init(bsp_params *init_params)
Initialize the EtherCAT FWHAL It does following things: .
bsp_read_dword
uint32_t bsp_read_dword(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a 32-bit value at 'Address' from ESC memory: SM mailbox (single buffer) mapped or register area.
bsp_start_esc_isr
void bsp_start_esc_isr(PRUICSS_Handle pruIcssHandle)
Register IRQ handlers for various PRU-ICSS interrupts from firmware to host to clear corresponding ev...
bsp_get_timer_register
uint32_t bsp_get_timer_register(void)
Returns the time difference from last call of bsp_clear_timer_register to this bsp_get_timer_register...
bsp_get_eeprom_updated_time
uint32_t bsp_get_eeprom_updated_time(void)
Get EEPROM Updated time.
bsp_params::pruicss_handle
PRUICSS_Handle pruicss_handle
Definition: tiescbsp.h:452
bsp_pruss_cmd_intfc_write_word
void bsp_pruss_cmd_intfc_write_word(uint16_t val, volatile uint16_t *ptr)
Read a 16-bit value from PRU-ICSS IEP command interface.
t_host_interface::param1low
uint16_t param1low
Definition: tiescbsp.h:511
t_mdio_params::link0pol
uint8_t link0pol
Definition: tiescbsp.h:549
bsp_get_local_sys_time
void bsp_get_local_sys_time(uint32_t *systime_low, uint32_t *systime_high)
Return EtherCAT time base for application use.
bsp_write_dword
void bsp_write_dword(PRUICSS_Handle pruIcssHandle, uint32_t val, uint16_t address)
Write a 32-bit value at 'address' in ESC memory.
bsp_pruss_cmd_intfc_read_word
uint16_t bsp_pruss_cmd_intfc_read_word(volatile uint16_t *ptr)
Read a 16-bit value from PRU-ICSS IEP command interface.
reserved
uint16_t reserved
Definition: tisci_boardcfg_rm.h:2
bsp_pruss_iepreg_read
uint32_t bsp_pruss_iepreg_read(PRUICSS_Handle pruIcssHandle, uint32_t regoffset)
Read a 32-bit value from PRU-ICSS IEP register at 'regoffset'.
bsp_eeprom_emulation_init
void bsp_eeprom_emulation_init(void)
Initialize the EEPROM cache in volatile RAM. If the non-volatile storage has valid data(read is perfo...
bsp_pdi_access_perm_array
uint8_t bsp_pdi_access_perm_array(uint16_t address, uint8_t access, uint16_t size)
Checks if all PDI registers starting from 'address' has the requested access permission and returns t...
t_sm_processdata::addr
uint16_t addr
Definition: tiescbsp.h:495
bsp_set_pdi_perm_read_write
void bsp_set_pdi_perm_read_write(uint16_t *perm_array, uint16_t address)
Set the PDI register [byte] access permission to read and write.
mode
char mode[32]
Definition: tisci_pm_core.h:1
bsp_params::phy0_address
uint32_t phy0_address
Definition: tiescbsp.h:475
bsp_params::eeprom_write
bsp_eeprom_write_t eeprom_write
Definition: tiescbsp.h:464
bsp_clear_timer_register
void bsp_clear_timer_register(void)
Update the time when bsp_clear_timer_register last invoked. This is a wrapper API used by SSC.
bsp_eeprom_write_t
int32_t(* bsp_eeprom_write_t)(uint8_t *buf, uint32_t len)
Definition: tiescbsp.h:436
Sync1Isr
void Sync1Isr(void *args)
SYNC1 IRQ Handler.
bsp_pdi_mbx_read_start
void bsp_pdi_mbx_read_start(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side read from write mailbox has started.
t_mdio_params::clkdiv
uint16_t clkdiv
Definition: tiescbsp.h:546
bsp_get_pdi_write_access_fail_cnt
uint32_t bsp_get_pdi_write_access_fail_cnt()
Returns the count of PDI write access failures.
bsp_pdi_mbx_read_complete
void bsp_pdi_mbx_read_complete(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side read from write mailbox has completed.
Sync0Isr
void Sync0Isr(void *args)
SYNC0 IRQ handler.
bsp_get_phy_address_t
int8_t(* bsp_get_phy_address_t)(uint8_t instance, uint8_t portNumber)
Definition: tiescbsp.h:441
bsp_pruss_mdio_init
int16_t bsp_pruss_mdio_init(PRUICSS_Handle pruIcssHandle, t_mdio_params *pmdio_params)
Initializes PRU-ICSS MDIO for EtherCAT firmware to communicate with PHYs. Must be called after poweri...
bsp_function_handler
void(* bsp_function_handler)(void)
Definition: tiescbsp.h:433
bsp_pdi_mbx_write_complete
void bsp_pdi_mbx_write_complete(PRUICSS_Handle pruIcssHandle)
Indicates to the firmware that PDI side write to read mailbox has completed.
bsp_clear_digio_out
void bsp_clear_digio_out(PRUICSS_Handle pruIcssHandle, uint8_t num)
Clear selected digital output pin.
bsp_get_sm_properties
t_sm_properties * bsp_get_sm_properties(uint8_t sm)
Get the pointer to requested SM properties. It is used for Buffer/Mailbox read/write detection from H...
bsp_get_eeprom_update_status
uint8_t bsp_get_eeprom_update_status(void)
Read the EEPROM update status from FWHAL. Typically called from low priority task periodically check ...
t_host_interface::cmdlow
uint16_t cmdlow
Definition: tiescbsp.h:509
bsp_get_sm_index
int16_t bsp_get_sm_index(uint16_t address, uint16_t len)
bsp_read_byte_isr
uint8_t bsp_read_byte_isr(PRUICSS_Handle pruIcssHandle, uint16_t address)
Read a byte value at 'Address' from ESC process data memory: SM buffer (3-buffer) mapped area.
bsp_set_digio_sw_dataout_enable
void bsp_set_digio_sw_dataout_enable(PRUICSS_Handle pruIcssHandle)
Configure digio for sw controlled dataout mode.
EcatIsr
void EcatIsr(void *args)
ECAT IRQ Handler.
bsp_params
Struct for FWHAL initialization Parameters.
Definition: tiescbsp.h:451
bsp_get_eeprom_cache_base
uint8_t * bsp_get_eeprom_cache_base(void)
Return pointer to volatile EEPROM cache in FWHAL for processing to access the EEPROM.
bsp_pruss_mdioreg_write
void bsp_pruss_mdioreg_write(PRUICSS_Handle pruIcssHandle, uint32_t val, uint32_t regoffset)
Write a 32-bit value from PRU-ICSS MDIO register at 'regoffset'.
bsp_params::link1_polarity
uint32_t link1_polarity
Definition: tiescbsp.h:473
bsp_pdi_sm_config_ongoing
uint8_t bsp_pdi_sm_config_ongoing(PRUICSS_Handle pruIcssHandle)
Checks whether firmware has finished updating internal state for SM configuration change initiated by...
bsp_params::eeprom_read
bsp_eeprom_read_t eeprom_read
Definition: tiescbsp.h:462
t_host_interface::sm_config_ongoing
uint8_t sm_config_ongoing
Definition: tiescbsp.h:507
bsp_pruss_mdio_phy_link_state
uint32_t bsp_pruss_mdio_phy_link_state(PRUICSS_Handle pruIcssHandle, uint8_t phyaddr)
Get the link status for selected PHY, this API considers MII_link signal polarity differences and rec...
PRUICSS_Handle
struct PRUICSS_Config_s * PRUICSS_Handle
A handle that is returned from a PRUICSS_open() call. This handle is required for calling other APIs.
Definition: pruicss/v0/pruicss.h:234
t_sm_properties::physical_start_addr
uint16_t physical_start_addr
Definition: tiescbsp.h:537
bsp_params::default_tiesc_eeprom
const unsigned char * default_tiesc_eeprom
Definition: tiescbsp.h:479
bsp_ethphy_init_t
void(* bsp_ethphy_init_t)(PRUICSS_Handle pruIcssHandle, uint8_t phy0addr, uint8_t phy1addr, uint8_t enhancedlink_enable)
Definition: tiescbsp.h:440
bsp_get_latch0_negedge_time
void bsp_get_latch0_negedge_time(PRUICSS_Handle pruIcssHandle, uint32_t *systime_low, uint32_t *systime_high)
Return latch0 negedge timestamp for application use(nanosec resolution)
bsp_hwspinlock_init
void bsp_hwspinlock_init(void)
Initialize SOC spinlock, enable clocks and init spinlock instance 0 through 7 to unlocked state.