AM64x MCU+ SDK  07.03.00
icss_emac.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
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12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
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18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef ICSS_EMAC_H_
34 #define ICSS_EMAC_H_
35 
47 /* ========================================================================== */
48 /* Include Files */
49 /* ========================================================================== */
50 
51 #include <stdint.h>
52 #include <kernel/dpl/SystemP.h>
53 #include <drivers/pruicss.h>
54 #include <drivers/hw_include/csl_types.h>
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
60 /* ========================================================================== */
61 /* Macros & Typedefs */
62 /* ========================================================================== */
63 
65 #define ICSS_EMAC_MAX_PORTS_PER_INSTANCE (2)
66 
74 #define ICSS_EMAC_MODE_MAC1 (1U)
75 
76 #define ICSS_EMAC_MODE_MAC2 (2U)
77 
78 #define ICSS_EMAC_MODE_SWITCH (3U)
79 
80 #define ICSS_EMAC_MODE_DUALMAC (4U)
81 
90 #define ICSS_EMAC_LEARNING_DISABLE (0U)
91 
92 #define ICSS_EMAC_LEARNING_ENABLE (1U)
93 
102 #define ICSS_EMAC_ENABLE_PACING (0)
103 
104 #define ICSS_EMAC_DISABLE_PACING (1)
105 
114 #define ICSS_EMAC_INTR_PACING_MODE1 (0)
115 
124 #define ICSS_EMAC_QUEUE1 ((uint32_t)0U)
125 
126 #define ICSS_EMAC_QUEUE2 ((uint32_t)1U)
127 
128 #define ICSS_EMAC_QUEUE3 ((uint32_t)2U)
129 
130 #define ICSS_EMAC_QUEUE4 ((uint32_t)3U)
131 
132 #define ICSS_EMAC_QUEUE5 ((uint32_t)4U)
133 
134 #define ICSS_EMAC_QUEUE6 ((uint32_t)5U)
135 
136 #define ICSS_EMAC_QUEUE7 ((uint32_t)6U)
137 
138 #define ICSS_EMAC_QUEUE8 ((uint32_t)7U)
139 
140 #define ICSS_EMAC_QUEUE9 ((uint32_t)8U)
141 
142 #define ICSS_EMAC_QUEUE10 ((uint32_t)9U)
143 
144 #define ICSS_EMAC_QUEUE11 ((uint32_t)10U)
145 
146 #define ICSS_EMAC_QUEUE12 ((uint32_t)11U)
147 
148 #define ICSS_EMAC_QUEUE13 ((uint32_t)12U)
149 
150 #define ICSS_EMAC_QUEUE14 ((uint32_t)13U)
151 
152 #define ICSS_EMAC_QUEUE15 ((uint32_t)14U)
153 
154 #define ICSS_EMAC_QUEUE16 ((uint32_t)15U)
155 
156 #define ICSS_EMAC_COLQUEUE ((uint32_t)16U)
157 
160 #define ICSS_EMAC_NUMQUEUES ((uint32_t)17U)
161 
167 #define ICSS_EMAC_SWITCH_INSTANCE_CODE ((uint32_t)0u)
168 
169 #define ICSS_EMAC_SWITCH_ERROR_BASE ((uint32_t)0x200001Fu)
170 
171 #define ICSS_EMAC_SWITCH_ERROR_CODE ((ICSS_EMAC_SWITCH_ERROR_BASE | ((ICSS_EMAC_SWITCH_INSTANCE_CODE) << 16)))
172 
173 #define ICSS_EMAC_SWITCH_ERROR_INFO (ICSS_EMAC_SWITCH_ERROR_CODE)
174 
175 #define ICSS_EMAC_SWITCH_ERROR_WARNING (ICSS_EMAC_SWITCH_ERROR_CODE | 0x10000000u)
176 
177 #define ICSS_EMAC_SWITCH_ERROR_MINOR (ICSS_EMAC_SWITCH_ERROR_CODE | 0x20000000u)
178 
179 #define ICSS_EMAC_SWITCH_ERROR_MAJOR (ICSS_EMAC_SWITCH_ERROR_CODE | 0x30000000u)
180 
181 #define ICSS_EMAC_SWITCH_ERROR_CRITICAL (ICSS_EMAC_SWITCH_ERROR_CODE | 0x40000000u)
182 
185 #define ICSS_EMAC_SWITCH_SUCCESS (0u)
186 
188 #define ICSS_EMAC_ERR_DEV_ALREADY_INSTANTIATED(instID) (0x30000000u + ICSS_EMAC_SWITCH_ERROR_BASE + ((instId) << 16) )
189 
190 #define ICSS_EMAC_ERR_DEV_NOT_INSTANTIATED (ICSS_EMAC_SWITCH_ERROR_MAJOR + 1u)
191 
192 #define ICSS_EMAC_ERR_SWITCH_INVALID_PARAM (ICSS_EMAC_SWITCH_ERROR_MAJOR + 2u)
193 
194 #define ICSS_EMAC_ERR_CH_INVALID (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 3u)
195 
196 #define ICSS_EMAC_ERR_CH_ALREADY_INIT (ICSS_EMAC_SWITCH_ERROR_MAJOR + 4u)
197 
198 #define ICSS_EMAC_ERR_TX_CH_ALREADY_CLOSED (ICSS_EMAC_SWITCH_ERROR_MAJOR + 5u)
199 
200 #define ICSS_EMAC_ERR_TX_CH_NOT_OPEN (ICSS_EMAC_SWITCH_ERROR_MAJOR + 6u)
201 
202 #define ICSS_EMAC_ERR_TX_NO_LINK (ICSS_EMAC_SWITCH_ERROR_MAJOR + 7u)
203 
204 #define ICSS_EMAC_ERR_TX_OUT_OF_BD (ICSS_EMAC_SWITCH_ERROR_MAJOR + 8u)
205 
206 #define ICSS_EMAC_ERR_RX_CH_INVALID (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 9u)
207 
208 #define ICSS_EMAC_ERR_RX_CH_ALREADY_INIT (ICSS_EMAC_SWITCH_ERROR_MAJOR + 10u)
209 
210 #define ICSS_EMAC_ERR_RX_CH_ALREADY_CLOSED (ICSS_EMAC_SWITCH_ERROR_MAJOR + 11u)
211 
212 #define ICSS_EMAC_ERR_RX_CH_NOT_OPEN (ICSS_EMAC_SWITCH_ERROR_MAJOR + 12u)
213 
214 #define ICSS_EMAC_ERR_DEV_ALREADY_CREATED (ICSS_EMAC_SWITCH_ERROR_MAJOR + 13u)
215 
216 #define ICSS_EMAC_ERR_DEV_NOT_OPEN (ICSS_EMAC_SWITCH_ERROR_MAJOR + 14u)
217 
218 #define ICSS_EMAC_ERR_DEV_ALREADY_CLOSED (ICSS_EMAC_SWITCH_ERROR_MAJOR + 15u)
219 
220 #define ICSS_EMAC_ERR_DEV_ALREADY_OPEN (ICSS_EMAC_SWITCH_ERROR_MAJOR + 16u)
221 
222 #define ICSS_EMAC_ERR_RX_BUFFER_ALLOC_FAIL (ICSS_EMAC_SWITCH_ERROR_CRITICAL +17u)
223 
224 #define ICSS_EMAC_SWITCH_INTERNAL_FAILURE (ICSS_EMAC_SWITCH_ERROR_MAJOR + 18u)
225 
226 #define ICSS_EMAC_SWITCH_VLAN_UNAWARE_MODE (ICSS_EMAC_SWITCH_ERROR_MAJOR + 19u)
227 
228 #define ICSS_EMAC_SWITCH_ALE_TABLE_FULL (ICSS_EMAC_SWITCH_ERROR_MAJOR + 20u)
229 
230 #define ICSS_EMAC_SWITCH_ADDR_NOTFOUND (ICSS_EMAC_SWITCH_ERROR_MAJOR + 21u)
231 
232 #define ICSS_EMAC_SWITCH_INVALID_VLANID (ICSS_EMAC_SWITCH_ERROR_MAJOR + 22u)
233 
234 #define ICSS_EMAC_SWITCH_INVALID_PORT (ICSS_EMAC_SWITCH_ERROR_MAJOR + 23u)
235 
236 #define ICSS_EMAC_SWITCH_BD_ALLOC_FAIL (ICSS_EMAC_SWITCH_ERROR_MAJOR + 24u)
237 
238 #define ICSS_EMAC_ERR_BADPACKET (ICSS_EMAC_SWITCH_ERROR_MAJOR + 25u)
239 
240 #define ICSS_EMAC_ERR_COLLISION_FAIL (ICSS_EMAC_SWITCH_ERROR_MAJOR + 26u)
241 
242 #define ICSS_EMAC_ERR_MACFATAL (ICSS_EMAC_SWITCH_ERROR_CRITICAL + 26u)
243 
246 /*TODO: Review if this file is appropriate for this macro*/
248 #define ICSS_EMAC_MAXMTU (1518U)
249 
250 #define ICSS_EMAC_MINMTU (14U)
251 
256 #define ICSS_EMAC_PORT_0 (0)
257 
262 #define ICSS_EMAC_PORT_1 (1U)
263 
268 #define ICSS_EMAC_PORT_2 (2U)
269 
273 #define ICSS_EMAC_IOCTL_PORT_CTRL_DISABLE (0u)
274 
276 #define ICSS_EMAC_IOCTL_PORT_CTRL_ENABLE (1u)
277 
285 #define ICSS_EMAC_STORM_PREV_CTRL_ENABLE (0u)
286 
287 #define ICSS_EMAC_STORM_PREV_CTRL_DISABLE (1u)
288 
289 #define ICSS_EMAC_STORM_PREV_CTRL_SET_CREDITS (2u)
290 
291 #define ICSS_EMAC_STORM_PREV_CTRL_INIT (3u)
292 
293 #define ICSS_EMAC_STORM_PREV_CTRL_RESET (4u)
294 
295 #define ICSS_EMAC_STORM_PREV_CTRL_ENABLE_BC (5u)
296 
297 #define ICSS_EMAC_STORM_PREV_CTRL_DISABLE_BC (6u)
298 
299 #define ICSS_EMAC_STORM_PREV_CTRL_SET_CREDITS_BC (7u)
300 
301 #define ICSS_EMAC_STORM_PREV_CTRL_INIT_BC (8u)
302 
303 #define ICSS_EMAC_STORM_PREV_CTRL_RESET_BC (9u)
304 
305 #define ICSS_EMAC_STORM_PREV_CTRL_ENABLE_MC (10u)
306 
307 #define ICSS_EMAC_STORM_PREV_CTRL_DISABLE_MC (11u)
308 
309 #define ICSS_EMAC_STORM_PREV_CTRL_SET_CREDITS_MC (12u)
310 
311 #define ICSS_EMAC_STORM_PREV_CTRL_INIT_MC (13u)
312 
313 #define ICSS_EMAC_STORM_PREV_CTRL_RESET_MC (14u)
314 
315 #define ICSS_EMAC_STORM_PREV_CTRL_ENABLE_UC (15u)
316 
317 #define ICSS_EMAC_STORM_PREV_CTRL_DISABLE_UC (16u)
318 
319 #define ICSS_EMAC_STORM_PREV_CTRL_SET_CREDITS_UC (17u)
320 
321 #define ICSS_EMAC_STORM_PREV_CTRL_INIT_UC (18u)
322 
323 #define ICSS_EMAC_STORM_PREV_CTRL_RESET_UC (19u)
324 
333 #define ICSS_EMAC_LEARN_CTRL_UPDATE_TABLE (0u)
334 
335 #define ICSS_EMAC_LEARN_CTRL_CLR_TABLE (1u)
336 
337 #define ICSS_EMAC_LEARN_CTRL_AGEING (2u)
338 
339 #define ICSS_EMAC_LEARN_CTRL_FIND_MAC (3u)
340 
341 #define ICSS_EMAC_LEARN_CTRL_REMOVE_MAC (4u)
342 
343 #define ICSS_EMAC_LEARN_CTRL_INC_COUNTER (5u)
344 
345 #define ICSS_EMAC_LEARN_CTRL_INIT_TABLE (6u)
346 
347 #define ICSS_EMAC_LEARN_CTRL_SET_PORTSTATE (7u)
348 
357 #define ICSS_EMAC_IOCTL_STAT_CTRL_GET (0u)
358 
359 #define ICSS_EMAC_IOCTL_STAT_CTRL_CLEAR (1u)
360 
369 #define ICSS_EMAC_IOCTL_PORT_CTRL (0u)
370 
371 #define ICSS_EMAC_IOCTL_LEARNING_CTRL (1u)
372 
373 #define ICSS_EMAC_IOCTL_STORM_PREV_CTRL (2u)
374 
375 #define ICSS_EMAC_IOCTL_STATS_CTRL (3u)
376 
377 #define ICSS_EMAC_IOCTL_PROMISCUOUS_CTRL (4u)
378 
379 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL (5u)
380 
381 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL (6u)
382 
391 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_ENABLE (0u)
392 
393 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_DISABLE (1u)
394 
395 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_OVERRIDE_HASHMASK (2u)
396 
397 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_ADD_MACID (3u)
398 
399 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_REMOVE_MACID (4u)
400 
401 #define ICSS_EMAC_IOCTL_MULTICAST_FILTER_CTRL_GET_DROPPED (5u)
402 
411 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_ENABLE_CMD (0u)
412 
413 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_DISABLE_CMD (1u)
414 
415 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_UNTAG_HOST_RCV_ALL_CMD (2u)
416 
417 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_UNTAG_HOST_RCV_NAL_CMD (3u)
418 
419 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_PRIOTAG_HOST_RCV_ALL_CMD (4u)
420 
421 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_PRIOTAG_HOST_RCV_NAL_CMD (5u)
422 
423 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_ADD_VID_CMD (6u)
424 
425 #define ICSS_EMAC_IOCTL_VLAN_FILTER_CTRL_REMOVE_VID_CMD (7u)
426 
432 #define ICSS_EMAC_LEARNING_PORT_STATE_LEARNING (0U)
433 #define ICSS_EMAC_LEARNING_PORT_STATE_NOT_LEARNING (1U)
434 #define ICSS_EMAC_LEARNING_PORT_STATE_LOCKED (2U)
435 
436 /*TODO: Update this with correct value */
437 #define ICSS_EMAC_OBJECT_SIZE_IN_BYTES (45200)
438 
442 typedef struct ICSS_EMAC_Config_s *ICSS_EMAC_Handle;
443 
444 /*TODO: Review this */
448 typedef int32_t (*ICSS_EMAC_CallBack)(void *arg0, void *arg1, void *arg2);
449 
450 /* ========================================================================== */
451 /* Structure Declarations */
452 /* ========================================================================== */
453 
457 typedef struct ICSS_EMAC_FwStaticMmap_s
458 {
459  /* PRU0 and PRU1 DRAM */
460  uint32_t versionOffset; /* Version offset for release 1 */
461  uint32_t version2Offset; /* Version offset for release 2 */
462  uint32_t featureOffset; /* Feature offset */
463  uint32_t futureFeatureOffset; /* Offset reserved for enhance features, future use*/
464  uint32_t statisticsOffset; /* Statistics offset */
465  uint32_t statisticsSize; /* Statistics block size */
466  uint32_t stormPreventionOffsetBC; /* Storm prevention offset */
467  uint32_t phySpeedOffset; /* Phy Speed Offset */
468  uint32_t portStatusOffset; /* Port Status Offset */
469  uint32_t portControlAddr; /* Port Control Addr offset */
470  uint32_t portMacAddr; /* Port Mac Addr offset*/
471  uint32_t rxInterruptStatusOffset; /* RX Interrupt Status Offset */
472  uint32_t stormPreventionOffsetMC; /* Storm prevention offset (multicast) */
473  uint32_t stormPreventionOffsetUC; /* Storm prevention offset (unicast) */
474  uint32_t p0QueueDescOffset; /* Port 0 QueueDescOffset */
475  uint32_t p0ColQueueDescOffset; /* Port 0 Collision QueueDescOffset */
476  uint32_t emacTtsConfigBaseOffset; /* TTS Config Base Offset */
477  uint32_t interfaceMacAddrOffset; /* Interface Mac AddressrOffset */
478  uint32_t colStatusAddr; /* Collision status address offset */
479  uint32_t promiscuousModeOffset; /* promiscuous mode feature control offset */
481 
485 typedef struct ICSS_EMAC_FwDynamicMmap_s
486 {
487  uint32_t queueSizeOffset; /* offset for queue size */
488  uint32_t queueOffset; /* offset for queue */
489  uint32_t queueDescriptorOffset; /* offset for queue descriptors */
490  uint32_t txQueueSize[ICSS_EMAC_NUMQUEUES-1U]; /* TX queue sizes, */
491  uint32_t rxHostQueueSize[ICSS_EMAC_NUMQUEUES - 1U]; /* RX Host queue sizes */
492  uint32_t collisionQueueSize; /* Collision queue size */
493  /* Following are placed in ICSS Shared RAM */
494  uint32_t p0Q1BufferDescOffset; /* Port 0 Queue1 Buffer Descriptor offset */
495  uint32_t p0ColBufferDescOffset; /* Port 0 Collision Buffer Descriptor offset */
496  /* Following are placed in L3/OCMC RAM */
497  uint32_t p0Q1BufferOffset; /* Port 0 Queue1 Buffer offset */
498  uint32_t transmitQueuesBufferOffset; /* Transmit Queue Buffer offset */
499  uint32_t p0ColBufferOffset; /* Port 0 Collision Buffer offset */
500  uint32_t hostQ1RxContextOffset; /* Receive Host Queue 1 Context offset */
501  uint32_t p1Q1SwitchTxContextOffset; /* Port 1 queue 1 Switch TX Context offset */
502  uint32_t portQueueDescOffset; /* Port queue descriptor offset */
503  uint32_t q1EmacTxContextOffset; /* Queueu1 Emac TX Context Offset */
504  uint32_t numQueues; /* number of port queues */
506 
510 typedef struct ICSS_EMAC_FwVlanFilterParams_s
511 {
512  uint32_t ctrlBitmapOffset;
513  uint32_t ctrlEnableBit;
514  uint32_t ctrlUntagHostRcvAllowBit;
515  uint32_t ctrlPriotagHostRcvAllowBit;
516  uint32_t filterTableBaseAddress;
517  uint32_t vidMaxValue;
519 
523 typedef struct ICSS_EMAC_FwMulticastFilterParams_s
524 {
525  uint32_t ctrlOffset;
526  uint32_t maskSizeBytes;
527  uint32_t maskInitVal;
528  uint32_t maskOffset;
529  uint32_t overrideStatusOffset;
530  uint32_t tableOffset;
531  uint32_t ctrlEnabledValue;
532  uint32_t ctrlDisabledValue;
533  uint32_t maskOverrideSetValue;
534  uint32_t maskOverrideNotSetValue;
535  uint32_t hostRcvAllowedValue;
536  uint32_t hostRcvNotAllowedValue;
538 
539 /*
540 * @brief ICSS EMAC Init Configuration Structure
541 */
542 typedef struct ICSS_EMAC_Attrs_s
543 {
544  uint8_t emacMode;
546  uint32_t phyAddr[ICSS_EMAC_MAX_PORTS_PER_INSTANCE];
550  uint8_t halfDuplexEnable;
554  uint8_t enableIntrPacing;
558  uint8_t intrPacingMode;
562  uint16_t pacingThreshold;
564  uint8_t ethPrioQueue;
569  uint8_t learningEnable;
573  uint8_t portMask;
578  uint32_t linkIntNum;
579  /* Link interrupt number */
580  uint32_t rxIntNum;
581  /* Recieve Packet interrupt number */
582  uint32_t txIntNum;
583  /* Transmit completion interrupt number */
584  uint8_t macId[6];
586  uint32_t l3OcmcBaseAddr;
588  uint32_t l3OcmcSize;
590  uint32_t linkTaskPriority;
591  /* Link Task Priority */
592  uint32_t rxTaskPriority;
593  /* RX Task Priority */
594  uint32_t txTaskPriority;
595  /* TX Task Priority */
597 
601 typedef struct ICSS_EMAC_InternalObject_t
602 {
603  uint32_t reserved[ICSS_EMAC_OBJECT_SIZE_IN_BYTES/sizeof(uint32_t)];
606 
611 typedef struct ICSS_EMAC_Config_s
612 {
613  void *object;
615  const ICSS_EMAC_Attrs *attrs;
618 
622 typedef struct ICSS_EMAC_CallBackConfig_s
623 {
624  ICSS_EMAC_CallBack callBack;
625  void *userArg;
627 
628 typedef struct ICSS_EMAC_CallBackObject_s
629 {
630  ICSS_EMAC_CallBackConfig port0LinkCallBack;
631  ICSS_EMAC_CallBackConfig port1LinkCallBack;
635  ICSS_EMAC_CallBackConfig learningExCallBack;
637 
648 typedef struct ICSS_EMAC_Params_s
649 {
650  PRUICSS_Handle pruicssHandle;
652  const PRUICSS_IntcInitData *pruicssIntcInitData;
654  ICSS_EMAC_FwStaticMmap *fwStaticMMap;
655  ICSS_EMAC_FwDynamicMmap *fwDynamicMMap;
656  ICSS_EMAC_FwVlanFilterParams *fwVlanFilterParams;
657  ICSS_EMAC_FwMulticastFilterParams *fwMulticastFilterParams;
658  ICSS_EMAC_CallBackObject callBackObject;
660 
665 typedef struct ICSS_EMAC_RxArgument_s
666 {
667  ICSS_EMAC_Handle icssEmacHandle;
669  uint32_t destAddress;
671  uint8_t queueNumber;
673  uint8_t port;
675  uint32_t more;
678 
683 typedef struct ICSS_EMAC_TxArgument_s
684 {
685  ICSS_EMAC_Handle icssEmacHandle;
687  const uint8_t *srcAddress;
689  uint8_t portNumber;
691  uint8_t queuePriority;
693  uint16_t lengthOfPacket;
696 
700 typedef struct ICSS_EMAC_IoctlCmd_s
701 {
702  uint8_t command;
703  void *ioctlVal;
705 
710 typedef struct ICSS_EMAC_PruStatistics_s
711 {
712 /* The fields here are aligned here so that it's consistent
713  with the memory layout in PRU DRAM, this is to facilitate easy
714  memcpy or DMA transfer. Don't change the order of fields without
715  modifying the order of fields in PRU DRAM. For details refer to guide
716 */
717  volatile uint32_t txBcast;
718  volatile uint32_t txMcast;
719  volatile uint32_t txUcast;
720  volatile uint32_t txOctets;
722  volatile uint32_t rxBcast;
723  volatile uint32_t rxMcast;
724  volatile uint32_t rxUcast;
725  volatile uint32_t rxOctets;
727  volatile uint32_t tx64byte;
728  volatile uint32_t tx65_127byte;
729  volatile uint32_t tx128_255byte;
730  volatile uint32_t tx256_511byte;
731  volatile uint32_t tx512_1023byte;
732  volatile uint32_t tx1024byte;
734  volatile uint32_t rx64byte;
735  volatile uint32_t rx65_127byte;
736  volatile uint32_t rx128_255byte;
737  volatile uint32_t rx256_511byte;
738  volatile uint32_t rx512_1023byte;
739  volatile uint32_t rx1024byte;
741  volatile uint32_t lateColl;
742  volatile uint32_t singleColl;
743  volatile uint32_t multiColl;
744  volatile uint32_t excessColl;
746  volatile uint32_t rxMisAlignmentFrames;
747  volatile uint32_t stormPrevCounter;
748  volatile uint32_t stormPrevCounterMC;
749  volatile uint32_t stormPrevCounterUC;
750  volatile uint32_t macRxError;
752  volatile uint32_t SFDError;
753  volatile uint32_t defTx;
754  volatile uint32_t macTxError;
755  volatile uint32_t rxOverSizedFrames;
756  volatile uint32_t rxUnderSizedFrames;
757  volatile uint32_t rxCRCFrames;
759  volatile uint32_t droppedPackets;
760 /* Debug variables, these are not part of standard MIB. Useful for debugging */
761 /* Reserved for future Use */
762  volatile uint32_t txOverFlow;
763  volatile uint32_t txUnderFlow;
764  volatile uint32_t sqeTestError;
765  volatile uint32_t TXqueueLevel;
766  volatile uint32_t CSError;
768 /* ========================================================================== */
769 /* Function Declarations */
770 /* ========================================================================== */
771 
775 void ICSS_EMAC_init(void);
776 
780 void ICSS_EMAC_deinit(void);
781 
788 
797 ICSS_EMAC_Handle ICSS_EMAC_open(uint32_t idx, const ICSS_EMAC_Params *params);
798 
805 void ICSS_EMAC_close(ICSS_EMAC_Handle icssEmacHandle);
806 
831 int32_t ICSS_EMAC_ioctl(ICSS_EMAC_Handle icssEmacHandle,
832  uint32_t ioctlCommand,
833  uint8_t portNo,
834  void *ioctlParams);
835 
849 int32_t ICSS_EMAC_rxPktGet(ICSS_EMAC_RxArgument *rxArg, void *userArg);
850 
863 int32_t ICSS_EMAC_rxPktInfo(ICSS_EMAC_Handle icssEmacHandle,
864  int32_t *portNumber,
865  int32_t *queueNumber);
866 
879 int32_t ICSS_EMAC_txPacket(const ICSS_EMAC_TxArgument *txArg, void *userArg);
880 
881 /* ========================================================================== */
882 /* Global Variables */
883 /* ========================================================================== */
884 
885 #ifdef __cplusplus
886 }
887 #endif
888 
891 #endif /* #ifndef ICSS_EMAC_H_ */
ICSS_EMAC_TxArgument
Tx packet processing information block that needs to passed into call to ICSS_EMAC_TxPacket.
Definition: icss_emac.h:685
ICSS_EMAC_Handle
struct ICSS_EMAC_Config_s * ICSS_EMAC_Handle
Alias for ICSS EMAC Handle containing base addresses and modules.
Definition: icss_emac.h:443
ICSS_EMAC_RxArgument
Rx packet processing information block that needs to passed into call to ICSS_EMAC_RxPktGet.
Definition: icss_emac.h:667
ICSS_EMAC_txPacket
int32_t ICSS_EMAC_txPacket(const ICSS_EMAC_TxArgument *txArg, void *userArg)
API to queue a frame which has to be transmitted on the specified port queue.
SystemP.h
ICSS_EMAC_NUMQUEUES
#define ICSS_EMAC_NUMQUEUES
Definition: icss_emac.h:160
ICSS_EMAC_ioctl
int32_t ICSS_EMAC_ioctl(ICSS_EMAC_Handle icssEmacHandle, uint32_t ioctlCommand, uint8_t portNo, void *ioctlParams)
IOCTL Function for ICSS EMAC.
pruicss.h
ICSS_EMAC_OBJECT_SIZE_IN_BYTES
#define ICSS_EMAC_OBJECT_SIZE_IN_BYTES
Definition: icss_emac.h:438
ICSS_EMAC_params_init
void ICSS_EMAC_params_init(ICSS_EMAC_Params *params)
Initialize the parmeters data structure with defaults.
ICSS_EMAC_init
void ICSS_EMAC_init(void)
This function initializes the ICSS_EMAC module.
ICSS_EMAC_FwDynamicMmap
ICSS EMAC Dynamic Firmware Memory Map offsets.
Definition: icss_emac.h:487
ICSS_EMAC_CallBack
int32_t(* ICSS_EMAC_CallBack)(void *arg0, void *arg1, void *arg2)
definition for a generic protocol callback function
Definition: icss_emac.h:449
ICSS_EMAC_rxPktGet
int32_t ICSS_EMAC_rxPktGet(ICSS_EMAC_RxArgument *rxArg, void *userArg)
Retrieves a frame from a host queue and copies it in the allocated stack buffer.
ICSS_EMAC_FwVlanFilterParams
ICSS EMAC VLAN Filtering Parameters.
Definition: icss_emac.h:512
ICSS_EMAC_open
ICSS_EMAC_Handle ICSS_EMAC_open(uint32_t idx, const ICSS_EMAC_Params *params)
API to initialize and configure ICSS in MAC/Switch Mode.
ICSS_EMAC_PruStatistics
Statistics structure for capturing statistics on PRU.
Definition: icss_emac.h:712
reserved
uint16_t reserved
Definition: tisci_boardcfg_rm.h:2
ICSS_EMAC_close
void ICSS_EMAC_close(ICSS_EMAC_Handle icssEmacHandle)
API to stop MAC/Switch Mode.
PRUICSS_IntcInitData
PRUICSS Interrupt controller initialisation data structure.
Definition: pruicss/v0/pruicss.h:273
ICSS_EMAC_rxPktInfo
int32_t ICSS_EMAC_rxPktInfo(ICSS_EMAC_Handle icssEmacHandle, int32_t *portNumber, int32_t *queueNumber)
API to retrieve the information about the received frame which is then used to dequeue the frame from...
ICSS_EMAC_deinit
void ICSS_EMAC_deinit(void)
This function de-initializes the ICSS_EMAC module.
ICSS_EMAC_CallBackObject
Definition: icss_emac.h:630
ICSS_EMAC_FwStaticMmap
ICSS EMAC Static Firmware Memory Map offsets.
Definition: icss_emac.h:459
ICSS_EMAC_InternalObject
Opaque ICSS EMAC driver object.
Definition: icss_emac.h:603
ICSS_EMAC_Attrs
Definition: icss_emac.h:544
ICSS_EMAC_FwMulticastFilterParams
ICSS EMAC Multicast Filtering Parameters.
Definition: icss_emac.h:525
ICSS_EMAC_Params
ICSS_EMAC Parameters.
Definition: icss_emac.h:650
ICSS_EMAC_CallBackConfig
Generic callback configuration for protocol specific callbacks.
Definition: icss_emac.h:624
ICSS_EMAC_IoctlCmd
IOCTL command members for configuring switch/EMAC.
Definition: icss_emac.h:702
PRUICSS_Handle
struct PRUICSS_Config_s * PRUICSS_Handle
A handle that is returned from a PRUICSS_open() call. This handle is required for calling other APIs.
Definition: pruicss/v0/pruicss.h:234
ICSS_EMAC_MAX_PORTS_PER_INSTANCE
#define ICSS_EMAC_MAX_PORTS_PER_INSTANCE
Definition: icss_emac.h:65
ICSS_EMAC_Config
Base EMAC handle containing pointers to all modules required for driver to work.
Definition: icss_emac.h:613