AM64x MCU+ SDK  07.03.00
uart/v0/uart.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 typedef void *UART_Handle;
73 
83 #define UART_TRANSFER_STATUS_SUCCESS (0U)
84 
85 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
86 
87 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
88 
89 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
90 
91 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
92 
93 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
94 
95 #define UART_TRANSFER_STATUS_CANCELLED (6U)
96 
97 #define UART_TRANSFER_STATUS_STARTED (7U)
98 
99 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
100 
101 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
102 
103 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
104 
125 #define UART_TRANSFER_MODE_BLOCKING (0U)
126 
130 #define UART_TRANSFER_MODE_CALLBACK (1U)
131 
153 #define UART_READ_RETURN_MODE_FULL (0U)
154 
157 #define UART_READ_RETURN_MODE_PARTIAL (1U)
158 
168 #define UART_LEN_5 (0U)
169 #define UART_LEN_6 (1U)
170 #define UART_LEN_7 (2U)
171 #define UART_LEN_8 (3U)
172 
182 #define UART_STOPBITS_1 (0U)
183 #define UART_STOPBITS_2 (1U)
184 
194 #define UART_PARITY_NONE (0x00U)
195 #define UART_PARITY_ODD (0x01U)
196 #define UART_PARITY_EVEN (0x03U)
197 #define UART_PARITY_FORCED0 (0x07U)
198 #define UART_PARITY_FORCED1 (0x05U)
199 
209 #define UART_FCTYPE_NONE (0x00U)
210 #define UART_FCTYPE_HW (0x02U)
211 
221 #define UART_FCPARAM_RXNONE (0x00U)
222 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
223 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
224 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
225 #define UART_FCPARAM_AUTO_RTS (0x40U)
226 
236 #define UART_FCPARAM_TXNONE (0x00U)
237 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
238 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
239 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
240 #define UART_FCPARAM_AUTO_CTS (0x80U)
241 
251 #define UART_RXTRIGLVL_1 (1U)
252 #define UART_RXTRIGLVL_8 (8U)
253 #define UART_RXTRIGLVL_16 (16U)
254 #define UART_RXTRIGLVL_56 (56U)
255 #define UART_RXTRIGLVL_60 (60U)
256 
266 #define UART_TXTRIGLVL_1 (1U)
267 #define UART_TXTRIGLVL_8 (8U)
268 #define UART_TXTRIGLVL_16 (16U)
269 #define UART_TXTRIGLVL_32 (32U)
270 #define UART_TXTRIGLVL_56 (56U)
271 
281 #define UART_OPER_MODE_16X (0U)
282 #define UART_OPER_MODE_SIR (1U)
283 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
284 #define UART_OPER_MODE_13X (3U)
285 #define UART_OPER_MODE_MIR (4U)
286 #define UART_OPER_MODE_FIR (5U)
287 #define UART_OPER_MODE_CIR (6U)
288 #define UART_OPER_MODE_DISABLED (7U)
289 
300 #define UART_TX_FIFO_NOT_FULL ( \
301  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
302 #define UART_TX_FIFO_FULL ( \
303  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
304 
314 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
315  << \
316  UART_IIR_IT_TYPE_SHIFT)
317 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
318  << \
319  UART_IIR_IT_TYPE_SHIFT)
320 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
321  << \
322  UART_IIR_IT_TYPE_SHIFT)
323 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
324  << \
325  UART_IIR_IT_TYPE_SHIFT)
326 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
327  << \
328  UART_IIR_IT_TYPE_SHIFT)
329 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
330  << \
331  UART_IIR_IT_TYPE_SHIFT)
332 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
333  << \
334  UART_IIR_IT_TYPE_SHIFT)
335 
337 #define UART_INTR_PENDING (0U)
338 #define UART_N0_INTR_PENDING (1U)
339 
348 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
349 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
350 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
351 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
352 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
353 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
354 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
355 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
356 
357 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
358 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
359 
368 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
369 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
370 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
371 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
372 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
373 
382 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
383 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
384 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
385 
386 /* ========================================================================== */
387 /* Structures and Enums */
388 /* ========================================================================== */
389 
394 typedef struct
395 {
396  void *buf;
399  uint32_t count;
403  uint32_t timeout;
405  uint32_t status;
407  void *args;
410 
418 typedef void (*UART_CallbackFxn) (UART_Handle handle,
419  UART_Transaction *transaction);
420 
431 typedef struct
432 {
433  uint32_t baudRate;
435  uint32_t dataLength;
437  uint32_t stopBits;
439  uint32_t parityType;
441  uint32_t readMode;
443  uint32_t readReturnMode;
445  uint32_t writeMode;
451  uint32_t hwFlowControl;
456  /*
457  * Driver configuration
458  */
459  uint32_t intrEnable;
461  uint32_t intrNum;
463  uint8_t intrPriority;
465  uint32_t skipIntrReg;
467  uint32_t dmaEnable;
470  /*
471  * UART configuration
472  */
473  uint32_t rxTrigLvl;
475  uint32_t txTrigLvl;
477 } UART_Params;
478 
480 typedef struct
481 {
482  /*
483  * SOC configuration
484  */
485  uint32_t baseAddr;
487  uint32_t inputClkFreq;
489 } UART_Attrs;
490 
491 /* ========================================================================== */
492 /* Internal/Private Structure Declarations */
493 /* ========================================================================== */
494 
498 typedef struct
499 {
500  /*
501  * User parameters
502  */
507  /*
508  * UART write variables
509  */
510  const void *writeBuf;
512  uint32_t writeCount;
516  /*
517  * UART receive variables
518  */
519  void *readBuf;
521  uint32_t readCount;
525  uint32_t rxTimeoutCnt;
527  uint32_t readErrorCnt;
529  /*
530  * UART ransaction status variables
531  */
536  /*
537  * State variables
538  */
539  uint32_t isOpen;
541  void *lock;
555  void *hwiHandle;
559 } UART_Object;
560 
570 typedef struct
571 {
576 } UART_Config;
577 
579 extern UART_Config gUartConfig[];
581 extern uint32_t gUartConfigNum;
582 
583 /* ========================================================================== */
584 /* Global Variables Declarations */
585 /* ========================================================================== */
586 
587 /* None */
588 
589 /* ========================================================================== */
590 /* Function Declarations */
591 /* ========================================================================== */
592 
596 void UART_init(void);
597 
601 void UART_deinit(void);
602 
619 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
620 
630 void UART_close(UART_Handle handle);
631 
666 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
667 
702 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
703 
736 
769 
779 
785 static inline void UART_Params_init(UART_Params *prms);
786 
793 static inline void UART_Transaction_init(UART_Transaction *trans);
794 
795 /* ========================================================================== */
796 /* Static Function Definitions */
797 /* ========================================================================== */
798 
799 static inline void UART_Params_init(UART_Params *prms)
800 {
801  if(prms != NULL)
802  {
803  prms->baudRate = 115200U;
804  prms->dataLength = UART_LEN_8;
805  prms->stopBits = UART_STOPBITS_1;
810  prms->readCallbackFxn = NULL;
811  prms->writeCallbackFxn = NULL;
812  prms->hwFlowControl = FALSE;
814  prms->intrNum = 210U;
815  prms->intrEnable = TRUE;
816  prms->intrPriority = 4U;
817  prms->skipIntrReg = FALSE;
818  prms->dmaEnable = FALSE;
819  prms->rxTrigLvl = UART_RXTRIGLVL_8;
821  }
822 }
823 
824 static inline void UART_Transaction_init(UART_Transaction *trans)
825 {
826  if(trans != NULL)
827  {
828  trans->buf = NULL;
829  trans->count = 0U;
830  trans->timeout = SystemP_WAIT_FOREVER;
832  trans->args = NULL;
833  }
834 }
835 
836 /* ========================================================================== */
837 /* Advanced Function Declarations */
838 /* ========================================================================== */
839 uint32_t UART_getBaseAddr(UART_Handle handle);
857 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
858 
873 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
874 
903 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
904 
929 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
930 
949 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
950 
968 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
969 
995 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
996 
1009 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1010 
1011 /* ========================================================================== */
1012 /* Advanced Function Definitions */
1013 /* ========================================================================== */
1014 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1015 {
1016  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1017  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1018 }
1019 
1020 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1021 {
1022  uint32_t lcrRegValue = 0U;
1023  uint32_t retVal = FALSE;
1024 
1025  /* Preserving the current value of LCR. */
1026  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1027 
1028  /* Switching to Register Operational Mode of operation. */
1029  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1030  & 0x7FU);
1031 
1032  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1033  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1034  (HW_RD_REG32(baseAddr + UART_LSR) &
1035  UART_LSR_RX_FIFO_E_MASK))
1036  {
1037  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1038  *pChar = (uint8_t)tempRetVal;
1039  retVal = TRUE;
1040  }
1041 
1042  /* Restoring the value of LCR. */
1043  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1044 
1045  return retVal;
1046 }
1047 
1048 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1049 {
1050  uint32_t enhanFnBitVal = 0U;
1051  uint32_t lcrRegValue = 0U;
1052 
1053  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1054  if ((intrFlag & 0xF0U) > 0U)
1055  {
1056  /* Preserving the current value of LCR. */
1057  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1058  /* Switching to Register Configuration Mode B. */
1059  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1060 
1061  /* Collecting the current value of EFR[4] and later setting it. */
1062  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1063 
1064  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1065  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1066 
1067  /* Restoring the value of LCR. */
1068  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1069 
1070  /* Preserving the current value of LCR. */
1071  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1072 
1073  /* Switching to Register Operational Mode of operation. */
1074  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1075  & 0x7FU);
1076 
1077  /*
1078  ** It is suggested that the System Interrupts for UART in the
1079  ** Interrupt Controller are enabled after enabling the peripheral
1080  ** interrupts of the UART using this API. If done otherwise, there
1081  ** is a risk of LCR value not getting restored and illicit characters
1082  ** transmitted or received from/to the UART. The situation is explained
1083  ** below.
1084  ** The scene is that the system interrupt for UART is already enabled
1085  ** and the current API is invoked. On enabling the interrupts
1086  ** corresponding to IER[7:4] bits below, if any of those interrupt
1087  ** conditions already existed, there is a possibility that the control
1088  ** goes to Interrupt Service Routine (ISR) without executing the
1089  ** remaining statements in this API. Executing the remaining statements
1090  ** is critical in that the LCR value is restored in them.
1091  ** However, there seems to be no risk in this API for enabling
1092  ** interrupts corresponding to IER[3:0] because it is done at the end
1093  ** and no statements follow that.
1094  */
1095 
1096  /************* ATOMIC STATEMENTS START *************************/
1097 
1098  /* Programming the bits IER[7:4]. */
1099  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1100 
1101  /* Restoring the value of LCR. */
1102  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1103 
1104  /* Preserving the current value of LCR. */
1105  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1106  /* Switching to Register Configuration Mode B. */
1107  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1108 
1109  /* Restoring the value of EFR[4] to its original value. */
1110  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1111 
1112  /* Restoring the value of LCR. */
1113  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1114 
1115  /************** ATOMIC STATEMENTS END *************************/
1116  }
1117 
1118  /* Programming the bits IER[3:0]. */
1119  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1120  (intrFlag & 0x0FU));
1121 }
1122 
1123 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1124 {
1125  uint32_t enhanFnBitVal;
1126  uint32_t lcrRegValue;
1127 
1128  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1129  if((intrFlag & 0xF0U) > 0U)
1130  {
1131  /* Preserving the current value of LCR. */
1132  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1133  /* Switching to Register Configuration Mode B. */
1134  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1135 
1136  /* Collecting the current value of EFR[4] and later setting it. */
1137  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1138 
1139  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1140  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1141 
1142  /* Restoring the value of LCR. */
1143  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1144  }
1145 
1146  /* Preserving the current value of LCR. */
1147  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1148 
1149  /* Switching to Register Operational Mode of operation. */
1150  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1151  & 0x7FU);
1152 
1153  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1154  ~(intrFlag & 0xFFU));
1155 
1156  /* Restoring the value of LCR. */
1157  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1158 
1159  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1160  if((intrFlag & 0xF0U) > 0U)
1161  {
1162  /* Preserving the current value of LCR. */
1163  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1164  /* Switching to Register Configuration Mode B. */
1165  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1166 
1167  /* Restoring the value of EFR[4] to its original value. */
1168  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1169 
1170  /* Restoring the value of LCR. */
1171  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1172  }
1173 }
1174 
1175 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1176 {
1177  /* Programming the bits IER2[1:0]. */
1178  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1179  (intrFlag & 0x03U));
1180 }
1181 
1182 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1183 {
1184  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1185  ~(intrFlag & 0x3U));
1186 }
1187 
1188 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1189 {
1190  uint32_t lcrRegValue = 0U;
1191  uint32_t retVal = 0U;
1192 
1193  /* Preserving the current value of LCR. */
1194  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1195 
1196  /* Switching to Register Operational Mode of operation. */
1197  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1198  & 0x7FU);
1199 
1200  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1201 
1202  /* Restoring the value of LCR. */
1203  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1204 
1205  return retVal;
1206 }
1207 
1208 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1209 {
1210  uint32_t retVal = 0U;
1211 
1212  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1213  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1214 
1215  return retVal;
1216 }
1217 
1218 #ifdef __cplusplus
1219 }
1220 #endif
1221 
1222 #endif /* #ifndef UART_V0_H_ */
1223 
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v0/uart.h:545
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v0/uart.h:125
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v0/uart.h:543
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v0/uart.h:824
UART_Object::readTransferSemObj
SemaphoreP_Object readTransferSemObj
Definition: uart/v0/uart.h:548
UART_REG_CONFIG_MODE_B
#define UART_REG_CONFIG_MODE_B
Definition: uart/v0/uart.h:383
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v0/uart.h:182
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v0/uart.h:83
UART_Object::handle
UART_Handle handle
Definition: uart/v0/uart.h:503
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1175
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v0/uart.h:555
index
uint16_t index
Definition: tisci_rm_proxy.h:3
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v0/uart.h:510
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v0/uart.h:403
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v0/uart.h:72
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v0/uart.h:534
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v0/uart.h:571
UART_Params::writeMode
uint32_t writeMode
Definition: uart/v0/uart.h:445
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v0/uart.h:1208
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v0/uart.h:514
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v0/uart.h:418
UART_Params::dataLength
uint32_t dataLength
Definition: uart/v0/uart.h:435
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v0/uart.h:463
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v0/uart.h:441
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v0/uart.h:252
UART_Params::intrEnable
uint32_t intrEnable
Definition: uart/v0/uart.h:459
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1123
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v0/uart.h:194
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v0/uart.h:473
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v0/uart.h:1020
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v0/uart.h:1188
UART_Transaction::args
void * args
Definition: uart/v0/uart.h:407
UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v0/uart.h:153
UART_Object::isOpen
uint32_t isOpen
Definition: uart/v0/uart.h:539
UART_Params::skipIntrReg
uint32_t skipIntrReg
Definition: uart/v0/uart.h:465
UART_Config::attrs
UART_Attrs * attrs
Definition: uart/v0/uart.h:572
UART_Params::dmaEnable
uint32_t dmaEnable
Definition: uart/v0/uart.h:467
UART_Object::writeTransferSemObj
SemaphoreP_Object writeTransferSemObj
Definition: uart/v0/uart.h:553
UART_Object::lock
void * lock
Definition: uart/v0/uart.h:541
UART_Object::readCount
uint32_t readCount
Definition: uart/v0/uart.h:521
UART_Params::parityType
uint32_t parityType
Definition: uart/v0/uart.h:439
UART_Object::rxTimeoutCnt
uint32_t rxTimeoutCnt
Definition: uart/v0/uart.h:525
UART_putChar
static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v0/uart.h:1014
UART_Object::writeCount
uint32_t writeCount
Definition: uart/v0/uart.h:512
UART_Params::hwFlowControl
uint32_t hwFlowControl
Definition: uart/v0/uart.h:451
UART_Object::readSizeRemaining
uint32_t readSizeRemaining
Definition: uart/v0/uart.h:523
UART_Params::readReturnMode
uint32_t readReturnMode
Definition: uart/v0/uart.h:443
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v0/uart.h:432
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
UART_Params::baudRate
uint32_t baudRate
Definition: uart/v0/uart.h:433
UART_Params::readCallbackFxn
UART_CallbackFxn readCallbackFxn
Definition: uart/v0/uart.h:447
UART_Object::readErrorCnt
uint32_t readErrorCnt
Definition: uart/v0/uart.h:527
UART_Object::writeTransferSem
void * writeTransferSem
Definition: uart/v0/uart.h:550
UART_Transaction::status
uint32_t status
Definition: uart/v0/uart.h:405
UART_Config::object
UART_Object * object
Definition: uart/v0/uart.h:574
UART_Transaction
Data structure used with UART_read() and UART_write()
Definition: uart/v0/uart.h:395
UART_getBaseAddr
uint32_t UART_getBaseAddr(UART_Handle handle)
UART_LEN_8
#define UART_LEN_8
Definition: uart/v0/uart.h:171
UART_Params::intrNum
uint32_t intrNum
Definition: uart/v0/uart.h:461
UART_Attrs::inputClkFreq
uint32_t inputClkFreq
Definition: uart/v0/uart.h:487
UART_open
UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_Params::writeCallbackFxn
UART_CallbackFxn writeCallbackFxn
Definition: uart/v0/uart.h:449
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:91
UART_Object
UART driver object.
Definition: uart/v0/uart.h:499
UART_Params::hwFlowControlThr
uint32_t hwFlowControlThr
Definition: uart/v0/uart.h:453
UART_Object::readTrans
UART_Transaction * readTrans
Definition: uart/v0/uart.h:532
UART_Params::stopBits
uint32_t stopBits
Definition: uart/v0/uart.h:437
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1182
UART_Object::readBuf
void * readBuf
Definition: uart/v0/uart.h:519
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v0/uart.h:799
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v0/uart.h:269
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v0/uart.h:481
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v0/uart.h:253
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v0/uart.h:485
UART_Transaction::buf
void * buf
Definition: uart/v0/uart.h:396
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1048
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v0/uart.h:557
UART_Object::prms
UART_Params prms
Definition: uart/v0/uart.h:505
UART_Transaction::count
uint32_t count
Definition: uart/v0/uart.h:399
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v0/uart.h:475