AM64x MCU+ SDK
07.03.00
udma_soc.h
Go to the documentation of this file.
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/*
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* Copyright (C) 2018-2021 Texas Instruments Incorporated
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef UDMA_SOC_H_
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#define UDMA_SOC_H_
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/* ========================================================================== */
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/* Include Files */
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/* ========================================================================== */
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/* None */
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#ifdef __cplusplus
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extern
"C"
{
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#endif
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/* ========================================================================== */
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/* Macros & Typedefs */
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/* ========================================================================== */
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#define UDMA_INST_ID_BCDMA_0 (UDMA_INST_ID_2)
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#define UDMA_INST_ID_PKTDMA_0 (UDMA_INST_ID_3)
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#define UDMA_INST_ID_START (UDMA_INST_ID_2)
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#define UDMA_INST_ID_MAX (UDMA_INST_ID_3)
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#define UDMA_NUM_INST_ID (UDMA_INST_ID_MAX - UDMA_INST_ID_START + 1U)
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#define UDMA_SOC_CFG_LCDMA_PRESENT (1U)
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#define UDMA_SOC_CFG_RA_LCDMA_PRESENT (1U)
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#define UDMA_TX_UHC_CHANS_FDEPTH (0U)
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#define UDMA_TX_HC_CHANS_FDEPTH (0U)
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#define UDMA_TX_CHANS_FDEPTH (192U)
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#define UDMA_RINGACC_ASEL_ENDPOINT_PHYSADDR ((uint32_t) 0U)
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#define UDMA_RINGACC_ASEL_ENDPOINT_PCIE0 ((uint32_t) 1U)
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#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_WR_ALLOC ((uint32_t) 14U)
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#define UDMA_RINGACC_ASEL_ENDPOINT_ACP_RD_ALLOC ((uint32_t) 15U)
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#define UDMA_NUM_MAPPED_TX_GROUP (4U)
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#define UDMA_MAPPED_TX_GROUP_CPSW (UDMA_MAPPED_GROUP0)
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#define UDMA_MAPPED_TX_GROUP_SAUL (UDMA_MAPPED_GROUP1)
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#define UDMA_MAPPED_TX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP2)
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#define UDMA_MAPPED_TX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP3)
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#define UDMA_NUM_MAPPED_RX_GROUP (4U)
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#define UDMA_MAPPED_RX_GROUP_CPSW (UDMA_MAPPED_GROUP4)
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#define UDMA_MAPPED_RX_GROUP_SAUL (UDMA_MAPPED_GROUP5)
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#define UDMA_MAPPED_RX_GROUP_ICSSG_0 (UDMA_MAPPED_GROUP6)
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#define UDMA_MAPPED_RX_GROUP_ICSSG_1 (UDMA_MAPPED_GROUP7)
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/*
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* Locally used core ID to define default RM configuration.
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* Not to be used by caller
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*/
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#define UDMA_CORE_ID_MPU1_0 (0U)
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#define UDMA_CORE_ID_MCU2_0 (1U)
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#define UDMA_CORE_ID_MCU2_1 (2U)
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#define UDMA_CORE_ID_MCU1_0 (3U)
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#define UDMA_CORE_ID_MCU1_1 (4U)
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#define UDMA_CORE_ID_M4F_0 (5U)
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/* Total number of cores */
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#define UDMA_NUM_CORE (6U)
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#define UDMA_RM_RES_ID_BC_UHC (0U)
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#define UDMA_RM_RES_ID_BC_HC (1U)
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#define UDMA_RM_RES_ID_BC (2U)
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#define UDMA_RM_RES_ID_TX_UHC (3U)
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#define UDMA_RM_RES_ID_TX_HC (4U)
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#define UDMA_RM_RES_ID_TX (5U)
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#define UDMA_RM_RES_ID_RX_UHC (6U)
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#define UDMA_RM_RES_ID_RX_HC (7U)
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#define UDMA_RM_RES_ID_RX (8U)
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#define UDMA_RM_RES_ID_GLOBAL_EVENT (9U)
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#define UDMA_RM_RES_ID_VINTR (10U)
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#define UDMA_RM_RES_ID_MAPPED_TX_CPSW (11U)
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#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_0 (12U)
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#define UDMA_RM_RES_ID_MAPPED_TX_SAUL_1 (13U)
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#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_0 (14U)
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#define UDMA_RM_RES_ID_MAPPED_TX_ICSSG_1 (15U)
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#define UDMA_RM_RES_ID_MAPPED_RX_CPSW (16U)
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#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_0 (17U)
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#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_1 (18U)
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#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_2 (19U)
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#define UDMA_RM_RES_ID_MAPPED_RX_SAUL_3 (20U)
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#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_0 (21U)
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#define UDMA_RM_RES_ID_MAPPED_RX_ICSSG_1 (22U)
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#define UDMA_RM_RES_ID_MAPPED_TX_RING_CPSW (23U)
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#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_0 (24U)
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#define UDMA_RM_RES_ID_MAPPED_TX_RING_SAUL_1 (25U)
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#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_0 (26U)
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#define UDMA_RM_RES_ID_MAPPED_TX_RING_ICSSG_1 (27U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_CPSW (28U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_0 (29U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_1 (30U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_2 (31U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_SAUL_3 (32U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_0 (33U)
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#define UDMA_RM_RES_ID_MAPPED_RX_RING_ICSSG_1 (34U)
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#define UDMA_RM_NUM_BCDMA_RES (11U)
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#define UDMA_RM_NUM_PKTDMA_RES (35U)
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#define UDMA_RM_NUM_RES (35U)
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#define UDMA_RM_NUM_SHARED_RES (2U)
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#define UDMA_RM_SHARED_RES_MAX_INST (UDMA_NUM_CORE)
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#define UDMA_PSIL_DEST_THREAD_OFFSET (0x8000U)
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#define UDMA_PSIL_CH_CPSW2_RX (0x4500U)
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#define UDMA_PSIL_CH_SAUL0_RX (0x4000U)
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#define UDMA_PSIL_CH_ICSS_G0_RX (0x4100U)
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#define UDMA_PSIL_CH_ICSS_G1_RX (0x4200U)
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#define UDMA_PSIL_CH_CPSW2_TX (UDMA_PSIL_CH_CPSW2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PSIL_CH_SAUL0_TX (UDMA_PSIL_CH_SAUL0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PSIL_CH_ICSS_G0_TX (UDMA_PSIL_CH_ICSS_G0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PSIL_CH_ICSS_G1_TX (UDMA_PSIL_CH_ICSS_G1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PSIL_CH_CPSW2_TX_CNT (8U)
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#define UDMA_PSIL_CH_SAUL0_TX_CNT (2U)
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#define UDMA_PSIL_CH_ICSS_G0_TX_CNT (9U)
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#define UDMA_PSIL_CH_ICSS_G1_TX_CNT (9U)
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#define UDMA_PSIL_CH_CPSW2_RX_CNT (1U)
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#define UDMA_PSIL_CH_SAUL0_RX_CNT (4U)
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#define UDMA_PSIL_CH_ICSS_G0_RX_CNT (5U)
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#define UDMA_PSIL_CH_ICSS_G1_RX_CNT (5U)
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/*
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* PDMA MAIN0 MCSPI RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX (0x4300U + 0U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX (0x4300U + 1U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX (0x4300U + 2U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX (0x4300U + 3U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX (0x4300U + 4U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX (0x4300U + 5U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX (0x4300U + 6U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX (0x4300U + 7U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX (0x4300U + 8U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX (0x4300U + 9U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX (0x4300U + 10U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX (0x4300U + 11U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX (0x4300U + 12U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX (0x4300U + 13U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX (0x4300U + 14U)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX (0x4300U + 15U)
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/*
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* PDMA MAIN0 UART RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN0_UART0_RX (0x4300U + 16U)
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#define UDMA_PDMA_CH_MAIN0_UART1_RX (0x4300U + 17U)
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/*
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* PDMA MAIN0 MCSPI TX Channels
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*/
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI0_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI1_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI2_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_TX (UDMA_PDMA_CH_MAIN0_MCSPI3_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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/*
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* PDMA MAIN0 UART TX Channels
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*/
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#define UDMA_PDMA_CH_MAIN0_UART0_TX (UDMA_PDMA_CH_MAIN0_UART0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN0_UART1_TX (UDMA_PDMA_CH_MAIN0_UART1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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/*
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* PDMA MAIN1 MCSPI RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX (0x4400U + 0U)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX (0x4400U + 1U)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX (0x4400U + 2U)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX (0x4400U + 3U)
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/*
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* PDMA MAIN1 UART RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_UART2_RX (0x4400U + 4U)
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#define UDMA_PDMA_CH_MAIN1_UART3_RX (0x4400U + 5U)
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#define UDMA_PDMA_CH_MAIN1_UART4_RX (0x4400U + 6U)
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#define UDMA_PDMA_CH_MAIN1_UART5_RX (0x4400U + 7U)
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#define UDMA_PDMA_CH_MAIN1_UART6_RX (0x4400U + 8U)
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/*
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* PDMA MAIN1 MCAN RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX (0x4400U + 9U)
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX (0x4400U + 10U)
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX (0x4400U + 11U)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX (0x4400U + 12U)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX (0x4400U + 13U)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX (0x4400U + 14U)
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/*
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* PDMA MAIN1 ADC RX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_ADC0_CH0_RX (0x4400U + 15U)
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#define UDMA_PDMA_CH_MAIN1_ADC0_CH1_RX (0x4400U + 16U)
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/*
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* PDMA MAIN1 MCSPI TX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_TX (UDMA_PDMA_CH_MAIN1_MCSPI4_CH3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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/*
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* PDMA MAIN1 UART TX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_UART2_TX (UDMA_PDMA_CH_MAIN1_UART2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_UART3_TX (UDMA_PDMA_CH_MAIN1_UART3_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_UART4_TX (UDMA_PDMA_CH_MAIN1_UART4_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_UART5_TX (UDMA_PDMA_CH_MAIN1_UART5_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_UART6_TX (UDMA_PDMA_CH_MAIN1_UART6_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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/*
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* PDMA MAIN1 MCAN TX Channels
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*/
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCAN0_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN0_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH0_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH0_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH1_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH1_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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#define UDMA_PDMA_CH_MAIN1_MCAN1_CH2_TX (UDMA_PDMA_CH_MAIN1_MCAN1_CH2_RX | UDMA_PSIL_DEST_THREAD_OFFSET)
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/* ========================================================================== */
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/* Structure Declarations */
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/* ========================================================================== */
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/* None */
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/* ========================================================================== */
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/* Function Declarations */
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/* ========================================================================== */
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uint32_t
Udma_isCacheCoherent
(
void
);
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/* ========================================================================== */
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/* Static Function Definitions */
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/* ========================================================================== */
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/* None */
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#ifdef __cplusplus
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}
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#endif
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#endif
/* #ifndef UDMA_SOC_H_ */
Udma_isCacheCoherent
uint32_t Udma_isCacheCoherent(void)
Returns TRUE if the memory is cache coherent.
source
drivers
udma
soc
am64x
udma_soc.h
generated by
1.8.20