Feature | Module |
UART DMA mode – driver, Sysconfig support and example: uart_echo_dma | drivers |
MCSPI DMA mode – driver, Sysconfig support and example: mcspi_loopback_dma | drivers |
RTI timer driver and example: rti_led_blink | drivers |
SOC driver APIs for Address translation, R5 set frequency, warm reset… | drivers |
MCAN driver features (Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode) | drivers |
Boot time profiling support | drivers |
QSPI SFDP support | drivers |
hsmclient driver for TIFS-MCU support | drivers |
secure IPC notify driver for TIFS-MCU support | drivers |
Cortex-M4 DPL for TIFS-MCU support | drivers |
EPWM Type5 features - driver, Sysconfig support and example | drivers |
EPWM: Sysconfig support for HRPWM | drivers |
FSI DMA driver support and example: fsi_loopback_dma, FSI TX delay line API | drivers |
ADC Differential Mode example, ADC burst mode oversampling example, ADC Odd Channel Selection | drivers |
Ramp wave and random voltage examples for DAC peripheral | drivers |
32 Task Priority Levels for FreeRTOS Tasks | DPL, FreeRTOS |
CpuId and Queue implementation | DPL |
CPSW Enhaced Scheduled Traffic (EST) support | networking |
Enet - CPDMA multiple channel support, example | networking |
ENET sysconfig support | networking |
C++ build support and example: hello_world_cpp | build |
Real time serial monitor | tools |
AM263x LaunchPad support | board/EVM support |
Refer here for information about using this release with E2 revision of ControlCard and LaunchPad
Peripheral | Supported CPUs | SysConfig Support | DMA Supported | Key features tested | Key features not tested / NOT supported |
ADC | R5F | YES | Yes. Example: adc_soc_continuous_dma | Single software triggered conversion, Multiple ADC trigger using PWM, Result read using DMA, EPWM trip through PPB limit, burst mode oversampling, differential mode | - |
Bootloader | R5F | YES | Yes. DMA enabled for SBL QSPI | Boot modes: QSPI, UART. All R5F's | - |
CMPSS | R5F | YES | NA | Asynchronous PWM trip | - |
CPSW | R5F | YES | No | MAC loopback, PHY loopback, LWIP: Getting IP, Ping, Iperf, Layer 2 MAC, Layer 2 PTP Timestamping and CPSW Switch support | - |
DAC | R5F | YES | Yes. Example: dac_sine_dma | Constant voltage, Square wave generation, Sine wave generation with and without DMA, Ramp wave generation, Random Voltage generation | - |
ECAP | R5F | YES | No | ECAP APWM mode, PWM capture | - |
EDMA | R5F | YES | NA | DMA transfer using interrupt and polling mode, QDMA Transfer, Channel Chaining, PaRAM Linking | - |
EPWM | R5F | YES | Yes. Example: epwm_dma | PWM outputs A and B in up-down count mode, Trip zone, Update PWM using EDMA, Valley switching, High resolution time period adjustment, type5 feature | - |
EQEP | R5F | YES | NA | Speed and Position measurement. | Frequency Measurement not tested |
FSI | R5F | YES | Yes. Example: fsi_loopback_dma | RX, TX, polling, interrupt mode, Dma, single lane loopback. | - FSI Spi Mode |
GPIO | R5F | YES | NA | Output, Input and Interrupt functionality | - |
I2C | R5F | YES | No | Controller mode, basic read/write | - |
IPC Notify | R5F | YES | NA | Mailbox functionality, IPC between RTOS/NORTOS CPUs | M4F core |
IPC Rpmsg | R5F | YES | NA | RPMessage protocol based IPC | M4F core |
MCAN | R5F | YES | No | RX, TX, interrupt and polling mode, Corrupt Message Transmission Prevention, Error Passive state, Bus Off State, Bus Monitoring Mode | - |
MCSPI | R5F | YES | Yes. Example: mcspi_loopback_dma | Controller/Peripheral mode, basic read/write, polling, interrupt and DMA mode | - |
MDIO | R5F | YES | NA | Register read/write, link status and link interrupt enable API | - |
MPU Firewall | R5F | YES | NA | Only compiled (Works only on HS-SE device) | - |
PINMUX | R5F | YES | NA | Tested with multiple peripheral pinmuxes | - |
PRUICSS | R5F | YES | NA | Tested with Ethercat FW HAL | - |
QSPI | R5F | YES | Yes. Example: qspi_flash_dma_transfer | Read direct, Write indirect, Read/Write commands, DMA for read | - |
RTI | R5F | YES | No | Counter read, timebase selction, comparator setup for Interrupt, DMA requests | Capture feature, fast enabling/disabling of events not tested |
SDFM | R5F | YES | No | Filter data read from CPU, Filter data read with PWM sync | - |
SOC | R5F | YES | NA | Lock/unlock MMRs, clock enable, set Hz, Xbar configuration, SW Warm Reset, Address Translation | - |
SPINLOCK | R5F | NA | NA | Lock, unlock HW spinlocks | - |
UART | R5F | YES | Yes. Example: uart_echo_dma | Basic read/write at baud rate 115200, polling, interrupt mode | HW flow control not tested, DMA mode not supported |
WATCHDOG | R5F | YES | NA | Reset mode | Interrupt mode |
ID | Head Line | Module | Applicable Releases | Applicable Devices | Resolution/Comments |
MCUSDK-2254 | [SBL] SBL QSPI bootmode is not working with DMA enabled | SBL | 08_02_01 | AM263x | Fixed. EDMA Parameters were configured incorrectly. |
MCUSDK-2703 | Interrupt XBAR instance for FSI is static | FSI | 08_00_03 | AM263x | Fixed. Enabled Dynamic FSI interrupt config. Updated AM263 FSI SysCfg to dynamically configure Interrupt XBAR's |
MCUSDK-3336 | FSI is not functional with clock divider value more than 8 | FSI | 08_02_00 | AM263x | Fixed |
MCUSDK-3398 | Address translation for R5FSS1 is missing | SBL | 08_02_00 | AM263x | Fixed |
MCUSDK-3408 | sbl_uart_uniflash incorrect data writing to flash | SBL | 08_02_01 | AM263x | xModem uses a 1k buffer for the reception of data, and it pads the received data with zeros to make it align with 1 KB. We were using the filesize returned by the xmodem receive API to determine how many bytes to flash. This was causing the extra bytes to get flashed. Added a parameter actual file size in the uniflash header. This parameter will be used to determine how many bytes to flash |
MCUSDK-3436 | QSPI flashing fails with uniflash | QSPI | 08_02_01 | AM263x | The internal pull up's in flash are weak. Enabled pull up's on D2 and D3 pins. |
MCUSDK-3440 | [Errata] USART: Spurious DMA Interrupts | UART | 08_02_01 | AM263x | Workaround: Use power of 2 values for TX/RX FIFO trigger levels (1, 2, 4, 8, 16, and 32). Resolution: UART FIFO trigger level is set to 1 always which is a power of 2. Please find the attached email for more details. |
MCUSDK-3618 | AM263x: ePWM_setPhaseShift() API function doesn't correctly configure TBPHS | EPWM | 08_02_00 | AM263x | EPWM_setPhaseShift() uses 16-bit read/write, but TBPHS is a 32-bit register. Hence EPWM_setPhaseShift() doesn't take effect. Problem is resolved in 32-bit read/write is used instead of 16-bit read/write. |
MCUSDK-3712 | [FSI]Maximum value of external inputs for triggering frame transmission is limited to 32 | FSI | 08_02_01 | AM263x | Updated FSI_TX_MAX_NUM_EXT_TRIGGERS to correct value i.e. 64 |
MCUSDK-3747 | Comments in R5F linker command file templates contradict SDK docs | Common | 08_02_01 | AM263x | Updated the comment and documentation to reflect the correct Interrupt nesting support |
MCUSDK-3773 | Enet LWIP example fails with SBL on AM263X-LP | SBL, LWIP | 08_02_01 | AM263x | Increased the memory region for updated Descriptor memory |
MCUSDK-3774 | Multi Core application with SBL QSPI DMA enabled is failing on AM263X-LP | EDMA, IPC_Notify, SBL | 08_02_01 | AM263x | For R5SS0-1 core, 0x8000 is the address where reset vectors needs to be copied. But in SBL QSPI with DMA enabled, actual physical address need to be passed while copying reset vectors via EDMA. During SBL execution R5SS0-0 core runs in Lockstep mode so Virtual to Physical Address calculation need to use LockStep TCM Size i.e. 64KB but only 32KB(R5SS0-0) is used.Updated this API. |
MCUSDK-3804 | SDFM: API doc/comments: Valid value macros have unexpected CSL_ prefix | SDFM | 08_02_00 | AM263x | Fixed. Removed unwanted CSL_ prefix used in the documentation/comments for SDFM macros |
MCUSDK-3823 | Wrong boot mode documentation for LP | Docs | 08_02_01 | AM263x | Boot mode switch setting not consistent in LP and CC. Fixed BOOT MODE documentation in Getting Started -> EVM Setup page. |
MCUSDK-3847 | am263x: cpsw: Ethernet cable disconnect not working | CPSW | 08_02_01 | AM263x | Rootcase: CPSW driver disables PHY state machine ticks once link is up. The driver relies on MDIO link monitoring to detect when cable is disconnected and reenables the PHY state machine in order to be able to detect new link partners.
While MDIO link monitor was enabled at MDIO level, the MDIO event still needed to be enabled in CPSW wrapper but it was not. This caused that cable disconnect/connect events were not detected.
Fix: Added MDIO events to CPSW wrapper event mask.
|
MCUSDK-3854 | docs - Elaborate why mailbox init needs to be done by SBL/GEL | MAILBOX | 08_02_01 | AM263x | Updated the documentation/comment |
MCUSDK-3864 | DAC: Incorrect reference voltage selection macros | DAC | 08_02_01 | AM263x | Fixed. enum DAC_ReferenceVoltage is now corrected with "DAC_REF_VREF and DAC_REF_VDDA" from "DAC_REF_VDAC and DAC_REF_ADC_VREFHI" |
MCUSDK-3879 | DPL : Inconsistent MPU config for shared memory across SOC's | DPL | 08_02_01 | AM263x | Accidentally used Strong Ordered attribute instead of Non Cached attribute for shared memory. Updated all example.syscfg files. |
MCUSDK-3888 | The attribute structure generated is not proper when the channel numbers 0 to 15 are not allocated and channels between 16 to 31 are allocated from gui. | EDMA | 08_02_01 | AM263x | Fixed |
MCUSDK-3896 | [RCM]MSS_RCM.R5SSx_POR_RST_CTRL0 source is missing from the R5FSS internal reset list | SOC RCM | 08_02_01 | AM263x | Added missing reset cause SOC_RcmResetCause_POR_RST_CTRL0 |
MCUSDK-3909 | Enet - examples sysconfig has Enet config missing | ENET | 08_02_01 | AM263x | Networking component missing from product.json Added networking as component in product.json |
MCUSDK-3930 | DAC Sysconfig: Incorrect argument passed to DAC_setPWMSyncSignal results in ASSERT | DAC | 08_02_01 | AM263x | Fixed. Sysconfig scripts fixed to pass correct argument (1-32 for EPWM0-EPWM31) as per the DAC_setPWMSyncSignal requirement |
MCUSDK-3932 | docs - fix e2e support forum link in SDK user guide | docs | 08_02_01 | AM263x | Updated the link in doc |
MCUSDK-3939 | networking: layer2_multichannel example only transmits 16 packets | networking | 08_02_01 | AM263x | tx queue for PTP traffic was not handled properly |
MCUSDK-3947 | [MCAN]MCAN message acceptance filter masking is incorrect | MCAN | 08_00_00 | AM263x | Fixed |
MCUSDK-3949 | DAC Driver abort on 8.2 SDK | DAC | 08_02_01 | AM263x | The Reset APIs were writing 0x7 to the respective control registers. but not 0x0 back. |
MCUSDK-4015 | AM263x: FSI functional clock not properly selected | FSI | 08_02_00 | AM263x | Fixed |
MCUSDK-4026 | SDFM: SDFM_configCompEventHighFilter writing to incorrect registers | SDFM | 08_02_01 | AM263x | Fixed SDFM_SDFIL_OFFSET -> SDFM_DIGFIL_OFFSET in SDFM_configCompEventLowFilter and SDFM_configCompEventHighFilter |
MCUSDK-4047 | Crossbar: Incorrect DMA XBAR macros for FSI triggers | XBAR | 08_02_01 | AM263x | Updated the DMA XBAR Macros with correct names and values. |
MCUSDK-4056 | am263x: enet: CPSW EST timestamp checks are incorrect after EST disable | ENET | 08_02_01 | AM263x | The CPSW EST example application performs a check on the EST timestamps generated for transmitted packets by testing whether or not the packet was transmitted in the correct EST window.
For this mechanism to work, it's critical to have an accurate ESTF start time. This can be ensured by starting ESTF at a future time, which the application enforces by setting the first admin base time to be currentTime + ENET_APP_EST_ADMIN_LIST_DELAY (100 msecs).
After this initial EST schedule is cleared (i.e. explicitly cleared by user via app menu or when link is lost), it's no longer possible for the application to ensure that an admin base time at future time will be configured. The user can program a new EST schedule and re-enable EST via two different app menu options, but starting ESTF at a future time cannot be effectively enforced anymore as it would depend on timing of user interaction.
So, the timestamp verification mechanism will be disabled after the initial EST schedule is cleared.
Resolution: Disable EST timestamp check if user enters a new EST schedule via app menu.
|
MCUSDK-4070 | SOC driver: ICSS GPI MUX selection API | SOC | 08_02_01 | AM263x | Added SOC API for ICSS GPI MUX selection |
MCUSDK-4071 | ICSS CSL - remove unsupported features (PWM) | ICSS | 08_02_01 | AM263x | Updated CSLR file with PWM macros removed |
MCUSDK-4072 | SDFM: Incorrect naming used for input macros to SDFM_enableInterrupt API | SDFM | 08_02_01 | AM263x | Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT changed to SDFM_CEVT2_INTERRUPT SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT changed to SDFM_CEVT1_INTERRUPT |
MCUSDK-4112 | ECAP: ECAP_setSyncInPulseSource has incorrect parameter documentation | ECAP | 08_02_01 | AM263x | Fixed supported values of source (type ECAP_SyncInPulseSource) argument to ECAP_setSyncInPulseSource |
MCUSDK-4113 | ECAP: Remove V2 from AM263x MCUSDK package | ECAP | 08_02_01 | AM263x | Excluded ECAP v2 from package |
MCUSDK-4334 | EPWM Trip preprocessor define not included in SDK | EPWM | 08_02_01 | AM263x | Incorrect description in TRM/register spec. Assumed compatible with C2000 and missed a macro in EPWM driver for TripInput 13 selection Added missing macro in EPWM driver for TripInput 13 selection |
MCUSDK-4339 | [pre-release testing] UDP test failure in LWIP example | networking | 08_02_01 | AM263x | UDP lite mode was enabled so udp ifperf was not working properly Disabled UDP lite mode |
MCUSDK-4190 | A fixed MAC address is hard-coded for CPDMA devices, this will cause issue when two boards are connected in the same network | ENET | 08_03_00 | AM263x | Reading MAC address from EFuse and Eeprom instead of fixed hardcoded MAC Address. |
ID | Head Line | Module | Reported in release | Workaround |
MCUSDK-1016 | Semaphore does not function as expected when "post" call is present in multiple ISRs at different priorities | DPL, FreeRTOS | 08_00_03 | Disable interrupt nesting |
MCUSDK-2294 | GPIO Pin Direction | GPIO. GPIO Pin Direction not getting automatically configured. | 08_00_02 | Use GPIO_setDirMode to set pin direction for GPIO pin. |
MCUSDK-2464 | ADC sysconfig code generation issue | ADC | 08_00_03 | - |
MCUSDK-2557 | eqep_frequency_measurement example is failing | SBL | 08_02_00 | - |
MCUSDK-3869 | AM263x - LwIP ICMP tests fails | Enet, LWIP | 08_02_00 | - |
MCUSDK-3886 | MDIO - Phy link issue for MAC PORT 1 on am263x-lp | Enet, LWIP | 08_02_00 | Issue summary: CPSW and ICSSG test cases fail to transfer packets due to PHY getting stuck.
Impacted boards : AM263x_LP E1 and AM263x_LP E2. Both PORT 1 and PORT 2.
Reproducibility: 100% reproducible on ICSS unit test. CPSW example tests shown failures only in long run tests (8+ hrs).
Root cause: MDIO IO and CLK lines had overshoot/undershoot that is more than the allowed margin, resulted in PHY getting hung.
Fix: Replace the MDIO IO and CLK lines termination resistors (R71, R72, R61, R62) of 0 Ohm with 33 Ohm resistor.
|
MCUSDK-4050 | Long delay before and after the MCSPI data transfer | MCSPI | 08_02_00 | None |
MCUSDK-4059 | AM263x: FSI first frame transmitted is incorrect in DMA mode | FSI | 08_03_00 | Please refer fsi_loopback_dma example. |
MCUSDK-4234 | FSI RX Generic Trigger Test is not working | FSI | 08_03_00 | - |
MCUSDK-4345 | EDMA: Region interrupt not triggered if Channel Id and TCC are not equal | EDMA | 08_02_00 | - |
MCUSDK-4437 | [AM263x] : Changing the order of Bootloader_loadCpu in SBL can lead to incorrect behaviour | SBL | 08_02_00 | - |
MCUSDK-4506 | DPL: interrupt_prioritization example for FreeRTOS fails | DPL | 08_03_00 | None. Interrupt nesting for FreeRTOS is disabled to fix UDP test failure in LWIP example |
SITARAAPPS-2040 | Dual Core configuration issue with CSP 1.1.3 (Sitara MCU Device Support) on AM263x | CSP Gel Scripts | 08_02_01 | Edit gel file as mentioned in Prerequisites while running multi core applications. |