AM263Px MCU+ SDK: resolver.h Source File

| AM263Px MCU+ SDK 26.00.00 |

resolver/v0/resolver.h
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1 /*
2 * Copyright (C) 2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
42 #ifndef RESOLVER_V1_H_
43 #define RESOLVER_V1_H_
44
45 //*****************************************************************************
46 //
47 // If building with a C++ compiler, make all of the definitions in this header
48 // have a C binding.
49 //
50 //*****************************************************************************
51 #ifdef __cplusplus
52 extern "C"
53 {
54 #endif
55
56 //*****************************************************************************
57 //
59 //
60 //*****************************************************************************
61 #include <stdint.h>
62 #include <stdbool.h>
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
65 #include <kernel/dpl/DebugP.h>
66 #include <drivers/hw_include/cslr_resolver.h>
67 #include <kernel/dpl/SystemP.h>
68
69 //*****************************************************************************
70 //
71 // Defines for the API.
72 //
73 //*****************************************************************************
74 //*****************************************************************************
75 //
77 //
78 //*****************************************************************************
79 #define RDC_CORE_OFFSET (CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_1 - CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0)
80
83 #define RDC_EXCITATION_FREQUENCY_MIN_PHASE (0U)
84
86 #define RDC_EXCITATION_FREQUENCY_MAX_PHASE (7999U)
87
90 #define RDC_MAX_EXCITATION_AMPLITUDE (249U)
91
94 #define RDC_RESOLVER_CORE0 (0U)
95
97 #define RDC_RESOLVER_CORE1 (1U)
98
102 #define RDC_ADC_CAL_CHANNEL0 (0U)
103 #define RDC_ADC_CAL_CHANNEL1 (1U)
104 #define RDC_ADC_CAL_CHANNEL2 (2U)
105 #define RDC_ADC_CAL_CHANNEL3 (3U)
106 #define RDC_ADC_CAL_CHANNEL_CAL2 (4U)
107 #define RDC_ADC_CAL_CHANNEL_CAL3 (5U)
108 #define RDC_ADC_CAL_CHANNEL_CAL0 (6U)
109 #define RDC_ADC_CAL_CHANNEL_CAL1 (7U)
110
111
112 #define RDC_DC_OFFSET_SIN_ESTIMATION (0U)
113 #define RDC_DC_OFFSET_COS_ESTIMATION (1U)
114
115
116 #define RDC_MIN_IDEAL_SAMPLE_PEAK_AVG_LIMIT (0U)
117 #define RDC_MAX_IDEAL_SAMPLE_PEAK_AVG_LIMIT (7U)
118
119 #define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST (0x0000001FU)
120
121 #define RDC_SINGALMODE_SINGLE_ENDED (0U)
122 #define RDC_SINGALMODE_DIFFERENTIAL_ENDED (1U)
123
124
125 //*****************************************************************************
126 //
130 //
131 //*****************************************************************************
134 #define RDC_ADC_BURST_COUNT_DISABLE (1U)
135
137 #define RDC_ADC_BURST_COUNT_2 (2U)
138
140 #define RDC_ADC_BURST_COUNT_4 (4U)
141
143 #define RDC_ADC_BURST_COUNT_8 (8U)
144
146 #define RDC_ADC_BURST_COUNT_16 (16U)
147
149 #define RDC_ADC_BURST_COUNT_32 (32U)
150
151
152 //*****************************************************************************
153 //
157 //
159 //
160 //*****************************************************************************
164 #define RDC_SEQUENCER_MODE_0 (0U)
165
168 #define RDC_SEQUENCER_MODE_1 (1U)
169
173 #define RDC_SEQUENCER_MODE_2 (2U)
174
181 #define RDC_SEQUENCER_MODE_3 (3U)
182
189 #define RDC_SEQUENCER_MODE_4 (4U)
190
196 #define RDC_SEQUENCER_MODE_5 (5U)
197
198
199 //*****************************************************************************
200 //
204 //
206 //
207 //*****************************************************************************
210 #define RDC_EXCITATION_FREQUENCY_5K (50)
211
213 #define RDC_EXCITATION_FREQUENCY_10K (100)
214
216 #define RDC_EXCITATION_FREQUENCY_20K (200)
217
218
219 //*****************************************************************************
220 //
224 //
226 //
227 //*****************************************************************************
232 #define OVERSAMPLING_RATIO_16 (8)
233
237 #define OVERSAMPLING_RATIO_20 (10)
238
239 //*****************************************************************************
240 //
245 //
248 //
249 //*****************************************************************************
254 #define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR (0x00000001U)
255 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR (0x00000002U)
256 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR (0x00000004U)
257 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR (0x00000008U)
258 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR (0x00000010U)
259 #define RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR (0x00000020U)
260 #define RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR (0x00000040U)
261 #define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR (0x00000080U)
262 #define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR (0x00000100U)
263 #define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR (0x00000200U)
264 #define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR (0x00000400U)
265 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR (0x00000800U)
266 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR (0x00001000U)
267 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR (0x00002000U)
268 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR (0x00004000U)
269 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR (0x00008000U)
270 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR (0x00010000U)
271 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR (0x00020000U)
272 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR (0x00040000U)
273 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR (0x00080000U)
274 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR (0x00100000U)
275 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR (0x00200000U)
276 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR (0x00400000U)
277 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR (0x00800000U)
278 #define RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR (0x01000000U)
279
280 #define RDC_INTERRUPT_SOURCE_ALL (RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR | \
281 RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR | \
282 RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR | \
283 RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR | \
284 RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR | \
285 RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR | \
286 RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR | \
287 RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR | \
288 RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR | \
289 RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR | \
290 RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR | \
291 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR | \
292 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR | \
293 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR | \
294 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR | \
295 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR | \
296 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR | \
297 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR | \
298 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR | \
299 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR | \
300 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR | \
301 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR | \
302 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR | \
303 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR | \
304 RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR)
305
306 //*****************************************************************************
307 //
311 //
312 //*****************************************************************************
315 #define RDC_CAL_ADC0 (0U)
316
318 #define RDC_CAL_ADC1 (1U)
319
320 //*****************************************************************************
321 //
325 //
326 //*****************************************************************************
330 #define RDC_IDEAL_SAMPLE_TIME_MODE_0_AUTO_DETECT (0U)
331
334 #define RDC_IDEAL_SAMPLE_TIME_MODE_1_AUTO_DETECT_ON_SIN (1U)
335
338 #define RDC_IDEAL_SAMPLE_TIME_MODE_2_AUTO_DETECT_ON_COS (2U)
339
342 #define RDC_IDEAL_SAMPLE_TIME_MODE_3_AUTO_DETECT_OFF (3U)
343
344 //*****************************************************************************
345 //
349 //
350 //*****************************************************************************
351
356 typedef struct
357 {
358 uint8_t kvelfilt;
359 } Track2Constants_t;
360
361 //*****************************************************************************
362 //
367 //
368 //*****************************************************************************
373 typedef struct
374 {
375 int16_t offset_drift_threshold_hi;
376 int16_t offset_drift_threshold_lo;
377 bool offset_drift_cos_hi;
378 bool offset_drift_cos_lo;
379 bool offset_drift_sin_hi;
380 bool offset_drift_sin_lo;
381 bool offset_drift_en;
382 } Diag_Mon_SinCos_Offset_drift_data;
383
384 //*****************************************************************************
385 //
390 //
391 //*****************************************************************************
396 typedef struct
397 {
398 uint16_t gain_drift_threshold_hi;
399 uint16_t gain_drift_threshold_lo;
400 uint8_t gain_drift_glitch_count;
401 bool gain_drift_cos_hi;
402 bool gain_drift_cos_lo;
403 bool gain_drift_sin_hi;
404 bool gain_drift_sin_lo;
405 bool gain_drift_en;
406 } Diag_Mon_SinCos_Gain_drift_data;
407
408 //*****************************************************************************
409 //
414 //
415 //*****************************************************************************
420 typedef struct
421 {
422 int16_t phase_drift_threshold_hi;
423 int16_t phase_drift_threshold_lo;
424 uint8_t phase_drift_glitch_count;
425 bool phase_drift_cos_hi;
426 bool phase_drift_cos_lo;
427 bool phase_drift_en;
428 } Diag_Mon_Cos_Phase_drift_data;
429
430 //*****************************************************************************
431 //
436 //
437 //*****************************************************************************
442 typedef struct
443 {
444 uint16_t excfreqdetected_sin;
445 uint16_t excfreqdetected_cos;
446 uint16_t excfreqdrift_threshold_hi;
447 uint16_t excfreqdrift_threshold_lo;
448 uint16_t excfreq_level;
449 uint8_t excfreqdrift_glitchcount;
450 bool excfreqdrift_hi;
451 bool excfreqdrift_cos_lo;
452 bool excfreqdrift_sin_lo;
453 bool excfreqdrift_en;
454 } Diag_Mon_ExcFreq_Degradataion_data;
455
456 //*****************************************************************************
457 //
462 //
463 //*****************************************************************************
468 typedef struct
469 {
470 bool cos_neg_zc_peak_mismatch_err;
471 bool cos_pos_zc_peak_mismatch_err;
472 bool sin_neg_zc_peak_mismatch_err;
473 bool sin_pos_zc_peak_mismatch_err;
474 bool sin_multi_zc_error_err;
475 bool cos_multi_zc_error_err;
476 uint8_t cos_multi_zc_error_count;
477 uint8_t sin_multi_zc_error_count;
478 uint16_t rotpeak_level;
479 uint16_t rotfreq_level;
480 bool zero_cross_rot_en;
481 } Diag_Mon_Rotational_Signal_Integrity_data;
482
483
484 //*****************************************************************************
485 //
490 //
491 //*****************************************************************************
496 typedef struct
497 {
498 uint16_t sinsqcossq_threshold_hi;
499 uint16_t sinsqcossq_threshold_lo;
500 uint8_t sinsqcossq_glitchcount;
501 uint16_t sinsqcossq_cossq;
502 uint16_t sinsqcossq_sinsq;
503 bool sinsqcossq_hi;
504 bool sinsqcossq_lo;
505 } Diag_Mon_Signal_Integrity_SinSq_CosSq;
506
507 //*****************************************************************************
508 //
513 //
514 //*****************************************************************************
519 typedef struct
520 {
521 uint16_t highAmplitude_threshold;
522 uint8_t highAmplitude_glitchcount;
523 int16_t highAmplitude_sin_value;
524 int16_t highAmplitude_cos_value;
525 bool highAmplitude_sin_error;
526 bool highAmplitude_cos_error;
527 } Diag_Mon_Sin_Cos_High_Amplitude;
528
529 //*****************************************************************************
530 //
535 //
536 //*****************************************************************************
541 typedef struct
542 {
543 uint16_t lowAmplitude_threshold;
544 uint8_t lowAmplitude_glitchcount;
545 bool lowAmplitude_error;
546 int16_t lowAmplitude_sin_value;
547 int16_t lowAmplitude_cos_value;
548 } Diag_Mon_Sin_Cos_Weak_Amplitude;
549
550
551 //*****************************************************************************
552 //
557 //
558 //*****************************************************************************
570 typedef struct
571 {
572 int16_t cos_adc;
573 int16_t sin_adc;
574 int16_t cos_rec;
575 int16_t sin_rec;
576 int16_t cos_dc;
577 int16_t sin_dc;
578 int16_t cos_pgc;
579 int16_t sin_pgc;
580 } ADC_observationalData;
581
582
588 typedef struct
589 {
590 bool BpfDc_bpfEnable;
591 bool BpfDc_offsetCorrectionEnable;
592 uint8_t BpfDc_dcOffCal1;
593 uint8_t BpfDc_dcOffCal2;
594 int16_t BpfDc_manualSin;
595 int16_t BpfDc_manualCos;
596
597 uint8_t IdealSample_overrideValue;
598 uint16_t IdealSample_absThresholdValue;
599 uint8_t IdealSample_sampleAdjustCount;
600 uint8_t IdealSample_mode;
601 bool IdealSample_bottomSampleEnable;
602
603 bool Pg_estimationEnable;
604 uint8_t Pg_estimationLimit;
605
606 bool Pg_correctionEnable;
607 bool Pg_autoCorrectionEnable;
608 uint16_t Pg_sinGainBypassValue;
609 uint16_t Pg_cosGainBypassValue;
610 int16_t Pg_cosPhaseBypassValue;
611
612 Track2Constants_t track2Constants;
613 }Core_config_t;
614
622 typedef struct
623 {
624 bool adv_config;
625 uint8_t Input_signalMode;
626 uint8_t Input_socWidth;
627 uint8_t Input_adcBurstCount;
628 uint8_t Input_resolverSequencerMode;
629
630 uint8_t ExcFrq_freqSel;
631 uint16_t ExcFrq_phase;
632 uint8_t ExcFrq_amplitude;
633 bool ExcFrq_enableSyncIn;
634 uint16_t ExcFrq_socDelay;
635
636 Core_config_t core0;
637 Core_config_t core1;
638
639 bool Int_seqEnable;
640 uint32_t Int_core0Interrupts;
641 uint32_t Int_core1Interrupts;
642
643 }RDC_configParams;
644
650 typedef struct
651 {
652 uint8_t adcParam1;
653 uint8_t IdealParam2;
654 uint8_t DcParam3;
655 uint16_t PgParam4;
656 uint8_t t2Param5;
657 uint8_t t2Param6;
658 uint8_t t2Param7;
659 uint8_t t2Param8;
660 bool t2Param9;
661 }baselineParameters;
662
663 //*****************************************************************************
664 //
668 //
669 //*****************************************************************************
676 typedef struct
677 {
678 uint8_t peakHistgoramBucket[20];
679 }PeakHistogram_observationalData;
680
681 //*****************************************************************************
682 // GLOBAL CONFIGURATIONS
683 //*****************************************************************************
690 static inline void
691 RDC_setAdcSocWidth(uint32_t base, uint8_t socWidth)
692 {
693 HW_WR_REG32(
694 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
695 (HW_RD_REG32(
696 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
697 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_MASK) |
698 (((uint8_t)socWidth) << CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_SHIFT));
699 }
700
707 static inline uint8_t
708 RDC_getConfiguredAdcSocWidth(uint32_t base)
709 {
710 return (
711 (uint8_t) ((HW_RD_REG32(base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
712 CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_MASK) >> CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_SHIFT));
713 }
714
728 static inline void
729 RDC_setAdcBurstCount(uint32_t base, uint8_t burstCount)
730 {
731 HW_WR_REG32(
732 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
733 (HW_RD_REG32(
734 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
735 ~CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_MASK) |
736 ((uint32_t)(((uint8_t)burstCount) << CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_SHIFT)));
737 }
738
751 static inline uint8_t
752 RDC_getConfiguredAdcBurstCount(uint32_t base)
753 {
754 return(
755 (uint8_t) ((HW_RD_REG32(base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
756 CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_MASK) >> CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_SHIFT)
757 );
758 }
759
766 static inline void
767 RDC_enableAdcSingleEndedMode(uint32_t base)
768 {
769 HW_WR_REG32(
770 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
771 (HW_RD_REG32(
772 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
773 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK) |
774 ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_SHIFT)));
775 }
776
783 static inline void
784 RDC_disableAdcSingleEndedMode(uint32_t base)
785 {
786 HW_WR_REG32(
787 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
788 (HW_RD_REG32(
789 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
790 ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK));
791 }
792
800 static inline bool
801 RDC_isAdcSingleEndedModeEnabled(uint32_t base)
802 {
803 return (
804 (HW_RD_REG32(base + CSL_RESOLVER_REGS_GLOBAL_CFG) & CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK) == CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK
805 );
806 }
807
808
827 static inline uint32_t
828 RDC_getAdcSequencerOperationalMode(uint32_t base)
829 {
830 return ((HW_RD_REG32(
831 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
832 CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) >>
833 CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT);
834 }
835
855 static inline void
856 RDC_setAdcSequencerOperationalMode(uint32_t base, uint8_t operationalMode)
857 {
858 DebugP_assert(
859 (operationalMode >= RDC_SEQUENCER_MODE_0) &&
860 (operationalMode <= RDC_SEQUENCER_MODE_5));
861
862 HW_WR_REG32(
863 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
864 (HW_RD_REG32(
865 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
866 ~CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) |
867 ((uint32_t)((operationalMode) << CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT)));
868 }
875 static inline void
876 RDC_enableResolver(uint32_t base)
877 {
878 HW_WR_REG32(
879 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
880 (HW_RD_REG32(
881 base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
882 ~CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) |
883 ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
884 }
891 static inline void
892 RDC_disableResolver(uint32_t base)
893 {
894 HW_WR_REG32(
895 base + CSL_RESOLVER_REGS_GLOBAL_CFG,
896 (HW_RD_REG32(
897 base + CSL_RESOLVER_REGS_GLOBAL_CFG) |
898 CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) &
899 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
900 }
901
909 static inline bool
910 RDC_isResolverEnabled(uint32_t base)
911 {
912 return (
913 (HW_RD_REG32(base + CSL_RESOLVER_REGS_GLOBAL_CFG) & CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) == CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK
914 );
915 }
916
917 //*****************************************************************************
918 // EXCITATION FREQUENCY AND SAMPLING CONFIGURATIONS
919 //*****************************************************************************
920
928 static inline void
929 RDC_setExcitationSignalPhase(uint32_t base, uint16_t phase)
930 {
931 DebugP_assert(
932 (phase >= RDC_EXCITATION_FREQUENCY_MIN_PHASE) && (phase <= RDC_EXCITATION_FREQUENCY_MAX_PHASE));
933 HW_WR_REG32(
934 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
935 (HW_RD_REG32(
936 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
937 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) |
938 ((uint32_t)(phase << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT)));
939 }
940
948 static inline uint32_t
949 RDC_getExcitationSignalPhase(uint32_t base)
950 {
951 return (
952 (HW_RD_REG32(
953 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
954 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) >>
955 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT);
956 }
957
967 static inline void
968 RDC_setExcitationSignalFrequencySelect(uint32_t base, uint8_t FrequencySel)
969 {
970 DebugP_assert(
971 (FrequencySel == RDC_EXCITATION_FREQUENCY_5K) ||
972 (FrequencySel == RDC_EXCITATION_FREQUENCY_10K) ||
973 (FrequencySel == RDC_EXCITATION_FREQUENCY_20K));
974 HW_WR_REG32(
975 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
976 (HW_RD_REG32(
977 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
978 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) |
979 ((uint32_t)(FrequencySel << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT)));
980 }
981
991 static inline uint32_t
992 RDC_getExcitationSignalFrequencySelect(uint32_t base)
993 {
994 return (
995 (HW_RD_REG32(
996 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
997 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) >>
998 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT);
999 }
1000
1007 static inline uint32_t
1008 RDC_getAdcSampleRate(uint32_t base)
1009 {
1010 return (
1011 (HW_RD_REG32(
1012 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
1013 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_MASK) >>
1014 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_SHIFT);
1015 }
1016
1022 static inline void
1023 RDC_enableExcitationSignalSyncIn(uint32_t base)
1024 {
1025 HW_WR_REG32(
1026 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1027 (HW_RD_REG32(
1028 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1029 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) |
1030 ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
1031 }
1032
1038 static inline void
1039 RDC_disableExcitationSignalSyncIn(uint32_t base)
1040 {
1041 HW_WR_REG32(
1042 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1043 (HW_RD_REG32(
1044 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) |
1045 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) &
1046 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
1047 }
1048
1056 static inline bool
1057 RDC_isExcitationSignalSyncInEnabled(uint32_t base)
1058 {
1059 return((HW_RD_REG32(base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1060 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) == CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK);
1061 }
1062
1073 static inline uint32_t
1074 RDC_getExcitationSignalEventStatus(uint32_t base)
1075 {
1076 return (
1077 (HW_RD_REG32(
1078 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1079 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) >>
1080 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT);
1081 }
1082
1088 static inline void
1089 RDC_clearExcitationSignalEventStatus(uint32_t base)
1090 {
1091 HW_WR_REG32(
1092 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1093 (HW_RD_REG32(
1094 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1095 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) |
1096 ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT)));
1097 }
1098
1106 static inline uint32_t
1107 RDC_getExcitationSignalPhaseInfo(uint32_t base)
1108 {
1109 return (
1110 (HW_RD_REG32(
1111 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1112 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_MASK) >>
1113 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_SHIFT);
1114 }
1115
1122 static inline void
1123 RDC_setExcitationSignalSocDelay(uint32_t base, uint16_t socDelay)
1124 {
1125 HW_WR_REG32(
1126 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1127 (HW_RD_REG32(
1128 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1129 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_MASK) |
1130 ((uint32_t)(socDelay << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_SHIFT)));
1131 }
1132
1139 static inline uint16_t
1140 RDC_getConfiguredExcitationSignalSocDelay(uint32_t base)
1141 {
1142 return(
1143 (uint16_t) ((HW_RD_REG32(base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1144 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_MASK) >> CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_SHIFT)
1145 );
1146 }
1147
1148
1149
1156 static inline void
1157 RDC_setExcitationSignalAmplitudeControl(uint32_t base, uint8_t amplitude)
1158 {
1159 DebugP_assert(amplitude <= RDC_MAX_EXCITATION_AMPLITUDE);
1160 HW_WR_REG32(
1161 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3,
1162 (HW_RD_REG32(
1163 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1164 ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) |
1165 ((uint32_t)(amplitude << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT)));
1166 }
1167
1174 static inline uint32_t
1175 RDC_getExcitationSignalAmplitudeControl(uint32_t base)
1176 {
1177 return (
1178 (HW_RD_REG32(
1179 base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1180 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) >>
1181 CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT);
1182 }
1183
1184 //*****************************************************************************
1185 // INTERRUPT CONFIGURATIONS
1186 //*****************************************************************************
1187
1193 static inline void
1194 RDC_enableSequencerInterrupt(uint32_t base)
1195 {
1196 HW_WR_REG32(
1197 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1198 (HW_RD_REG32(
1199 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1200 ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1201 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1202 }
1203
1209 static inline void
1210 RDC_disableSequencerInterrupt(uint32_t base)
1211 {
1212 HW_WR_REG32(
1213 base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS,
1214 (HW_RD_REG32(
1215 base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS) &
1216 ~CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_MASK) |
1217 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_SHIFT)));
1218 }
1219
1226 static inline bool
1227 RDC_isSequencerInterruptEnabled(uint32_t base)
1228 {
1229 return((HW_RD_REG32(base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) & CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) == CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK);
1230 }
1231
1237 static inline void
1238 RDC_clearSequencerInterrupt(uint32_t base)
1239 {
1240 HW_WR_REG32(
1241 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1242 (HW_RD_REG32(
1243 base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1244 ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1245 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1246 }
1247
1253 static inline void
1254 RDC_forceSequencerInterrupt(uint32_t base)
1255 {
1256 HW_WR_REG32(
1257 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS,
1258 (HW_RD_REG32(
1259 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1260 ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1261 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1262 }
1263
1269 static inline uint32_t
1270 RDC_getSequencerInterruptStatus(uint32_t base)
1271 {
1272 return (
1273 (HW_RD_REG32(
1274 base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1275 ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1276 ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1277 }
1278
1286 static inline void
1287 RDC_enableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1288 {
1289 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1290 DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1291
1292 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1293
1294 HW_WR_REG32(
1295 base + regOffset,
1296 HW_RD_REG32(
1297 base + regOffset) |
1298 ((uint32_t)interruptSource));
1299 }
1300
1308 static inline uint32_t
1309 RDC_getCoreEnabledInterruptSources(uint32_t base, uint8_t ResolverCore)
1310 {
1311 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1312 return (
1313 HW_RD_REG32(
1314 base + regOffset));
1315 }
1316
1324 static inline void
1325 RDC_disableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1326 {
1327 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1328 DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1329
1330 uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1331
1332 HW_WR_REG32(
1333 base + regOffset,
1334 HW_RD_REG32(
1335 base + regOffset) |
1336 ((uint32_t)interruptSource));
1337 }
1338
1346 static inline void
1347 RDC_clearCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1348 {
1349 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1350 DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1351
1352 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1353
1354 HW_WR_REG32(
1355 base + regOffset,
1356 (HW_RD_REG32(
1357 base + regOffset) &
1358 ~((uint32_t)RDC_INTERRUPT_SOURCE_ALL)) |
1359 interruptSource);
1360 }
1361
1369 static inline void
1370 RDC_forceCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1371 {
1372 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1373 DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1374
1375 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1376
1377 HW_WR_REG32(
1378 base + regOffset,
1379 (HW_RD_REG32(
1380 base + regOffset) &
1381 ~((uint32_t)RDC_INTERRUPT_SOURCE_ALL)) |
1382 interruptSource);
1383 }
1384
1391 static inline uint32_t
1392 RDC_getCoreInterruptStatus(uint32_t base, uint32_t ResolverCore)
1393 {
1394 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1395
1396 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1397
1398 return (
1399 (HW_RD_REG32(
1400 base + regOffset) &
1401 ((uint32_t)RDC_INTERRUPT_SOURCE_ALL)));
1402 }
1403
1410 static inline uint32_t
1411 RDC_getCoreInterruptSources(uint32_t base, uint32_t ResolverCore)
1412 {
1413 DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1414
1415 uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1416
1417 return (
1418 (HW_RD_REG32(
1419 base + regOffset) &
1420 ((uint32_t)RDC_INTERRUPT_SOURCE_ALL)));
1421 }
1422
1423 //*****************************************************************************
1424 // CALIBRATION CONFIGURATIONS
1425 //*****************************************************************************
1426
1433 static inline bool
1434 RDC_getCalibrationStatus(uint32_t base)
1435 {
1436 return (
1437 (((HW_RD_REG32(
1438 base + CSL_RESOLVER_REGS_CAL_CFG) &
1439 CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) >>
1440 CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT) &
1441 (1U)) != 0U);
1442 }
1443
1449 static inline void
1450 RDC_clearCalibrationStatus(uint32_t base)
1451 {
1452 HW_WR_REG32(
1453 base + CSL_RESOLVER_REGS_CAL_CFG,
1454 (HW_RD_REG32(
1455 base + CSL_RESOLVER_REGS_CAL_CFG) &
1456 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) |
1457 ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT)));
1458 }
1459
1474 static inline void
1475 RDC_selectCalibrationChannel(uint32_t base, uint8_t calChannel)
1476 {
1477 HW_WR_REG32(
1478 base + CSL_RESOLVER_REGS_CAL_CFG,
1479 (HW_RD_REG32(
1480 base + CSL_RESOLVER_REGS_CAL_CFG) &
1481 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_MASK) |
1482 ((uint32_t)(calChannel << CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_SHIFT)));
1483 }
1484
1490 static inline void
1491 RDC_enableCalibration(uint32_t base)
1492 {
1493 HW_WR_REG32(
1494 base + CSL_RESOLVER_REGS_CAL_CFG,
1495 (HW_RD_REG32(
1496 base + CSL_RESOLVER_REGS_CAL_CFG) &
1497 ~CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_MASK) |
1498 ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_SHIFT)));
1499 }
1500
1508 static inline uint16_t
1509 RDC_getCalibrationData(uint32_t base, uint8_t CalAdc)
1510 {
1511 uint32_t regData = HW_RD_REG32(
1512 base + CSL_RESOLVER_REGS_CAL_OBS) &
1513 (CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK |
1514 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK);
1515 if (CalAdc == RDC_CAL_ADC0)
1516 {
1517 return ((uint16_t)((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK) >>
1518 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_SHIFT));
1519 }
1520 return ((uint16_t)((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK) >>
1521 CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_SHIFT));
1522 }
1523
1524 //*****************************************************************************
1525 // DC OFFSET AND BAND PASS FILTER CONFIGURATIONS
1526 //*****************************************************************************
1527
1537 static inline void
1538 RDC_setDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t coef1, uint8_t coef2)
1539 {
1540 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1541 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1542 uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_MASK |
1543 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_MASK);
1544
1545 uint32_t value = (coef1 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_SHIFT) |
1546 (coef2 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_SHIFT);
1547 value &= mask;
1548
1549 HW_WR_REG32(
1550 base + regOffset,
1551 (HW_RD_REG32(
1552 base + regOffset) &
1553 (~mask)) |
1554 value);
1555 }
1556
1566 static inline void
1567 RDC_getConfiguredDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t* coef1, uint8_t* coef2)
1568 {
1569 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1570 uint32_t value = HW_RD_REG32(base+regOffset);
1571
1572 *coef1 = (uint8_t)((value & CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_MASK) >> CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_SHIFT);
1573 *coef2 = (uint8_t)((value & CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_MASK) >> CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_SHIFT);
1574 }
1575
1586 static inline void
1587 RDC_enableBPF(uint32_t base, uint8_t core)
1588 {
1589 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1590 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1591
1592 HW_WR_REG32(
1593 base + regOffset,
1594 (HW_RD_REG32(
1595 base + regOffset) &
1596 ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) |
1597 ((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1598 }
1599
1606 static inline void
1607 RDC_disableBPF(uint32_t base, uint8_t core)
1608 {
1609 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1610 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1611
1612 HW_WR_REG32(
1613 base + regOffset,
1614 (HW_RD_REG32(
1615 base + regOffset) |
1616 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) &
1617 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1618 }
1619
1628 static inline bool
1629 RDC_isBPFEnabled(uint32_t base, uint8_t core)
1630 {
1631 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1632 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1633
1634 return((HW_RD_REG32(base + regOffset) & CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) == CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK);
1635 }
1636
1645 static inline void
1646 RDC_disableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
1647 {
1648 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1649 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1650
1651 HW_WR_REG32(
1652 base + regOffset,
1653 (HW_RD_REG32(
1654 base + regOffset) &
1655 ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK));
1656 }
1657
1667 static inline bool
1668 RDC_isDcOffsetAutoCorrectionEnabled(uint32_t base, uint8_t core)
1669 {
1670 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1671 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1672
1673 return(
1674 (HW_RD_REG32(base + regOffset) &
1675 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK) == CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK
1676 );
1677 }
1678
1687 static inline void
1688 RDC_enableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
1689 {
1690 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1691 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1692
1693 HW_WR_REG32(
1694 base + regOffset,
1695 (HW_RD_REG32(
1696 base + regOffset) |
1697 CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK));
1698 }
1699
1710 static inline void
1711 RDC_setDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t sin, int16_t cos)
1712 {
1713 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1714 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG2_0 + (core * RDC_CORE_OFFSET);
1715 uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_MASK |
1716 CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_MASK);
1717
1718 uint32_t value = (((uint32_t)((uint16_t)sin)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_SHIFT) |
1719 (((uint32_t)((uint16_t)cos)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_SHIFT);
1720 value &= mask;
1721
1722 HW_WR_REG32(
1723 base + regOffset,
1724 (HW_RD_REG32(
1725 base + regOffset) &
1726 (~mask)) |
1727 value);
1728 }
1729
1741 static inline void
1742 RDC_getDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t* sin, int16_t* cos)
1743 {
1744 DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1745 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG2_0 + (core * RDC_CORE_OFFSET);
1746 uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_MASK |
1747 CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_MASK);
1748
1749 uint32_t value = HW_RD_REG32(base + regOffset) & mask;
1750
1751 *sin = (int16_t) (value >> CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_SHIFT);
1752 *cos = (int16_t) (value >> CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_SHIFT);
1753 }
1754
1766 static inline int16_t
1767 RDC_getDcOffsetEstimatedValues(uint32_t base, uint8_t core, uint8_t sinCosValue)
1768 {
1769 uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF0 + (core * RDC_CORE_OFFSET);
1770 uint32_t mask = CSL_RESOLVER_REGS_DC_OFF0_SIN_OFFSET_MASK | CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_MASK;
1771 DebugP_assert((sinCosValue == RDC_DC_OFFSET_SIN_ESTIMATION) || (sinCosValue == RDC_DC_OFFSET_COS_ESTIMATION));
1772 return ((int16_t)(HW_RD_REG32(
1773 base + regOffset) &
1774 mask) >>
1775 (sinCosValue * CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_SHIFT));
1776 }
1777
1778 //*****************************************************************************
1779 // Ideal Sample Time Configurations
1780 //*****************************************************************************
1781
1790 static inline void
1791 RDC_overrideIdealSampleTime(uint32_t base, uint8_t core, uint8_t overrideValue)
1792 {
1793 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core * RDC_CORE_OFFSET);
1794 HW_WR_REG32(
1795 base + regOffset,
1796 (HW_RD_REG32(
1797 base + regOffset) &
1798 ~CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_MASK) |
1799 ((uint32_t)(overrideValue << CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_SHIFT)));
1800 }
1801
1810 static inline uint8_t
1811 RDC_getConfiguredOverrideIdealSampleTime(uint32_t base, uint8_t core)
1812 {
1813 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core * RDC_CORE_OFFSET);
1814 uint32_t value = HW_RD_REG32(base + regOffset) & CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_MASK;
1815 return((uint8_t) (value >> CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_SHIFT));
1816 }
1817
1826 static inline uint8_t
1827 RDC_getIdealSampleTime(uint32_t base, uint8_t core)
1828 {
1829 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core * RDC_CORE_OFFSET);
1830 return (
1831 (HW_RD_REG32(
1832 base + regOffset) &
1833 CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_MASK) >>
1834 CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_SHIFT);
1835 }
1836
1848 static inline void
1849 RDC_setIdealSampleDetectionThreshold(uint32_t base, uint8_t core, uint16_t absThresholdValue)
1850 {
1851 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1852 HW_WR_REG32(
1853 base + regOffset,
1854 (HW_RD_REG32(
1855 base + regOffset) &
1856 ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_MASK) |
1857 ((uint32_t)(absThresholdValue << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_SHIFT)));
1858 }
1859
1868 static inline uint16_t
1869 RDC_getConfiguredIdealSampleDetectionThreshold(uint32_t base, uint8_t core)
1870 {
1871 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1872 return ((uint16_t) (
1873 (HW_RD_REG32 (base + regOffset) & CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_MASK)
1874 >> CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_SHIFT));
1875 }
1876
1886 static inline void
1887 RDC_setIdealSampleBpfAdjust(uint32_t base, uint8_t core, uint8_t sampleAdjustCount)
1888 {
1889 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1890 DebugP_assert(sampleAdjustCount <= RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST);
1891 HW_WR_REG32(
1892 base + regOffset,
1893 (HW_RD_REG32(
1894 base + regOffset) &
1895 ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_MASK) |
1896 ((uint32_t)(sampleAdjustCount << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_SHIFT)));
1897 }
1898
1899 static inline uint8_t
1900 RDC_getConfiguredIdealSampleBpfAdjust(uint32_t base, uint8_t core)
1901 {
1902 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1903 return ((uint8_t) ((HW_RD_REG32(base + regOffset) &
1904 ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_MASK)
1905 >> CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_SHIFT));
1906 }
1907
1917 static inline bool
1918 RDC_getIdealSamplePeakAvgLimitStatus(uint32_t base, uint8_t core)
1919 {
1920 uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1921 return (
1922 ((HW_RD_REG32(
1923 base + regOffset) &
1924 CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_MASK) &
1925 ((uint32_t)((1U) << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_SHIFT))) != 0U);
1926 }
1927 //note add clearIdealSamplePeakAvgLimitStatus API.
1928
1941 static inline void
1942 RDC_setIdealSampleMode(uint32_t base, uint8_t core, uint8_t mode)
1943 {
1944 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1945 DebugP_assert(
1946 (mode & ~(CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MAX)) == 0U);
1947 HW_WR_REG32(
1948 base + regOffset,
1949 (HW_RD_REG32(
1950 base + regOffset) &
1951 ~CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MASK) |
1952 ((uint32_t)(mode << CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_SHIFT)));
1953 }
1954
1968 static inline uint8_t
1969 RDC_getConfiguredIdealSampleMode(uint32_t base, uint8_t core)
1970 {
1971 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1972 uint32_t value = HW_RD_REG32(base + regOffset) & CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MASK;
1973 return ((uint8_t) (value >> CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_SHIFT));
1974 }
1975
1985 static inline void
1986 RDC_enableIdealSampleBottomSampling(uint32_t base, uint8_t core)
1987 {
1988 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1989 HW_WR_REG32(
1990 base + regOffset,
1991 (HW_RD_REG32(
1992 base + regOffset) &
1993 ~CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) |
1994 ((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
1995 }
1996
2006 static inline bool
2007 RDC_isIdealSampleBottomSamplingEnabled(uint32_t base, uint8_t core)
2008 {
2009 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
2010 return ((HW_RD_REG32(base + regOffset) &
2011 CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) == CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK);
2012 }
2013
2021 static inline void
2022 RDC_disableIdealSampleBottomSampling(uint32_t base, uint8_t core)
2023 {
2024 uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
2025 HW_WR_REG32(
2026 base + regOffset,
2027 (HW_RD_REG32(
2028 base + regOffset) |
2029 CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) &
2030 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
2031 }
2032
2033 //*****************************************************************************
2034 // PHASE GAIN ESTIMATION AND CORRECTION CONFIGURAITONS
2035 //*****************************************************************************
2036
2046 static inline bool
2047 RDC_getPhaseGainEstimationStatus(uint32_t base, uint8_t core)
2048 {
2049 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
2050 return (
2051 ((HW_RD_REG32(
2052 base + regOffset) &
2053 CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_MASK) &
2054 ((uint32_t)((1U) << CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_SHIFT))) != 0U);
2055 }
2056
2066 static inline void
2067 RDC_clearPhaseGainEstimationStatus(uint32_t base, uint8_t core)
2068 {
2069 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
2070 HW_WR_REG32(
2071 base + regOffset,
2072 HW_RD_REG32(base + regOffset) | CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_MASK);
2073 }
2074
2084 static inline void
2085 RDC_setPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core, uint8_t pgEstimationLimit)
2086 {
2087 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
2088 DebugP_assert(pgEstimationLimit <= CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MAX);
2089 HW_WR_REG32(
2090 base + regOffset,
2091 (HW_RD_REG32(
2092 base + regOffset) &
2093 ~CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MASK) |
2094 ((uint32_t)(pgEstimationLimit << CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_SHIFT)));
2095 }
2096
2105 static inline uint8_t
2106 RDC_getConfiguredPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core)
2107 {
2108 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
2109 return ((uint8_t) ((HW_RD_REG32(base + regOffset) &
2110 CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MASK) >> CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_SHIFT));
2111 }
2112
2122 static inline void
2123 RDC_setCosPhaseBypass(uint32_t base, uint8_t core, int16_t cosPhaseBypass)
2124 {
2125 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2126 DebugP_assert((cosPhaseBypass & (~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MAX)) == 0U);
2127 HW_WR_REG32(
2128 base + regOffset,
2129 (HW_RD_REG32(
2130 base + regOffset) &
2131 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MASK) |
2132 ((uint32_t)(cosPhaseBypass << CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_SHIFT)));
2133 }
2134
2144 static inline int16_t
2145 RDC_getConfiguredCosPhaseBypass(uint32_t base, uint8_t core)
2146 {
2147 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2148 return ((int16_t) ((HW_RD_REG32(base + regOffset) &
2149 CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MASK) >> CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_SHIFT));
2150 }
2151
2159 static inline void
2160 RDC_enablePhaseGainEstimation(uint32_t base, uint8_t core)
2161 {
2162 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2163 HW_WR_REG32(
2164 base + regOffset,
2165 (HW_RD_REG32(
2166 base + regOffset) |
2167 CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) &
2168 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
2169
2170 }
2171
2179 static inline void
2180 RDC_disablePhaseGainEstimation(uint32_t base, uint8_t core)
2181 {
2182 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2183 HW_WR_REG32(
2184 base + regOffset,
2185 (HW_RD_REG32(
2186 base + regOffset) &
2187 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) |
2188 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
2189 }
2190
2200 static inline bool
2201 RDC_isPhaseGainEstimationEnabled(uint32_t base, uint8_t core)
2202 {
2203 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2204 return (
2205 (HW_RD_REG32(base + regOffset) &
2206 CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) != CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK
2207 );
2208 }
2209
2217 static inline void
2218 RDC_enablePhaseAutoCorrection(uint32_t base, uint8_t core)
2219 {
2220 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2221 HW_WR_REG32(
2222 base + regOffset,
2223 (HW_RD_REG32(
2224 base + regOffset) &
2225 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) |
2226 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
2227 }
2228
2236 static inline void
2237 RDC_disablePhaseAutoCorrection(uint32_t base, uint8_t core)
2238 {
2239 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2240 HW_WR_REG32(
2241 base + regOffset,
2242 (HW_RD_REG32(
2243 base + regOffset) |
2244 CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) &
2245 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
2246 }
2247
2257 static inline bool
2258 RDC_isPhaseAutoCorrectionEnabled(uint32_t base, uint16_t core)
2259 {
2260 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2261 return(
2262 ((HW_RD_REG32(base + regOffset) & CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) == CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK)
2263 );
2264 }
2265
2273 static inline void
2274 RDC_enableGainAutoCorrection(uint32_t base, uint8_t core)
2275 {
2276 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2277 HW_WR_REG32(
2278 base + regOffset,
2279 (HW_RD_REG32(
2280 base + regOffset) &
2281 ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) |
2282 ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
2283 }
2284
2292 static inline void
2293 RDC_disableGainAutoCorrection(uint32_t base, uint8_t core)
2294 {
2295 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2296 HW_WR_REG32(
2297 base + regOffset,
2298 (HW_RD_REG32(
2299 base + regOffset) |
2300 CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) &
2301 ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
2302 }
2303
2313 static inline bool
2314 RDC_isGainAutoCorrectionEnabled(uint32_t base, uint8_t core)
2315 {
2316 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
2317 return(
2318 (HW_RD_REG32(base + regOffset) & CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) == CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK
2319 );
2320 }
2321
2331 static inline void
2332 RDC_setGainBypassValue(uint32_t base, uint8_t core, uint16_t sinGainBypass, uint16_t cosGainBypass)
2333 {
2334 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG3_0 + (core * RDC_CORE_OFFSET);
2335 DebugP_assert(sinGainBypass >= 16384U);
2336 uint32_t value = ((uint32_t)(((uint32_t)cosGainBypass) << 16)) | ((uint32_t)((uint16_t)sinGainBypass));
2337
2338 HW_WR_REG32(
2339 base + regOffset, value);
2340 }
2341
2351 static inline void
2352 RDC_getConfiguredGainBypassValue(uint32_t base, uint8_t core, uint16_t* sinGainBypass, uint16_t* cosGainBypass)
2353 {
2354 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG3_0 + (core * RDC_CORE_OFFSET);
2355 uint32_t value = HW_RD_REG32(base+regOffset);
2356
2357 *sinGainBypass = (uint16_t) ((value & CSL_RESOLVER_REGS_PG_EST_CFG3_0_GAINSINBYP0_MASK) >> CSL_RESOLVER_REGS_PG_EST_CFG3_0_GAINSINBYP0_SHIFT);
2358 *cosGainBypass = (uint16_t) ((value & CSL_RESOLVER_REGS_PG_EST_CFG3_0_GAINCOSBYP0_MASK) >> CSL_RESOLVER_REGS_PG_EST_CFG3_0_GAINCOSBYP0_SHIFT);
2359 }
2360
2370 static inline int16_t
2371 RDC_getPhaseEstimation(uint32_t base, uint8_t core)
2372 {
2373 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG4_0 + (core * RDC_CORE_OFFSET);
2374 return ((int16_t)
2375 (HW_RD_REG32(
2376 base + regOffset) &
2377 CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_MASK) >>
2378 CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_SHIFT);
2379 }
2380
2396 static inline void
2397 RDC_getGainEstimation(uint32_t base, uint8_t core, float *sinGainEstimateSq, float *cosGainEstimateSq)
2398 {
2399 uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG5_0 + (core * RDC_CORE_OFFSET);
2400 uint32_t cosSqAccValue = HW_RD_REG32(base + regOffset);
2401
2402 *cosGainEstimateSq = ((uint32_t) 1 << 29)/cosSqAccValue;
2403
2404 regOffset = CSL_RESOLVER_REGS_PG_EST_CFG6_0 + (core * RDC_CORE_OFFSET);
2405
2406 uint32_t sinSqAccValue = HW_RD_REG32(base + regOffset);
2407 *sinGainEstimateSq = ((uint32_t) 1 << 29)/sinSqAccValue;
2408 }
2409
2410 //*****************************************************************************
2411 // TRACK2 CONFIGURATIONS
2412 //*****************************************************************************
2413
2414
2425 static inline void
2426 RDC_setTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
2427 {
2428 uint8_t kvelfilt = track2Constants->kvelfilt;
2429 uint32_t cfg1 = (kvelfilt << CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_SHIFT);
2430
2431 uint32_t mask_cfg1 = (CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_MASK);
2432
2433 uint32_t regOffset_cfg1 = CSL_RESOLVER_REGS_TRACK2_CFG1_0 + (core * RDC_CORE_OFFSET);
2434 HW_WR_REG32(
2435 base + regOffset_cfg1,
2436 (HW_RD_REG32(
2437 base + regOffset_cfg1) &
2438 (~mask_cfg1)) |
2439 cfg1);
2440 }
2441
2450 static inline void
2451 RDC_getConfiguredTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t* track2Constants)
2452 {
2453 uint32_t regOffset_cfg1 = CSL_RESOLVER_REGS_TRACK2_CFG1_0 + (core * RDC_CORE_OFFSET);
2454 track2Constants->kvelfilt = (uint8_t) (HW_RD_REG32(base + regOffset_cfg1) >> CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_SHIFT);
2455 }
2456
2464 static inline void
2465 RDC_enableTrack2Boost(uint32_t base, uint8_t core)
2466 {
2467 uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core * RDC_CORE_OFFSET);
2468
2469 HW_WR_REG32(
2470 base + regOffset,
2471 (HW_RD_REG32(
2472 base + regOffset) &
2473 ~CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) |
2474 ((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2475 }
2483 static inline void
2484 RDC_disableTrack2Boost(uint32_t base, uint8_t core)
2485 {
2486 uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core * RDC_CORE_OFFSET);
2487
2488 HW_WR_REG32(
2489 base + regOffset,
2490 (HW_RD_REG32(
2491 base + regOffset) |
2492 CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) &
2493 ~((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2494 }
2495 // Add is boost enabled API.
2496
2507 static inline int16_t
2508 RDC_getArcTanAngle(uint32_t base, uint8_t core)
2509 {
2510 uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_ARCTAN_0 + (core * RDC_CORE_OFFSET);
2511 return (
2512 (int16_t)HW_RD_REG16(
2513 base + regOffset));
2514 }
2515
2525 static inline int16_t
2526 RDC_getTrack2Angle(uint32_t base, uint8_t core)
2527 {
2528 uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_TRACK2_0 + (core * RDC_CORE_OFFSET);
2529 return (
2530 (int16_t)HW_RD_REG16(
2531 base + regOffset));
2532 }
2533
2544 static inline int32_t
2545 RDC_getTrack2Velocity(uint32_t base, uint8_t core)
2546 {
2547 uint32_t regOffset = CSL_RESOLVER_REGS_VELOCITY_TRACK2_0 + (core * RDC_CORE_OFFSET);
2548 return (
2549 (int32_t)HW_RD_REG32(
2550 base + regOffset));
2551 }
2552
2553 //*****************************************************************************
2554 // DIAGNOSTIC RELATED APIS
2555 //*****************************************************************************
2556
2571 static inline void
2572 RDC_getDiagnosticsSinCosOffsetDriftData(uint32_t base,
2573 uint8_t resolverCore,
2574 Diag_Mon_SinCos_Offset_drift_data *monitorData)
2575 {
2576 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (RDC_CORE_OFFSET * resolverCore);
2577 uint32_t value = HW_RD_REG32(base + regOffset);
2578 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2579 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2580
2581 monitorData->offset_drift_threshold_hi = (int16_t)((uint16_t)((value &
2582 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_MASK) >>
2583 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT));
2584 monitorData->offset_drift_threshold_lo = (int16_t)((uint16_t)((value &
2585 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_MASK) >>
2586 CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT));
2587
2588 monitorData->offset_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR) != 0);
2589 monitorData->offset_drift_sin_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR) != 0);
2590 monitorData->offset_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR) != 0);
2591 monitorData->offset_drift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR) != 0);
2592 monitorData->offset_drift_en = ((enabledInterruptSources &
2593 (RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR |
2594 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR |
2595 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR |
2596 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR)) != 0);
2597 }
2598
2613 static inline void
2614 RDC_setDiagnosticsSinCosOffsetDriftData(uint32_t base,
2615 uint8_t resolverCore,
2616 Diag_Mon_SinCos_Offset_drift_data *monitorData)
2617 {
2618 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (RDC_CORE_OFFSET * resolverCore);
2619 uint32_t value = (((uint32_t)((uint16_t)(monitorData->offset_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT) |
2620 (((uint32_t)((uint16_t)(monitorData->offset_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT);
2621 uint32_t interruptSource = 0;
2622 /* if interrupt needs to be enabled */
2623 RDC_disableCoreInterrupt(base, resolverCore,
2624 (RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR |
2625 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR |
2626 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR |
2627 RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR));
2628
2629 /* writing the "value" */
2630 HW_WR_REG32(
2631 base + regOffset, value);
2632
2633 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2634
2635 if (monitorData->offset_drift_en)
2636 {
2637 if (monitorData->offset_drift_cos_hi)
2638 {
2639 interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR;
2640 }
2641
2642 if (monitorData->offset_drift_sin_hi)
2643 {
2644 interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR;
2645 }
2646
2647 if (monitorData->offset_drift_cos_lo)
2648 {
2649 interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR;
2650 }
2651
2652 if (monitorData->offset_drift_sin_lo)
2653 {
2654 interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR;
2655 }
2656
2657 RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2658 }
2659 }
2660
2676 static inline void
2677 RDC_getDiagnosticsSinCosGainDriftData(uint32_t base,
2678 uint8_t resolverCore,
2679 Diag_Mon_SinCos_Gain_drift_data *monitorData)
2680 {
2681 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (RDC_CORE_OFFSET * resolverCore);
2682
2683 uint32_t value = HW_RD_REG32(base + regOffset);
2684
2685 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2686 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2687
2688 monitorData->gain_drift_threshold_hi = ((uint16_t)((value &
2689 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_MASK) >>
2690 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT));
2691 monitorData->gain_drift_threshold_lo = ((uint16_t)((value &
2692 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_MASK) >>
2693 CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT));
2694
2695 monitorData->gain_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR) != 0);
2696 monitorData->gain_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR) != 0);
2697 monitorData->gain_drift_sin_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR) != 0);
2698 monitorData->gain_drift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR) != 0);
2699
2700 /* getting the glitch count value*/
2701 regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (RDC_CORE_OFFSET * resolverCore);
2702 monitorData->gain_drift_glitch_count = (uint8_t)HW_RD_REG32(base + regOffset);
2703
2704 monitorData->gain_drift_en = ((enabledInterruptSources &
2705 (RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR |
2706 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR |
2707 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR |
2708 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR)) != 0);
2709 }
2710
2726 static inline void
2727 RDC_setDiagnosticsSinCosGainDriftData(uint32_t base,
2728 uint8_t resolverCore,
2729 Diag_Mon_SinCos_Gain_drift_data *monitorData)
2730 {
2731 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (RDC_CORE_OFFSET * resolverCore);
2732 uint32_t value = (((uint32_t)((uint16_t)(monitorData->gain_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT) |
2733 (((uint32_t)((uint16_t)(monitorData->gain_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT);
2734
2735 uint32_t interruptSource = 0;
2736
2737 /* if interrupt needs to be enabled */
2738 RDC_disableCoreInterrupt(base, resolverCore,
2739 (RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR |
2740 RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR |
2741 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR |
2742 RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR));
2743
2744 /* setting the glitch count value */
2745 regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (RDC_CORE_OFFSET * resolverCore);
2746 HW_WR_REG32(
2747 base + regOffset, monitorData->gain_drift_glitch_count);
2748
2749 /* writing the "value" */
2750 HW_WR_REG32(
2751 base + regOffset, value);
2752
2753 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2754
2755 if (monitorData->gain_drift_en)
2756 {
2757 if (monitorData->gain_drift_cos_hi)
2758 {
2759 interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR;
2760 }
2761
2762 if (monitorData->gain_drift_sin_hi)
2763 {
2764 interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR;
2765 }
2766
2767 if (monitorData->gain_drift_cos_lo)
2768 {
2769 interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR;
2770 }
2771
2772 if (monitorData->gain_drift_sin_lo)
2773 {
2774 interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR;
2775 }
2776
2777 RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2778 }
2779 }
2780
2781
2795 static inline void
2796 RDC_getDiagnosticsCosPhaseDriftData(uint32_t base,
2797 uint8_t resolverCore,
2798 Diag_Mon_Cos_Phase_drift_data *monitorData)
2799 {
2800 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (RDC_CORE_OFFSET * resolverCore);
2801
2802 uint32_t value = HW_RD_REG32(base + regOffset);
2803
2804 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2805 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2806
2807 monitorData->phase_drift_threshold_hi = (int16_t)((uint16_t)((value &
2808 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_MASK) >>
2809 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT));
2810 monitorData->phase_drift_threshold_lo = (int16_t)((uint16_t)((value &
2811 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_MASK) >>
2812 CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT));
2813
2814 monitorData->phase_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR) != 0);
2815 monitorData->phase_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR) != 0);
2816
2817 /* getting the glitch count value*/
2818 regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (RDC_CORE_OFFSET * resolverCore);
2819 monitorData->phase_drift_glitch_count = (uint8_t)HW_RD_REG32(base + regOffset);
2820
2821 monitorData->phase_drift_en = ((enabledInterruptSources &
2822 (RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR |
2823 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR)) != 0);
2824 }
2825
2839 static inline void
2840 RDC_setDiagnosticsCosPhaseDriftData(uint32_t base,
2841 uint8_t resolverCore,
2842 Diag_Mon_Cos_Phase_drift_data *monitorData)
2843 {
2844 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (RDC_CORE_OFFSET * resolverCore);
2845 uint32_t value = (((uint32_t)((uint16_t)(monitorData->phase_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT) |
2846 (((uint32_t)((uint16_t)(monitorData->phase_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT);
2847
2848 uint32_t interruptSource = 0;
2849 /* if interrupt needs to be enabled */
2850 RDC_disableCoreInterrupt(base, resolverCore,
2851 (RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR |
2852 RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR));
2853 /* writing the glitch count value */
2854 regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (RDC_CORE_OFFSET * resolverCore);
2855 HW_WR_REG32(
2856 base + regOffset, monitorData->phase_drift_glitch_count);
2857
2858 /* writing the "value" */
2859 HW_WR_REG32(
2860 base + regOffset, value);
2861
2862 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2863
2864 if (monitorData->phase_drift_en)
2865 {
2866 if (monitorData->phase_drift_cos_hi)
2867 {
2868 interruptSource |= RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR;
2869 }
2870
2871 if (monitorData->phase_drift_cos_lo)
2872 {
2873 interruptSource |= RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR;
2874 }
2875
2876 RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2877 }
2878 }
2879
2880
2881
2899 static inline void
2900 RDC_getDiagnosticsExcFreqDegradationData(uint32_t base,
2901 uint8_t resolverCore,
2902 Diag_Mon_ExcFreq_Degradataion_data *monitorData)
2903 {
2904 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG2_0 + (RDC_CORE_OFFSET * resolverCore);
2905
2906 uint32_t value = HW_RD_REG32(base + regOffset);
2907
2908 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2909 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2910
2911 monitorData->excfreqdetected_sin = ((uint16_t)((value &
2912 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_MASK) >>
2913 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_SHIFT));
2914 monitorData->excfreqdetected_cos = ((uint16_t)((value &
2915 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_MASK) >>
2916 CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_SHIFT));
2917
2918 regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (RDC_CORE_OFFSET * resolverCore);
2919 value = HW_RD_REG32(base + regOffset);
2920
2921 monitorData->excfreqdrift_threshold_hi = ((uint16_t)((value &
2922 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_MASK) >>
2923 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT));
2924 monitorData->excfreqdrift_threshold_lo = ((uint16_t)((value &
2925 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_MASK) >>
2926 CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT));
2927
2928 regOffset = CSL_RESOLVER_REGS_DIAG4_0 + (RDC_CORE_OFFSET * resolverCore);
2929 value = HW_RD_REG32(base + regOffset);
2930
2931 monitorData->excfreq_level = ((uint16_t)((value &
2932 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_MASK) >>
2933 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT));
2934 monitorData->excfreqdrift_glitchcount = ((uint8_t)((value &
2935 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_MASK) >>
2936 CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT));
2937
2938 monitorData->excfreqdrift_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR) != 0);
2939 monitorData->excfreqdrift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR) != 0);
2940 monitorData->excfreqdrift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR) != 0);
2941
2942 monitorData->excfreqdrift_en = ((enabledInterruptSources &
2943 (RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR |
2944 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR |
2945 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR)) != 0);
2946 }
2947
2965 static inline void
2966 RDC_setDiagnosticsExcFreqDegradationData(uint32_t base,
2967 uint8_t resolverCore,
2968 Diag_Mon_ExcFreq_Degradataion_data *monitorData)
2969 {
2970 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (RDC_CORE_OFFSET * resolverCore);
2971 uint32_t value = (((uint32_t)((uint16_t)(monitorData->excfreqdrift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT) |
2972 (((uint32_t)((uint16_t)(monitorData->excfreqdrift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT);
2973 uint32_t interruptSource = 0;
2974
2975 RDC_disableCoreInterrupt(base, resolverCore,
2976 (RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR |
2977 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR |
2978 RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR));
2979
2980 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2981
2982 HW_WR_REG32(
2983 base + regOffset, value);
2984
2985 regOffset = CSL_RESOLVER_REGS_DIAG4_0 + (RDC_CORE_OFFSET * resolverCore);
2986 value = (((uint32_t)((uint16_t)(monitorData->excfreq_level))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT) |
2987 (((uint32_t)((uint16_t)(monitorData->excfreqdrift_glitchcount))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT);
2988
2989 HW_WR_REG32(
2990 base + regOffset, value);
2991
2992 if (monitorData->excfreqdrift_en)
2993 {
2994 if (monitorData->excfreqdrift_hi)
2995 {
2996 interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR;
2997 }
2998
2999 if (monitorData->excfreqdrift_cos_lo)
3000 {
3001 interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR;
3002 }
3003
3004 if (monitorData->excfreqdrift_sin_lo)
3005 {
3006 interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR;
3007 }
3008 RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
3009 }
3010 }
3011
3029 static inline void
3030 RDC_getDiagnosticsRotationalSignalIntegrityData(uint32_t base,
3031 uint8_t resolverCore,
3032 Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
3033 {
3034 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG13_0 + (RDC_CORE_OFFSET * resolverCore);
3035 uint32_t value = HW_RD_REG32(
3036 base + regOffset);
3037
3038 monitorData->sin_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_SHIFT);
3039
3040 monitorData->cos_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_SHIFT);
3041
3042 regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (RDC_CORE_OFFSET * resolverCore);
3043 value = HW_RD_REG32(
3044 base + regOffset);
3045 monitorData->rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT;
3046 monitorData->rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT;
3047
3048 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
3049 monitorData->cos_neg_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR) != 0);
3050 monitorData->cos_pos_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR) != 0);
3051 monitorData->sin_neg_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR) != 0);
3052 monitorData->sin_pos_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR) != 0);
3053
3054
3055 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
3056 monitorData->zero_cross_rot_en = (enabledInterruptSources & (RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR |
3057 RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR |
3058 RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR |
3059 RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR)) != 0;
3060 }
3061
3079 static inline void
3080 RDC_setDiagnosticsRotationalSignalIntegrityData(uint32_t base,
3081 uint8_t resolverCore,
3082 Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
3083 {
3084 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (RDC_CORE_OFFSET * resolverCore);
3085 uint32_t value = (((uint32_t)((uint16_t)(monitorData->rotpeak_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT) |
3086 (((uint32_t)((uint16_t)(monitorData->rotfreq_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT);
3087 HW_WR_REG32(
3088 base + regOffset,
3089 value);
3090 RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR));
3091 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
3092 uint32_t interruptSources = 0;
3093
3094 if (monitorData->zero_cross_rot_en)
3095 {
3096 if (monitorData->cos_neg_zc_peak_mismatch_err)
3097 {
3098 interruptSources |= RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR;
3099 }
3100
3101 if (monitorData->cos_pos_zc_peak_mismatch_err)
3102 {
3103 interruptSources |= RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR;
3104 }
3105
3106 if (monitorData->sin_neg_zc_peak_mismatch_err)
3107 {
3108 interruptSources |= RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR;
3109 }
3110
3111 if (monitorData->sin_pos_zc_peak_mismatch_err)
3112 {
3113 interruptSources |= RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR;
3114 }
3115
3116 RDC_enableCoreInterrupt(base, resolverCore, (interruptSources | enabledInterruptSources));
3117 }
3118 }
3119
3133 static inline void
3134 RDC_getDiagnosticsSignalIntegritySquareSumData(
3135 uint32_t base,
3136 uint32_t resolverCore,
3137 Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
3138 {
3139 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore * RDC_CORE_OFFSET);
3140 uint32_t value = HW_RD_REG32(
3141 base + regOffset);
3142
3143 monitorData->sinsqcossq_threshold_hi = (value & CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_MASK) >>
3144 CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT;
3145 monitorData->sinsqcossq_threshold_lo = (value & CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_MASK) >>
3146 CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT;
3147
3148 regOffset = CSL_RESOLVER_REGS_DIAG10_0 + (resolverCore * RDC_CORE_OFFSET);
3149 value = HW_RD_REG32(
3150 base + regOffset);
3151
3152 monitorData->sinsqcossq_cossq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_MASK) >>
3153 CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_SHIFT;
3154 monitorData->sinsqcossq_sinsq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_MASK) >>
3155 CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_SHIFT;
3156
3157 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
3158
3159 regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore * RDC_CORE_OFFSET);
3160 monitorData->sinsqcossq_glitchcount = (uint8_t)((HW_RD_REG32(
3161 base + regOffset) &
3162 CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_MASK) >>
3163 CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_SHIFT);
3164
3165 monitorData->sinsqcossq_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR) != 0);
3166 monitorData->sinsqcossq_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR) != 0);
3167 }
3168
3182 static inline void
3183 RDC_setDiagnosticsSignalIntegritySquareSumData(
3184 uint32_t base,
3185 uint32_t resolverCore,
3186 Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
3187 {
3188 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore * RDC_CORE_OFFSET);
3189 uint32_t value = (((uint32_t)((uint16_t)(monitorData->sinsqcossq_threshold_hi))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT) |
3190 (((uint32_t)((uint16_t)(monitorData->sinsqcossq_threshold_lo))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT);
3191 HW_WR_REG32(
3192 base + regOffset, value);
3193
3194 regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore * RDC_CORE_OFFSET);
3195 HW_WR_REG32(
3196 base + regOffset, (uint32_t)(monitorData->sinsqcossq_glitchcount));
3197
3198 RDC_disableCoreInterrupt(base, resolverCore,
3199 (RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR | RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR));
3200 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
3201 uint32_t interruptSources = 0;
3202
3203 if (monitorData->sinsqcossq_hi)
3204 {
3205 interruptSources |= RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR;
3206 }
3207 if (monitorData->sinsqcossq_lo)
3208 {
3209 interruptSources |= RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR;
3210 }
3211 RDC_enableCoreInterrupt(base, resolverCore, (enabledInterruptSources | interruptSources));
3212 }
3213
3214
3215
3228 static inline void
3229 RDC_getDiagnosticsHighAmplitudeData(
3230 uint32_t base,
3231 uint8_t resolverCore,
3232 Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
3233 {
3234 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore * RDC_CORE_OFFSET);
3235 uint32_t value = HW_RD_REG32(
3236 base + regOffset);
3237 uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
3238
3239 monitorData->highAmplitude_glitchcount = (value & CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_GLITCHCOUNT_MASK) >>
3240 CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT;
3241
3242 monitorData->highAmplitude_threshold = (value & CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_THRESHOLD_MASK) >>
3243 CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_THRESHOLD_SHIFT;
3244 regOffset = CSL_RESOLVER_REGS_DIAG8_0 + (resolverCore * RDC_CORE_OFFSET);
3245 value = HW_RD_REG32(
3246 base + regOffset);
3247
3248 monitorData->highAmplitude_sin_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_0_HIGHAMPLITUDE_SIN_MASK) >> \
3249 CSL_RESOLVER_REGS_DIAG8_0_HIGHAMPLITUDE_SIN_SHIFT);
3250
3251 monitorData->highAmplitude_cos_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_0_HIGHAMPLITUDE_COS_MASK) >> \
3252 CSL_RESOLVER_REGS_DIAG8_0_HIGHAMPLITUDE_COS_SHIFT);
3253 monitorData->highAmplitude_cos_error = ((interruptStatus & RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR) != 0);
3254 monitorData->highAmplitude_sin_error = ((interruptStatus & RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR) != 0);
3255 }
3256
3269 static inline void
3270 RDC_setDiagnosticsHighAmplitudeData(
3271 uint32_t base,
3272 uint8_t resolverCore,
3273 Diag_Mon_Sin_Cos_High_Amplitude* monitorData)
3274 {
3275 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore * RDC_CORE_OFFSET);
3276 uint32_t value = (((uint32_t)((uint16_t)(monitorData->highAmplitude_glitchcount))) << CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT) |
3277 (((uint32_t)((uint16_t)(monitorData->highAmplitude_threshold))) << CSL_RESOLVER_REGS_DIAG7_0_HIGHAMPLITUDE_THRESHOLD_SHIFT);
3278 uint32_t enabledInterruptSources = 0;
3279 uint32_t interruptSources = 0;
3280 HW_WR_REG32(
3281 base + regOffset,
3282 value);
3283 RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR | RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR));
3284 enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
3285
3286 if(monitorData->highAmplitude_cos_error)
3287 {
3288 interruptSources |= RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR;
3289 }
3290 if(monitorData->highAmplitude_sin_error)
3291 {
3292 interruptSources |= RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR;
3293 }
3294 RDC_enableCoreInterrupt(base, resolverCore, (interruptSources | enabledInterruptSources));
3295 }
3296
3308 static inline void
3309 RDC_getDiagnosticsWeakAmplitudeData(
3310 uint32_t base,
3311 uint8_t resolverCore,
3312 Diag_Mon_Sin_Cos_Weak_Amplitude * monitorData
3313 )
3314 {
3315 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore * RDC_CORE_OFFSET);
3316 uint32_t interruptSources = RDC_getCoreInterruptStatus(base, resolverCore);
3317 uint32_t value = HW_RD_REG32(
3318 base + regOffset);
3319 monitorData->lowAmplitude_threshold = (value & CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_THRESHOLD_MASK) >>
3320 CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_THRESHOLD_SHIFT;
3321 monitorData->lowAmplitude_glitchcount = (value & CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_GLITCHCOUNT_MASK) >>
3322 CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_GLITCHCOUNT_SHIFT;
3323
3324 monitorData->lowAmplitude_error = ((interruptSources & RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR) != 0U);
3325
3326 regOffset = CSL_RESOLVER_REGS_DIAG6_0 + (resolverCore * RDC_CORE_OFFSET);
3327 value = HW_RD_REG32(
3328 base + regOffset);
3329 monitorData->lowAmplitude_cos_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_0_LOWAMPLITUDE_COS_MASK) >>\
3330 CSL_RESOLVER_REGS_DIAG6_0_LOWAMPLITUDE_COS_SHIFT);
3331
3332 monitorData->lowAmplitude_sin_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_0_LOWAMPLITUDE_SIN_MASK) >>\
3333 CSL_RESOLVER_REGS_DIAG6_0_LOWAMPLITUDE_SIN_SHIFT);
3334 }
3335
3347 static inline void
3348 RDC_setDiagnosticsWeakAmplitudeData(
3349 uint32_t base,
3350 uint8_t resolverCore,
3351 Diag_Mon_Sin_Cos_Weak_Amplitude * monitorData
3352 )
3353 {
3354 uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore * RDC_CORE_OFFSET);
3355 uint32_t value = ((uint32_t)(monitorData->lowAmplitude_glitchcount << CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_GLITCHCOUNT_SHIFT)) |
3356 ((uint32_t) (monitorData->lowAmplitude_threshold << CSL_RESOLVER_REGS_DIAG5_0_LOWAMPLITUDE_THRESHOLD_SHIFT));
3357 uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
3358
3359 HW_WR_REG32(
3360 base + regOffset, value);
3361
3362 if(monitorData->lowAmplitude_error)
3363 {
3364 RDC_enableCoreInterrupt(base, resolverCore, (enabledInterruptSources | RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR));
3365 }
3366 else
3367 {
3368 RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR));
3369 }
3370 }
3371
3372 //*****************************************************************************
3373 // Observational Data
3374 //*****************************************************************************
3375
3390 static inline void
3391 RDC_getAdcObservationalData(
3392 uint32_t base,
3393 uint8_t resolverCore,
3394 ADC_observationalData * AdcData)
3395 {
3396 uint32_t regOffset = CSL_RESOLVER_REGS_OBS_ADC_0 + (resolverCore * RDC_CORE_OFFSET);
3397 uint32_t value = HW_RD_REG32(
3398 base + regOffset);
3399 AdcData->cos_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_SHIFT);
3400 AdcData->sin_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_SHIFT);
3401
3402 regOffset = CSL_RESOLVER_REGS_OBS_ADC_REC_0 + (resolverCore * RDC_CORE_OFFSET);
3403 value = HW_RD_REG32(
3404 base + regOffset);
3405 AdcData->cos_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_SHIFT);
3406 AdcData->sin_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_SHIFT);
3407
3408 regOffset = CSL_RESOLVER_REGS_OBS_ADC_DC_0 + (resolverCore * RDC_CORE_OFFSET);
3409 value = HW_RD_REG32(
3410 base + regOffset);
3411 AdcData->cos_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_SHIFT);
3412 AdcData->sin_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_SHIFT);
3413
3414 regOffset = CSL_RESOLVER_REGS_OBS_ADC_PGC_0 + (resolverCore * RDC_CORE_OFFSET);
3415 value = HW_RD_REG32(
3416 base + regOffset);
3417 AdcData->cos_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_SHIFT);
3418 AdcData->sin_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_SHIFT);
3419 }
3420
3428 static inline void
3429 RDC_getPeakHistogramObservationalData(uint32_t base, uint8_t resolverCore, PeakHistogram_observationalData* histogram)
3430 {
3431 uint32_t regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0 + (resolverCore * RDC_CORE_OFFSET);
3432 uint32_t value = HW_RD_REG32(
3433 base + regOffset);
3434 histogram->peakHistgoramBucket[0] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_SHIFT);
3435 histogram->peakHistgoramBucket[1] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_SHIFT);
3436 histogram->peakHistgoramBucket[2] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_SHIFT);
3437 histogram->peakHistgoramBucket[3] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_SHIFT);
3438
3439 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0 + (resolverCore * RDC_CORE_OFFSET);
3440 value = HW_RD_REG32(
3441 base + regOffset);
3442 histogram->peakHistgoramBucket[4] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_SHIFT);
3443 histogram->peakHistgoramBucket[5] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_SHIFT);
3444 histogram->peakHistgoramBucket[6] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_SHIFT);
3445 histogram->peakHistgoramBucket[7] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_SHIFT);
3446
3447 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0 + (resolverCore * RDC_CORE_OFFSET);
3448 value = HW_RD_REG32(
3449 base + regOffset);
3450 histogram->peakHistgoramBucket[8] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_SHIFT);
3451 histogram->peakHistgoramBucket[9] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_SHIFT);
3452 histogram->peakHistgoramBucket[10] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_SHIFT);
3453 histogram->peakHistgoramBucket[11] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_SHIFT);
3454
3455 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0 + (resolverCore * RDC_CORE_OFFSET);
3456 value = HW_RD_REG32(
3457 base + regOffset);
3458 histogram->peakHistgoramBucket[12] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_SHIFT);
3459 histogram->peakHistgoramBucket[13] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_SHIFT);
3460 histogram->peakHistgoramBucket[14] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_SHIFT);
3461 histogram->peakHistgoramBucket[15] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_SHIFT);
3462
3463 regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0 + (resolverCore * RDC_CORE_OFFSET);
3464 value = HW_RD_REG32(
3465 base + regOffset);
3466 histogram->peakHistgoramBucket[16] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_SHIFT);
3467 histogram->peakHistgoramBucket[17] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_SHIFT);
3468 histogram->peakHistgoramBucket[18] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_SHIFT);
3469 histogram->peakHistgoramBucket[19] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_SHIFT);
3470 }
3471
3477 extern void
3478 RDC_coreParamsInit(Core_config_t* coreParams);
3484 extern void
3485 RDC_paramsInit(RDC_configParams* params);
3493 extern void
3494 RDC_init(uint32_t base, RDC_configParams* params);
3495
3503 extern void
3504 RDC_getStaticConfigurations(uint32_t base, RDC_configParams* params);
3505
3516 extern int32_t
3517 RDC_verifyStaticConfigurations(uint32_t base, RDC_configParams* paramsInit, RDC_configParams* params);
3518
3524 extern void
3525 RDC_BaselineParametersInit(uint32_t base);
3526 //*****************************************************************************
3527 //
3528 // Close the Doxygen group.
3530 //
3531 //*****************************************************************************
3532
3533 //*****************************************************************************
3534 //
3535 // Mark the end of the C bindings section for C++ compilers.
3536 //
3537 //*****************************************************************************
3538 #ifdef __cplusplus
3539 }
3540 #endif
3541
3542 #endif // RESOLVER_V1_H_
Core_config_t::Pg_correctionEnable
bool Pg_correctionEnable
Definition: resolver/v0/resolver.h:606
RDC_CAL_ADC0
#define RDC_CAL_ADC0
Macro used to specify Calibration data for ADC 0.
Definition: resolver/v0/resolver.h:315
RDC_getArcTanAngle
static int16_t RDC_getArcTanAngle(uint32_t base, uint8_t core)
Returns signed 16bit angle data from ArcTan. the data corresponds to -180 to +180 degrees angle in de...
Definition: resolver/v0/resolver.h:2508
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_error
bool lowAmplitude_error
Definition: resolver/v0/resolver.h:545
RDC_isAdcSingleEndedModeEnabled
static bool RDC_isAdcSingleEndedModeEnabled(uint32_t base)
Returns if Single ended mode of sampling is enabled for the ADCs.
Definition: resolver/v0/resolver.h:801
RDC_getConfiguredDcOffsetCalCoef
static void RDC_getConfiguredDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t *coef1, uint8_t *coef2)
Returns the Configured Coefficient Values for DC Offset Estimation and correction logic.
Definition: resolver/v0/resolver.h:1567
RDC_configParams::Input_signalMode
uint8_t Input_signalMode
Definition: resolver/v0/resolver.h:625
RDC_isDcOffsetAutoCorrectionEnabled
static bool RDC_isDcOffsetAutoCorrectionEnabled(uint32_t base, uint8_t core)
Returns if DC Auto Offset Correction is enabled for give RDC Core.
Definition: resolver/v0/resolver.h:1668
RDC_getDcOffsetEstimatedValues
static int16_t RDC_getDcOffsetEstimatedValues(uint32_t base, uint8_t core, uint8_t sinCosValue)
returns DC OFFSET estimation values
Definition: resolver/v0/resolver.h:1767
Diag_Mon_ExcFreq_Degradataion_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor excitation frequenc...
Definition: resolver/v0/resolver.h:443
RDC_DC_OFFSET_COS_ESTIMATION
#define RDC_DC_OFFSET_COS_ESTIMATION
Definition: resolver/v0/resolver.h:113
Diag_Mon_Cos_Phase_drift_data::phase_drift_en
bool phase_drift_en
Definition: resolver/v0/resolver.h:427
RDC_verifyStaticConfigurations
int32_t RDC_verifyStaticConfigurations(uint32_t base, RDC_configParams *paramsInit, RDC_configParams *params)
Returns if the configurations in paramsInit to params.
RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:268
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_cossq
uint16_t sinsqcossq_cossq
Definition: resolver/v0/resolver.h:501
RDC_coreParamsInit
void RDC_coreParamsInit(Core_config_t *coreParams)
Inits the Core Parameters for the resolver core.
Diag_Mon_ExcFreq_Degradataion_data::excfreqdetected_sin
uint16_t excfreqdetected_sin
Definition: resolver/v0/resolver.h:444
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_lo
bool sinsqcossq_lo
Definition: resolver/v0/resolver.h:504
RDC_EXCITATION_FREQUENCY_MIN_PHASE
#define RDC_EXCITATION_FREQUENCY_MIN_PHASE
Minimum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:83
RDC_setDiagnosticsSinCosOffsetDriftData
static void RDC_setDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Sets the Monitor Sin or Cos Offset Drift (DOS) diagnostics controls int16_t offset_drift_threshold_hi...
Definition: resolver/v0/resolver.h:2614
Diag_Mon_Cos_Phase_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Cos Phase drift (DO...
Definition: resolver/v0/resolver.h:421
Diag_Mon_SinCos_Gain_drift_data::gain_drift_sin_hi
bool gain_drift_sin_hi
Definition: resolver/v0/resolver.h:403
Diag_Mon_ExcFreq_Degradataion_data::excfreq_level
uint16_t excfreq_level
Definition: resolver/v0/resolver.h:448
RDC_clearSequencerInterrupt
static void RDC_clearSequencerInterrupt(uint32_t base)
Clear the Sequencer Error Interrupt status.
Definition: resolver/v0/resolver.h:1238
RDC_getConfiguredOverrideIdealSampleTime
static uint8_t RDC_getConfiguredOverrideIdealSampleTime(uint32_t base, uint8_t core)
Returns the Configured Override value for the Ideal Sample Time.
Definition: resolver/v0/resolver.h:1811
ADC_observationalData::cos_adc
int16_t cos_adc
Definition: resolver/v0/resolver.h:572
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:275
RDC_disablePhaseGainEstimation
static void RDC_disablePhaseGainEstimation(uint32_t base, uint8_t core)
Disbales Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:2180
RDC_getStaticConfigurations
void RDC_getStaticConfigurations(uint32_t base, RDC_configParams *params)
Returns the Static Configurations.
RDC_setDcOffsetCalCoef
static void RDC_setDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t coef1, uint8_t coef2)
Sets the DC Offset Coefficients coef1, coef2.
Definition: resolver/v0/resolver.h:1538
baselineParameters::DcParam3
uint8_t DcParam3
Definition: resolver/v0/resolver.h:654
Core_config_t::BpfDc_offsetCorrectionEnable
bool BpfDc_offsetCorrectionEnable
Definition: resolver/v0/resolver.h:591
RDC_configParams::core1
Core_config_t core1
Definition: resolver/v0/resolver.h:637
RDC_getCoreInterruptSources
static uint32_t RDC_getCoreInterruptSources(uint32_t base, uint32_t ResolverCore)
Returns Core interrupt sources.
Definition: resolver/v0/resolver.h:1411
ADC_observationalData::sin_adc
int16_t sin_adc
Definition: resolver/v0/resolver.h:573
RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR
Definition: resolver/v0/resolver.h:258
Diag_Mon_SinCos_Offset_drift_data::offset_drift_cos_lo
bool offset_drift_cos_lo
Definition: resolver/v0/resolver.h:378
RDC_getDiagnosticsRotationalSignalIntegrityData
static void RDC_getDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Returns the Monitor rotational signal integrity (DOS) diagnostics data bool cos_neg_zc_peak_mismatch_...
Definition: resolver/v0/resolver.h:3030
RDC_getCoreInterruptStatus
static uint32_t RDC_getCoreInterruptStatus(uint32_t base, uint32_t ResolverCore)
Returns Core interrupt Status.
Definition: resolver/v0/resolver.h:1392
RDC_getCoreEnabledInterruptSources
static uint32_t RDC_getCoreEnabledInterruptSources(uint32_t base, uint8_t ResolverCore)
returns enabled Interrupt Sources
Definition: resolver/v0/resolver.h:1309
RDC_setTrack2Constants
static void RDC_setTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
sets up the Track2 loop constants the following are the constants that can be setup using this API
Definition: resolver/v0/resolver.h:2426
RDC_getCalibrationData
static uint16_t RDC_getCalibrationData(uint32_t base, uint8_t CalAdc)
Returns the CAL ADC data for given ADC, if the mode permits.
Definition: resolver/v0/resolver.h:1509
RDC_getDiagnosticsWeakAmplitudeData
static void RDC_getDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Returns the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics data uint16_t lowAmpli...
Definition: resolver/v0/resolver.h:3309
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_threshold_lo
uint16_t excfreqdrift_threshold_lo
Definition: resolver/v0/resolver.h:447
Diag_Mon_SinCos_Offset_drift_data::offset_drift_threshold_lo
int16_t offset_drift_threshold_lo
Definition: resolver/v0/resolver.h:376
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_en
bool excfreqdrift_en
Definition: resolver/v0/resolver.h:453
Diag_Mon_Rotational_Signal_Integrity_data::sin_pos_zc_peak_mismatch_err
bool sin_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:473
RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST
#define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST
Definition: resolver/v0/resolver.h:119
Core_config_t::BpfDc_manualCos
int16_t BpfDc_manualCos
Definition: resolver/v0/resolver.h:595
Diag_Mon_Cos_Phase_drift_data::phase_drift_cos_hi
bool phase_drift_cos_hi
Definition: resolver/v0/resolver.h:425
RDC_getConfiguredExcitationSignalSocDelay
static uint16_t RDC_getConfiguredExcitationSignalSocDelay(uint32_t base)
Returns Configured Excitation Signal SOC Delay.
Definition: resolver/v0/resolver.h:1140
RDC_getAdcSampleRate
static uint32_t RDC_getAdcSampleRate(uint32_t base)
Gets the ADC Sampling Ratio.
Definition: resolver/v0/resolver.h:1008
RDC_enableGainAutoCorrection
static void RDC_enableGainAutoCorrection(uint32_t base, uint8_t core)
Enable Gain Auto correction.
Definition: resolver/v0/resolver.h:2274
RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:261
RDC_EXCITATION_FREQUENCY_MAX_PHASE
#define RDC_EXCITATION_FREQUENCY_MAX_PHASE
Maximum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:86
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_cos_value
int16_t highAmplitude_cos_value
Definition: resolver/v0/resolver.h:524
Diag_Mon_Cos_Phase_drift_data::phase_drift_glitch_count
uint8_t phase_drift_glitch_count
Definition: resolver/v0/resolver.h:424
SystemP.h
RDC_disableCoreInterrupt
static void RDC_disableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Disable Core Interrupt.
Definition: resolver/v0/resolver.h:1325
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_threshold
uint16_t highAmplitude_threshold
Definition: resolver/v0/resolver.h:521
RDC_init
void RDC_init(uint32_t base, RDC_configParams *params)
Configures the RDC based on the parameter values.
Core_config_t
Struct holds the Resolver Core Configurations Can be passed to RDC_coreParamsInit(Core_config_t* core...
Definition: resolver/v0/resolver.h:589
RDC_enableTrack2Boost
static void RDC_enableTrack2Boost(uint32_t base, uint8_t core)
enables the track2 Boost
Definition: resolver/v0/resolver.h:2465
RDC_getIdealSamplePeakAvgLimitStatus
static bool RDC_getIdealSamplePeakAvgLimitStatus(uint32_t base, uint8_t core)
Gets the status if the Peak Averaging Limit is reached.
Definition: resolver/v0/resolver.h:1918
RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:269
RDC_setIdealSampleBpfAdjust
static void RDC_setIdealSampleBpfAdjust(uint32_t base, uint8_t core, uint8_t sampleAdjustCount)
the BPF sample adjust when the BPF is turned on. This configuration takes effect only on the auto mod...
Definition: resolver/v0/resolver.h:1887
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_cos_lo
bool excfreqdrift_cos_lo
Definition: resolver/v0/resolver.h:451
Diag_Mon_Rotational_Signal_Integrity_data::cos_pos_zc_peak_mismatch_err
bool cos_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:471
RDC_SEQUENCER_MODE_5
#define RDC_SEQUENCER_MODE_5
ADC0/1 Parallelly Sample Sin0, Cos0, Cos1, Sin1 Samples Sequentially For Core0/1. Both Sin(Cos) Sampl...
Definition: resolver/v0/resolver.h:196
RDC_getSequencerInterruptStatus
static uint32_t RDC_getSequencerInterruptStatus(uint32_t base)
Returns Sequencer interrupt Status.
Definition: resolver/v0/resolver.h:1270
Core_config_t::track2Constants
Track2Constants_t track2Constants
Definition: resolver/v0/resolver.h:612
Core_config_t::Pg_sinGainBypassValue
uint16_t Pg_sinGainBypassValue
Definition: resolver/v0/resolver.h:608
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR
Definition: resolver/v0/resolver.h:267
RDC_overrideIdealSampleTime
static void RDC_overrideIdealSampleTime(uint32_t base, uint8_t core, uint8_t overrideValue)
sets the Override value for the Ideal Sample Time selection.
Definition: resolver/v0/resolver.h:1791
RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR
Definition: resolver/v0/resolver.h:256
Core_config_t::IdealSample_bottomSampleEnable
bool IdealSample_bottomSampleEnable
Definition: resolver/v0/resolver.h:601
RDC_RESOLVER_CORE0
#define RDC_RESOLVER_CORE0
Macro used to specify resolver core 0.
Definition: resolver/v0/resolver.h:94
baselineParameters::t2Param8
uint8_t t2Param8
Definition: resolver/v0/resolver.h:659
RDC_setIdealSampleMode
static void RDC_setIdealSampleMode(uint32_t base, uint8_t core, uint8_t mode)
Ideal Sample Time Computation Mode selection.
Definition: resolver/v0/resolver.h:1942
Core_config_t::Pg_cosGainBypassValue
uint16_t Pg_cosGainBypassValue
Definition: resolver/v0/resolver.h:609
RDC_getConfiguredPhaseGainEstimationTrainLimit
static uint8_t RDC_getConfiguredPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core)
Returns the configured Phase gain Estimation Train Limit.
Definition: resolver/v0/resolver.h:2106
RDC_BaselineParametersInit
void RDC_BaselineParametersInit(uint32_t base)
Inits Baseline Parameter configurations.
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_threshold
uint16_t lowAmplitude_threshold
Definition: resolver/v0/resolver.h:543
Diag_Mon_Rotational_Signal_Integrity_data::cos_multi_zc_error_err
bool cos_multi_zc_error_err
Definition: resolver/v0/resolver.h:475
RDC_getConfiguredTrack2Constants
static void RDC_getConfiguredTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
Returns the configured Track2 Constants.
Definition: resolver/v0/resolver.h:2451
Core_config_t::BpfDc_bpfEnable
bool BpfDc_bpfEnable
Definition: resolver/v0/resolver.h:590
RDC_setGainBypassValue
static void RDC_setGainBypassValue(uint32_t base, uint8_t core, uint16_t sinGainBypass, uint16_t cosGainBypass)
Sets the Manual Gain Correction values for Sin and Cos.
Definition: resolver/v0/resolver.h:2332
RDC_getExcitationSignalAmplitudeControl
static uint32_t RDC_getExcitationSignalAmplitudeControl(uint32_t base)
returns the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1175
Diag_Mon_SinCos_Gain_drift_data::gain_drift_threshold_lo
uint16_t gain_drift_threshold_lo
Definition: resolver/v0/resolver.h:399
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_sin_error
bool highAmplitude_sin_error
Definition: resolver/v0/resolver.h:525
RDC_disableAdcSingleEndedMode
static void RDC_disableAdcSingleEndedMode(uint32_t base)
Disable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:784
RDC_configParams::Int_core1Interrupts
uint32_t Int_core1Interrupts
Definition: resolver/v0/resolver.h:641
RDC_configParams::adv_config
bool adv_config
Definition: resolver/v0/resolver.h:624
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:276
Diag_Mon_SinCos_Gain_drift_data::gain_drift_sin_lo
bool gain_drift_sin_lo
Definition: resolver/v0/resolver.h:404
RDC_enableExcitationSignalSyncIn
static void RDC_enableExcitationSignalSyncIn(uint32_t base)
Enables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:1023
RDC_getConfiguredIdealSampleMode
static uint8_t RDC_getConfiguredIdealSampleMode(uint32_t base, uint8_t core)
Returns the configured Ideal Sample Mode.
Definition: resolver/v0/resolver.h:1969
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_glitchcount
uint8_t lowAmplitude_glitchcount
Definition: resolver/v0/resolver.h:544
RDC_isPhaseGainEstimationEnabled
static bool RDC_isPhaseGainEstimationEnabled(uint32_t base, uint8_t core)
Returns if the Phase Gain Estimation logic is enabled.
Definition: resolver/v0/resolver.h:2201
Track2Constants_t
struct to hold the track2 constant data
Definition: resolver/v0/resolver.h:357
RDC_clearCoreInterrupt
static void RDC_clearCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Clear the Core Interrupt status.
Definition: resolver/v0/resolver.h:1347
RDC_CORE_OFFSET
#define RDC_CORE_OFFSET
Header Files.
Definition: resolver/v0/resolver.h:79
RDC_configParams::Input_adcBurstCount
uint8_t Input_adcBurstCount
Definition: resolver/v0/resolver.h:627
RDC_setDiagnosticsRotationalSignalIntegrityData
static void RDC_setDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Sets the Monitor rotational signal integrity (DOS) diagnostics Controls bool cos_neg_zc_peak_mismatch...
Definition: resolver/v0/resolver.h:3080
Diag_Mon_Sin_Cos_High_Amplitude
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos saturati...
Definition: resolver/v0/resolver.h:520
RDC_selectCalibrationChannel
static void RDC_selectCalibrationChannel(uint32_t base, uint8_t calChannel)
Selects Calibration Channel for Cal sequence.
Definition: resolver/v0/resolver.h:1475
ADC_observationalData::cos_pgc
int16_t cos_pgc
Definition: resolver/v0/resolver.h:578
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_hi
bool sinsqcossq_hi
Definition: resolver/v0/resolver.h:503
Core_config_t::IdealSample_overrideValue
uint8_t IdealSample_overrideValue
Definition: resolver/v0/resolver.h:597
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_glitchcount
uint8_t excfreqdrift_glitchcount
Definition: resolver/v0/resolver.h:449
Diag_Mon_Cos_Phase_drift_data::phase_drift_cos_lo
bool phase_drift_cos_lo
Definition: resolver/v0/resolver.h:426
Diag_Mon_Sin_Cos_Weak_Amplitude
Structure to hold the control/status data for Diagnostics mentioned under Monitor weak Sin or Cos sig...
Definition: resolver/v0/resolver.h:542
RDC_RESOLVER_CORE1
#define RDC_RESOLVER_CORE1
Macro used to specify resolver core 1.
Definition: resolver/v0/resolver.h:97
RDC_configParams::Input_resolverSequencerMode
uint8_t Input_resolverSequencerMode
Definition: resolver/v0/resolver.h:628
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_sin_value
int16_t highAmplitude_sin_value
Definition: resolver/v0/resolver.h:523
RDC_disableGainAutoCorrection
static void RDC_disableGainAutoCorrection(uint32_t base, uint8_t core)
Disable Gain Auto Correction.
Definition: resolver/v0/resolver.h:2293
ADC_observationalData::sin_rec
int16_t sin_rec
Definition: resolver/v0/resolver.h:575
Diag_Mon_Rotational_Signal_Integrity_data::cos_neg_zc_peak_mismatch_err
bool cos_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:470
ADC_observationalData::cos_dc
int16_t cos_dc
Definition: resolver/v0/resolver.h:576
RDC_isPhaseAutoCorrectionEnabled
static bool RDC_isPhaseAutoCorrectionEnabled(uint32_t base, uint16_t core)
Returns if the Phase Auto Correction is enabled.
Definition: resolver/v0/resolver.h:2258
RDC_getExcitationSignalFrequencySelect
static uint32_t RDC_getExcitationSignalFrequencySelect(uint32_t base)
Returns the selected Excitation Signal Frequency select.
Definition: resolver/v0/resolver.h:992
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:277
RDC_configParams::core0
Core_config_t core0
Definition: resolver/v0/resolver.h:636
RDC_setExcitationSignalPhase
static void RDC_setExcitationSignalPhase(uint32_t base, uint16_t phase)
Sets the Phase value for the Excitation Signal. Phase values in the range [RDC_EXCITATION_FREQUENCY_M...
Definition: resolver/v0/resolver.h:929
PeakHistogram_observationalData
Struct to hold the peakHistogram Buckets for Ideal Sample Calculation by SW. once the auto ideal samp...
Definition: resolver/v0/resolver.h:677
RDC_enableBPF
static void RDC_enableBPF(uint32_t base, uint8_t core)
enables Band Pass Filter before DC Offset logic.
Definition: resolver/v0/resolver.h:1587
baselineParameters::t2Param6
uint8_t t2Param6
Definition: resolver/v0/resolver.h:657
RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR
#define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR
Interrupt Sources Macros.
Definition: resolver/v0/resolver.h:254
RDC_setDiagnosticsHighAmplitudeData
static void RDC_setDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Sets the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics Controls uint16_t hig...
Definition: resolver/v0/resolver.h:3270
Diag_Mon_Rotational_Signal_Integrity_data::rotpeak_level
uint16_t rotpeak_level
Definition: resolver/v0/resolver.h:478
RDC_getConfiguredIdealSampleBpfAdjust
static uint8_t RDC_getConfiguredIdealSampleBpfAdjust(uint32_t base, uint8_t core)
Definition: resolver/v0/resolver.h:1900
Diag_Mon_Rotational_Signal_Integrity_data::sin_neg_zc_peak_mismatch_err
bool sin_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:472
RDC_disableSequencerInterrupt
static void RDC_disableSequencerInterrupt(uint32_t base)
Disable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1210
RDC_enableDcOffsetAutoCorrection
static void RDC_enableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Enables Auto DC Offset Correction from the estimated values Disables DC Offset Manual Correction logi...
Definition: resolver/v0/resolver.h:1688
RDC_setDiagnosticsSinCosGainDriftData
static void RDC_setDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Sets the Monitor Sin or Cos Gain drift (DOS) diagnostics Controls uint16_t gain_drift_threshold_hi - ...
Definition: resolver/v0/resolver.h:2727
RDC_getPeakHistogramObservationalData
static void RDC_getPeakHistogramObservationalData(uint32_t base, uint8_t resolverCore, PeakHistogram_observationalData *histogram)
Returns the Peak Histogram Bucket data.
Definition: resolver/v0/resolver.h:3429
Core_config_t::Pg_cosPhaseBypassValue
int16_t Pg_cosPhaseBypassValue
Definition: resolver/v0/resolver.h:610
RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:271
Diag_Mon_Rotational_Signal_Integrity_data::sin_multi_zc_error_count
uint8_t sin_multi_zc_error_count
Definition: resolver/v0/resolver.h:477
RDC_forceSequencerInterrupt
static void RDC_forceSequencerInterrupt(uint32_t base)
Force the Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1254
RDC_configParams::ExcFrq_socDelay
uint16_t ExcFrq_socDelay
Definition: resolver/v0/resolver.h:634
RDC_configParams::Int_seqEnable
bool Int_seqEnable
Definition: resolver/v0/resolver.h:639
Diag_Mon_SinCos_Offset_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos offset d...
Definition: resolver/v0/resolver.h:374
baselineParameters::adcParam1
uint8_t adcParam1
Definition: resolver/v0/resolver.h:652
RDC_disableIdealSampleBottomSampling
static void RDC_disableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Disables Bottom Sampling.
Definition: resolver/v0/resolver.h:2022
RDC_isBPFEnabled
static bool RDC_isBPFEnabled(uint32_t base, uint8_t core)
Returns if the BPF is enabled for given RDC Core.
Definition: resolver/v0/resolver.h:1629
RDC_setIdealSampleDetectionThreshold
static void RDC_setIdealSampleDetectionThreshold(uint32_t base, uint8_t core, uint16_t absThresholdValue)
sets Ideal Sample Detetction Threshold. validates the sample for the Ideal Sample time detection comp...
Definition: resolver/v0/resolver.h:1849
Diag_Mon_SinCos_Gain_drift_data::gain_drift_glitch_count
uint8_t gain_drift_glitch_count
Definition: resolver/v0/resolver.h:400
RDC_isSequencerInterruptEnabled
static bool RDC_isSequencerInterruptEnabled(uint32_t base)
Returns if the sequencer error interrupt is enabled.
Definition: resolver/v0/resolver.h:1227
RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR
Definition: resolver/v0/resolver.h:257
RDC_getDiagnosticsHighAmplitudeData
static void RDC_getDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Returns the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics data uint16_t high...
Definition: resolver/v0/resolver.h:3229
RDC_getPhaseEstimation
static int16_t RDC_getPhaseEstimation(uint32_t base, uint8_t core)
returns the Cos Phase Offset Estimation this can be used only if the RDC_getPhaseGainEstimationStatus...
Definition: resolver/v0/resolver.h:2371
RDC_enableCoreInterrupt
static void RDC_enableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
enable Core Interrupt
Definition: resolver/v0/resolver.h:1287
RDC_enablePhaseAutoCorrection
static void RDC_enablePhaseAutoCorrection(uint32_t base, uint8_t core)
Enables Phase Auto Correction.
Definition: resolver/v0/resolver.h:2218
Diag_Mon_Signal_Integrity_SinSq_CosSq
Structure to hold the control/status data for Diagnostics mentioned under Monitor signal integrity by...
Definition: resolver/v0/resolver.h:497
RDC_getDcOffsetManualCorrectionValue
static void RDC_getDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t *sin, int16_t *cos)
Gets the Sin, Cosine Manual Correction values for the Dc Offset block in the given resolver core.
Definition: resolver/v0/resolver.h:1742
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:266
RDC_getPhaseGainEstimationStatus
static bool RDC_getPhaseGainEstimationStatus(uint32_t base, uint8_t core)
Gets status if the Phase Gain Estimation is complete.
Definition: resolver/v0/resolver.h:2047
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_glitchcount
uint8_t highAmplitude_glitchcount
Definition: resolver/v0/resolver.h:522
Diag_Mon_SinCos_Offset_drift_data::offset_drift_sin_hi
bool offset_drift_sin_hi
Definition: resolver/v0/resolver.h:379
Core_config_t::BpfDc_manualSin
int16_t BpfDc_manualSin
Definition: resolver/v0/resolver.h:594
Core_config_t::BpfDc_dcOffCal2
uint8_t BpfDc_dcOffCal2
Definition: resolver/v0/resolver.h:593
RDC_SEQUENCER_MODE_0
#define RDC_SEQUENCER_MODE_0
or returned by RDC_getAdcSequencerOperationalMode()
Definition: resolver/v0/resolver.h:164
RDC_getTrack2Angle
static int16_t RDC_getTrack2Angle(uint32_t base, uint8_t core)
Returns Signed 16 bit angle data from Track2 Loop. the data corresponds to -180 to 180 degrees angle ...
Definition: resolver/v0/resolver.h:2526
Core_config_t::Pg_estimationLimit
uint8_t Pg_estimationLimit
Definition: resolver/v0/resolver.h:604
baselineParameters::t2Param9
bool t2Param9
Definition: resolver/v0/resolver.h:660
RDC_isGainAutoCorrectionEnabled
static bool RDC_isGainAutoCorrectionEnabled(uint32_t base, uint8_t core)
Returns if the Gain Auto Correction is.
Definition: resolver/v0/resolver.h:2314
RDC_paramsInit
void RDC_paramsInit(RDC_configParams *params)
Inits the resolver Configuration parameters.
Diag_Mon_Rotational_Signal_Integrity_data::rotfreq_level
uint16_t rotfreq_level
Definition: resolver/v0/resolver.h:479
RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:272
Track2Constants_t::kvelfilt
uint8_t kvelfilt
Definition: resolver/v0/resolver.h:358
Diag_Mon_ExcFreq_Degradataion_data::excfreqdetected_cos
uint16_t excfreqdetected_cos
Definition: resolver/v0/resolver.h:445
RDC_INTERRUPT_SOURCE_ALL
#define RDC_INTERRUPT_SOURCE_ALL
Definition: resolver/v0/resolver.h:280
baselineParameters::PgParam4
uint16_t PgParam4
Definition: resolver/v0/resolver.h:655
RDC_setDcOffsetManualCorrectionValue
static void RDC_setDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t sin, int16_t cos)
Sets the Sin, Cosine Manual Correction values for the Dc Offset block in the given resolver core.
Definition: resolver/v0/resolver.h:1711
baselineParameters::t2Param5
uint8_t t2Param5
Definition: resolver/v0/resolver.h:656
ADC_observationalData::sin_dc
int16_t sin_dc
Definition: resolver/v0/resolver.h:577
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_cos_error
bool highAmplitude_cos_error
Definition: resolver/v0/resolver.h:526
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_threshold_hi
uint16_t sinsqcossq_threshold_hi
Definition: resolver/v0/resolver.h:498
RDC_disableResolver
static void RDC_disableResolver(uint32_t base)
Disables the Resolver Operation.
Definition: resolver/v0/resolver.h:892
Diag_Mon_SinCos_Gain_drift_data::gain_drift_en
bool gain_drift_en
Definition: resolver/v0/resolver.h:405
RDC_setExcitationSignalFrequencySelect
static void RDC_setExcitationSignalFrequencySelect(uint32_t base, uint8_t FrequencySel)
Sets the Excitation frequency value from the selected values.
Definition: resolver/v0/resolver.h:968
RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:273
RDC_setDiagnosticsSignalIntegritySquareSumData
static void RDC_setDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Sets the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics Controls uint16_t ...
Definition: resolver/v0/resolver.h:3183
RDC_configParams::ExcFrq_freqSel
uint8_t ExcFrq_freqSel
Definition: resolver/v0/resolver.h:630
RDC_disableTrack2Boost
static void RDC_disableTrack2Boost(uint32_t base, uint8_t core)
disables the track2 Boost
Definition: resolver/v0/resolver.h:2484
RDC_clearCalibrationStatus
static void RDC_clearCalibrationStatus(uint32_t base)
Clears Calibration Status for re-enabling Calibration Sequence.
Definition: resolver/v0/resolver.h:1450
Diag_Mon_Cos_Phase_drift_data::phase_drift_threshold_hi
int16_t phase_drift_threshold_hi
Definition: resolver/v0/resolver.h:422
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_sinsq
uint16_t sinsqcossq_sinsq
Definition: resolver/v0/resolver.h:502
RDC_disablePhaseAutoCorrection
static void RDC_disablePhaseAutoCorrection(uint32_t base, uint8_t core)
Disables Phase Auto Correction.
Definition: resolver/v0/resolver.h:2237
RDC_getExcitationSignalPhase
static uint32_t RDC_getExcitationSignalPhase(uint32_t base)
Returns the Phase Value programmed for Excitation signal.
Definition: resolver/v0/resolver.h:949
RDC_setDiagnosticsCosPhaseDriftData
static void RDC_setDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Sets the Monitor Cos Phase drift (DOS) diagnostics Controls int16_t phase_drift_threshold_hi - the ph...
Definition: resolver/v0/resolver.h:2840
RDC_configParams::ExcFrq_phase
uint16_t ExcFrq_phase
Definition: resolver/v0/resolver.h:631
RDC_getAdcObservationalData
static void RDC_getAdcObservationalData(uint32_t base, uint8_t resolverCore, ADC_observationalData *AdcData)
Returns the Observational ADC data to struct type ADC_observationalData int16_t cos_adc - SW Observat...
Definition: resolver/v0/resolver.h:3391
RDC_enableAdcSingleEndedMode
static void RDC_enableAdcSingleEndedMode(uint32_t base)
Enable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:767
baselineParameters::t2Param7
uint8_t t2Param7
Definition: resolver/v0/resolver.h:658
RDC_configParams::Int_core0Interrupts
uint32_t Int_core0Interrupts
Definition: resolver/v0/resolver.h:640
RDC_enableIdealSampleBottomSampling
static void RDC_enableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Enables bottom Sampling. twice the sampling rate than disabled. the track2 loop runs twice the speed ...
Definition: resolver/v0/resolver.h:1986
Diag_Mon_Cos_Phase_drift_data::phase_drift_threshold_lo
int16_t phase_drift_threshold_lo
Definition: resolver/v0/resolver.h:423
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_sin_lo
bool excfreqdrift_sin_lo
Definition: resolver/v0/resolver.h:452
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_glitchcount
uint8_t sinsqcossq_glitchcount
Definition: resolver/v0/resolver.h:500
RDC_getCalibrationStatus
static bool RDC_getCalibrationStatus(uint32_t base)
Returns the Calibration Status.
Definition: resolver/v0/resolver.h:1434
Diag_Mon_SinCos_Gain_drift_data::gain_drift_cos_lo
bool gain_drift_cos_lo
Definition: resolver/v0/resolver.h:402
DebugP.h
RDC_getDiagnosticsSinCosOffsetDriftData
static void RDC_getDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Returns the Monitor Sin or Cos Offset Drift (DOS) diagnostics data int16_t offset_drift_threshold_hi ...
Definition: resolver/v0/resolver.h:2572
RDC_enableCalibration
static void RDC_enableCalibration(uint32_t base)
Enables ADC Calibration.
Definition: resolver/v0/resolver.h:1491
RDC_getConfiguredIdealSampleDetectionThreshold
static uint16_t RDC_getConfiguredIdealSampleDetectionThreshold(uint32_t base, uint8_t core)
Returns the confiugured Ideal Sample Detection Threshold.
Definition: resolver/v0/resolver.h:1869
Diag_Mon_SinCos_Gain_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos Gain dri...
Definition: resolver/v0/resolver.h:397
Core_config_t::IdealSample_absThresholdValue
uint16_t IdealSample_absThresholdValue
Definition: resolver/v0/resolver.h:598
RDC_disableExcitationSignalSyncIn
static void RDC_disableExcitationSignalSyncIn(uint32_t base)
Disables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:1039
ADC_observationalData::sin_pgc
int16_t sin_pgc
Definition: resolver/v0/resolver.h:579
Diag_Mon_Rotational_Signal_Integrity_data::zero_cross_rot_en
bool zero_cross_rot_en
Definition: resolver/v0/resolver.h:480
RDC_getDiagnosticsSinCosGainDriftData
static void RDC_getDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Returns the Monitor Sin or Cos Gain drift (DOS) diagnostics data uint16_t gain_drift_threshold_hi - t...
Definition: resolver/v0/resolver.h:2677
RDC_clearPhaseGainEstimationStatus
static void RDC_clearPhaseGainEstimationStatus(uint32_t base, uint8_t core)
Clears the Phase Gain Estimation status. This can be used for any udpates to the thresholds or the tr...
Definition: resolver/v0/resolver.h:2067
RDC_setAdcSequencerOperationalMode
static void RDC_setAdcSequencerOperationalMode(uint32_t base, uint8_t operationalMode)
sets Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 SAM...
Definition: resolver/v0/resolver.h:856
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:265
RDC_enableResolver
static void RDC_enableResolver(uint32_t base)
Enables the Resolver Operation.
Definition: resolver/v0/resolver.h:876
RDC_setAdcBurstCount
static void RDC_setAdcBurstCount(uint32_t base, uint8_t burstCount)
sets the ADC Burst count, samples to be averaged.
Definition: resolver/v0/resolver.h:729
RDC_enableSequencerInterrupt
static void RDC_enableSequencerInterrupt(uint32_t base)
Enable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1194
RDC_getIdealSampleTime
static uint8_t RDC_getIdealSampleTime(uint32_t base, uint8_t core)
Returns the Ideal Sample Time Esitimated by the resolver core.
Definition: resolver/v0/resolver.h:1827
RDC_configParams::Input_socWidth
uint8_t Input_socWidth
Definition: resolver/v0/resolver.h:626
RDC_setDiagnosticsExcFreqDegradationData
static void RDC_setDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Sets the Monitor excitation frequency degradation or loss (DOS) diagnostics Controls uint16_t excfreq...
Definition: resolver/v0/resolver.h:2966
RDC_getConfiguredCosPhaseBypass
static int16_t RDC_getConfiguredCosPhaseBypass(uint32_t base, uint8_t core)
Returns the configrued Cosine Phase Bypass value.
Definition: resolver/v0/resolver.h:2145
Diag_Mon_SinCos_Offset_drift_data::offset_drift_sin_lo
bool offset_drift_sin_lo
Definition: resolver/v0/resolver.h:380
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_threshold_hi
uint16_t excfreqdrift_threshold_hi
Definition: resolver/v0/resolver.h:446
RDC_EXCITATION_FREQUENCY_20K
#define RDC_EXCITATION_FREQUENCY_20K
select 20KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:216
RDC_getDiagnosticsSignalIntegritySquareSumData
static void RDC_getDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Returns the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics data uint16_t s...
Definition: resolver/v0/resolver.h:3134
RDC_DC_OFFSET_SIN_ESTIMATION
#define RDC_DC_OFFSET_SIN_ESTIMATION
Definition: resolver/v0/resolver.h:112
RDC_getConfiguredAdcBurstCount
static uint8_t RDC_getConfiguredAdcBurstCount(uint32_t base)
Returns the configured Burst count value.
Definition: resolver/v0/resolver.h:752
RDC_enablePhaseGainEstimation
static void RDC_enablePhaseGainEstimation(uint32_t base, uint8_t core)
Enables Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:2160
RDC_MAX_EXCITATION_AMPLITUDE
#define RDC_MAX_EXCITATION_AMPLITUDE
Maximum Excitation Signal Amplitude.
Definition: resolver/v0/resolver.h:90
Diag_Mon_Rotational_Signal_Integrity_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor rotational signal i...
Definition: resolver/v0/resolver.h:469
RDC_clearExcitationSignalEventStatus
static void RDC_clearExcitationSignalEventStatus(uint32_t base)
Clears SyncIn event status.
Definition: resolver/v0/resolver.h:1089
RDC_disableDcOffsetAutoCorrection
static void RDC_disableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Disbales Auto Offset correction from the estimated values Enables DC Offset Manual Correction logic.
Definition: resolver/v0/resolver.h:1646
RDC_getConfiguredGainBypassValue
static void RDC_getConfiguredGainBypassValue(uint32_t base, uint8_t core, uint16_t *sinGainBypass, uint16_t *cosGainBypass)
Returns the sine and cosine gain bypass values configured.
Definition: resolver/v0/resolver.h:2352
RDC_setCosPhaseBypass
static void RDC_setCosPhaseBypass(uint32_t base, uint8_t core, int16_t cosPhaseBypass)
sets the Cos Phase Manual Bypass Value
Definition: resolver/v0/resolver.h:2123
baselineParameters::IdealParam2
uint8_t IdealParam2
Definition: resolver/v0/resolver.h:653
RDC_setPhaseGainEstimationTrainLimit
static void RDC_setPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core, uint8_t pgEstimationLimit)
Sets the Phase Gain Estimation train limit. if the programmed value is x, 2^x rotations are considere...
Definition: resolver/v0/resolver.h:2085
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:274
Core_config_t::BpfDc_dcOffCal1
uint8_t BpfDc_dcOffCal1
Definition: resolver/v0/resolver.h:592
RDC_forceCoreInterrupt
static void RDC_forceCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Force the Core Interrupt.
Definition: resolver/v0/resolver.h:1370
RDC_setExcitationSignalSocDelay
static void RDC_setExcitationSignalSocDelay(uint32_t base, uint16_t socDelay)
Sets the SOC Delay from the PWM Exciation Signal.
Definition: resolver/v0/resolver.h:1123
Core_config_t::IdealSample_sampleAdjustCount
uint8_t IdealSample_sampleAdjustCount
Definition: resolver/v0/resolver.h:599
RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:263
RDC_EXCITATION_FREQUENCY_5K
#define RDC_EXCITATION_FREQUENCY_5K
or returned by RDC_getExcitationSignalFrequencySelect()
Definition: resolver/v0/resolver.h:210
Diag_Mon_SinCos_Offset_drift_data::offset_drift_threshold_hi
int16_t offset_drift_threshold_hi
Definition: resolver/v0/resolver.h:375
RDC_getExcitationSignalPhaseInfo
static uint32_t RDC_getExcitationSignalPhaseInfo(uint32_t base)
Returns the latched value of the last pwm_sync_in rise event of the pwm phase. this is updated on eve...
Definition: resolver/v0/resolver.h:1107
baselineParameters
Struct holds the Baseline Parameter values Can be passed to RDC_BaselineParametersInit(uint32_t base)...
Definition: resolver/v0/resolver.h:651
Diag_Mon_Rotational_Signal_Integrity_data::cos_multi_zc_error_count
uint8_t cos_multi_zc_error_count
Definition: resolver/v0/resolver.h:476
Core_config_t::IdealSample_mode
uint8_t IdealSample_mode
Definition: resolver/v0/resolver.h:600
Diag_Mon_Rotational_Signal_Integrity_data::sin_multi_zc_error_err
bool sin_multi_zc_error_err
Definition: resolver/v0/resolver.h:474
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_threshold_lo
uint16_t sinsqcossq_threshold_lo
Definition: resolver/v0/resolver.h:499
ADC_observationalData::cos_rec
int16_t cos_rec
Definition: resolver/v0/resolver.h:574
RDC_EXCITATION_FREQUENCY_10K
#define RDC_EXCITATION_FREQUENCY_10K
select 10KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:213
RDC_getAdcSequencerOperationalMode
static uint32_t RDC_getAdcSequencerOperationalMode(uint32_t base)
returns Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 ...
Definition: resolver/v0/resolver.h:828
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_cos_value
int16_t lowAmplitude_cos_value
Definition: resolver/v0/resolver.h:547
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:187
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_hi
bool excfreqdrift_hi
Definition: resolver/v0/resolver.h:450
Core_config_t::Pg_estimationEnable
bool Pg_estimationEnable
Definition: resolver/v0/resolver.h:603
RDC_getTrack2Velocity
static int32_t RDC_getTrack2Velocity(uint32_t base, uint8_t core)
Returns Signed 32 bit Velocity data from Track2 Loop.
Definition: resolver/v0/resolver.h:2545
PeakHistogram_observationalData::peakHistgoramBucket
uint8_t peakHistgoramBucket[20]
Definition: resolver/v0/resolver.h:678
RDC_disableBPF
static void RDC_disableBPF(uint32_t base, uint8_t core)
Disables Band Pass Filter Logic before DC Offset logic.
Definition: resolver/v0/resolver.h:1607
RDC_configParams::ExcFrq_enableSyncIn
bool ExcFrq_enableSyncIn
Definition: resolver/v0/resolver.h:633
RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:262
RDC_isIdealSampleBottomSamplingEnabled
static bool RDC_isIdealSampleBottomSamplingEnabled(uint32_t base, uint8_t core)
Returns if the Bottom Sampling is enabled in the sample selection.
Definition: resolver/v0/resolver.h:2007
RDC_setDiagnosticsWeakAmplitudeData
static void RDC_setDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Sets the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics Controls uint16_t lowAmpl...
Definition: resolver/v0/resolver.h:3348
RDC_setExcitationSignalAmplitudeControl
static void RDC_setExcitationSignalAmplitudeControl(uint32_t base, uint8_t amplitude)
set the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1157
RDC_setAdcSocWidth
static void RDC_setAdcSocWidth(uint32_t base, uint8_t socWidth)
sets the Start of Conversion Width for the ADC conversion
Definition: resolver/v0/resolver.h:691
RDC_getConfiguredAdcSocWidth
static uint8_t RDC_getConfiguredAdcSocWidth(uint32_t base)
Returns the configured ADC SOC Width value.
Definition: resolver/v0/resolver.h:708
RDC_getDiagnosticsExcFreqDegradationData
static void RDC_getDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Returns the Monitor excitation frequency degradation or loss (DOS) diagnostics data uint16_t excfreqd...
Definition: resolver/v0/resolver.h:2900
Diag_Mon_SinCos_Gain_drift_data::gain_drift_threshold_hi
uint16_t gain_drift_threshold_hi
Definition: resolver/v0/resolver.h:398
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_sin_value
int16_t lowAmplitude_sin_value
Definition: resolver/v0/resolver.h:546
RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:270
RDC_configParams::ExcFrq_amplitude
uint8_t ExcFrq_amplitude
Definition: resolver/v0/resolver.h:632
RDC_getDiagnosticsCosPhaseDriftData
static void RDC_getDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Returns the Monitor Cos Phase drift (DOS) diagnostics data int16_t phase_drift_threshold_hi - the con...
Definition: resolver/v0/resolver.h:2796
RDC_isResolverEnabled
static bool RDC_isResolverEnabled(uint32_t base)
Returns if Resolver is enabled.
Definition: resolver/v0/resolver.h:910
RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR
Definition: resolver/v0/resolver.h:255
RDC_isExcitationSignalSyncInEnabled
static bool RDC_isExcitationSignalSyncInEnabled(uint32_t base)
Returns if the Excitation Sync-in Signal is enabled.
Definition: resolver/v0/resolver.h:1057
Diag_Mon_SinCos_Offset_drift_data::offset_drift_cos_hi
bool offset_drift_cos_hi
Definition: resolver/v0/resolver.h:377
RDC_getExcitationSignalEventStatus
static uint32_t RDC_getExcitationSignalEventStatus(uint32_t base)
returns if there is a sync in event after the RDC_enableResolver() has been called once this returns ...
Definition: resolver/v0/resolver.h:1074
RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:264
Core_config_t::Pg_autoCorrectionEnable
bool Pg_autoCorrectionEnable
Definition: resolver/v0/resolver.h:607
ADC_observationalData
Structure to hold the Observational Data reads int16_t cos_adc - SW Observational ADC data post latch...
Definition: resolver/v0/resolver.h:571
Diag_Mon_SinCos_Offset_drift_data::offset_drift_en
bool offset_drift_en
Definition: resolver/v0/resolver.h:381
RDC_getGainEstimation
static void RDC_getGainEstimation(uint32_t base, uint8_t core, float *sinGainEstimateSq, float *cosGainEstimateSq)
returns the Gain Squared estimates for sin and cosine gain values
Definition: resolver/v0/resolver.h:2397
RDC_configParams
Struct holds the RDC configurations Can be passed to RDC_paramsInit(RDC_configParams* params); RDC_in...
Definition: resolver/v0/resolver.h:623
Diag_Mon_SinCos_Gain_drift_data::gain_drift_cos_hi
bool gain_drift_cos_hi
Definition: resolver/v0/resolver.h:401