AM263Px MCU+ SDK: sdlr_esm.h Source File

| AM263Px MCU+ SDK 26.00.00 |

v0/v0_0/sdlr_esm.h
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1 /********************************************************************
2 * Copyright (C) 2022-2024 Texas Instruments Incorporated.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33 #ifndef SDLR_ESM_H_
34 #define SDLR_ESM_H_
35
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40
41 #include <stdint.h>
42
43 /**************************************************************************
44 * Module Base Offset Values
45 **************************************************************************/
46
47 #define SDL_ESM_REGS_BASE (0x00000000U)
48
49
50 /**************************************************************************
51 * Hardware Region : ESM Registers
52 **************************************************************************/
53
54
55 /**************************************************************************
56 * Register Overlay Structure
57 **************************************************************************/
58
59 typedef struct {
60 volatile uint32_t RAW; /* Config Error Raw Status/Set Register */
61 volatile uint32_t STS; /* Level Error Interrupt Enable Status/Clear Register */
62 volatile uint32_t INTR_EN_SET; /* Level Error Interrutp Enable Set Register */
63 volatile uint32_t INTR_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
64 volatile uint32_t INT_PRIO; /* Level Error Interrupt Enabled Clear Register */
65 volatile uint32_t PIN_EN_SET; /* Level Error Interrupt Enabled Clear Register */
66 volatile uint32_t PIN_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
67 volatile uint8_t Resv_32[4];
68 } SDL_esmRegs_ERR_GRP;
69
70
71 typedef struct {
72 volatile uint32_t PID; /* Revision Register */
73 volatile uint32_t INFO; /* Info Register */
74 volatile uint32_t EN; /* Global Enable Register */
75 volatile uint32_t SFT_RST; /* Global Soft Reset Register */
76 volatile uint32_t ERR_RAW; /* Config Error Raw Status/Set Register */
77 volatile uint32_t ERR_STS; /* Config Error Interrupt Enable Status/Clear Register */
78 volatile uint32_t ERR_EN_SET; /* Config Error Interrutp Enable Set Register */
79 volatile uint32_t ERR_EN_CLR; /* Config Error Interrupt Enabled Clear Register */
80 volatile uint32_t LOW_PRI; /* Low Priority Prioritized Register */
81 volatile uint32_t HI_PRI; /* High Priority Prioritized Register */
82 volatile uint32_t LOW; /* Low Priority Interrupt Status Register */
83 volatile uint32_t HI; /* High Priority Interrupt Status Register */
84 volatile uint32_t EOI; /* EOI Interrupt Register */
85 volatile uint8_t Resv_64[12];
86 volatile uint32_t PIN_CTRL; /* Error Pin Control Register */
87 volatile uint32_t PIN_STS; /* Error Pin Status Register */
88 volatile uint32_t PIN_CNTR; /* Error Counter Value Register */
89 volatile uint32_t PIN_CNTR_PRE; /* Error Counter Value Pre-Load Register */
90 volatile uint32_t PWMH_PIN_CNTR; /* Error PWM High Counter Value Register */
91 volatile uint32_t PWMH_PIN_CNTR_PRE; /* Error PWM High Counter Value Pre-Load Register */
92 volatile uint32_t PWML_PIN_CNTR; /* Error PWM Low Counter Value Register */
93 volatile uint32_t PWML_PIN_CNTR_PRE; /* Error PWM Low Counter Value Pre-Load Register */
94 volatile uint8_t Resv_1024[944];
95 SDL_esmRegs_ERR_GRP ERR_GRP[32];
96 } SDL_esmRegs;
97
98
99 /**************************************************************************
100 * Register Macros
101 **************************************************************************/
102
103 #define SDL_ESM_PID (0x00000000U)
104 #define SDL_ESM_INFO (0x00000004U)
105 #define SDL_ESM_EN (0x00000008U)
106 #define SDL_ESM_SFT_RST (0x0000000CU)
107 #define SDL_ESM_ERR_RAW (0x00000010U)
108 #define SDL_ESM_ERR_STS (0x00000014U)
109 #define SDL_ESM_ERR_EN_SET (0x00000018U)
110 #define SDL_ESM_ERR_EN_CLR (0x0000001CU)
111 #define SDL_ESM_LOW_PRI (0x00000020U)
112 #define SDL_ESM_HI_PRI (0x00000024U)
113 #define SDL_ESM_LOW (0x00000028U)
114 #define SDL_ESM_HI (0x0000002CU)
115 #define SDL_ESM_EOI (0x00000030U)
116 #define SDL_ESM_PIN_CTRL (0x00000040U)
117 #define SDL_ESM_PIN_STS (0x00000044U)
118 #define SDL_ESM_PIN_CNTR (0x00000048U)
119 #define SDL_ESM_PIN_CNTR_PRE (0x0000004CU)
120 #define SDL_ESM_PWMH_PIN_CNTR (0x00000050U)
121 #define SDL_ESM_PWMH_PIN_CNTR_PRE (0x00000054U)
122 #define SDL_ESM_PWML_PIN_CNTR (0x00000058U)
123 #define SDL_ESM_PWML_PIN_CNTR_PRE (0x0000005CU)
124 #define SDL_ESM_ERR_GRP_RAW(ERR_GRP) (0x00000400U+((ERR_GRP)*0x20U))
125 #define SDL_ESM_ERR_GRP_STS(ERR_GRP) (0x00000404U+((ERR_GRP)*0x20U))
126 #define SDL_ESM_ERR_GRP_INTR_EN_SET(ERR_GRP) (0x00000408U+((ERR_GRP)*0x20U))
127 #define SDL_ESM_ERR_GRP_INTR_EN_CLR(ERR_GRP) (0x0000040CU+((ERR_GRP)*0x20U))
128 #define SDL_ESM_ERR_GRP_INT_PRIO(ERR_GRP) (0x00000410U+((ERR_GRP)*0x20U))
129 #define SDL_ESM_ERR_GRP_PIN_EN_SET(ERR_GRP) (0x00000414U+((ERR_GRP)*0x20U))
130 #define SDL_ESM_ERR_GRP_PIN_EN_CLR(ERR_GRP) (0x00000418U+((ERR_GRP)*0x20U))
131
132 /**************************************************************************
133 * Field Definition Macros
134 **************************************************************************/
135
136
137 /* RAW */
138
139 #define SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)
140 #define SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)
141 #define SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)
142
143 /* STS */
144
145 #define SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)
146 #define SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)
147 #define SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)
148
149 /* INTR_EN_SET */
150
151 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)
152 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
153 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)
154
155 /* INTR_EN_CLR */
156
157 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
158 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
159 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
160
161 /* INT_PRIO */
162
163 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)
164 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)
165 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)
166
167 /* PIN_EN_SET */
168
169 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)
170 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)
171 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)
172
173 /* PIN_EN_CLR */
174
175 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)
176 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)
177 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)
178
179 /* PID */
180
181 #define SDL_ESM_PID_MINOR_MASK (0x0000003FU)
182 #define SDL_ESM_PID_MINOR_SHIFT (0x00000000U)
183 #define SDL_ESM_PID_MINOR_MAX (0x0000003FU)
184
185 #define SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)
186 #define SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)
187 #define SDL_ESM_PID_CUSTOM_MAX (0x00000003U)
188
189 #define SDL_ESM_PID_MAJOR_MASK (0x00000700U)
190 #define SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)
191 #define SDL_ESM_PID_MAJOR_MAX (0x00000007U)
192
193 #define SDL_ESM_PID_RTL_MASK (0x0000F800U)
194 #define SDL_ESM_PID_RTL_SHIFT (0x0000000BU)
195 #define SDL_ESM_PID_RTL_MAX (0x0000001FU)
196
197 #define SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)
198 #define SDL_ESM_PID_FUNC_SHIFT (0x00000010U)
199 #define SDL_ESM_PID_FUNC_MAX (0x00000FFFU)
200
201 #define SDL_ESM_PID_BU_MASK (0x30000000U)
202 #define SDL_ESM_PID_BU_SHIFT (0x0000001CU)
203 #define SDL_ESM_PID_BU_MAX (0x00000003U)
204
205 #define SDL_ESM_PID_SCHEME_MASK (0xC0000000U)
206 #define SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)
207 #define SDL_ESM_PID_SCHEME_MAX (0x00000003U)
208
209 /* INFO */
210
211 #define SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)
212 #define SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)
213 #define SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)
214
215 #define SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)
216 #define SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)
217 #define SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)
218
219 #define SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)
220 #define SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)
221 #define SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)
222
223 /* EN */
224
225 #define SDL_ESM_EN_KEY_MASK (0x0000000FU)
226 #define SDL_ESM_EN_KEY_SHIFT (0x00000000U)
227 #define SDL_ESM_EN_KEY_MAX (0x0000000FU)
228
229 /* SFT_RST */
230
231 #define SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)
232 #define SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)
233 #define SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)
234
235 /* ERR_RAW */
236
237 #define SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)
238 #define SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)
239 #define SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)
240
241 /* ERR_STS */
242
243 #define SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)
244 #define SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)
245 #define SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)
246
247 /* ERR_EN_SET */
248
249 #define SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)
250 #define SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)
251 #define SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)
252
253 /* ERR_EN_CLR */
254
255 #define SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
256 #define SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)
257 #define SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
258
259 /* LOW_PRI */
260
261 #define SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)
262 #define SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)
263 #define SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)
264
265 #define SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)
266 #define SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)
267 #define SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)
268
269 /* HI_PRI */
270
271 #define SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)
272 #define SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)
273 #define SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)
274
275 #define SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)
276 #define SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)
277 #define SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)
278
279 /* LOW */
280
281 #define SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)
282 #define SDL_ESM_LOW_STS_SHIFT (0x00000000U)
283 #define SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)
284
285 /* HI */
286
287 #define SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)
288 #define SDL_ESM_HI_STS_SHIFT (0x00000000U)
289 #define SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)
290
291 /* EOI */
292
293 #define SDL_ESM_EOI_KEY_MASK (0x000007FFU)
294 #define SDL_ESM_EOI_KEY_SHIFT (0x00000000U)
295 #define SDL_ESM_EOI_KEY_MAX (0x000007FFU)
296
297 /* PIN_CTRL */
298
299 #define SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)
300 #define SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)
301 #define SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)
302
303 #define SDL_ESM_PIN_CTRL_PWM_EN_MASK (0x000000F0U)
304 #define SDL_ESM_PIN_CTRL_PWM_EN_SHIFT (0x00000004U)
305 #define SDL_ESM_PIN_CTRL_PWM_EN_MAX (0x0000000FU)
306
307 /* PIN_STS */
308
309 #define SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)
310 #define SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)
311 #define SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)
312
313 /* PIN_CNTR */
314
315 #define SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)
316 #define SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)
317 #define SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)
318
319 /* PIN_CNTR_PRE */
320
321 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)
322 #define SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)
323 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)
324
325 #ifdef __cplusplus
326 }
327 #endif
328 #endif /* SDLR_ESM_ */
SDL_esmRegs::ERR_EN_SET
volatile uint32_t ERR_EN_SET
Definition: v0/v0_0/sdlr_esm.h:78
SDL_esmRegs::HI
volatile uint32_t HI
Definition: v0/v0_0/sdlr_esm.h:83
SDL_esmRegs_ERR_GRP::STS
volatile uint32_t STS
Definition: v0/v0_0/sdlr_esm.h:61
SDL_esmRegs::PIN_CNTR
volatile uint32_t PIN_CNTR
Definition: v0/v0_0/sdlr_esm.h:88
SDL_esmRegs::PIN_STS
volatile uint32_t PIN_STS
Definition: v0/v0_0/sdlr_esm.h:87
SDL_esmRegs::PWML_PIN_CNTR_PRE
volatile uint32_t PWML_PIN_CNTR_PRE
Definition: v0/v0_0/sdlr_esm.h:93
SDL_esmRegs::PWML_PIN_CNTR
volatile uint32_t PWML_PIN_CNTR
Definition: v0/v0_0/sdlr_esm.h:92
SDL_esmRegs_ERR_GRP::PIN_EN_SET
volatile uint32_t PIN_EN_SET
Definition: v0/v0_0/sdlr_esm.h:65
SDL_esmRegs::PID
volatile uint32_t PID
Definition: v0/v0_0/sdlr_esm.h:72
SDL_esmRegs_ERR_GRP::RAW
volatile uint32_t RAW
Definition: v0/v0_0/sdlr_esm.h:60
SDL_esmRegs::ERR_RAW
volatile uint32_t ERR_RAW
Definition: v0/v0_0/sdlr_esm.h:76
SDL_esmRegs::PIN_CTRL
volatile uint32_t PIN_CTRL
Definition: v0/v0_0/sdlr_esm.h:86
SDL_esmRegs::SFT_RST
volatile uint32_t SFT_RST
Definition: v0/v0_0/sdlr_esm.h:75
SDL_esmRegs::INFO
volatile uint32_t INFO
Definition: v0/v0_0/sdlr_esm.h:73
SDL_esmRegs
Definition: v0/v0_0/sdlr_esm.h:71
SDL_esmRegs_ERR_GRP
Definition: v0/v0_0/sdlr_esm.h:59
SDL_esmRegs_ERR_GRP::PIN_EN_CLR
volatile uint32_t PIN_EN_CLR
Definition: v0/v0_0/sdlr_esm.h:66
SDL_esmRegs::EOI
volatile uint32_t EOI
Definition: v0/v0_0/sdlr_esm.h:84
SDL_esmRegs::LOW
volatile uint32_t LOW
Definition: v0/v0_0/sdlr_esm.h:82
SDL_esmRegs::PWMH_PIN_CNTR
volatile uint32_t PWMH_PIN_CNTR
Definition: v0/v0_0/sdlr_esm.h:90
SDL_esmRegs::HI_PRI
volatile uint32_t HI_PRI
Definition: v0/v0_0/sdlr_esm.h:81
SDL_esmRegs::PIN_CNTR_PRE
volatile uint32_t PIN_CNTR_PRE
Definition: v0/v0_0/sdlr_esm.h:89
SDL_esmRegs_ERR_GRP::INT_PRIO
volatile uint32_t INT_PRIO
Definition: v0/v0_0/sdlr_esm.h:64
SDL_esmRegs::LOW_PRI
volatile uint32_t LOW_PRI
Definition: v0/v0_0/sdlr_esm.h:80
SDL_esmRegs::ERR_STS
volatile uint32_t ERR_STS
Definition: v0/v0_0/sdlr_esm.h:77
SDL_esmRegs::EN
volatile uint32_t EN
Definition: v0/v0_0/sdlr_esm.h:74
SDL_esmRegs_ERR_GRP::INTR_EN_SET
volatile uint32_t INTR_EN_SET
Definition: v0/v0_0/sdlr_esm.h:62
SDL_esmRegs::ERR_EN_CLR
volatile uint32_t ERR_EN_CLR
Definition: v0/v0_0/sdlr_esm.h:79
SDL_esmRegs_ERR_GRP::INTR_EN_CLR
volatile uint32_t INTR_EN_CLR
Definition: v0/v0_0/sdlr_esm.h:63
SDL_esmRegs::PWMH_PIN_CNTR_PRE
volatile uint32_t PWMH_PIN_CNTR_PRE
Definition: v0/v0_0/sdlr_esm.h:91