AM263Px MCU+ SDK: How to add compiler generated sections for instrumentation binaries?

| AM263Px MCU+ SDK 26.00.00 |

How to add compiler generated sections for instrumentation binaries?

# Introduction

When all libraries and application is compiled in instrumentation mode, some extra ELF sections are created by the compiler. In any examples, these additional section handling needs to be done in linker script.

If custom linker command file is used then changes in `Memory Configurator` (Memory Configurator) is not required.

## Using Memory Configurator

Open `Memory Configurator`. And under that, open "`Section`". Something like following will be shown:

On top, it can be seen that there are a total of 14 sections that are present. In the same list, scroll down to `Memory Segments` and click on it. Show as following:

From here, delete `.bss` from the `Output Section`. The sections that are generated by the compiler for instrumented binaries are uninitialized sections. Section `.bss` is also an uninitialized section.

Add a new section by clicking add button at the top in the above image.

`Name` of this new section can be `uninit_section`.

`Start Group` field is `__BSS_START`.

`End Group` field is `__BSS_END`.

Make sure that `Split Across Memories` is un-checked.

`Load Memory` is selected to any destination memory as per application.

In the `output section` add following 3 sections.

Name | Start Section | End Section | Alignment
--- | --- | --- | ---
.bss |  |  | 8
__llvm_prf_cnts |  |  | 8
__llvm_prf_bits |  |  | 8

Here, `start section` and `end section` fields for all `output sections` are to be left blank

After all of the above changes, the section would look like the following:

Above changes clubs all the uninit sections in input object files in one section in output ELF file which will be cleared on runtime in the application. This clearing is handled automatically by the startup code and no changes are required for this.

The generated linker file would contain the following:

GROUP : {
.bss : {
} palign(8)
__llvm_prf_cnts : {
} palign(8)
__llvm_prf_bits : {
} palign(8)
} > MSRAM AT > MSRAM
RUN_START(__BSS_START)
RUN_END(__BSS_END)

In this particular example, load and run address is chosen as MSRAM which is just a representative name of a part of on chip RAM memory.

## Linker changes

In the linker file, some change are required. Add following lines of code in linker file when using ti-arm-clang compiler. This code should be inside `SECTIONS`.

GROUP
{
.bss:{} palign(8)
__llvm_prf_cnts: {} align(8)
__llvm_prf_bits: {} align(8)
} > OCRAM
RUN_START(__BSS_START)
RUN_END(__BSS_END)

Few things to keep tack of:

1. Sections `.bss`, `__llvm_prf_cnts` and `__llvm_prf_bits` should not be present anywhere else in the linker file.
2. `OCRAM` should be replaced with correct memory name.