AM263Px MCU+ SDK: sdl_dcc.h Source File

| AM263Px MCU+ SDK 26.00.00 |

dcc/v1/sdl_dcc.h
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1 /*
2 * Copyright (c) Texas Instruments Incorporated 2022
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
50 #ifndef SDL_DCC_H_
51 #define SDL_DCC_H_
52
53
54
55 /* ========================================================================== */
56 /* Include Files */
57 /* ========================================================================== */
58
59
60 #include <stdint.h>
61 #include <stdbool.h>
62 #include <sdl/include/hw_types.h>
63 #include <sdl/include/sdl_types.h>
64
65 #include <sdl/dcc/v1/sdl_dcc.h>
66 #include <sdl/dcc/v1/soc/sdl_dcc_soc.h>
67
68
69
70
71 #ifdef __cplusplus
72 extern "C" {
73 #endif
74
95 /* ========================================================================== */
96 /* Macros & Typedefs */
97 /* ========================================================================== */
98
108 #define DCC_SRC0_COUNT_MAX (0xFFFFFU)
109
112 #define DCC_SRC0_VALID_MAX (0x0FFFFU)
113
116 #define DCC_SRC1_COUNT_MAX (0xFFFFFU)
117
118 #define MIN_CLK0_VLD_SEED (4u)
119
141 typedef uint32_t SDL_DCC_mode;
142
143 #define SDL_DCC_MODE_SINGLE_SHOT (DCC_DCCGCTRL_SINGLESHOT_MODE)
144
147 #define SDL_DCC_MODE_CONTINUOUS (DCC_DCCGCTRL_SINGLESHOT_DISABLE)
148
159 typedef uint32_t SDL_DCC_clkSrc0;
160
161 #define SDL_DCC_CLK0_SRC_CLOCK0_0 (DCC_DCCCLKSRC0_CLKSRC0_0)
162
163 #define SDL_DCC_CLK0_SRC_CLOCK0_1 (DCC_DCCCLKSRC0_CLKSRC0_1)
164
165 #define SDL_DCC_CLK0_SRC_CLOCK0_2 (DCC_DCCCLKSRC0_CLKSRC0_2)
166
177 typedef uint32_t SDL_DCC_clkSrc1;
178
179 #define SDL_DCC_CLK1_SRC_CLOCKSRC0 (DCC_DCCCLKSRC1_CLKSRC_0)
180
181 #define SDL_DCC_CLK1_SRC_CLOCKSRC1 (DCC_DCCCLKSRC1_CLKSRC_1)
182
183 #define SDL_DCC_CLK1_SRC_CLOCKSRC2 (DCC_DCCCLKSRC1_CLKSRC_2)
184
185 #define SDL_DCC_CLK1_SRC_CLOCKSRC3 (DCC_DCCCLKSRC1_CLKSRC_3)
186
187 #define SDL_DCC_CLK1_SRC_CLOCKSRC4 (DCC_DCCCLKSRC1_CLKSRC_4)
188
189 #define SDL_DCC_CLK1_SRC_CLOCKSRC5 (DCC_DCCCLKSRC1_CLKSRC_5)
190
191 #define SDL_DCC_CLK1_SRC_CLOCKSRC6 (DCC_DCCCLKSRC1_CLKSRC_6)
192
193 #define SDL_DCC_CLK1_SRC_CLOCKSRC7 (DCC_DCCCLKSRC1_CLKSRC_7)
194
195 #define SDL_DCC_CLK1_SRC_FICLK (SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER)
196
208 typedef uint32_t SDL_DCC_intrType;
209
210 #define SDL_DCC_INTERRUPT_ERR (0x0U)
211
212 #define SDL_DCC_INTERRUPT_DONE (0x1U)
213
218 /* ========================================================================== */
219 /* Structures */
220 /* ========================================================================== */
221
222
231 typedef struct SDL_DCC_config_st
232 {
233 SDL_DCC_mode mode;
237 SDL_DCC_clkSrc0 clk0Src;
241 uint32_t clk1Src;
245 uint32_t clk0Seed;
247 uint32_t clk0ValidSeed;
249 uint32_t clk1Seed;
251 }SDL_DCC_config;
252
253
254 typedef struct
255 {
256 bool doneIntr;
257 /* Indicates if a done interrupt is currently pending */
258 bool errIntr;
259 /* Indicates if an error interrupt is currently pending */
260 SDL_DCC_config config;
261 /* Pointer to DCC config structure */
262 uint32_t clk0Cnt;
263 /* Current COUNT0 value of clock source 0 */
264 uint32_t clk0Valid;
265 /* Current VALID0 value */
266 uint32_t clk1Cnt;
267 /* Current COUNT1 value of clock source 1 */
268 }SDL_DCC_Status;
269
270
271 typedef struct SDL_DCC_staticRegs_st
272 {
273 uint32_t DCC_REV;
274 /* DCC revision register */
275 uint32_t DCC_CNTSEED0;
276 /* COUNT0 SEED register */
277 uint32_t DCC_VALIDSEED0;
278 /* VALID0 SEED register */
279 uint32_t DCC_CNTSEED1;
280 /* COUNT1 SEED register */
281 uint32_t DCC_CLKSRC1;
282 /* CLOCK SOURCE1 register */
283 uint32_t DCC_CLKSRC0;
284 /* CLOCK SOURCE0 register */
285 }SDL_DCC_staticRegs;
286
290 /* ========================================================================== */
291 /* Global Variables */
292 /* ========================================================================== */
293
294 /* None */
295
296 /* ========================================================================== */
297 /* Function Declarations */
298 /* ========================================================================== */
299
316 int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig);
317
325 int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig);
331 int32_t SDL_DCC_enable(SDL_DCC_Inst instance);
337 int32_t SDL_DCC_disable(SDL_DCC_Inst instance);
345 int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_Status *pStatus);
353 int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr);
361 int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr);
369 int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs);
370
375 /****************************************************************************************************
376 * Register Definitions
377 ****************************************************************************************************/
378
379 #define DCC_DCCGCTRL (0x0U)
380 #define DCC_DCCREV (0x4U)
381 #define DCC_DCCCNTSEED0 (0x8U)
382 #define DCC_DCCVALIDSEED0 (0xcU)
383 #define DCC_DCCCNTSEED1 (0x10U)
384 #define DCC_DCCSTAT (0x14U)
385 #define DCC_DCCCNT0 (0x18U)
386 #define DCC_DCCVALID0 (0x1cU)
387 #define DCC_DCCCNT1 (0x20U)
388 #define DCC_DCCCLKSRC1 (0x24U)
389 #define DCC_DCCCLKSRC0 (0x28U)
390
391 /****************************************************************************************************
392 * Field Definition Macros
393 ****************************************************************************************************/
394
395 #define DCC_DCCGCTRL_DCCENA_SHIFT (0U)
396 #define DCC_DCCGCTRL_DCCENA_MASK (0x0000000fU)
397 #define DCC_DCCGCTRL_DCCENA_ENABLE (0xAU)
398 #define DCC_DCCGCTRL_DCCENA_DISABLE (0x5U)
399
400 #define DCC_DCCGCTRL_ERRENA_SHIFT (4U)
401 #define DCC_DCCGCTRL_ERRENA_MASK (0x000000f0U)
402 #define DCC_DCCGCTRL_ERRENA_ENABLE (0xAU)
403 #define DCC_DCCGCTRL_ERRENA_DISABLE (0x5U)
404
405 #define DCC_DCCGCTRL_SINGLESHOT_SHIFT (8U)
406 #define DCC_DCCGCTRL_SINGLESHOT_MASK (0x00000f00U)
407 #define DCC_DCCGCTRL_SINGLESHOT_MODE (0xAU)
408
409 #define DCC_DCCGCTRL_SINGLESHOT_DISABLE (0x5U)
410
411 #define DCC_DCCGCTRL_DONEENA_SHIFT (12U)
412 #define DCC_DCCGCTRL_DONEENA_MASK (0x0000f000U)
413 #define DCC_DCCGCTRL_DONEENA_ENABLE (0xAU)
414 #define DCC_DCCGCTRL_DONEENA_DISABLE (0x5U)
415
416 #define DCC_DCCGCTRL_RES_SHIFT (16U)
417 #define DCC_DCCGCTRL_RES_MASK (0xffff0000U)
418
419 #define DCC_DCCREV_MINOR_SHIFT (0U)
420 #define DCC_DCCREV_MINOR_MASK (0x0000003fU)
421
422 #define DCC_DCCREV_CUSTOM_SHIFT (6U)
423 #define DCC_DCCREV_CUSTOM_MASK (0x000000c0U)
424
425 #define DCC_DCCREV_MAJOR_SHIFT (8U)
426 #define DCC_DCCREV_MAJOR_MASK (0x00000700U)
427
428 #define DCC_DCCREV_RTL_SHIFT (11U)
429 #define DCC_DCCREV_RTL_MASK (0x0000f800U)
430
431 #define DCC_DCCREV_FUNC_SHIFT (16U)
432 #define DCC_DCCREV_FUNC_MASK (0x0fff0000U)
433
434 #define DCC_DCCREV_RES_SHIFT (28U)
435 #define DCC_DCCREV_RES_MASK (0x30000000U)
436
437 #define DCC_DCCREV_SCHEME_SHIFT (30U)
438 #define DCC_DCCREV_SCHEME_MASK (0xc0000000U)
439
440 #define DCC_DCCCNTSEED0_COUNTSEED0_SHIFT (0U)
441 #define DCC_DCCCNTSEED0_COUNTSEED0_MASK (0x000fffffU)
442
443 #define DCC_DCCCNTSEED0_RES_SHIFT (20U)
444 #define DCC_DCCCNTSEED0_RES_MASK (0xfff00000U)
445
446 #define DCC_DCCVALIDSEED0_VALIDSEED0_SHIFT (0U)
447 #define DCC_DCCVALIDSEED0_VALIDSEED0_MASK (0x0000ffffU)
448
449 #define DCC_DCCVALIDSEED0_RES_SHIFT (16U)
450 #define DCC_DCCVALIDSEED0_RES_MASK (0xffff0000U)
451
452 #define DCC_DCCCNTSEED1_COUNTSEED1_SHIFT (0U)
453 #define DCC_DCCCNTSEED1_COUNTSEED1_MASK (0x000fffffU)
454
455 #define DCC_DCCCNTSEED1_RES_SHIFT (20U)
456 #define DCC_DCCCNTSEED1_RES_MASK (0xfff00000U)
457
458 #define DCC_DCCSTAT_ERRFLG_SHIFT (0U)
459 #define DCC_DCCSTAT_ERRFLG_MASK (0x00000001U)
460 #define DCC_DCCSTAT_ERRFLG_DISABLE (1U)
461
462 #define DCC_DCCSTAT_DONEFLG_SHIFT (1U)
463 #define DCC_DCCSTAT_DONEFLG_MASK (0x00000002U)
464 #define DCC_DCCSTAT_DONEFLG_DISABLE (1U)
465
466 #define DCC_DCCSTAT_RES_SHIFT (2U)
467 #define DCC_DCCSTAT_RES_MASK (0xfffffffcU)
468
469 #define DCC_DCCCNT0_COUNT0_SHIFT (0U)
470 #define DCC_DCCCNT0_COUNT0_MASK (0x000fffffU)
471
472 #define DCC_DCCCNT0_RES_SHIFT (20U)
473 #define DCC_DCCCNT0_RES_MASK (0xfff00000U)
474
475 #define DCC_DCCVALID0_VALID0_SHIFT (0U)
476 #define DCC_DCCVALID0_VALID0_MASK (0x0000ffffU)
477
478 #define DCC_DCCVALID0_RES_SHIFT (16U)
479 #define DCC_DCCVALID0_RES_MASK (0xffff0000U)
480
481 #define DCC_DCCCNT1_COUNT1_SHIFT (0U)
482 #define DCC_DCCCNT1_COUNT1_MASK (0x000fffffU)
483
484 #define DCC_DCCCNT1_RES_SHIFT (20U)
485 #define DCC_DCCCNT1_RES_MASK (0xfff00000U)
486
487 #define DCC_DCCCLKSRC1_CLKSRC_SHIFT (0U)
488 #define DCC_DCCCLKSRC1_CLKSRC_MASK (0x0000000fU)
489 #define DCC_DCCCLKSRC1_CLKSRC_0 (0x0U)
490 #define DCC_DCCCLKSRC1_CLKSRC_1 (0x1U)
491 #define DCC_DCCCLKSRC1_CLKSRC_2 (0x2U)
492 #define DCC_DCCCLKSRC1_CLKSRC_3 (0x3U)
493 #define DCC_DCCCLKSRC1_CLKSRC_4 (0x4U)
494 #define DCC_DCCCLKSRC1_CLKSRC_5 (0x5U)
495 #define DCC_DCCCLKSRC1_CLKSRC_6 (0x6U)
496 #define DCC_DCCCLKSRC1_CLKSRC_7 (0x7U)
497 #define SDL_DCC2_DCCCLKSRC1_CLKSRC_OTHER (0xFU)
498
499 #define DCC_DCCCLKSRC1_RES1_SHIFT (4U)
500 #define DCC_DCCCLKSRC1_RES1_MASK (0x00000ff0U)
501
502 #define DCC_DCCCLKSRC1_KEY_SHIFT (12U)
503 #define DCC_DCCCLKSRC1_KEY_MASK (0x0000f000U)
504 #define DCC_DCCCLKSRC1_KEY_ENABLE (0xAU)
505 #define DCC_DCCCLKSRC1_KEY_DISABLE (0x0U)
506
507 #define DCC_DCCCLKSRC1_RES0_SHIFT (16U)
508 #define DCC_DCCCLKSRC1_RES0_MASK (0xffff0000U)
509
510 #define DCC_DCCCLKSRC0_CLKSRC0_SHIFT (0U)
511 #define DCC_DCCCLKSRC0_CLKSRC0_MASK (0x0000000fU)
512 #define DCC_DCCCLKSRC0_CLKSRC0_0 (0x0U)
513 #define DCC_DCCCLKSRC0_CLKSRC0_1 (0x1U)
514 #define DCC_DCCCLKSRC0_CLKSRC0_2 (0x2U)
515
516 #define DCC_DCCCLKSRC0_RES1_SHIFT (4U)
517 #define DCC_DCCCLKSRC0_RES1_MASK (0xfffffff0)
518
519 #define DCC_DCCCLKSRC0_KEY_SHIFT (12U)
520 #define DCC_DCCCLKSRC0_KEY_MASK (0x0000f000U)
521 #define DCC_DCCCLKSRC0_KEY_ENABLE (0xAU)
522 #define DCC_DCCCLKSRC0_KEY_DISABLE (0x0U)
523
524 #define DCC_DCCCLKSRC0_RES0_SHIFT (16U)
525 #define DCC_DCCCLKSRC0_RES0_MASK (0xffff0000U)
526
527 #ifdef __cplusplus
528 }
529
530 #endif /*extern "C" */
531
532 #endif
533
SDL_DCC_mode
uint32_t SDL_DCC_mode
Enum to select the DCC Operation Mode.
Definition: dcc/v1/sdl_dcc.h:141
SDL_DCC_getStaticRegs
int32_t SDL_DCC_getStaticRegs(SDL_DCC_Inst instance, SDL_DCC_staticRegs *pStaticRegs)
This API is used to get the value of static registers for DCC module.
SDL_DCC_Status::clk0Valid
uint32_t clk0Valid
Definition: dcc/v1/sdl_dcc.h:264
SDL_DCC_configure
int32_t SDL_DCC_configure(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to configure DCC module.
SDL_DCC_clkSrc1
uint32_t SDL_DCC_clkSrc1
Enum to select the COUNT1 clock source.
Definition: dcc/v1/sdl_dcc.h:177
SDL_DCC_getStatus
int32_t SDL_DCC_getStatus(SDL_DCC_Inst instance, SDL_DCC_Status *pStatus)
This API is used to get the stauts of DCC module.
SDL_DCC_Inst
SDL_DCC_Inst
Definition: sdl_soc_dcc.h:72
SDL_DCC_disable
int32_t SDL_DCC_disable(SDL_DCC_Inst instance)
This API is used to disable the DCC module.
SDL_DCC_Status::clk1Cnt
uint32_t clk1Cnt
Definition: dcc/v1/sdl_dcc.h:266
SDL_DCC_Status::errIntr
bool errIntr
Definition: dcc/v1/sdl_dcc.h:258
SDL_DCC_staticRegs::DCC_CNTSEED0
uint32_t DCC_CNTSEED0
Definition: dcc/v1/sdl_dcc.h:275
SDL_DCC_Status::doneIntr
bool doneIntr
Definition: dcc/v1/sdl_dcc.h:256
SDL_DCC_config::clk0Src
SDL_DCC_clkSrc0 clk0Src
Definition: dcc/v1/sdl_dcc.h:237
SDL_DCC_enableIntr
int32_t SDL_DCC_enableIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to Enable the interrupts.
SDL_DCC_intrType
uint32_t SDL_DCC_intrType
Enum for DCC interrupts.
Definition: dcc/v1/sdl_dcc.h:208
SDL_DCC_staticRegs::DCC_REV
uint32_t DCC_REV
Definition: dcc/v1/sdl_dcc.h:273
SDL_DCC_config::clk1Src
uint32_t clk1Src
Definition: dcc/v1/sdl_dcc.h:241
SDL_DCC_staticRegs
Definition: dcc/v1/sdl_dcc.h:272
SDL_DCC_staticRegs::DCC_CNTSEED1
uint32_t DCC_CNTSEED1
Definition: dcc/v1/sdl_dcc.h:279
SDL_DCC_Status::config
SDL_DCC_config config
Definition: dcc/v1/sdl_dcc.h:260
SDL_DCC_config::mode
SDL_DCC_mode mode
Definition: dcc/v1/sdl_dcc.h:233
SDL_DCC_verifyConfig
int32_t SDL_DCC_verifyConfig(SDL_DCC_Inst instance, const SDL_DCC_config *pConfig)
This API is used to verify the configuration for DCC module.
SDL_DCC_Status::clk0Cnt
uint32_t clk0Cnt
Definition: dcc/v1/sdl_dcc.h:262
SDL_DCC_config::clk1Seed
uint32_t clk1Seed
Definition: dcc/v1/sdl_dcc.h:249
SDL_DCC_staticRegs::DCC_CLKSRC0
uint32_t DCC_CLKSRC0
Definition: dcc/v1/sdl_dcc.h:283
sdl_dcc.h
This file contains the prototypes of the APIs present in the device abstraction layer file of DCC....
SDL_DCC_config::clk0ValidSeed
uint32_t clk0ValidSeed
Definition: dcc/v1/sdl_dcc.h:247
SDL_DCC_enable
int32_t SDL_DCC_enable(SDL_DCC_Inst instance)
This API is used to enable the DCC module.
SDL_DCC_config::clk0Seed
uint32_t clk0Seed
Definition: dcc/v1/sdl_dcc.h:245
SDL_DCC_config
Structure containing parameters for DCC module configuration.
Definition: dcc/v1/sdl_dcc.h:232
SDL_DCC_staticRegs::DCC_VALIDSEED0
uint32_t DCC_VALIDSEED0
Definition: dcc/v1/sdl_dcc.h:277
SDL_DCC_clearIntr
int32_t SDL_DCC_clearIntr(SDL_DCC_Inst instance, SDL_DCC_intrType intr)
This API is used to clear the interrupts.
SDL_DCC_clkSrc0
uint32_t SDL_DCC_clkSrc0
Enum to select the COUNT0 clock source.
Definition: dcc/v1/sdl_dcc.h:159
SDL_DCC_Status
Definition: dcc/v1/sdl_dcc.h:255
SDL_DCC_staticRegs::DCC_CLKSRC1
uint32_t DCC_CLKSRC1
Definition: dcc/v1/sdl_dcc.h:281