AM263Px MCU+ SDK: sipc_notify_src.h Source File

| AM263Px MCU+ SDK 26.00.00 |

sipc_notify_src.h
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31 */
32
33 #ifndef SIPC_NOTIFY__H_
34 #define SIPC_NOTIFY__H_
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include <security_common/drivers/secure_ipc_notify/sipc_notify.h>
41 #include <security_common/drivers/secure_ipc_notify/soc/sipc_notify_soc.h>
42 #include <kernel/dpl/HwiP.h>
43 #include <kernel/dpl/ClockP.h>
44 #include <kernel/dpl/CpuIdP.h>
45 #include <security_common/drivers/secure_ipc_notify/sipc_notify_mailbox.h>
46
52 typedef struct SIPC_InterruptConfig_s
53 {
54 uint32_t intNum;
55 uint32_t eventId;
56 HwiP_Object hwiObj;
57 uint8_t numCores;
59 uint8_t coreIdList[MAX_SEC_CORES_WITH_HSM];
63 uint32_t clearIntOnInit; /* 0: do not clear pending interrupts during SIPC_init, 1: clear pending interrupts */
64 } SIPC_InterruptConfig;
65
69 typedef struct SIPC_MailboxConfig_s
70 {
71 uint32_t writeDoneMailboxBaseAddr;
72 uint32_t readReqMailboxBaseAddr;
73 uint32_t readReqMailboxClrBaseAddr;
74 uint8_t wrIntrBitPos;
75 uint8_t rdIntrBitPos;
76 SIPC_SwQueue *swQ;
78 } SIPC_MailboxConfig;
79
86 extern SIPC_MailboxConfig gSIPC_SecureHostMboxConfig[CORE_ID_MAX - 1U] ;
93 extern SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1U] ;
94
101 extern SIPC_SwQueue* gSIPC_QueSecureHostToHsm [MAX_SEC_CORES_WITH_HSM - 1U];
108 extern SIPC_SwQueue* gSIPC_QueHsmToSecureHost[MAX_SEC_CORES_WITH_HSM - 1U];
109
118 int32_t SIPC_Register_Isr(HwiP_Params *pHwiParams, SIPC_InterruptConfig *pInterruptConfig, SIPC_Params *params, HwiP_FxnCallback callback);
119
120 /* Secure IPC Isr */
121 void SIPC_isr(void *args);
122
123 #ifdef __cplusplus
124 }
125 #endif
126
127 #endif /* IPC_NOTIFY_V0_H_ */
128
SIPC_Params
Parameters used by SIPC_init.
Definition: sipc_notify.h:84
args
void * args
Definition: hsmclient_msg.h:4
HwiP_Params
Parameters passed during HwiP_construct.
Definition: HwiP.h:127
SIPC_InterruptConfig
This structure describes the information related to one interrupt that is setup for receiving mailbox...
Definition: sipc_notify_src.h:53
SIPC_MailboxConfig::writeDoneMailboxBaseAddr
uint32_t writeDoneMailboxBaseAddr
Definition: sipc_notify_src.h:71
gSIPC_QueHsmToSecureHost
SIPC_SwQueue * gSIPC_QueHsmToSecureHost[MAX_SEC_CORES_WITH_HSM - 1U]
Global structure holding HSM -> R5 queues addresses indexed by sec core id.
MAX_SEC_CORES_WITH_HSM
#define MAX_SEC_CORES_WITH_HSM
Definition: sipc_notify_cfg.h:130
sipc_notify.h
ClockP.h
SIPC_SwQueue
SIPC swQ structure which holds the data pointer to a fifo Queue in HSM MBOX memory.
Definition: sipc_notify_mailbox.h:63
HwiP.h
SIPC_InterruptConfig::intNum
uint32_t intNum
Definition: sipc_notify_src.h:54
SIPC_InterruptConfig::clearIntOnInit
uint32_t clearIntOnInit
Definition: sipc_notify_src.h:63
SIPC_InterruptConfig::numCores
uint8_t numCores
Definition: sipc_notify_src.h:57
SIPC_InterruptConfig::hwiObj
HwiP_Object hwiObj
Definition: sipc_notify_src.h:56
CpuIdP.h
SIPC_Register_Isr
int32_t SIPC_Register_Isr(HwiP_Params *pHwiParams, SIPC_InterruptConfig *pInterruptConfig, SIPC_Params *params, HwiP_FxnCallback callback)
Register SIPC interrupts for SOC.
SIPC_MailboxConfig::rdIntrBitPos
uint8_t rdIntrBitPos
Definition: sipc_notify_src.h:75
SIPC_MailboxConfig
This structure describes the mailbox information to send a message from core A to core B.
Definition: sipc_notify_src.h:70
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:142
gSIPC_SecureHostMboxConfig
SIPC_MailboxConfig gSIPC_SecureHostMboxConfig[CORE_ID_MAX - 1U]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
SIPC_MailboxConfig::readReqMailboxClrBaseAddr
uint32_t readReqMailboxClrBaseAddr
Definition: sipc_notify_src.h:73
gSIPC_QueSecureHostToHsm
SIPC_SwQueue * gSIPC_QueSecureHostToHsm[MAX_SEC_CORES_WITH_HSM - 1U]
Global structure holding R5 to HSM queues addresses indexed by sec core id.
SIPC_MailboxConfig::swQ
SIPC_SwQueue * swQ
Definition: sipc_notify_src.h:76
SIPC_MailboxConfig::readReqMailboxBaseAddr
uint32_t readReqMailboxBaseAddr
Definition: sipc_notify_src.h:72
sipc_notify_mailbox.h
CORE_ID_MAX
#define CORE_ID_MAX
Definition: sipc_notify_cfg.h:116
SIPC_MailboxConfig::wrIntrBitPos
uint8_t wrIntrBitPos
Definition: sipc_notify_src.h:74
gSIPC_HsmMboxConfig
SIPC_MailboxConfig gSIPC_HsmMboxConfig[CORE_ID_MAX - 1U]
Global structure that is pre-defined for this SOC to configure any R5 CPU to HSM mailbox communicatio...
HwiP_FxnCallback
void(* HwiP_FxnCallback)(void *args)
Callback that is called when a HW interrupt is received.
Definition: HwiP.h:112
SIPC_isr
void SIPC_isr(void *args)
SIPC_InterruptConfig::eventId
uint32_t eventId
Definition: sipc_notify_src.h:55