AM263Px MCU+ SDK: soc_rcm.h Source File

| AM263Px MCU+ SDK 26.00.00 |

soc_rcm.h
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1 /*
2 * Copyright (C) 2021 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef SOC_RCM_AM263PX_H_
34 #define SOC_RCM_AM263PX_H_
35
36 #include <stdint.h>
37
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif
42
52 #include <kernel/dpl/SystemP.h>
53
54 #define SOC_RCM_FREQ_MHZ2HZ(x) ((x) * 1000 * 1000)
55 #define SOC_RCM_FREQ_HZ2MHZ(x) ((x) / (1000 * 1000))
56
62 typedef enum SOC_WarmResetCause_e
63 {
67 SOC_WarmResetCause_POWER_ON_RESET = 0x41U,
71 SOC_WarmResetCause_MSS_WDT0 = 0x42U,
75 SOC_WarmResetCause_MSS_WDT1 = 0x44U,
79 SOC_WarmResetCause_MSS_WDT2 = 0x48U,
83 SOC_WarmResetCause_MSS_WDT3 = 0x50U,
87 SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ = 0x60U,
91 SOC_WarmResetCause_EXT_PAD_RESET = 0x40U,
95 SOC_WarmResetCause_HSM_WDT = 0xC0U,
99 SOC_WarmResetCause_DBG_RESET = 0x140U,
103 SOC_WarmResetCause_TEMP_SENSOR0_RESET = 0x240U,
107 SOC_WarmResetCause_TEMP_SENSOR1_RESET = 0x440U,
108
109 }SOC_WarmResetCause;
117 typedef enum SOC_WarmResetSource_e
118 {
122 SOC_WarmResetSource_PAD_BYPASS = CSL_TOP_RCM_WARM_RESET_CONFIG_PAD_BYPASS_MASK,
126 SOC_WarmResetSource_DEBUGSS = CSL_TOP_RCM_WARM_RESET_CONFIG_DEBUGSS_RST_EN_MASK,
130 SOC_WarmResetSource_TSENSE0 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE0_RST_EN_MASK,
134 SOC_WarmResetSource_TSENSE1 = CSL_TOP_RCM_WARM_RESET_CONFIG_TSENSE1_RST_EN_MASK,
138 SOC_WarmResetSource_WDOG0 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG0_RST_EN_MASK,
142 SOC_WarmResetSource_WDOG1 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG1_RST_EN_MASK,
146 SOC_WarmResetSource_WDOG2 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG2_RST_EN_MASK,
150 SOC_WarmResetSource_WDOG3 = CSL_TOP_RCM_WARM_RESET_CONFIG_WDOG3_RST_EN_MASK,
151
152 }SOC_WarmResetSource;
161 typedef enum SOC_RcmWarm_ResetTime123_e
162 {
166 SOC_WARM_RESET_PAD_TIME_500NS = 0U,
170 SOC_WARM_RESET_PAD_TIME_1US,
174 SOC_WARM_RESET_PAD_TIME_2US,
178 SOC_WARM_RESET_PAD_TIME_4US,
182 SOC_WARM_RESET_PAD_TIME_8US,
186 SOC_WARM_RESET_PAD_TIME_16US,
190 SOC_WARM_RESET_PAD_TIME_32US,
194 SOC_WARM_RESET_PAD_TIME_64US,
198 SOC_WARM_RESET_PAD_TIME_128US,
202 SOC_WARM_RESET_PAD_TIME_256US,
206 SOC_WARM_RESET_PAD_TIME_512US,
210 SOC_WARM_RESET_PAD_TIME_1024US,
214 SOC_WARM_RESET_PAD_TIME_2048US,
218 SOC_WARM_RESET_PAD_TIME_4096US,
222 SOC_WARM_RESET_PAD_TIME_8192US,
226 SOC_WARM_RESET_PAD_TIME_16384US,
227
228 } SOC_RcmWarm_ResetTime123;
236 typedef enum SOC_RcmResetCause_e
237 {
241 SOC_RcmResetCause_POWER_ON_RESET = 0x0U,
245 SOC_RcmResetCause_WARM_RESET = 0x1U,
249 SOC_RcmResetCause_STC_RESET = 0x2U,
253 SOC_RcmResetCause_MMR_CPU0_VIM0_RESET = 0x3U,
257 SOC_RcmResetCause_MMR_CPU1_VIM1_RESET = 0x4U,
261 SOC_RcmResetCause_MMR_CPU0_RESET = 0x5U,
265 SOC_RcmResetCause_MMR_CPU1_RESET = 0x6U,
269 SOC_RcmResetCause_DBG_CPU0_RESET = 0x7U,
273 SOC_RcmResetCause_DBG_CPU1_RESET = 0x8U,
277 SOC_RcmResetCause_FSM_TRIGGER_RESET = 0x9U,
281 SOC_RcmResetCause_POR_RST_CTRL0 = 0xAU,
285 SOC_RcmResetCause_RST_CAUSE_UNKNOWN = 0xBU,
286
287 }SOC_RcmResetCause;
295 typedef enum SOC_Rcmr5fssNum_e
296 {
300 r5fss0 = 0x0U,
304 r5fss1 = 0x1U,
305 }SOC_Rcmr5fssNum;
313 typedef enum SOC_RcmPeripheralId_e
314 {
318 SOC_RcmPeripheralId_MCAN0,
322 SOC_RcmPeripheralId_MCAN1,
326 SOC_RcmPeripheralId_MCAN2,
330 SOC_RcmPeripheralId_MCAN3,
334 SOC_RcmPeripheralId_OSPI0,
338 SOC_RcmPeripheralId_RTI0,
342 SOC_RcmPeripheralId_RTI1,
346 SOC_RcmPeripheralId_RTI2,
350 SOC_RcmPeripheralId_RTI3,
354 SOC_RcmPeripheralId_RTI4,
358 SOC_RcmPeripheralId_RTI5,
362 SOC_RcmPeripheralId_RTI6,
366 SOC_RcmPeripheralId_RTI7,
370 SOC_RcmPeripheralId_WDT0,
374 SOC_RcmPeripheralId_WDT1,
378 SOC_RcmPeripheralId_WDT2,
382 SOC_RcmPeripheralId_WDT3,
386 SOC_RcmPeripheralId_MCSPI0,
390 SOC_RcmPeripheralId_MCSPI1,
394 SOC_RcmPeripheralId_MCSPI2,
398 SOC_RcmPeripheralId_MCSPI3,
402 SOC_RcmPeripheralId_MCSPI4,
406 SOC_RcmPeripheralId_MCSPI5,
410 SOC_RcmPeripheralId_MCSPI6,
414 SOC_RcmPeripheralId_MCSPI7,
418 SOC_RcmPeripheralId_MMC0,
422 SOC_RcmPeripheralId_ICSSM0_UART0,
426 SOC_RcmPeripheralId_CPTS,
430 SOC_RcmPeripheralId_GPMC,
434 SOC_RcmPeripheralId_CONTROLSS_PLL,
438 SOC_RcmPeripheralId_I2C,
442 SOC_RcmPeripheralId_LIN0_UART0,
446 SOC_RcmPeripheralId_LIN1_UART1,
450 SOC_RcmPeripheralId_LIN2_UART2,
454 SOC_RcmPeripheralId_LIN3_UART3,
458 SOC_RcmPeripheralId_LIN4_UART4,
462 SOC_RcmPeripheralId_LIN5_UART5,
466 SOC_RcmPeripheralId_MCAN4,
470 SOC_RcmPeripheralId_MCAN5,
474 SOC_RcmPeripheralId_MCAN6,
478 SOC_RcmPeripheralId_MCAN7,
479 }SOC_RcmPeripheralId;
487 typedef enum SOC_RcmPeripheralClockSource_e
488 {
492 SOC_RcmPeripheralClockSource_XTALCLK,
496 SOC_RcmPeripheralClockSource_SYS_CLK,
500 SOC_RcmPeripheralClockSource_WUCPUCLK,
504 SOC_RcmPeripheralClockSource_EXT_REFCLK,
508 SOC_RcmPeripheralClockSource_RCCLK10M,
512 SOC_RcmPeripheralClockSource_RCCLK32K,
516 SOC_RcmPeripheralClockSource_CTPS_GENF0,
520 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0,
524 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1,
528 SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
532 SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0,
536 SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
537 } SOC_RcmPeripheralClockSource;
545 typedef enum SOC_RcmPllFoutFreqId_e
546 {
550 RCM_PLL_FOUT_FREQID_CLK_2000MHZ,
554 RCM_PLL_FOUT_FREQID_CLK_1920MHZ,
558 RCM_PLL_FOUT_FREQID_CLK_800MHZ,
559 } SOC_RcmPllFoutFreqId;
567 typedef enum SOC_RcmXtalFreqId_e
568 {
572 RCM_XTAL_FREQID_CLK_25MHZ,
573 } SOC_RcmXtalFreqId;
574
575 typedef enum SOC_RcmPllId_e
576 {
577 RCM_PLLID_CORE,
578 RCM_PLLID_PER,
579 RCM_PLLID_XTALCLK,
580 RCM_PLLID_WUCPUCLK,
581 RCM_PLLID_RCCLK32K,
582 RCM_PLLID_RCCLK10M,
583 RCM_PLLID_EXTREFCLK,
584 } SOC_RcmPllId;
592 typedef enum SOC_RcmPllHSDIVOutId_e
593 {
597 RCM_PLLHSDIV_OUT_0,
601 RCM_PLLHSDIV_OUT_1,
605 RCM_PLLHSDIV_OUT_2,
609 RCM_PLLHSDIV_OUT_NONE,
610 } SOC_RcmPllHSDIVOutId;
613 typedef struct SOC_RcmClkSrcInfo_s
614 {
615 SOC_RcmPllId pllId;
616 SOC_RcmPllHSDIVOutId hsDivOut;
617 } SOC_RcmClkSrcInfo;
618
619 typedef struct SOC_RcmXTALInfo_s
620 {
621 uint32_t Finp;
622 Bool div2flag;
623 } SOC_RcmXTALInfo;
624
625 typedef struct SOC_RcmADPLLJConfig_s
626 {
627 uint32_t N; /* Input Clock divider/Pre-divider (N) */
628 uint32_t M2; /* Post divider (M2) */
629 uint32_t M; /* Multiplier integer (M) */
630 uint32_t FracM; /* Multiplier fractional (M) */
631 uint32_t Fout; /* Output frequency of PLL */
632 uint32_t Finp; /* Output frequency of PLL */
633 } SOC_RcmADPLLJConfig_t;
634
635 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_0 (1U << 0U)
636 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_1 (1U << 1U)
637 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_2 (1U << 2U)
638 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_3 (1U << 3U)
639 #define RCM_PLL_HSDIV_OUTPUT_ENABLE_ALL (RCM_PLL_HSDIV_OUTPUT_ENABLE_0 | \
640 RCM_PLL_HSDIV_OUTPUT_ENABLE_1 | \
641 RCM_PLL_HSDIV_OUTPUT_ENABLE_2 | \
642 RCM_PLL_HSDIV_OUTPUT_ENABLE_3)
643
644 #define RCM_PLL_HSDIV_OUTPUT_IDX0 (0)
645 #define RCM_PLL_HSDIV_OUTPUT_IDX1 (1)
646 #define RCM_PLL_HSDIV_OUTPUT_IDX2 (2)
647 #define RCM_PLL_HSDIV_OUTPUT_IDX3 (3)
648 #define RCM_PLL_HSDIV_OUTPUT_COUNT (RCM_PLL_HSDIV_OUTPUT_IDX3 + 1)
649
650 typedef struct SOC_RcmPllHsDivOutConfig_s
651 {
652 uint32_t hsdivOutEnMask;
653 uint32_t hsDivOutFreqHz[RCM_PLL_HSDIV_OUTPUT_COUNT];
654 } SOC_RcmPllHsDivOutConfig;
655
663 extern void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
664
668 extern uint32_t SOC_rcmCoreApllRelockPreRequisite(void);
669
673 extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
674
675
683 extern void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
684
692 extern void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg);
693
702 extern void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz,
703 uint32_t cpuId);
704
711 extern void SOC_rcmsetTraceClock(uint32_t traceFreqHz);
712
720 extern void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz);
721
735 extern int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz);
736
747 extern SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum);
748
761 int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable);
762
772 int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId);
773
780 uint32_t SOC_rcmGetR5Clock(uint32_t cpuId);
781
786 void SOC_rcmR5ConfigLockStep(uint32_t cpuId);
787
792 void SOC_rcmR5ConfigDualCore(uint32_t cpuId);
793
797 extern void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc);
798
802 void SOC_rcmR5SS0TriggerReset(void);
803
808 void SOC_rcmCoreR5FUnhalt(uint32_t cpuId);
809
814 void SOC_rcmStartMemInitTCMA(uint32_t cpuId);
815
820 void SOC_rcmWaitMemInitTCMA(uint32_t cpuId);
821
826 void SOC_rcmStartMemInitTCMB(uint32_t cpuId);
827
832 void SOC_rcmWaitMemInitTCMB(uint32_t cpuId);
833
837 void SOC_rcmMemInitMailboxMemory(void);
841 void SOC_rcmMemInitL2Memory(void);
845 void SOC_rcmR5SS0PowerOnReset(void);
846
850 void SOC_rcmR5SS1TriggerReset(void);
851
855 void SOC_rcmR5SS1PowerOnReset(void);
856
864 uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId);
865
869 void SOC_generateSwWarmReset(void);
870
877 void SOC_configureWarmResetSource(uint32_t source);
878
884 SOC_WarmResetCause SOC_getWarmResetCause(void);
885
889 void SOC_clearWarmResetCause(void);
890
896 void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue);
897
903 void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue);
904
910 void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue);
911
914 #ifdef __cplusplus
915 }
916 #endif
917
918 #endif
SOC_Rcmr5fssNum
SOC_Rcmr5fssNum
Definition: soc_rcm.h:296
RCM_PLLHSDIV_OUT_NONE
@ RCM_PLLHSDIV_OUT_NONE
Value specifying invalid/no HSDIVIDER ID.
Definition: soc_rcm.h:609
SOC_RcmPeripheralId_LIN0_UART0
@ SOC_RcmPeripheralId_LIN0_UART0
Value specifying LIN0_UART0.
Definition: soc_rcm.h:442
SOC_RcmPeripheralId_MCAN5
@ SOC_RcmPeripheralId_MCAN5
Value specifying MCAN5.
Definition: soc_rcm.h:470
SOC_rcmR5SS1PowerOnReset
void SOC_rcmR5SS1PowerOnReset(void)
Reset R5SS1 Core.
RCM_PLLHSDIV_OUT_1
@ RCM_PLLHSDIV_OUT_1
Value specifying HSDIVIDER 1.
Definition: soc_rcm.h:601
SOC_RcmPeripheralId_MCSPI7
@ SOC_RcmPeripheralId_MCSPI7
Value specifying MCSPI7.
Definition: soc_rcm.h:414
SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
@ SOC_RcmResetCause_MMR_CPU0_VIM0_RESET
Value specifying R5 Core A Subsytem Reset.
Definition: soc_rcm.h:253
SOC_WARM_RESET_PAD_TIME_1024US
@ SOC_WARM_RESET_PAD_TIME_1024US
Delay Value specifying in time 1024us.
Definition: soc_rcm.h:210
SOC_RcmPeripheralId_WDT2
@ SOC_RcmPeripheralId_WDT2
Value specifying WDT2.
Definition: soc_rcm.h:378
SOC_configureWarmResetInputFallDelay
void SOC_configureWarmResetInputFallDelay(uint16_t inpFallDelayValue)
Program output delay on warm reset Pad 3.
SOC_RcmPeripheralId_RTI7
@ SOC_RcmPeripheralId_RTI7
Value specifying RTI7.
Definition: soc_rcm.h:366
RCM_PLLID_CORE
@ RCM_PLLID_CORE
Definition: soc_rcm.h:577
SOC_RcmResetCause_MMR_CPU0_RESET
@ SOC_RcmResetCause_MMR_CPU0_RESET
Value specifying R5 Core A (core only) Reset.
Definition: soc_rcm.h:261
SOC_rcmCoreApllHSDivConfig
void SOC_rcmCoreApllHSDivConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL HSDIVIDERS.
RCM_PLLID_PER
@ RCM_PLLID_PER
Definition: soc_rcm.h:578
SOC_rcmEnablePeripheralClock
int32_t SOC_rcmEnablePeripheralClock(SOC_RcmPeripheralId periphId, uint32_t enable)
Enable/disable module clock (IP clock configuration)
SOC_rcmCoreR5FUnhalt
void SOC_rcmCoreR5FUnhalt(uint32_t cpuId)
Unhalt R5 cores.
SOC_rcmCoreApllRelockPreRequisite
uint32_t SOC_rcmCoreApllRelockPreRequisite(void)
Pre-requisite sequence to Re-configure CORE PLL.
SOC_WarmResetSource_TSENSE1
@ SOC_WarmResetSource_TSENSE1
Value specifying Temperature Sensor 1.
Definition: soc_rcm.h:134
r5fss1
@ r5fss1
Value specifying Warm Reset.
Definition: soc_rcm.h:304
SOC_RcmPeripheralId_RTI1
@ SOC_RcmPeripheralId_RTI1
Value specifying RTI1.
Definition: soc_rcm.h:342
SOC_RcmADPLLJConfig_t
Definition: soc_rcm.h:626
SOC_RcmPeripheralId_MCSPI2
@ SOC_RcmPeripheralId_MCSPI2
Value specifying MCSPI2.
Definition: soc_rcm.h:394
SystemP.h
SOC_RcmPeripheralId_RTI5
@ SOC_RcmPeripheralId_RTI5
Value specifying RTI5.
Definition: soc_rcm.h:358
SOC_RcmPeripheralClockSource
SOC_RcmPeripheralClockSource
Definition: soc_rcm.h:488
SOC_RcmADPLLJConfig_t::FracM
uint32_t FracM
Definition: soc_rcm.h:630
SOC_WARM_RESET_PAD_TIME_128US
@ SOC_WARM_RESET_PAD_TIME_128US
Delay Value specifying in time 128us.
Definition: soc_rcm.h:198
SOC_rcmsetTraceClock
void SOC_rcmsetTraceClock(uint32_t traceFreqHz)
Set Trace clock frequency.
SOC_RcmPeripheralId_MCSPI0
@ SOC_RcmPeripheralId_MCSPI0
Value specifying MCSPI0.
Definition: soc_rcm.h:386
RCM_PLL_FOUT_FREQID_CLK_800MHZ
@ RCM_PLL_FOUT_FREQID_CLK_800MHZ
Value specifying PLL output frequency 800MHz.
Definition: soc_rcm.h:558
SOC_rcmStartMemInitTCMA
void SOC_rcmStartMemInitTCMA(uint32_t cpuId)
Start memory initialization for R5 TCMA.
SOC_WARM_RESET_PAD_TIME_512US
@ SOC_WARM_RESET_PAD_TIME_512US
Delay Value specifying in time 512us.
Definition: soc_rcm.h:206
SOC_RcmADPLLJConfig_t::M
uint32_t M
Definition: soc_rcm.h:629
SOC_WARM_RESET_PAD_TIME_4US
@ SOC_WARM_RESET_PAD_TIME_4US
Delay Value specifying in time 4us.
Definition: soc_rcm.h:178
SOC_configureWarmResetInputRiseDelay
void SOC_configureWarmResetInputRiseDelay(uint16_t inpRiseDelayValue)
Program input rise delay on warm reset Pad 2.
SOC_WARM_RESET_PAD_TIME_2048US
@ SOC_WARM_RESET_PAD_TIME_2048US
Delay Value specifying in time 2048us.
Definition: soc_rcm.h:214
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0
Value specifying PLL Core Clock Out 0 (400 Mhz)
Definition: soc_rcm.h:520
SOC_RcmADPLLJConfig_t::Fout
uint32_t Fout
Definition: soc_rcm.h:631
SOC_WARM_RESET_PAD_TIME_2US
@ SOC_WARM_RESET_PAD_TIME_2US
Delay Value specifying in time 2us.
Definition: soc_rcm.h:174
SOC_WarmResetCause_MSS_WDT0
@ SOC_WarmResetCause_MSS_WDT0
Value specifying MSS WDT0.
Definition: soc_rcm.h:71
SOC_rcmSetR5ClockSource
void SOC_rcmSetR5ClockSource(uint32_t r5ClkSrc)
Set R5 clock source.
SOC_WarmResetCause_EXT_PAD_RESET
@ SOC_WarmResetCause_EXT_PAD_RESET
Value specifying External Pad Reset.
Definition: soc_rcm.h:91
SOC_WarmResetCause_MSS_WDT3
@ SOC_WarmResetCause_MSS_WDT3
Value specifying MSS WDT3.
Definition: soc_rcm.h:83
SOC_RcmPeripheralId_LIN4_UART4
@ SOC_RcmPeripheralId_LIN4_UART4
Value specifying LIN4_UART4.
Definition: soc_rcm.h:458
SOC_RcmResetCause_POWER_ON_RESET
@ SOC_RcmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:241
SOC_rcmWaitMemInitTCMB
void SOC_rcmWaitMemInitTCMB(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMB.
SOC_RcmPeripheralId
SOC_RcmPeripheralId
Definition: soc_rcm.h:314
SOC_RcmPeripheralClockSource_XTALCLK
@ SOC_RcmPeripheralClockSource_XTALCLK
Value specifying Crystal Clock.
Definition: soc_rcm.h:492
SOC_rcmStartMemInitTCMB
void SOC_rcmStartMemInitTCMB(uint32_t cpuId)
Start memory initialization for R5 TCMB.
SOC_WARM_RESET_PAD_TIME_8US
@ SOC_WARM_RESET_PAD_TIME_8US
Delay Value specifying in time 8us.
Definition: soc_rcm.h:182
SOC_RcmResetCause_RST_CAUSE_UNKNOWN
@ SOC_RcmResetCause_RST_CAUSE_UNKNOWN
Value specifying R5 Reset due to Unknown reason.
Definition: soc_rcm.h:285
SOC_rcmsetClkoutClock
void SOC_rcmsetClkoutClock(uint32_t clkout0FreqHz, uint32_t clkout1FreqHz)
Set CLKOUT clock frequency.
SOC_RcmPeripheralId_WDT1
@ SOC_RcmPeripheralId_WDT1
Value specifying WDT1.
Definition: soc_rcm.h:374
SOC_WARM_RESET_PAD_TIME_32US
@ SOC_WARM_RESET_PAD_TIME_32US
Delay Value specifying in time 32us.
Definition: soc_rcm.h:190
SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ
@ SOC_WarmResetCause_TOP_RCM_WARM_RESET_REQ
Value specifying Software Warm Reset.
Definition: soc_rcm.h:87
SOC_RcmPeripheralId_GPMC
@ SOC_RcmPeripheralId_GPMC
Value specifying GPMC.
Definition: soc_rcm.h:430
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0
Value specifying PLL Core Clock Out 0 (160 Mhz)
Definition: soc_rcm.h:532
SOC_configureWarmResetOutputDelay
void SOC_configureWarmResetOutputDelay(uint16_t opDelayValue)
Program output delay on warm reset Pad 1.
SOC_RcmPeripheralClockSource_SYS_CLK
@ SOC_RcmPeripheralClockSource_SYS_CLK
Value specifying System Clock (200Mhz)
Definition: soc_rcm.h:496
SOC_WARM_RESET_PAD_TIME_1US
@ SOC_WARM_RESET_PAD_TIME_1US
Delay Value specifying in time 1us.
Definition: soc_rcm.h:170
SOC_RcmXTALInfo::div2flag
Bool div2flag
Definition: soc_rcm.h:622
SOC_RcmPeripheralId_MCSPI1
@ SOC_RcmPeripheralId_MCSPI1
Value specifying MCSPI1.
Definition: soc_rcm.h:390
SOC_WarmResetSource_TSENSE0
@ SOC_WarmResetSource_TSENSE0
Value specifying Temperature Sensor 0.
Definition: soc_rcm.h:130
SOC_RcmPllHsDivOutConfig
Definition: soc_rcm.h:651
SOC_RcmPeripheralId_MCSPI3
@ SOC_RcmPeripheralId_MCSPI3
Value specifying MCSPI3.
Definition: soc_rcm.h:398
SOC_WarmResetSource_WDOG2
@ SOC_WarmResetSource_WDOG2
Value specifying Watchdog 2.
Definition: soc_rcm.h:146
SOC_RcmPeripheralId_WDT3
@ SOC_RcmPeripheralId_WDT3
Value specifying WDT3.
Definition: soc_rcm.h:382
SOC_RcmPllHSDIVOutId
SOC_RcmPllHSDIVOutId
Definition: soc_rcm.h:593
SOC_RcmPeripheralId_MCSPI6
@ SOC_RcmPeripheralId_MCSPI6
Value specifying MCSPI6.
Definition: soc_rcm.h:410
SOC_RcmXtalFreqId
SOC_RcmXtalFreqId
Definition: soc_rcm.h:568
SOC_rcmSetPeripheralClock
int32_t SOC_rcmSetPeripheralClock(SOC_RcmPeripheralId periphId, SOC_RcmPeripheralClockSource clkSource, uint32_t freqHz)
Set module clock (IP clock configuration)
SOC_RcmXTALInfo
Definition: soc_rcm.h:620
SOC_RcmClkSrcInfo::pllId
SOC_RcmPllId pllId
Definition: soc_rcm.h:615
SOC_rcmGetResetCause
SOC_RcmResetCause SOC_rcmGetResetCause(SOC_Rcmr5fssNum r5fssNum)
Get R5FSS reset cause.
SOC_RcmPeripheralId_MCAN4
@ SOC_RcmPeripheralId_MCAN4
Value specifying MCAN4.
Definition: soc_rcm.h:466
SOC_rcmsetR5SysClock
void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5FSS and Sysclk frequency (Root clock configuration)
SOC_WARM_RESET_PAD_TIME_8192US
@ SOC_WARM_RESET_PAD_TIME_8192US
Delay Value specifying in time 8192us.
Definition: soc_rcm.h:222
SOC_RcmXTALInfo::Finp
uint32_t Finp
Definition: soc_rcm.h:621
SOC_WARM_RESET_PAD_TIME_16384US
@ SOC_WARM_RESET_PAD_TIME_16384US
Delay Value specifying in time 16384us.
Definition: soc_rcm.h:226
SOC_WARM_RESET_PAD_TIME_500NS
@ SOC_WARM_RESET_PAD_TIME_500NS
Delay Value specifying in time 500ns.
Definition: soc_rcm.h:166
SOC_RcmPeripheralId_I2C
@ SOC_RcmPeripheralId_I2C
Value specifying I2C.
Definition: soc_rcm.h:438
SOC_RcmPeripheralId_MCAN2
@ SOC_RcmPeripheralId_MCAN2
Value specifying MCAN2.
Definition: soc_rcm.h:326
SOC_RcmResetCause_FSM_TRIGGER_RESET
@ SOC_RcmResetCause_FSM_TRIGGER_RESET
Value specifying R5 Reset due to FSM Trigger.
Definition: soc_rcm.h:277
SOC_rcmIsR5FInLockStepMode
uint32_t SOC_rcmIsR5FInLockStepMode(uint32_t r5fClusterGroupId)
Return R5SS status operating in lockstep or dual core mode.
SOC_RcmResetCause
SOC_RcmResetCause
Definition: soc_rcm.h:237
RCM_PLLID_WUCPUCLK
@ RCM_PLLID_WUCPUCLK
Definition: soc_rcm.h:580
SOC_RcmPeripheralId_LIN5_UART5
@ SOC_RcmPeripheralId_LIN5_UART5
Value specifying LIN5_UART5.
Definition: soc_rcm.h:462
SOC_clearWarmResetCause
void SOC_clearWarmResetCause(void)
Clear Reset Cause register.
SOC_RcmResetCause_DBG_CPU1_RESET
@ SOC_RcmResetCause_DBG_CPU1_RESET
Value specifying R5 Core B Debug Reset.
Definition: soc_rcm.h:273
SOC_WarmResetCause_TEMP_SENSOR1_RESET
@ SOC_WarmResetCause_TEMP_SENSOR1_RESET
Value specifying Temperature Sensor1 Reset.
Definition: soc_rcm.h:107
SOC_rcmMemInitMailboxMemory
void SOC_rcmMemInitMailboxMemory(void)
Wait memory initialization to complete for Mailbox memory.
SOC_RcmResetCause_DBG_CPU0_RESET
@ SOC_RcmResetCause_DBG_CPU0_RESET
Value specifying R5 Core A Debug Reset.
Definition: soc_rcm.h:269
SOC_RcmPeripheralId_MCAN0
@ SOC_RcmPeripheralId_MCAN0
Value specifying MCAN0.
Definition: soc_rcm.h:318
SOC_RcmPeripheralId_MCAN6
@ SOC_RcmPeripheralId_MCAN6
Value specifying MCAN6.
Definition: soc_rcm.h:474
RCM_PLLID_RCCLK32K
@ RCM_PLLID_RCCLK32K
Definition: soc_rcm.h:581
SOC_WarmResetSource_WDOG0
@ SOC_WarmResetSource_WDOG0
Value specifying Watchdog 0.
Definition: soc_rcm.h:138
RCM_PLLID_RCCLK10M
@ RCM_PLLID_RCCLK10M
Definition: soc_rcm.h:582
SOC_WARM_RESET_PAD_TIME_16US
@ SOC_WARM_RESET_PAD_TIME_16US
Delay Value specifying in time 16us.
Definition: soc_rcm.h:186
RCM_XTAL_FREQID_CLK_25MHZ
@ RCM_XTAL_FREQID_CLK_25MHZ
Value specifying XTAL frequency 25MHZ.
Definition: soc_rcm.h:572
SOC_rcmR5SS1TriggerReset
void SOC_rcmR5SS1TriggerReset(void)
Trigger R5SS1 core reset.
RCM_PLLHSDIV_OUT_0
@ RCM_PLLHSDIV_OUT_0
Value specifying HSDIVIDER 0.
Definition: soc_rcm.h:597
SOC_RcmPllHsDivOutConfig::hsdivOutEnMask
uint32_t hsdivOutEnMask
Definition: soc_rcm.h:652
SOC_WarmResetCause_HSM_WDT
@ SOC_WarmResetCause_HSM_WDT
Value specifying HSM WDT.
Definition: soc_rcm.h:95
SOC_RcmPeripheralId_MCSPI5
@ SOC_RcmPeripheralId_MCSPI5
Value specifying MCSPI5.
Definition: soc_rcm.h:406
SOC_RcmClkSrcInfo
Definition: soc_rcm.h:614
SOC_rcmR5ConfigLockStep
void SOC_rcmR5ConfigLockStep(uint32_t cpuId)
Configure R5 in lock step mode.
SOC_RcmPeripheralId_RTI0
@ SOC_RcmPeripheralId_RTI0
Value specifying RTI0.
Definition: soc_rcm.h:338
SOC_rcmR5SS0TriggerReset
void SOC_rcmR5SS0TriggerReset(void)
Trigger R5 core reset.
SOC_RcmPeripheralId_RTI4
@ SOC_RcmPeripheralId_RTI4
Value specifying RTI4.
Definition: soc_rcm.h:354
SOC_rcmPerApllConfig
void SOC_rcmPerApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure PER PLL.
SOC_rcmWaitMemInitTCMA
void SOC_rcmWaitMemInitTCMA(uint32_t cpuId)
Wait memory initialization to complete for R5 TCMA.
SOC_rcmSetR5Clock
int32_t SOC_rcmSetR5Clock(uint32_t r5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
Set R5SS0/R5SS1 and SysClk frequency.
SOC_RcmPeripheralClockSource_RCCLK32K
@ SOC_RcmPeripheralClockSource_RCCLK32K
Value specifying RC clock (32KHz)
Definition: soc_rcm.h:512
SOC_WARM_RESET_PAD_TIME_64US
@ SOC_WARM_RESET_PAD_TIME_64US
Delay Value specifying in time 64us.
Definition: soc_rcm.h:194
SOC_RcmPeripheralId_MCSPI4
@ SOC_RcmPeripheralId_MCSPI4
Value specifying MCSPI4.
Definition: soc_rcm.h:402
SOC_WarmResetCause_MSS_WDT2
@ SOC_WarmResetCause_MSS_WDT2
Value specifying MSS WDT2.
Definition: soc_rcm.h:79
SOC_RcmPeripheralClockSource_EXT_REFCLK
@ SOC_RcmPeripheralClockSource_EXT_REFCLK
Value specifying external reference clock.
Definition: soc_rcm.h:504
SOC_RcmPeripheralId_ICSSM0_UART0
@ SOC_RcmPeripheralId_ICSSM0_UART0
Value specifying ICSSM0_UART0.
Definition: soc_rcm.h:422
SOC_WarmResetCause_MSS_WDT1
@ SOC_WarmResetCause_MSS_WDT1
Value specifying MSS WDT1.
Definition: soc_rcm.h:75
SOC_WARM_RESET_PAD_TIME_256US
@ SOC_WARM_RESET_PAD_TIME_256US
Delay Value specifying in time 256us.
Definition: soc_rcm.h:202
SOC_RcmPeripheralId_MCAN3
@ SOC_RcmPeripheralId_MCAN3
Value specifying MCAN3.
Definition: soc_rcm.h:330
SOC_RcmADPLLJConfig_t::Finp
uint32_t Finp
Definition: soc_rcm.h:632
SOC_RcmPllId
SOC_RcmPllId
Definition: soc_rcm.h:576
RCM_PLL_FOUT_FREQID_CLK_2000MHZ
@ RCM_PLL_FOUT_FREQID_CLK_2000MHZ
Value specifying PLL output frequency 2000MHz.
Definition: soc_rcm.h:550
SOC_RcmWarm_ResetTime123
SOC_RcmWarm_ResetTime123
Definition: soc_rcm.h:162
SOC_RcmPeripheralId_LIN3_UART3
@ SOC_RcmPeripheralId_LIN3_UART3
Value specifying LIN3_UART3.
Definition: soc_rcm.h:454
SOC_RcmPeripheralId_RTI6
@ SOC_RcmPeripheralId_RTI6
Value specifying RTI6.
Definition: soc_rcm.h:362
SOC_WarmResetCause_POWER_ON_RESET
@ SOC_WarmResetCause_POWER_ON_RESET
Value specifying Power ON Reset.
Definition: soc_rcm.h:67
SOC_RcmPeripheralClockSource_WUCPUCLK
@ SOC_RcmPeripheralClockSource_WUCPUCLK
Value specifying wake up clock.
Definition: soc_rcm.h:500
SOC_RcmPeripheralId_RTI3
@ SOC_RcmPeripheralId_RTI3
Value specifying RTI3.
Definition: soc_rcm.h:350
SOC_rcmR5SS0PowerOnReset
void SOC_rcmR5SS0PowerOnReset(void)
Reset R5SS0 Core.
SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1
@ SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (192 Mhz)
Definition: soc_rcm.h:536
SOC_RcmPeripheralId_LIN1_UART1
@ SOC_RcmPeripheralId_LIN1_UART1
Value specifying LIN1_UART1.
Definition: soc_rcm.h:446
SOC_RcmPeripheralId_MCAN1
@ SOC_RcmPeripheralId_MCAN1
Value specifying MCAN1.
Definition: soc_rcm.h:322
SOC_generateSwWarmReset
void SOC_generateSwWarmReset(void)
Generate SW WARM reset.
SOC_WarmResetSource_WDOG1
@ SOC_WarmResetSource_WDOG1
Value specifying Watchdog 1.
Definition: soc_rcm.h:142
SOC_RcmPeripheralId_RTI2
@ SOC_RcmPeripheralId_RTI2
Value specifying RTI2.
Definition: soc_rcm.h:346
SOC_WarmResetCause_TEMP_SENSOR0_RESET
@ SOC_WarmResetCause_TEMP_SENSOR0_RESET
Value specifying Temperature Sensor0 Reset.
Definition: soc_rcm.h:103
SOC_RcmADPLLJConfig_t::N
uint32_t N
Definition: soc_rcm.h:627
SOC_RcmResetCause_STC_RESET
@ SOC_RcmResetCause_STC_RESET
Value specifying STC Reset.
Definition: soc_rcm.h:249
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1
Value specifying PLL Core Clock Out 1 (500 Mhz)
Definition: soc_rcm.h:524
RCM_PLL_FOUT_FREQID_CLK_1920MHZ
@ RCM_PLL_FOUT_FREQID_CLK_1920MHZ
Value specifying PLL output frequency 1920MHz.
Definition: soc_rcm.h:554
SOC_RcmResetCause_WARM_RESET
@ SOC_RcmResetCause_WARM_RESET
Value specifying Warm Reset.
Definition: soc_rcm.h:245
SOC_RcmPeripheralId_MMC0
@ SOC_RcmPeripheralId_MMC0
Value specifying MMC0.
Definition: soc_rcm.h:418
SOC_WarmResetSource
SOC_WarmResetSource
Definition: soc_rcm.h:118
SOC_rcmR5ConfigDualCore
void SOC_rcmR5ConfigDualCore(uint32_t cpuId)
Configure R5 in dual core mode.
SOC_rcmMemInitL2Memory
void SOC_rcmMemInitL2Memory(void)
Wait memory initialization to complete for L2 Bank2 and Bank3 memory.
SOC_RcmPeripheralId_OSPI0
@ SOC_RcmPeripheralId_OSPI0
Value specifying OSPI0.
Definition: soc_rcm.h:334
SOC_WARM_RESET_PAD_TIME_4096US
@ SOC_WARM_RESET_PAD_TIME_4096US
Delay Value specifying in time 4096us.
Definition: soc_rcm.h:218
SOC_WarmResetCause
SOC_WarmResetCause
Definition: soc_rcm.h:63
SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
@ SOC_RcmResetCause_MMR_CPU1_VIM1_RESET
Value specifying R5 Core B Subsytem Reset.
Definition: soc_rcm.h:257
SOC_RcmPeripheralId_MCAN7
@ SOC_RcmPeripheralId_MCAN7
Value specifying MCAN7.
Definition: soc_rcm.h:478
SOC_WarmResetSource_DEBUGSS
@ SOC_WarmResetSource_DEBUGSS
Value specifying DebugSS.
Definition: soc_rcm.h:126
SOC_RcmClkSrcInfo::hsDivOut
SOC_RcmPllHSDIVOutId hsDivOut
Definition: soc_rcm.h:616
SOC_WarmResetCause_DBG_RESET
@ SOC_WarmResetCause_DBG_RESET
Value specifying Debugger Reset.
Definition: soc_rcm.h:99
RCM_PLLID_EXTREFCLK
@ RCM_PLLID_EXTREFCLK
Definition: soc_rcm.h:583
SOC_getWarmResetCause
SOC_WarmResetCause SOC_getWarmResetCause(void)
Returns cause of WARM reset.
SOC_RcmPeripheralId_LIN2_UART2
@ SOC_RcmPeripheralId_LIN2_UART2
Value specifying LIN2_UART2.
Definition: soc_rcm.h:450
SOC_RcmPllFoutFreqId
SOC_RcmPllFoutFreqId
Definition: soc_rcm.h:546
RCM_PLLID_XTALCLK
@ RCM_PLLID_XTALCLK
Definition: soc_rcm.h:579
SOC_WarmResetSource_WDOG3
@ SOC_WarmResetSource_WDOG3
Value specifying Watchdog 3.
Definition: soc_rcm.h:150
SOC_RcmADPLLJConfig_t::M2
uint32_t M2
Definition: soc_rcm.h:628
r5fss0
@ r5fss0
Value specifying Power ON Reset.
Definition: soc_rcm.h:300
SOC_RcmResetCause_MMR_CPU1_RESET
@ SOC_RcmResetCause_MMR_CPU1_RESET
Value specifying R5 Core B (core only) Reset.
Definition: soc_rcm.h:265
RCM_PLLHSDIV_OUT_2
@ RCM_PLLHSDIV_OUT_2
Value specifying HSDIVIDER 2.
Definition: soc_rcm.h:605
SOC_RcmPeripheralId_WDT0
@ SOC_RcmPeripheralId_WDT0
Value specifying WDT0.
Definition: soc_rcm.h:370
SOC_rcmGetR5Clock
uint32_t SOC_rcmGetR5Clock(uint32_t cpuId)
Get R5SS0/1 frequency.
SOC_RcmPeripheralId_CONTROLSS_PLL
@ SOC_RcmPeripheralId_CONTROLSS_PLL
Value specifying CONTROLSS_PLL.
Definition: soc_rcm.h:434
SOC_WarmResetSource_PAD_BYPASS
@ SOC_WarmResetSource_PAD_BYPASS
Value specifying Pad Warm Reset pin.
Definition: soc_rcm.h:122
SOC_RcmPeripheralId_CPTS
@ SOC_RcmPeripheralId_CPTS
Value specifying CPTS.
Definition: soc_rcm.h:426
SOC_configureWarmResetSource
void SOC_configureWarmResetSource(uint32_t source)
Configure WARM reset source.
SOC_RcmPeripheralClockSource_CTPS_GENF0
@ SOC_RcmPeripheralClockSource_CTPS_GENF0
Value specifying CPTS GENF0 clock.
Definition: soc_rcm.h:516
RCM_PLL_HSDIV_OUTPUT_COUNT
#define RCM_PLL_HSDIV_OUTPUT_COUNT
Definition: soc_rcm.h:648
SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
@ SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2
Value specifying PLL Core Clock Out 2 (400 Mhz)
Definition: soc_rcm.h:528
SOC_rcmCoreApllConfig
void SOC_rcmCoreApllConfig(SOC_RcmPllFoutFreqId outFreqId, SOC_RcmPllHsDivOutConfig *hsDivCfg)
Configure CORE PLL.
SOC_RcmResetCause_POR_RST_CTRL0
@ SOC_RcmResetCause_POR_RST_CTRL0
Value specifying R5 Reset due to write to debug POR RST CTRL Reg.
Definition: soc_rcm.h:281
SOC_RcmPeripheralClockSource_RCCLK10M
@ SOC_RcmPeripheralClockSource_RCCLK10M
Value specifying RC clock (10MHz)
Definition: soc_rcm.h:508