AM263Px MCU+ SDK: adc.h Source File

| AM263Px MCU+ SDK 26.00.00 |

adc/v2/adc.h
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1 /*
2 * Copyright (C) 2024 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
42 #ifndef ADC_V2_H_
43 #define ADC_V2_H_
44
45 //*****************************************************************************
46 //
47 // If building with a C++ compiler, make all of the definitions in this header
48 // have a C binding.
49 //
50 //*****************************************************************************
51 #ifdef __cplusplus
52 extern "C"
53 {
54 #endif
55
56 //*****************************************************************************
57 //
59 //
60 //*****************************************************************************
61 #include <stdint.h>
62 #include <stdbool.h>
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
65 #include <kernel/dpl/DebugP.h>
66 #include <drivers/hw_include/cslr_adc.h>
67 //*****************************************************************************
68 //
70 //
71 //*****************************************************************************
73 #define ADC_ADCSOCxCTL_STEP (CSL_ADC_ADCSOC1CTL - CSL_ADC_ADCSOC0CTL)
74 #define ADC_ADCINTSELxNy_STEP (CSL_ADC_ADCINTSEL3N4 - CSL_ADC_ADCINTSEL1N2)
76 #define ADC_ADCPPBx_STEP (CSL_ADC_ADCPPB2CONFIG - CSL_ADC_ADCPPB1CONFIG)
78 #define ADC_ADCPPBTRIP_MASK ((uint32_t)CSL_ADC_ADCPPB1TRIPHI_LIMITHI_MASK \
80 | (uint32_t)CSL_ADC_ADCPPB1TRIPHI_HSIGN_MASK)
81 #define ADC_RESULT_ADCPPBxRESULT_STEP (CSL_ADC_RESULT_ADCPPB2RESULT -\
83 CSL_ADC_RESULT_ADCPPB1RESULT)
84 #define ADC_RESULT_ADCRESULTx_STEP (CSL_ADC_RESULT_ADCRESULT1 - \
86 CSL_ADC_RESULT_ADCRESULT0)
87 //*****************************************************************************
88 //
89 // Define to mask out the bits in the REPxCTL register that aren't associated
90 // with repeater configuration.
91 //
92 //*****************************************************************************
93 #define ADC_REPCTL_MASK (CSL_ADC_REP1CTL_MODE_MASK |\
94 CSL_ADC_REP1CTL_TRIGGER_MASK |\
95 CSL_ADC_REP1CTL_SYNCINSEL_MASK)
96
98
99 #define ADC_ADCPPBxCONFIG2_STEP (CSL_ADC_ADCPPB2CONFIG2 - CSL_ADC_ADCPPB1CONFIG2)
100 #define ADC_REPxCTL_STEP (CSL_ADC_REP2CTL - CSL_ADC_REP1CTL)
101 #define ADC_REPxN_STEP (CSL_ADC_REP2N - CSL_ADC_REP1N)
102 #define ADC_REPxPHASE_STEP (CSL_ADC_REP2PHASE - CSL_ADC_REP1PHASE)
103 #define ADC_REPxSPREAD_STEP (CSL_ADC_REP2SPREAD - CSL_ADC_REP1SPREAD)
104
105
106 #define ADC_PPBxTRIPHI_STEP (CSL_ADC_ADCPPB1TRIPHI - CSL_ADC_ADCPPB1TRIPHI)
107 #define ADC_PPBxTRIPLO_STEP (CSL_ADC_ADCPPB2TRIPLO - CSL_ADC_ADCPPB1TRIPLO)
108 #define ADC_ADCPPBxLIMIT_STEP (CSL_ADC_ADCPPB2LIMIT - CSL_ADC_ADCPPB1LIMIT)
109 #define ADC_ADCPPBxPCOUNT_STEP (CSL_ADC_ADCPPBP2PCOUNT - CSL_ADC_ADCPPBP1PCOUNT)
110 #define ADC_ADCPPBxCONFIG2_STEP (CSL_ADC_ADCPPB2CONFIG2 - CSL_ADC_ADCPPB1CONFIG2)
111 #define ADC_ADCPPBxPSUM_STEP (CSL_ADC_ADCPPB2PSUM - CSL_ADC_ADCPPB1PSUM)
112 #define ADC_ADCPPBxPMAX_STEP (CSL_ADC_ADCPPB2PMAX - CSL_ADC_ADCPPB1PMAX)
113 #define ADC_ADCPPBxPMAXI_STEP (CSL_ADC_ADCPPB2PMAXI - CSL_ADC_ADCPPB1PMAXI)
114 #define ADC_ADCPPBxPMIN_STEP (CSL_ADC_ADCPPB2PMIN - CSL_ADC_ADCPPB1PMIN)
115 #define ADC_ADCPPBxPMINI_STEP (CSL_ADC_ADCPPB2PMINI - CSL_ADC_ADCPPB1PMINI)
116 #define ADC_ADCPPBxTRIPLO2_STEP (CSL_ADC_ADCPPB2TRIPLO2 - CSL_ADC_ADCPPB1TRIPLO2)
117
118 //*****************************************************************************
119 //
120 // Define to mask out the bits in the REPSTATUS register that aren't
121 // associated with trigger repeater block status.
122 //
123 //*****************************************************************************
124 #define ADC_REPSTATUS_MASK (CSL_ADC_REP1CTL_MODULEBUSY_MASK |\
125 CSL_ADC_REP1CTL_PHASEOVF_MASK |\
126 CSL_ADC_REP1CTL_TRIGGEROVF_MASK)
127
128 //*****************************************************************************
129 //
130 // Define to mask out the bits in the CHECKSTATUS register that aren't
131 // associated with safety checker result status.
132 //
133 //*****************************************************************************
134 #define ADC_SAFECHECK_STATUS_MASK (CSL_ADC_SAFETY_CHECKSTATUS_RES1READY_MASK|\
135 CSL_ADC_SAFETY_CHECKSTATUS_RES2READY_MASK|\
136 CSL_ADC_SAFETY_CHECKSTATUS_OOT_MASK)
137 //*****************************************************************************
138 //
139 // Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(),
140 // ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and
141 // ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also
142 // make up the enumerated bit field returned by ADC_getPPBEventStatus().
143 //
144 //*****************************************************************************
145 #define ADC_EVT_TRIPHI (0x0001U)
146 #define ADC_EVT_TRIPLO (0x0002U)
147 #define ADC_EVT_ZERO (0x0004U)
148
149 //*****************************************************************************
150 //
151 // Values that can be passed to ADC_forceMultipleSOC() as socMask parameter.
152 // These values can be OR'd together to trigger multiple SOCs at a time.
153 //
154 //*****************************************************************************
155 #define ADC_FORCE_SOC0 (0x0001U)
156 #define ADC_FORCE_SOC1 (0x0002U)
157 #define ADC_FORCE_SOC2 (0x0004U)
158 #define ADC_FORCE_SOC3 (0x0008U)
159 #define ADC_FORCE_SOC4 (0x0010U)
160 #define ADC_FORCE_SOC5 (0x0020U)
161 #define ADC_FORCE_SOC6 (0x0040U)
162 #define ADC_FORCE_SOC7 (0x0080U)
163 #define ADC_FORCE_SOC8 (0x0100U)
164 #define ADC_FORCE_SOC9 (0x0200U)
165 #define ADC_FORCE_SOC10 (0x0400U)
166 #define ADC_FORCE_SOC11 (0x0800U)
167 #define ADC_FORCE_SOC12 (0x1000U)
168 #define ADC_FORCE_SOC13 (0x2000U)
169 #define ADC_FORCE_SOC14 (0x4000U)
170 #define ADC_FORCE_SOC15 (0x8000U)
171
172 //*****************************************************************************
173 //
176 //
177 //*****************************************************************************
178 typedef enum
179 {
180 ADC_CLK_DIV_1_0 = 0,
181 ADC_CLK_DIV_2_0 = 2,
182 ADC_CLK_DIV_2_5 = 3,
183 ADC_CLK_DIV_3_0 = 4,
184 ADC_CLK_DIV_3_5 = 5,
185 ADC_CLK_DIV_4_0 = 6,
186 ADC_CLK_DIV_4_5 = 7,
187 ADC_CLK_DIV_5_0 = 8,
188 ADC_CLK_DIV_5_5 = 9,
189 ADC_CLK_DIV_6_0 = 10,
190 ADC_CLK_DIV_6_5 = 11,
191 ADC_CLK_DIV_7_0 = 12,
192 ADC_CLK_DIV_7_5 = 13,
193 ADC_CLK_DIV_8_0 = 14,
194 ADC_CLK_DIV_8_5 = 15
195 } ADC_ClkPrescale;
196
197 //*****************************************************************************
198 //
201 //
202 //*****************************************************************************
203 typedef enum
204 {
205 ADC_RESOLUTION_12BIT = 0
206 } ADC_Resolution;
207
208 //*****************************************************************************
209 //
212 //
213 //*****************************************************************************
214 typedef enum
215 {
216 ADC_MODE_SINGLE_ENDED = 0,
217 ADC_MODE_DIFFERENTIAL = 1
218 } ADC_SignalMode;
219
220 //*****************************************************************************
221 //
225 //
226 //*****************************************************************************
227 typedef enum
228 {
229 ADC_TRIGGER_SW_ONLY = 0x00,
230 ADC_TRIGGER_RTI0 = 0x01,
231 ADC_TRIGGER_RTI1 = 0x02,
232 ADC_TRIGGER_RTI2 = 0x03,
233 ADC_TRIGGER_RTI3 = 0x04,
234 ADC_TRIGGER_INPUT_XBAR_OUT5 = 0x05,
235 ADC_TRIGGER_EPWM0_SOCA = 0x08,
236 ADC_TRIGGER_EPWM0_SOCB = 0x09,
237 ADC_TRIGGER_EPWM1_SOCA = 0x0A,
238 ADC_TRIGGER_EPWM1_SOCB = 0x0B,
239 ADC_TRIGGER_EPWM2_SOCA = 0x0C,
240 ADC_TRIGGER_EPWM2_SOCB = 0x0D,
241 ADC_TRIGGER_EPWM3_SOCA = 0x0E,
242 ADC_TRIGGER_EPWM3_SOCB = 0x0F,
243 ADC_TRIGGER_EPWM4_SOCA = 0x10,
244 ADC_TRIGGER_EPWM4_SOCB = 0x11,
245 ADC_TRIGGER_EPWM5_SOCA = 0x12,
246 ADC_TRIGGER_EPWM5_SOCB = 0x13,
247 ADC_TRIGGER_EPWM6_SOCA = 0x14,
248 ADC_TRIGGER_EPWM6_SOCB = 0x15,
249 ADC_TRIGGER_EPWM7_SOCA = 0x16,
250 ADC_TRIGGER_EPWM7_SOCB = 0x17,
251 ADC_TRIGGER_EPWM8_SOCA = 0x18,
252 ADC_TRIGGER_EPWM8_SOCB = 0x19,
253 ADC_TRIGGER_EPWM9_SOCA = 0x1A,
254 ADC_TRIGGER_EPWM9_SOCB = 0x1B,
255 ADC_TRIGGER_EPWM10_SOCA = 0x1C,
256 ADC_TRIGGER_EPWM10_SOCB = 0x1D,
257 ADC_TRIGGER_EPWM11_SOCA = 0x1E,
258 ADC_TRIGGER_EPWM11_SOCB = 0x1F,
259 ADC_TRIGGER_EPWM12_SOCA = 0x20,
260 ADC_TRIGGER_EPWM12_SOCB = 0x21,
261 ADC_TRIGGER_EPWM13_SOCA = 0x22,
262 ADC_TRIGGER_EPWM13_SOCB = 0x23,
263 ADC_TRIGGER_EPWM14_SOCA = 0x24,
264 ADC_TRIGGER_EPWM14_SOCB = 0x25,
265 ADC_TRIGGER_EPWM15_SOCA = 0x26,
266 ADC_TRIGGER_EPWM15_SOCB = 0x27,
267 ADC_TRIGGER_EPWM16_SOCA = 0x28,
268 ADC_TRIGGER_EPWM16_SOCB = 0x29,
269 ADC_TRIGGER_EPWM17_SOCA = 0x2A,
270 ADC_TRIGGER_EPWM17_SOCB = 0x2B,
271 ADC_TRIGGER_EPWM18_SOCA = 0x2C,
272 ADC_TRIGGER_EPWM18_SOCB = 0x2D,
273 ADC_TRIGGER_EPWM19_SOCA = 0x2E,
274 ADC_TRIGGER_EPWM19_SOCB = 0x2F,
275 ADC_TRIGGER_EPWM20_SOCA = 0x30,
276 ADC_TRIGGER_EPWM20_SOCB = 0x31,
277 ADC_TRIGGER_EPWM21_SOCA = 0x32,
278 ADC_TRIGGER_EPWM21_SOCB = 0x33,
279 ADC_TRIGGER_EPWM22_SOCA = 0x34,
280 ADC_TRIGGER_EPWM22_SOCB = 0x35,
281 ADC_TRIGGER_EPWM23_SOCA = 0x36,
282 ADC_TRIGGER_EPWM23_SOCB = 0x37,
283 ADC_TRIGGER_EPWM24_SOCA = 0x38,
284 ADC_TRIGGER_EPWM24_SOCB = 0x39,
285 ADC_TRIGGER_EPWM25_SOCA = 0x3A,
286 ADC_TRIGGER_EPWM25_SOCB = 0x3B,
287 ADC_TRIGGER_EPWM26_SOCA = 0x3C,
288 ADC_TRIGGER_EPWM26_SOCB = 0x3D,
289 ADC_TRIGGER_EPWM27_SOCA = 0x3E,
290 ADC_TRIGGER_EPWM27_SOCB = 0x3F,
291 ADC_TRIGGER_EPWM28_SOCA = 0x40,
292 ADC_TRIGGER_EPWM28_SOCB = 0x41,
293 ADC_TRIGGER_EPWM29_SOCA = 0x42,
294 ADC_TRIGGER_EPWM29_SOCB = 0x43,
295 ADC_TRIGGER_EPWM30_SOCA = 0x44,
296 ADC_TRIGGER_EPWM30_SOCB = 0x45,
297 ADC_TRIGGER_EPWM31_SOCA = 0x46,
298 ADC_TRIGGER_EPWM31_SOCB = 0x47,
299 ADC_TRIGGER_ECAP0_SOCEVT = 0x48,
300 ADC_TRIGGER_ECAP1_SOCEVT = 0x49,
301 ADC_TRIGGER_ECAP2_SOCEVT = 0x4A,
302 ADC_TRIGGER_ECAP3_SOCEVT = 0x4B,
303 ADC_TRIGGER_ECAP4_SOCEVT = 0x4C,
304 ADC_TRIGGER_ECAP5_SOCEVT = 0x4D,
305 ADC_TRIGGER_ECAP6_SOCEVT = 0x4E,
306 ADC_TRIGGER_ECAP7_SOCEVT = 0x4F,
307 ADC_TRIGGER_ECAP8_SOCEVT = 0x50,
308 ADC_TRIGGER_ECAP9_SOCEVT = 0x51,
309 ADC_TRIGGER_ECAP10_SOCEVT = 0x52,
310 ADC_TRIGGER_ECAP11_SOCEVT = 0x53,
311 ADC_TRIGGER_ECAP12_SOCEVT = 0x54,
312 ADC_TRIGGER_ECAP13_SOCEVT = 0x55,
313 ADC_TRIGGER_ECAP14_SOCEVT = 0x56,
314 ADC_TRIGGER_ECAP15_SOCEVT = 0x57,
315 ADC_TRIGGER_RTI4 = 0x58,
316 ADC_TRIGGER_RTI5 = 0x59,
317 ADC_TRIGGER_RTI6 = 0x5A,
318 ADC_TRIGGER_RTI7 = 0x5B,
319 ADC_TRIGGER_REPEATER1 = 0x7E,
320 ADC_TRIGGER_REPEATER2 = 0x7F,
321 } ADC_Trigger;
322
323 //*****************************************************************************
324 //
328 //
329 //*****************************************************************************
330 typedef enum
331 {
332 ADC_CH_ADCIN0 = 0,
333 ADC_CH_ADCIN1 = 1,
334 ADC_CH_ADCIN2 = 2,
335 ADC_CH_ADCIN3 = 3,
336 ADC_CH_ADCIN4 = 4,
337 ADC_CH_ADCIN5 = 5,
338 ADC_CH_ADCIN6 = 7,
339 ADC_CH_CAL0 = 6,
340 ADC_CH_CAL1 = 7,
341 ADC_CH_ADCIN0_ADCIN1 = 0,
342 ADC_CH_ADCIN1_ADCIN0 = 1,
343 ADC_CH_ADCIN2_ADCIN3 = 2,
344 ADC_CH_ADCIN3_ADCIN2 = 3,
345 ADC_CH_ADCIN4_ADCIN5 = 4,
346 ADC_CH_ADCIN5_ADCIN4 = 5,
347 ADC_CH_CAL0_CAL1 = 6,
348 ADC_CH_CAL1_CAL0 = 7,
349 ADC_CH_CAL0_ADCIN6 = 6,
350 ADC_CH_ADCIN6_CAL0 = 7,
351 } ADC_Channel;
352
353 //*****************************************************************************
354 //
357 //
358 //*****************************************************************************
359 typedef enum
360 {
362 ADC_PULSE_END_OF_ACQ_WIN = 0,
364 ADC_PULSE_END_OF_CONV = 1
365 } ADC_PulseMode;
366
367 //*****************************************************************************
368 //
374 //
375 //*****************************************************************************
376 typedef enum
377 {
378 ADC_INT_NUMBER1 = 0,
379 ADC_INT_NUMBER2 = 1,
380 ADC_INT_NUMBER3 = 2,
381 ADC_INT_NUMBER4 = 3
382 } ADC_IntNumber;
383
384 //*****************************************************************************
385 //
388 //
389 //*****************************************************************************
390 typedef enum
391 {
392 ADC_PPB_NUMBER1 = 0,
393 ADC_PPB_NUMBER2 = 1,
394 ADC_PPB_NUMBER3 = 2,
395 ADC_PPB_NUMBER4 = 3
396 } ADC_PPBNumber;
397
398 //*****************************************************************************
399 //
405 //
406 //*****************************************************************************
407 typedef enum
408 {
409 ADC_SOC_NUMBER0 = 0,
410 ADC_SOC_NUMBER1 = 1,
411 ADC_SOC_NUMBER2 = 2,
412 ADC_SOC_NUMBER3 = 3,
413 ADC_SOC_NUMBER4 = 4,
414 ADC_SOC_NUMBER5 = 5,
415 ADC_SOC_NUMBER6 = 6,
416 ADC_SOC_NUMBER7 = 7,
417 ADC_SOC_NUMBER8 = 8,
418 ADC_SOC_NUMBER9 = 9,
419 ADC_SOC_NUMBER10 = 10,
420 ADC_SOC_NUMBER11 = 11,
421 ADC_SOC_NUMBER12 = 12,
422 ADC_SOC_NUMBER13 = 13,
423 ADC_SOC_NUMBER14 = 14,
424 ADC_SOC_NUMBER15 = 15
425 } ADC_SOCNumber;
426
427 //*****************************************************************************
428 //
431 //
432 //*****************************************************************************
433 typedef enum
434 {
435 ADC_INT_SOC_TRIGGER_NONE = 0,
436 ADC_INT_SOC_TRIGGER_ADCINT1 = 1,
437 ADC_INT_SOC_TRIGGER_ADCINT2 = 2
438 } ADC_IntSOCTrigger;
439
440 //*****************************************************************************
441 //
444 //
445 //*****************************************************************************
446 typedef enum
447 {
448 ADC_PRI_ALL_ROUND_ROBIN = 0,
449 ADC_PRI_SOC0_HIPRI = 1,
450 ADC_PRI_THRU_SOC1_HIPRI = 2,
451 ADC_PRI_THRU_SOC2_HIPRI = 3,
452 ADC_PRI_THRU_SOC3_HIPRI = 4,
453 ADC_PRI_THRU_SOC4_HIPRI = 5,
454 ADC_PRI_THRU_SOC5_HIPRI = 6,
455 ADC_PRI_THRU_SOC6_HIPRI = 7,
456 ADC_PRI_THRU_SOC7_HIPRI = 8,
457 ADC_PRI_THRU_SOC8_HIPRI = 9,
458 ADC_PRI_THRU_SOC9_HIPRI = 10,
459 ADC_PRI_THRU_SOC10_HIPRI = 11,
460 ADC_PRI_THRU_SOC11_HIPRI = 12,
461 ADC_PRI_THRU_SOC12_HIPRI = 13,
462 ADC_PRI_THRU_SOC13_HIPRI = 14,
463 ADC_PRI_THRU_SOC14_HIPRI = 15,
464 ADC_PRI_ALL_HIPRI = 16
465 } ADC_PriorityMode;
466
467 //*****************************************************************************
468 //
471 //
472 //*****************************************************************************
473 typedef enum
474 {
475 ADC_OSDETECT_MODE_DISABLED = 0x0U,
476 ADC_OSDETECT_MODE_VSSA = 0x1U,
478 ADC_OSDETECT_MODE_VDDA = 0x2U,
480 ADC_OSDETECT_MODE_5BY12_VDDA = 0x3U,
482 ADC_OSDETECT_MODE_7BY12_VDDA = 0x4U,
484 ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5U,
486 ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA = 0x6U,
488 ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7U
490 } ADC_OSDetectMode;
492
493 //*****************************************************************************
494 //
497 //
498 //*****************************************************************************
499 typedef enum
500 {
501 ADC_OFFSET_TRIM_COMMON = 0x0000U,
502 ADC_OFFSET_TRIM_INDIVIDUAL = 0x0100U
504 } ADC_OffsetTrim;
506
507 typedef enum
508 {
509 ADC_SYNCIN_DISABLE = 0x00,
510 ADC_SYNCIN_EPWM0SYNCOUT = 0x01,
511 ADC_SYNCIN_EPWM1SYNCOUT = 0x02,
512 ADC_SYNCIN_EPWM2SYNCOUT = 0x03,
513 ADC_SYNCIN_EPWM3SYNCOUT = 0x04,
514 ADC_SYNCIN_EPWM4SYNCOUT = 0x05,
515 ADC_SYNCIN_EPWM5SYNCOUT = 0x06,
516 ADC_SYNCIN_EPWM6SYNCOUT = 0x07,
517 ADC_SYNCIN_EPWM7SYNCOUT = 0x08,
518 ADC_SYNCIN_EPWM8SYNCOUT = 0x09,
519 ADC_SYNCIN_EPWM9SYNCOUT = 0x0A,
520 ADC_SYNCIN_EPWM10SYNCOUT = 0x0B,
521 ADC_SYNCIN_EPWM11SYNCOUT = 0x0C,
522 ADC_SYNCIN_EPWM12SYNCOUT = 0x0D,
523 ADC_SYNCIN_EPWM13SYNCOUT = 0x0E,
524 ADC_SYNCIN_EPWM14SYNCOUT = 0x0F,
525 ADC_SYNCIN_EPWM15SYNCOUT = 0x10,
526 ADC_SYNCIN_EPWM16SYNCOUT = 0x11,
527 ADC_SYNCIN_EPWM17SYNCOUT = 0x12,
528 ADC_SYNCIN_EPWM18SYNCOUT = 0x13,
529 ADC_SYNCIN_EPWM19SYNCOUT = 0x14,
530 ADC_SYNCIN_EPWM20SYNCOUT = 0x15,
531 ADC_SYNCIN_EPWM21SYNCOUT = 0x16,
532 ADC_SYNCIN_EPWM22SYNCOUT = 0x17,
533 ADC_SYNCIN_EPWM23SYNCOUT = 0x18,
534 ADC_SYNCIN_EPWM24SYNCOUT = 0x19,
535 ADC_SYNCIN_EPWM25SYNCOUT = 0x1A,
536 ADC_SYNCIN_EPWM26SYNCOUT = 0x1B,
537 ADC_SYNCIN_EPWM27SYNCOUT = 0x1C,
538 ADC_SYNCIN_EPWM28SYNCOUT = 0x1D,
539 ADC_SYNCIN_EPWM29SYNCOUT = 0x1E,
540 ADC_SYNCIN_EPWM30SYNCOUT = 0x1F,
541 ADC_SYNCIN_EPWM31SYNCOUT = 0x20,
542 ADC_SYNCIN_ECAP0SYNCOUT = 0x21,
543 ADC_SYNCIN_ECAP1SYNCOUT = 0x22,
544 ADC_SYNCIN_ECAP2SYNCOUT = 0x23,
545 ADC_SYNCIN_ECAP3SYNCOUT = 0x24,
546 ADC_SYNCIN_ECAP4SYNCOUT = 0x25,
547 ADC_SYNCIN_ECAP5SYNCOUT = 0x26,
548 ADC_SYNCIN_ECAP6SYNCOUT = 0x27,
549 ADC_SYNCIN_ECAP7SYNCOUT = 0x28,
550 ADC_SYNCIN_ECAP8SYNCOUT = 0x29,
551 ADC_SYNCIN_ECAP9SYNCOUT = 0x2A,
552 ADC_SYNCIN_ECAP10SYNCOUT = 0x2B,
553 ADC_SYNCIN_ECAP11SYNCOUT = 0x2C,
554 ADC_SYNCIN_ECAP12SYNCOUT = 0x2D,
555 ADC_SYNCIN_ECAP13SYNCOUT = 0x2E,
556 ADC_SYNCIN_ECAP14SYNCOUT = 0x2F,
557 ADC_SYNCIN_ECAP15SYNCOUT = 0x30,
558 ADC_SYNCIN_INPUTXBAROUTPUT6 = 0x31,
559 ADC_SYNCIN_INPUTXBAROUTPUT7 = 0x32,
560 ADC_SYNCIN_CPSW_CTPS_SYNC = 0x33,
561 } ADC_SyncInput;
562
563 //*****************************************************************************
564 //
567 //
568 //*****************************************************************************
569 typedef enum
570 {
571 ADC_PPB_OS_INT_1 = 0x0U,
572 ADC_PPB_OS_INT_2 = 0x1U
573 } ADC_PPBIntSrcSelect;
574
575 //*****************************************************************************
576 //
579 //
580 //*****************************************************************************
581 typedef enum
582 {
583 ADC_CH_ADCINX_0 = 0x0,
584 ADC_CH_ADCINX_1 = 0x1,
585 ADC_CH_ADCINX_2 = 0x2,
586 ADC_CH_ADCINX_3 = 0x3,
587 } ADC_ExtChannel;
588
589 //*****************************************************************************
590 //
593 //
594 //*****************************************************************************
595 typedef enum
596 {
597 ADC_INT_TRIGGER_EOC0 = 0,
598 ADC_INT_TRIGGER_EOC1 = 1,
599 ADC_INT_TRIGGER_EOC2 = 2,
600 ADC_INT_TRIGGER_EOC3 = 3,
601 ADC_INT_TRIGGER_EOC4 = 4,
602 ADC_INT_TRIGGER_EOC5 = 5,
603 ADC_INT_TRIGGER_EOC6 = 6,
604 ADC_INT_TRIGGER_EOC7 = 7,
605 ADC_INT_TRIGGER_EOC8 = 8,
606 ADC_INT_TRIGGER_EOC9 = 9,
607 ADC_INT_TRIGGER_EOC10 = 10,
608 ADC_INT_TRIGGER_EOC11 = 11,
609 ADC_INT_TRIGGER_EOC12 = 12,
610 ADC_INT_TRIGGER_EOC13 = 13,
611 ADC_INT_TRIGGER_EOC14 = 14,
612 ADC_INT_TRIGGER_EOC15 = 15,
613 ADC_INT_TRIGGER_OSINT1 = 16,
614 ADC_INT_TRIGGER_OSINT2 = 17,
615 ADC_INT_TRIGGER_OSINT3 = 18,
616 ADC_INT_TRIGGER_OSINT4 = 19
617 } ADC_IntTrigger;
618
619 //*****************************************************************************
620 //
623 //
624 //*****************************************************************************
625 typedef enum
626 {
627 ADC_PPB_COMPSOURCE_RESULT = 0x0,
628 ADC_PPB_COMPSOURCE_PSUM = 0x1,
629 ADC_PPB_COMPSOURCE_SUM = 0x2
630 } ADC_PPBCompSource;
631
632 //*****************************************************************************
633 //
636 //
637 //*****************************************************************************
638 typedef enum
639 {
640 ADC_0 = 0,
641 ADC_1 = 1,
642 ADC_2 = 2,
643 ADC_3 = 3,
644 ADC_4 = 4
645 } ADC_Select;
646
647 //*****************************************************************************
648 //
651 //
652 //*****************************************************************************
653 typedef enum
654 {
655 ADC_RESULT0 = 0,
656 ADC_RESULT1 = 1,
657 ADC_RESULT2 = 2,
658 ADC_RESULT3 = 3,
659 ADC_RESULT4 = 4,
660 ADC_RESULT5 = 5,
661 ADC_RESULT6 = 6,
662 ADC_RESULT7 = 7,
663 ADC_RESULT8 = 8,
664 ADC_RESULT9 = 9,
665 ADC_RESULT10 = 10,
666 ADC_RESULT11 = 11,
667 ADC_RESULT12 = 12,
668 ADC_RESULT13 = 13,
669 ADC_RESULT14 = 14,
670 ADC_RESULT15 = 15
671 } ADC_ResultSelect;
672
673 //*****************************************************************************
674 //
677 //
678 //*****************************************************************************
679 typedef enum
680 {
681 ADC_SAFETY_CHECKER_INPUT_DISABLE = 0x0,
682 ADC_SAFETY_CHECKER_INPUT_SOCx = 0x1,
683 ADC_SAFETY_CHECKER_INPUT_PPBx = 0x2,
684 ADC_SAFETY_CHECKER_INPUT_PPBSUMx = 0x3
685 } ADC_SafetyCheckerInput;
686
687 //*****************************************************************************
688 //
691 //
692 //*****************************************************************************
693 typedef enum
694 {
695 ADC_SAFETY_CHECK1 = 0x0,
696 ADC_SAFETY_CHECK2 = 0x4
697 } ADC_SafetyCheckInst;
698
699 //*****************************************************************************
700 //
703 //
704 //*****************************************************************************
705 typedef enum
706 {
707 ADC_SAFETY_CHECK_EVENT1 = 0,
708 ADC_SAFETY_CHECK_EVENT2 = 16,
709 ADC_SAFETY_CHECK_EVENT3 = 32,
710 ADC_SAFETY_CHECK_EVENT4 = 48
711 } ADC_SafetyCheckEvent;
712
713 //*****************************************************************************
714 //
718 //
719 //*****************************************************************************
720 typedef enum
721 {
722 ADC_SAFETY_CHECK_RES1OVF = 0,
723 ADC_SAFETY_CHECK_RES2OVF = 4,
724 ADC_SAFETY_CHECK_OOT = 8
725 } ADC_SafetyCheckResult;
726
727 //*****************************************************************************
728 //
734 //
735 //*****************************************************************************
736 typedef enum
737 {
738 ADC_SAFETY_CHECKER1 = 0,
739 ADC_SAFETY_CHECKER2 = 1,
740 ADC_SAFETY_CHECKER3 = 2,
741 ADC_SAFETY_CHECKER4 = 3,
742 ADC_SAFETY_CHECKER5 = 4,
743 ADC_SAFETY_CHECKER6 = 5,
744 ADC_SAFETY_CHECKER7 = 6,
745 ADC_SAFETY_CHECKER8 = 7,
746 ADC_SAFETY_CHECKER9 = 8,
747 ADC_SAFETY_CHECKER10 = 9,
748 ADC_SAFETY_CHECKER11 = 10,
749 ADC_SAFETY_CHECKER12 = 11
750 }ADC_Checker;
751
752 //*****************************************************************************
753 //
756 //
757 //*****************************************************************************
758 typedef enum
759 {
760 ADC_SAFETY_CHECK_OOT_FLG = 0,
761 ADC_SAFETY_CHECK_RES1OVF_FLG = 4,
762 ADC_SAFETY_CHECK_RES2OVF_FLG = 8
763 }ADC_SafetyCheckFlag;
764
765 //*****************************************************************************
766 //
769 //
770 //*****************************************************************************
771 typedef enum
772 {
773 ADC_REPINST1 = 0x0,
774 ADC_REPINST2 = 0x1
775 } ADC_RepInstance;
776
777 //*****************************************************************************
778 //
781 //
782 //*****************************************************************************
783 typedef enum
784 {
785 ADC_REPMODE_OVERSAMPLING = 0x0,
786 ADC_REPMODE_UNDERSAMPLING = 0x1
787 } ADC_RepMode;
788
789 //*****************************************************************************
790 //
793 //
794 //*****************************************************************************
795 typedef struct
796 {
797 ADC_RepMode repMode;
798 ADC_Trigger repTrigger;
799 ADC_SyncInput repSyncin;
800 uint16_t repCount;
801 uint16_t repPhase;
802 uint16_t repSpread;
803 } ADC_RepeaterConfig;
804
805 //*****************************************************************************
806 //
808 //
809 //*****************************************************************************
811 #define ADC_ADCSOCxCTL_STEP (CSL_ADC_ADCSOC1CTL - CSL_ADC_ADCSOC0CTL)
812 #define ADC_ADCINTSELxNy_STEP (CSL_ADC_ADCINTSEL3N4 - CSL_ADC_ADCINTSEL1N2)
814 #define ADC_ADCPPBx_STEP (CSL_ADC_ADCPPB2CONFIG - CSL_ADC_ADCPPB1CONFIG)
816 #define ADC_ADCPPBTRIP_MASK ((uint32_t)CSL_ADC_ADCPPB1TRIPHI_LIMITHI_MASK \
818 | (uint32_t)CSL_ADC_ADCPPB1TRIPHI_HSIGN_MASK)
819 #define ADC_RESULT_ADCPPBxRESULT_STEP (CSL_ADC_RESULT_ADCPPB2RESULT -\
821 CSL_ADC_RESULT_ADCPPB1RESULT)
822 #define ADC_RESULT_ADCRESULTx_STEP (CSL_ADC_RESULT_ADCRESULT1 - \
824 CSL_ADC_RESULT_ADCRESULT0)
825
826 //*****************************************************************************
827 //
828 // Prototypes for the APIs.
829 //
830 //*****************************************************************************
831 //*****************************************************************************
832 //
847 //
848 //*****************************************************************************
849 static inline void
850 ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale)
851 {
852 //
853 // Set the configuration of the ADC module prescaler.
854 //
855 HW_WR_REG16(base + CSL_ADC_ADCCTL2,
856 ((HW_RD_REG16(base + CSL_ADC_ADCCTL2) &
857 ~CSL_ADC_ADCCTL2_PRESCALE_MASK) | (uint16_t)clkPrescale));
858 }
859
860 //*****************************************************************************
861 //
895 //
896 //*****************************************************************************
897 static inline void
898 ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger,
899 ADC_Channel channel, uint32_t sampleWindow)
900 {
901 uint32_t ctlRegAddr;
902
903 //
904 // Check the arguments.
905 //
906 DebugP_assert((sampleWindow >= 16U) && (sampleWindow <= 512U));
907
908 //
909 // Calculate address for the SOC control register.
910 //
911 ctlRegAddr = base + CSL_ADC_ADCSOC0CTL +
912 ((uint32_t)socNumber * ADC_ADCSOCxCTL_STEP);
913
914 //
915 // Set the configuration of the specified SOC.
916 //
917 HW_WR_REG32(ctlRegAddr,
918 (((uint32_t)channel << CSL_ADC_ADCSOC0CTL_CHSEL_SHIFT) |
919 ((uint32_t)trigger << CSL_ADC_ADCSOC0CTL_TRIGSEL_SHIFT) |
920 (sampleWindow - 1U)));
921 }
922
923 //*****************************************************************************
924 //
943 //
944 //*****************************************************************************
945 static inline void
946 ADC_selectSOCExtChannel(uint32_t base, ADC_SOCNumber socNumber,
947 uint16_t extChannel)
948 {
949 uint32_t ctlRegAddr;
950
951 //
952 // Check the arguments.
953 //
954 DebugP_assert(extChannel <= 3U);
955
956 //
957 // Calculate address for the SOC control register.
958 //
959 ctlRegAddr = base + CSL_ADC_ADCSOC0CTL +
960 ((uint32_t)socNumber * ADC_ADCSOCxCTL_STEP);
961
962 //
963 // Set the external channel configuration of the specified SOC.
964 //
965 HW_WR_REG32(ctlRegAddr,
966 ((HW_RD_REG32(ctlRegAddr) & ~((uint32_t)CSL_ADC_ADCSOC0CTL_EXTCHSEL_MASK)) |
967 ((uint32_t)extChannel << CSL_ADC_ADCSOC0CTL_EXTCHSEL_SHIFT)));
968
969 }
970
971 //*****************************************************************************
972 //
984 //
985 //*****************************************************************************
986 static inline void
987 ADC_forceRepeaterTrigger(uint32_t base, uint16_t repInstance)
988 {
989 uint32_t regOffset;
990
991 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
992
993 //
994 // Triggers the selected repeater instance
995 //
996 HW_WR_REG16(regOffset + CSL_ADC_REP1FRC,
997 ((HW_RD_REG16(regOffset + CSL_ADC_REP1FRC) |
998 CSL_ADC_REP1FRC_SWFRC_MASK)));
999
1000 }
1001
1002 //*****************************************************************************
1003 //
1014 //
1015 //*****************************************************************************
1016 static inline uint16_t
1017 ADC_getRepeaterStatus(uint32_t base, uint16_t repInstance)
1018 {
1019 uint32_t regOffset;
1020
1021 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
1022
1023 //
1024 // Return the status of repeater.
1025 //
1026 return(HW_RD_REG16(regOffset + CSL_ADC_REP1CTL) & ADC_REPSTATUS_MASK);
1027 }
1028
1029 //*****************************************************************************
1030 //
1054 //
1055 //*****************************************************************************
1056 static inline void
1057 ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber,
1058 ADC_IntSOCTrigger trigger)
1059 {
1060 uint16_t shiftVal;
1061
1062 //
1063 // Each SOC has a 2-bit field in this register.
1064 //
1065 shiftVal = (uint16_t)socNumber << 1U;
1066
1067 //
1068 // Set the configuration of the specified SOC. Note that we're treating
1069 // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here.
1070 //
1071 HW_WR_REG32(base + CSL_ADC_ADCINTSOCSEL1,
1072 ((HW_RD_REG32(base + CSL_ADC_ADCINTSOCSEL1) &
1073 ~((uint32_t)CSL_ADC_ADCINTSOCSEL1_SOC0_MASK << shiftVal)) |
1074 ((uint32_t)trigger << shiftVal)));
1075 }
1076
1077 //*****************************************************************************
1078 //
1092 //
1093 //*****************************************************************************
1094 static inline void
1095 ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode)
1096 {
1097 //
1098 // Set the position of the pulse.
1099 //
1100 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1101 ((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
1102 ~CSL_ADC_ADCCTL1_INTPULSEPOS_MASK) |
1103 ((uint16_t)pulseMode<<CSL_ADC_ADCCTL1_INTPULSEPOS_SHIFT)));
1104 }
1105
1106 //*****************************************************************************
1107 //
1123 //
1124 //*****************************************************************************
1125 static inline void
1126 ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset)
1127 {
1128 //
1129 // Set the position of the pulse.
1130 //
1131 HW_WR_REG16(base + CSL_ADC_ADCINTCYCLE, cycleOffset);
1132 }
1133
1134 //*****************************************************************************
1135 //
1145 //
1146 //*****************************************************************************
1147 static inline void
1148 ADC_enableAltDMATiming(uint32_t base)
1149 {
1150
1151 //
1152 // Enable the Alternate DMA timings wherein DMA is triggered
1153 // at tDMA.
1154 //
1155 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1156 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) | CSL_ADC_ADCCTL1_TDMAEN_MASK));
1157 }
1158
1159 //*****************************************************************************
1160 //
1169 //
1170 //*****************************************************************************
1171 static inline void
1172 ADC_disableAltDMATiming(uint32_t base)
1173 {
1174
1175 //
1176 // Disable the Alternate DMA timings wherein DMA is triggered at the same
1177 // time as CPU interrupt.
1178 //
1179 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1180 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) & ~CSL_ADC_ADCCTL1_TDMAEN_MASK));
1181 }
1182
1183 //*****************************************************************************
1184 //
1196 //
1197 //*****************************************************************************
1198 static inline void
1199 ADC_enableExtMuxPreselect(uint32_t base)
1200 {
1201
1202 //
1203 // Enable the external mux selection at the end of S+H window of
1204 // previous conversion.
1205 //
1206 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1207 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) |
1208 CSL_ADC_ADCCTL1_EXTMUXPRESELECTEN_MASK));
1209 }
1210
1211 //*****************************************************************************
1212 //
1222 //
1223 //*****************************************************************************
1224 static inline void
1225 ADC_disableExtMuxPreselect(uint32_t base)
1226 {
1227
1228 //
1229 // Enable the external mux selection at the beginning of S+H window of
1230 // current conversion.
1231 //
1232 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1233 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
1234 ~CSL_ADC_ADCCTL1_EXTMUXPRESELECTEN_MASK));
1235 }
1236
1237 //*****************************************************************************
1238 //
1254 //
1255 //*****************************************************************************
1256 static inline void
1257 ADC_selectOffsetTrimMode(uint32_t base, ADC_OffsetTrim mode)
1258 {
1259
1260 //
1261 // Enable the external mux selection at the end of S+H window of
1262 // previous conversion.
1263 //
1264 HW_WR_REG16(base + CSL_ADC_ADCCTL2,
1265 ((HW_RD_REG16(base + CSL_ADC_ADCCTL2) &
1266 ~CSL_ADC_ADCCTL2_OFFTRIMMODE_MASK) | (uint16_t)mode));
1267 }
1268
1269 //*****************************************************************************
1270 //
1286 //
1287 //*****************************************************************************
1288 static inline bool
1289 ADC_getIntResultStatus(uint32_t base, ADC_IntNumber adcIntNum)
1290 {
1291
1292 //
1293 // Get the specified ADC interrupt result ready status.
1294 //
1295 return((HW_RD_REG16(base + CSL_ADC_ADCINTFLG) &
1296 (1U << ((uint16_t)adcIntNum + 4U))) != 0U);
1297
1298 }
1299
1300 //*****************************************************************************
1301 //
1313 //
1314 //*****************************************************************************
1315 static inline void
1316 ADC_enableConverter(uint32_t base)
1317 {
1318 //
1319 // Set the bit that powers up the analog circuitry.
1320 //
1321 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1322 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) | CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
1323 }
1324
1325 //*****************************************************************************
1326 //
1334 //
1335 //*****************************************************************************
1336 static inline void
1337 ADC_disableConverter(uint32_t base)
1338 {
1339 //
1340 // Clear the bit that powers down the analog circuitry.
1341 //
1342 HW_WR_REG16(base + CSL_ADC_ADCCTL1,
1343 (HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
1344 ~CSL_ADC_ADCCTL1_ADCPWDNZ_MASK));
1345 }
1346
1347 //*****************************************************************************
1348 //
1360 //
1361 //*****************************************************************************
1362 static inline void
1363 ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber)
1364 {
1365 //
1366 // Write to the register that will force a 1 to the corresponding SOC flag
1367 //
1368 HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, ((uint16_t)1U << (uint16_t)socNumber));
1369 }
1370
1371 //*****************************************************************************
1372 //
1390 //
1391 //*****************************************************************************
1392 static inline void
1393 ADC_forceMultipleSOC(uint32_t base, uint16_t socMask)
1394 {
1395 //
1396 // Write to the register that will force a 1 to desired SOCs
1397 //
1398 HW_WR_REG16(base + CSL_ADC_ADCSOCFRC1, socMask);
1399 }
1400
1401 //*****************************************************************************
1402 //
1417 //
1418 //*****************************************************************************
1419 static inline bool
1420 ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
1421 {
1422 //
1423 // Get the specified ADC interrupt status.
1424 //
1425 return((HW_RD_REG16(base + CSL_ADC_ADCINTFLG) &
1426 (1U << (uint16_t)adcIntNum)) != 0U);
1427 }
1428
1429 //*****************************************************************************
1430 //
1445 //
1446 //*****************************************************************************
1447 static inline void
1448 ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
1449 {
1450 //
1451 // Clear the specified interrupt.
1452 //
1453 HW_WR_REG16(base + CSL_ADC_ADCINTFLGCLR, ((uint16_t)1U << (uint16_t)adcIntNum));
1454 }
1455
1456 //*****************************************************************************
1457 //
1473 //
1474 //*****************************************************************************
1475 static inline bool
1476 ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
1477 {
1478 //
1479 // Get the specified ADC interrupt status.
1480 //
1481 return((HW_RD_REG16(base + CSL_ADC_ADCINTOVF) &
1482 (1U << (uint16_t)adcIntNum)) != 0U);
1483 }
1484
1485 //*****************************************************************************
1486 //
1501 //
1502 //*****************************************************************************
1503 static inline void
1504 ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
1505 {
1506 //
1507 // Clear the specified interrupt overflow bit.
1508 //
1509 HW_WR_REG16(base + CSL_ADC_ADCINTOVFCLR, ((uint16_t)1U << (uint16_t)adcIntNum));
1510 }
1511
1512 //*****************************************************************************
1513 //
1529 //
1530 //*****************************************************************************
1531 static inline uint16_t
1532 ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber)
1533 {
1534 //
1535 // Return the ADC result for the selected SOC.
1536 //
1537 return(HW_RD_REG16(resultBase + CSL_ADC_RESULT_ADCRESULT0 +
1538 ((uint32_t)socNumber * ADC_RESULT_ADCRESULTx_STEP)));
1539 }
1540
1541 //*****************************************************************************
1542 //
1552 //
1553 //*****************************************************************************
1554 static inline bool
1555 ADC_isBusy(uint32_t base)
1556 {
1557 //
1558 // Determine if the ADC is busy.
1559 //
1560 return((HW_RD_REG16(base + CSL_ADC_ADCCTL1) &
1561 CSL_ADC_ADCCTL1_ADCBSY_MASK) != 0U);
1562 }
1563
1564 //*****************************************************************************
1565 //
1583 //
1584 //*****************************************************************************
1585 static inline void
1586 ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize)
1587 {
1588 uint16_t regValue;
1589
1590 //
1591 // Check the arguments.
1592 //
1593 DebugP_assert(((uint32_t)trigger & ~0x7FU) == 0U);
1594 DebugP_assert((burstSize >= 1U) && (burstSize <= 16U));
1595
1596 //
1597 // Write the burst mode configuration to the register.
1598 //
1599 regValue = (uint16_t)trigger |
1600 ((burstSize - 1U) << CSL_ADC_ADCBURSTCTL_BURSTSIZE_SHIFT);
1601
1602 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
1603 ((HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
1604 ~((uint16_t)CSL_ADC_ADCBURSTCTL_BURSTTRIGSEL_MASK |
1605 CSL_ADC_ADCBURSTCTL_BURSTSIZE_MASK)) | regValue));
1606 }
1607
1608 //*****************************************************************************
1609 //
1621 //
1622 //*****************************************************************************
1623 static inline void
1624 ADC_enableBurstMode(uint32_t base)
1625 {
1626 //
1627 // Enable burst mode.
1628 //
1629 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
1630 (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) |
1631 CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
1632 }
1633
1634 //*****************************************************************************
1635 //
1645 //
1646 //*****************************************************************************
1647 static inline void
1648 ADC_disableBurstMode(uint32_t base)
1649 {
1650 //
1651 // Disable burst mode.
1652 //
1653 HW_WR_REG16(base + CSL_ADC_ADCBURSTCTL,
1654 (HW_RD_REG16(base + CSL_ADC_ADCBURSTCTL) &
1655 ~CSL_ADC_ADCBURSTCTL_BURSTEN_MASK));
1656 }
1657
1658 //*****************************************************************************
1659 //
1683 //
1684 //*****************************************************************************
1685 static inline void
1686 ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode)
1687 {
1688 //
1689 // Set SOC priority
1690 //
1691 HW_WR_REG16(base + CSL_ADC_ADCSOCPRICTL,
1692 ((HW_RD_REG16(base + CSL_ADC_ADCSOCPRICTL) &
1693 ~CSL_ADC_ADCSOCPRICTL_SOCPRIORITY_MASK) | (uint16_t)priMode));
1694 }
1695
1696 //*****************************************************************************
1697 //
1706 //
1707 //*****************************************************************************
1708 static inline void
1709 ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal)
1710 {
1711 //
1712 // Configure open/shorts detection circuit mode.
1713 //
1714 HW_WR_REG16(base + CSL_ADC_ADCOSDETECT,
1715 ((HW_RD_REG16(base + CSL_ADC_ADCOSDETECT) &
1716 ~CSL_ADC_ADCOSDETECT_DETECTCFG_MASK) | (uint16_t)modeVal));
1717 }
1718
1719 //*****************************************************************************
1720 //
1743 //
1744 //*****************************************************************************
1745 static inline void
1746 ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber)
1747 {
1748 uint32_t ppbOffset;
1749
1750 //
1751 // Get the offset to the appropriate PPB configuration register.
1752 //
1753 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
1754 CSL_ADC_ADCPPB1CONFIG;
1755
1756 //
1757 // Write the configuration to the register.
1758 //
1759 HW_WR_REG16(base + ppbOffset,
1760 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK) |
1761 ((uint16_t)socNumber & CSL_ADC_ADCPPB1CONFIG_CONFIG_MASK)));
1762 }
1763
1764 //*****************************************************************************
1765 //
1777 //
1778 //*****************************************************************************
1779 static inline void
1780 ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
1781 {
1782 //
1783 // Check the arguments.
1784 //
1785 DebugP_assert((evtFlags & ~0x7U) == 0U);
1786
1787 //
1788 // Enable the specified event.
1789 //
1790 HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
1791 (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) |
1792 (evtFlags << ((uint16_t)ppbNumber * 4U))));
1793 }
1794
1795 //*****************************************************************************
1796 //
1807 //
1808 //*****************************************************************************
1809 static inline void
1810 ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
1811 {
1812 //
1813 // Check the arguments.
1814 //
1815 DebugP_assert((evtFlags & ~0x7U) == 0U);
1816
1817 //
1818 // Disable the specified event.
1819 //
1820 HW_WR_REG16(base + CSL_ADC_ADCEVTSEL,
1821 (HW_RD_REG16(base + CSL_ADC_ADCEVTSEL) &
1822 ~(evtFlags << ((uint16_t)ppbNumber * 4U))));
1823 }
1824
1825 //*****************************************************************************
1826 //
1838 //
1839 //*****************************************************************************
1840 static inline void
1841 ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
1842 uint16_t intFlags)
1843 {
1844 //
1845 // Check the arguments.
1846 //
1847 DebugP_assert((intFlags & ~0x7U) == 0U);
1848
1849 //
1850 // Enable the specified event interrupts.
1851 //
1852 HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
1853 (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) |
1854 (intFlags << ((uint16_t)ppbNumber * 4U))));
1855 }
1856
1857 //*****************************************************************************
1858 //
1870 //
1871 //*****************************************************************************
1872 static inline void
1873 ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber,
1874 uint16_t intFlags)
1875 {
1876 //
1877 // Check the arguments.
1878 //
1879 DebugP_assert((intFlags & ~0x7U) == 0U);
1880
1881 //
1882 // Disable the specified event interrupts.
1883 //
1884 HW_WR_REG16(base + CSL_ADC_ADCEVTINTSEL,
1885 (HW_RD_REG16(base + CSL_ADC_ADCEVTINTSEL) &
1886 ~(intFlags << ((uint16_t)ppbNumber * 4U))));
1887 }
1888
1889 //*****************************************************************************
1890 //
1899 //
1900 //*****************************************************************************
1901 static inline uint16_t
1902 ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber)
1903 {
1904 //
1905 // Get the event status for the specified post-processing block.
1906 //
1907 return((HW_RD_REG16(base + CSL_ADC_ADCEVTSTAT) >>
1908 ((uint16_t)ppbNumber * 4U)) & 0x7U);
1909 }
1910
1911 //*****************************************************************************
1912 //
1924 //
1925 //*****************************************************************************
1926 static inline void
1927 ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber,
1928 uint16_t evtFlags)
1929 {
1930 //
1931 // Check the arguments.
1932 //
1933 DebugP_assert((evtFlags & ~0x7U) == 0U);
1934
1935 //
1936 // Clear the specified event interrupts.
1937 //
1938 HW_WR_REG16(base + CSL_ADC_ADCEVTCLR,
1939 (HW_RD_REG16(base + CSL_ADC_ADCEVTCLR) |
1940 (evtFlags << ((uint16_t)ppbNumber * 4U))));
1941 }
1942
1943 //*****************************************************************************
1944 //
1956 //
1957 //*****************************************************************************
1958 static inline void
1959 ADC_enablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
1960 {
1961 uint32_t ppbOffset;
1962
1963 //
1964 // Get the offset to the appropriate PPB configuration register.
1965 //
1966 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
1967 CSL_ADC_ADCPPB1CONFIG;
1968
1969 //
1970 // Set automatic cycle-by-cycle flag clear bit
1971 //
1972 HW_WR_REG16(base + ppbOffset,
1973 (HW_RD_REG16(base + ppbOffset) | CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
1974 }
1975
1976 //*****************************************************************************
1977 //
1988 //
1989 //*****************************************************************************
1990 static inline void
1991 ADC_disablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
1992 {
1993 uint32_t ppbOffset;
1994
1995 //
1996 // Get the offset to the appropriate PPB configuration register.
1997 //
1998 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
1999 CSL_ADC_ADCPPB1CONFIG;
2000
2001 //
2002 // Clear automatic cycle-by-cycle flag clear bit
2003 //
2004 HW_WR_REG16(base + ppbOffset,
2005 (HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_CBCEN_MASK));
2006 }
2007
2008 //*****************************************************************************
2009 //
2021 //
2022 //*****************************************************************************
2023 static inline void
2024 ADC_setPPBCountLimit(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t limit)
2025 {
2026 uint32_t ppbOffset;
2027
2028 //
2029 // Check the arguments.
2030 //
2031 DebugP_assert(limit <= CSL_ADC_ADCPPB1LIMIT_LIMIT_MAX);
2032
2033 //
2034 // Get the offset to the appropriate PPB configuration register.
2035 //
2036 ppbOffset = (ADC_ADCPPBxLIMIT_STEP * (uint32_t)ppbNumber) +
2037 CSL_ADC_ADCPPB1LIMIT;
2038
2039 //
2040 // Enable PPB two's complement.
2041 //
2042 HW_WR_REG16(base + ppbOffset,
2043 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1LIMIT_LIMIT_MASK) |
2044 (limit << CSL_ADC_ADCPPB1LIMIT_LIMIT_SHIFT)));
2045
2046 }
2047
2048 //*****************************************************************************
2049 //
2060 //
2061 //*****************************************************************************
2062 static inline uint16_t
2063 ADC_getPPBCountLimit(uint32_t base, ADC_PPBNumber ppbNumber)
2064 {
2065 uint16_t limit;
2066 uint32_t ppbOffset;
2067
2068 //
2069 // Get the offset to the appropriate PPB configuration register.
2070 //
2071 ppbOffset = (ADC_ADCPPBxLIMIT_STEP * (uint32_t)ppbNumber) +
2072 CSL_ADC_ADCPPB1LIMIT;
2073
2074 limit = (HW_RD_REG16(base + ppbOffset) &
2075 ~(CSL_ADC_ADCPPB1LIMIT_LIMIT_MASK)) >> CSL_ADC_ADCPPB1LIMIT_LIMIT_SHIFT;
2076 return(limit);
2077 }
2078
2079 //*****************************************************************************
2080 //
2090 //
2091 //*****************************************************************************
2092 static inline uint16_t
2093 ADC_readPPBPCount(uint32_t base, ADC_PPBNumber ppbNumber)
2094 {
2095
2096 //
2097 // Returns the partial count of the selected PPB.
2098 //
2099 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPBP1PCOUNT +
2100 ((uint32_t)ppbNumber * ADC_ADCPPBxPCOUNT_STEP)));
2101 }
2102
2103 //*****************************************************************************
2104 //
2115 //
2116 //*****************************************************************************
2117 static inline int32_t
2118 ADC_readPPBPSum(uint32_t base, ADC_PPBNumber ppbNumber)
2119 {
2120
2121 //
2122 // Returns the partial sum result of selected PPB.
2123 //
2124 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPB1PSUM +
2125 ((uint32_t)ppbNumber * ADC_ADCPPBxPSUM_STEP)));
2126 }
2127
2128 //*****************************************************************************
2129 //
2139 //
2140 //*****************************************************************************
2141 static inline int32_t
2142 ADC_readPPBPMax(uint32_t base, ADC_PPBNumber ppbNumber)
2143 {
2144
2145 //
2146 // Return the partial maximum value of selected PPB.
2147 //
2148 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPB1PMAX +
2149 ((uint32_t)ppbNumber * ADC_ADCPPBxPMAX_STEP)));
2150 }
2151
2152 //*****************************************************************************
2153 //
2163 //
2164 //*****************************************************************************
2165 static inline int32_t
2166 ADC_readPPBPMin(uint32_t base, ADC_PPBNumber ppbNumber)
2167 {
2168
2169 //
2170 // Return the partial minimum value of selected PPB.
2171 //
2172 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPB1PMIN +
2173 ((uint32_t)ppbNumber * ADC_ADCPPBxPMIN_STEP)));
2174 }
2175
2176 //*****************************************************************************
2177 //
2188 //
2189 //*****************************************************************************
2190 static inline uint16_t
2191 ADC_readPPBPMaxIndex(uint32_t base, ADC_PPBNumber ppbNumber)
2192 {
2193
2194 //
2195 // Returns the index of the partial maximum value of selected PPB.
2196 //
2197 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPB1PMAXI +
2198 ((uint32_t)ppbNumber * ADC_ADCPPBxPMAXI_STEP)));
2199 }
2200
2201 //*****************************************************************************
2202 //
2213 //
2214 //*****************************************************************************
2215 static inline uint16_t
2216 ADC_readPPBPMinIndex(uint32_t base, ADC_PPBNumber ppbNumber)
2217 {
2218
2219 //
2220 // Returns the index of the partial minimum value of selected PPB.
2221 //
2222 return(HW_RD_REG32(base + (uint32_t)CSL_ADC_ADCPPB1PMINI +
2223 ((uint32_t)ppbNumber * ADC_ADCPPBxPMINI_STEP)));
2224 }
2225
2226 //*****************************************************************************
2227 //
2240 //
2241 //*****************************************************************************
2242 static inline void
2243 ADC_enablePPBAbsoluteValue(uint32_t base, ADC_PPBNumber ppbNumber)
2244 {
2245 uint32_t ppbOffset;
2246
2247 //
2248 // Get the offset to the appropriate PPB configuration register.
2249 //
2250 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2251 CSL_ADC_ADCPPB1CONFIG;
2252
2253 //
2254 // Enable PPB absolute value.
2255 //
2256 HW_WR_REG16(base + ppbOffset,
2257 (HW_RD_REG16(base + ppbOffset) | CSL_ADC_ADCPPB1CONFIG_ABSEN_MASK));
2258 }
2259
2260 //*****************************************************************************
2261 //
2274 //
2275 //*****************************************************************************
2276 static inline void
2277 ADC_disablePPBAbsoluteValue(uint32_t base, ADC_PPBNumber ppbNumber)
2278 {
2279 uint32_t ppbOffset;
2280
2281 //
2282 // Get the offset to the appropriate PPB configuration register.
2283 //
2284 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2285 CSL_ADC_ADCPPB1CONFIG;
2286
2287 //
2288 // Disable PPB abosulte value.
2289 //
2290 HW_WR_REG16(base + ppbOffset,
2291 (HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG_ABSEN_MASK));
2292 }
2293
2294 //*****************************************************************************
2295 //
2307 //
2308 //*****************************************************************************
2309 static inline void
2310 ADC_setPPBShiftValue(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t shiftVal)
2311 {
2312 uint32_t ppbOffset;
2313
2314 //
2315 // Check the arguments.
2316 //
2317 DebugP_assert(shiftVal <= 10U);
2318
2319 //
2320 // Get the offset to the appropriate PPB configuration register.
2321 //
2322 ppbOffset = (ADC_ADCPPBxCONFIG2_STEP * (uint32_t)ppbNumber) +
2323 CSL_ADC_ADCPPB1CONFIG2;
2324
2325 //
2326 // Configure shift value for the PPB.
2327 //
2328 HW_WR_REG16(base + ppbOffset,
2329 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG2_SHIFT_MASK) |
2330 (shiftVal << CSL_ADC_ADCPPB1CONFIG2_SHIFT_SHIFT)));
2331
2332 }
2333
2334 //*****************************************************************************
2335 //
2348 //
2349 //*****************************************************************************
2350 static inline void
2351 ADC_selectPPBSyncInput(uint32_t base, ADC_PPBNumber ppbNumber,
2352 uint16_t syncInput)
2353 {
2354 uint32_t ppbOffset;
2355
2356 //
2357 // Get the offset to the appropriate PPB configuration register.
2358 //
2359 ppbOffset = (ADC_ADCPPBxCONFIG2_STEP * (uint32_t)ppbNumber) +
2360 CSL_ADC_ADCPPB1CONFIG2;
2361
2362 //
2363 // Select sync input for the PPB.
2364 //
2365 HW_WR_REG16(base + ppbOffset,
2366 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG2_SYNCINSEL_MASK) |
2367 (syncInput << CSL_ADC_ADCPPB1CONFIG2_SYNCINSEL_SHIFT)));
2368
2369 }
2370
2371 //*****************************************************************************
2372 //
2381 //
2382 //*****************************************************************************
2383 static inline void
2384 ADC_forcePPBSync(uint32_t base, ADC_PPBNumber ppbNumber)
2385 {
2386 uint32_t ppbOffset;
2387
2388 //
2389 // Get the offset to the appropriate PPB configuration register.
2390 //
2391 ppbOffset = (ADC_ADCPPBxCONFIG2_STEP * (uint32_t)ppbNumber) +
2392 CSL_ADC_ADCPPB1CONFIG2;
2393
2394 //
2395 // Force software sync for the PPB.
2396 //
2397 HW_WR_REG16(base + ppbOffset,
2398 (HW_RD_REG16(base + ppbOffset) | CSL_ADC_ADCPPB1CONFIG2_SWSYNC_MASK));
2399
2400 }
2401
2402 //*****************************************************************************
2403 //
2416 //*****************************************************************************
2417 static inline void
2418 ADC_selectPPBOSINTSource(uint32_t base, ADC_PPBNumber ppbNumber,
2419 uint16_t osIntSrc)
2420 {
2421 uint32_t ppbOffset;
2422
2423 //
2424 // Check the arguments.
2425 //
2426 DebugP_assert(osIntSrc <= 1U);
2427
2428 //
2429 // Get the offset to the appropriate PPB configuration register.
2430 //
2431 ppbOffset = (ADC_ADCPPBxCONFIG2_STEP * (uint32_t)ppbNumber) +
2432 CSL_ADC_ADCPPB1CONFIG2;
2433
2434 //
2435 // Select PPB OSINT source.
2436 //
2437 HW_WR_REG16(base + ppbOffset,
2438 ((HW_RD_REG16(base + ppbOffset) &
2439 ~CSL_ADC_ADCPPB1CONFIG2_OSINTSEL_MASK) |
2440 (osIntSrc << CSL_ADC_ADCPPB1CONFIG2_OSINTSEL_SHIFT)));
2441
2442 }
2443
2444 //*****************************************************************************
2445 //
2458 //
2459 //*****************************************************************************
2460 static inline void
2461 ADC_selectPPBCompareSource(uint32_t base, ADC_PPBNumber ppbNumber,
2462 uint16_t compSrc)
2463 {
2464 uint32_t ppbOffset;
2465
2466 //
2467 // Check the arguments.
2468 //
2469 DebugP_assert(compSrc <= 2U);
2470
2471 //
2472 // Get the offset to the appropriate PPB configuration register.
2473 //
2474 ppbOffset = (ADC_ADCPPBxCONFIG2_STEP * (uint32_t)ppbNumber) +
2475 CSL_ADC_ADCPPB1CONFIG2;
2476
2477 //
2478 // Select PPB compare source..
2479 //
2480 HW_WR_REG16(base + ppbOffset,
2481 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1CONFIG2_COMPSEL_MASK) |
2482 (compSrc << CSL_ADC_ADCPPB1CONFIG2_COMPSEL_SHIFT)));
2483
2484 }
2485
2486 //*****************************************************************************
2487 //
2501 //
2502 //*****************************************************************************
2503 static inline int32_t
2504 ADC_readPPBSum(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2505 {
2506
2507 //
2508 // Return the result of selected PPB.
2509 //
2510 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1SUM +
2511 ((uint32_t)ppbNumber * 8UL)));
2512
2513 }
2514
2515 //*****************************************************************************
2516 //
2530 //
2531 //*****************************************************************************
2532 static inline uint32_t
2533 ADC_readPPBCount(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2534 {
2535
2536 //
2537 // Return the final count of selected PPB.
2538 //
2539 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1COUNT +
2540 ((uint32_t)ppbNumber * 8UL)));
2541
2542 }
2543
2544 //*****************************************************************************
2545 //
2559 //
2560 //*****************************************************************************
2561 static inline int32_t
2562 ADC_readPPBMax(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2563 {
2564
2565 //
2566 // Return the final maximum value of selected PPB.
2567 //
2568 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1MAX +
2569 ((uint32_t)ppbNumber * 16UL)));
2570
2571 }
2572
2573 //*****************************************************************************
2574 //
2588 //
2589 //*****************************************************************************
2590 static inline int32_t
2591 ADC_readPPBMin(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2592 {
2593
2594 //
2595 // Return the final minimum value of selected PPB.
2596 //
2597 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1MIN +
2598 ((uint32_t)ppbNumber * 16UL)));
2599
2600 }
2601
2602 //*****************************************************************************
2603 //
2617 //
2618 //*****************************************************************************
2619 static inline uint16_t
2620 ADC_readPPBMaxIndex(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2621 {
2622
2623 //
2624 // Returns the index of the final maximum value of selected PPB.
2625 //
2626 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1MAXI +
2627 ((uint32_t)ppbNumber * 16UL)));
2628
2629 }
2630
2631 //*****************************************************************************
2632 //
2646 //
2647 //*****************************************************************************
2648 static inline uint16_t
2649 ADC_readPPBMinIndex(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2650 {
2651
2652 //
2653 // Returns the index of the final minimum value of the selected PPB.
2654 //
2655 return(HW_RD_REG32(resultBase + (uint32_t)CSL_ADC_RESULT_ADCPPB1MINI +
2656 ((uint32_t)ppbNumber * 16UL)));
2657
2658 }
2659
2660 //*****************************************************************************
2661 //
2675 //
2676 //*****************************************************************************
2677 static inline int32_t
2678 ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber)
2679 {
2680 //
2681 // Return the result of selected PPB.
2682 //
2683 return((int32_t)HW_RD_REG32(resultBase + CSL_ADC_RESULT_ADCPPB1RESULT +
2684 ((uint32_t)ppbNumber * ADC_RESULT_ADCPPBxRESULT_STEP)));
2685 }
2686
2687 //*****************************************************************************
2688 //
2699 //
2700 //*****************************************************************************
2701 static inline uint16_t
2702 ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber)
2703 {
2704 uint32_t ppbOffset;
2705
2706 //
2707 // Get the offset to the appropriate delay.
2708 //
2709 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2710 CSL_ADC_ADCPPB1STAMP;
2711
2712 //
2713 // Return the delay time stamp.
2714 //
2715 return(HW_RD_REG16(base + ppbOffset) & CSL_ADC_ADCPPB1STAMP_DLYSTAMP_MASK);
2716 }
2717
2718 //*****************************************************************************
2719 //
2742 //
2743 //*****************************************************************************
2744 static inline void
2745 ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber,
2746 int16_t offset)
2747 {
2748 uint32_t ppbOffset;
2749
2750 //
2751 // Get the offset to the appropriate offset register.
2752 //
2753 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2754 CSL_ADC_ADCPPB1OFFCAL;
2755
2756 //
2757 // Write the offset amount.
2758 //
2759 HW_WR_REG16(base + ppbOffset,
2760 ((HW_RD_REG16(base + ppbOffset) & ~CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK) |
2761 ((uint16_t)offset & CSL_ADC_ADCPPB1OFFCAL_OFFCAL_MASK)));
2762 }
2763
2764 //*****************************************************************************
2765 //
2785 //
2786 //*****************************************************************************
2787 static inline void
2788 ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber,
2789 uint16_t offset)
2790 {
2791 uint32_t ppbOffset;
2792
2793 //
2794 // Get the offset to the appropriate offset register.
2795 //
2796 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2797 CSL_ADC_ADCPPB1OFFREF;
2798
2799 //
2800 // Write the offset amount.
2801 //
2802 HW_WR_REG16(base + ppbOffset, offset);
2803 }
2804
2805 //*****************************************************************************
2806 //
2820 //
2821 //*****************************************************************************
2822 static inline void
2823 ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
2824 {
2825 uint32_t ppbOffset;
2826
2827 //
2828 // Get the offset to the appropriate PPB configuration register.
2829 //
2830 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2831 CSL_ADC_ADCPPB1CONFIG;
2832
2833 //
2834 // Enable the twos complement
2835 //
2836 HW_WR_REG16(base + ppbOffset,
2837 (HW_RD_REG16(base + ppbOffset) |
2838 CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
2839 }
2840
2841 //*****************************************************************************
2842 //
2856 //
2857 //*****************************************************************************
2858 static inline void
2859 ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
2860 {
2861 uint32_t ppbOffset;
2862
2863 //
2864 // Get the offset to the appropriate PPB configuration register.
2865 //
2866 ppbOffset = (ADC_ADCPPBx_STEP * (uint32_t)ppbNumber) +
2867 CSL_ADC_ADCPPB1CONFIG;
2868
2869 //
2870 // Disable the twos complement
2871 //
2872 HW_WR_REG16(base + ppbOffset,
2873 (HW_RD_REG16(base + ppbOffset) &
2874 ~CSL_ADC_ADCPPB1CONFIG_TWOSCOMPEN_MASK));
2875 }
2876
2877 //*****************************************************************************
2878 //
2888 //
2889 //*****************************************************************************
2890 static inline void
2891 ADC_enablePPBExtendedLowLimit(uint32_t base, ADC_PPBNumber ppbNumber)
2892 {
2893 uint32_t ppbLoOffset;
2894
2895 //
2896 // Get the offset to the appropriate trip limit registers.
2897 //
2898 ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) +
2899 CSL_ADC_ADCPPB1TRIPLO;
2900
2901 //
2902 // Enable PPB extended low limit.
2903 //
2904 HW_WR_REG32(base + ppbLoOffset,
2905 (HW_RD_REG32(base + ppbLoOffset) | CSL_ADC_ADCPPB1TRIPLO_LIMITLO2EN_MASK));
2906
2907 }
2908
2909 //*****************************************************************************
2910 //
2920 //
2921 //*****************************************************************************
2922 static inline void
2923 ADC_disablePPBExtendedLowLimit(uint32_t base, ADC_PPBNumber ppbNumber)
2924 {
2925 uint32_t ppbOffset;
2926
2927 //
2928 // Get the offset to the appropriate PPB configuration register.
2929 //
2930 ppbOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) +
2931 CSL_ADC_ADCPPB1TRIPLO;
2932
2933 //
2934 // Disable PPB extended low limit.
2935 //
2936 HW_WR_REG32(base + ppbOffset,
2937 (HW_RD_REG32(base + ppbOffset) &
2938 ~CSL_ADC_ADCPPB1TRIPLO_LIMITLO2EN_MASK));
2939
2940 }
2941
2942 //*****************************************************************************
2943 //
2958 //
2959 //*****************************************************************************
2960 static inline void
2961 ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
2962 {
2963 uint32_t intRegAddr;
2964 uint16_t shiftVal;
2965
2966 //
2967 // Each INTSEL register manages two interrupts. If the interrupt number is
2968 // even, we'll be accessing the upper byte and will need to shift.
2969 //
2970 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
2971 (((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP);
2972 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
2973
2974 //
2975 // Enable the specified ADC interrupt.
2976 //
2977 HW_WR_REG16(intRegAddr,
2978 HW_RD_REG16(intRegAddr) |
2979 (CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
2980 }
2981
2982 //*****************************************************************************
2983 //
2998 //
2999 //*****************************************************************************
3000 static inline void
3001 ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
3002 {
3003 uint32_t intRegAddr;
3004 uint16_t shiftVal;
3005
3006 //
3007 // Each INTSEL register manages two interrupts. If the interrupt number is
3008 // even, we'll be accessing the upper byte and will need to shift.
3009 //
3010 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
3011 (((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP);
3012 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
3013
3014 //
3015 // Disable the specified ADC interrupt.
3016 //
3017 HW_WR_REG16(intRegAddr,
3018 HW_RD_REG16(intRegAddr) &
3019 ~(CSL_ADC_ADCINTSEL1N2_INT1E_MASK << shiftVal));
3020 }
3021
3022 //*****************************************************************************
3023 //
3041 //
3042 //*****************************************************************************
3043 static inline void
3044 ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum,
3045 uint16_t intTrigger)
3046 {
3047 uint32_t intRegAddr;
3048 uint16_t shiftVal;
3049
3050 //
3051 // Each INTSEL register manages two interrupts. If the interrupt number is
3052 // even, we'll be accessing the upper byte and will need to shift.
3053 //
3054 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
3055 (((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP);
3056 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
3057
3058 //
3059 // Set the specified ADC interrupt source.
3060 //
3061 HW_WR_REG16(intRegAddr,
3062 ((HW_RD_REG16(intRegAddr) &
3063 ~(CSL_ADC_ADCINTSEL1N2_INT1SEL_MASK << shiftVal)) |
3064 ((uint16_t)intTrigger << shiftVal)));
3065 }
3066
3067 //*****************************************************************************
3068 //
3084 //
3085 //*****************************************************************************
3086 static inline void
3087 ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
3088 {
3089 uint32_t intRegAddr;
3090 uint16_t shiftVal;
3091
3092 //
3093 // Each INTSEL register manages two interrupts. If the interrupt number is
3094 // even, we'll be accessing the upper byte and will need to shift.
3095 //
3096 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
3097 (((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP);
3098 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
3099
3100 //
3101 // Enable continuous mode for the specified ADC interrupt.
3102 //
3103 HW_WR_REG16(intRegAddr,
3104 HW_RD_REG16(intRegAddr) |
3105 (CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
3106 }
3107
3108 //*****************************************************************************
3109 //
3126 //
3127 //*****************************************************************************
3128 static inline void
3129 ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
3130 {
3131 uint32_t intRegAddr;
3132 uint16_t shiftVal;
3133
3134 //
3135 // Each INTSEL register manages two interrupts. If the interrupt number is
3136 // even, we'll be accessing the upper byte and will need to shift.
3137 //
3138 intRegAddr = base + CSL_ADC_ADCINTSEL1N2 +
3139 (((uint32_t)adcIntNum >> 1) * ADC_ADCINTSELxNy_STEP);
3140 shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U;
3141
3142 //
3143 // Disable continuous mode for the specified ADC interrupt.
3144 //
3145 HW_WR_REG16(intRegAddr,
3146 HW_RD_REG16(intRegAddr) &
3147 ~(CSL_ADC_ADCINTSEL1N2_INT1CONT_MASK << shiftVal));
3148 }
3149
3150 //*****************************************************************************
3151 //
3168 //
3169 //*****************************************************************************
3170 static inline void
3171 ADC_configSOCSafetyCheckerInput(uint32_t base, ADC_SOCNumber socNumber,
3172 ADC_SafetyCheckerInput scInput)
3173 {
3174 uint32_t socShift;
3175
3176 //
3177 // Calculate the SOC shift.
3178 //
3179 socShift = ((uint32_t)socNumber * 2U);
3180
3181 //
3182 // Configure the Safety Checker Result mode.
3183 //
3184 HW_WR_REG32(base + CSL_ADC_ADCSAFECHECKRESEN,
3185 ((HW_RD_REG32(base + CSL_ADC_ADCSAFECHECKRESEN) &
3186 ~(CSL_ADC_ADCSAFECHECKRESEN_SOC0CHKEN_MASK << socShift)) |
3187 ((uint32_t)scInput << socShift)));
3188 }
3189
3190 //*****************************************************************************
3191 //
3199 //
3200 //*****************************************************************************
3201 static inline void
3202 ADC_enableSafetyChecker(uint32_t scBase)
3203 {
3204
3205 //
3206 // Enable the Saftey Checker module
3207 //
3208 HW_WR_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG,
3209 (HW_RD_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG) |
3210 CSL_ADC_SAFETY_CHECKCONFIG_CHKEN_MASK));
3211 }
3212
3213 //*****************************************************************************
3214 //
3222 //
3223 //*****************************************************************************
3224 static inline void
3225 ADC_disableSafetyChecker(uint32_t scBase)
3226 {
3227
3228 //
3229 // Disable the Saftey Checker module.
3230 //
3231 HW_WR_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG,
3232 (HW_RD_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG) &
3233 ~CSL_ADC_SAFETY_CHECKCONFIG_CHKEN_MASK));
3234 }
3235
3236 //*****************************************************************************
3237 //
3245 //
3246 //*****************************************************************************
3247 static inline void
3248 ADC_forceSafetyCheckerSync(uint32_t scBase)
3249 {
3250
3251 //
3252 // Force software sync for the safety checker module.
3253 //
3254 HW_WR_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG,
3255 (HW_RD_REG16(scBase + CSL_ADC_SAFETY_CHECKCONFIG) |
3256 CSL_ADC_SAFETY_CHECKCONFIG_SWSYNC_MASK));
3257 }
3258
3259 //*****************************************************************************
3260 //
3273 //
3274 //*****************************************************************************
3275 static inline uint16_t
3276 ADC_getSafetyCheckerStatus(uint32_t scBase)
3277 {
3278
3279 //
3280 // Returns Safety Checker module status
3281 //
3282 return(HW_RD_REG16(scBase + CSL_ADC_SAFETY_CHECKSTATUS) &
3283 ADC_SAFECHECK_STATUS_MASK);
3284 }
3285
3286 //*****************************************************************************
3287 //
3304 //
3305 //*****************************************************************************
3306 static inline void
3307 ADC_configureSafetyChecker(uint32_t scBase, ADC_SafetyCheckInst checkInst,
3308 ADC_Select adcInst, ADC_ResultSelect adcResultInst)
3309 {
3310
3311 //
3312 // Configure safety checker instance
3313 //
3314 HW_WR_REG16(scBase + CSL_ADC_SAFETY_ADCRESSEL1 + ((uint16_t)checkInst),
3315 ((HW_RD_REG16(scBase + CSL_ADC_SAFETY_ADCRESSEL1 + ((uint16_t)checkInst)) &
3316 ~(CSL_ADC_SAFETY_ADCRESSEL1_ADCSEL_MASK |
3317 CSL_ADC_SAFETY_ADCRESSEL1_ADCRESULTSEL_MASK)) |
3318 ((uint16_t)adcInst << CSL_ADC_SAFETY_ADCRESSEL1_ADCSEL_SHIFT) |
3319 ((uint16_t)adcResultInst << CSL_ADC_SAFETY_ADCRESSEL1_ADCRESULTSEL_SHIFT)));
3320
3321 }
3322
3323 //*****************************************************************************
3324 //
3334 //
3335 //*****************************************************************************
3336 static inline void
3337 ADC_setSafetyCheckerTolerance(uint32_t scBase, uint32_t tolerance)
3338 {
3339 //
3340 // Check the arguments.
3341 //
3342 DebugP_assert(tolerance <= CSL_ADC_SAFETY_TOLERANCE_TOLERANCE_MASK);
3343
3344 //
3345 // Set safety checker tolerance
3346 //
3347 HW_WR_REG32(scBase + CSL_ADC_SAFETY_TOLERANCE,
3348 (tolerance & CSL_ADC_SAFETY_TOLERANCE_TOLERANCE_MASK));
3349 }
3350
3351 //*****************************************************************************
3352 //
3366 //
3367 //*****************************************************************************
3368 static inline uint32_t
3369 ADC_getSafetyCheckerResult(uint32_t scBase, ADC_SafetyCheckInst checkInst)
3370 {
3371
3372 //
3373 // Returns the safety check result for the selected instance
3374 //
3375 return(HW_RD_REG32(scBase + CSL_ADC_SAFETY_CHECKRESULT1 +
3376 (uint16_t)checkInst) & CSL_ADC_SAFETY_CHECKRESULT1_RESULT_MASK);
3377
3378 }
3379
3380 //*****************************************************************************
3381 //
3407 //
3408 //*****************************************************************************
3409 static inline void
3410 ADC_enableSafetyCheckEvt(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3411 ADC_SafetyCheckEvent checkEvent, ADC_SafetyCheckResult checkResult)
3412 {
3413
3414 //
3415 // Enables the safety checker event source.
3416 //
3417 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKEVT1SEL1 +
3418 (uint32_t)checkEvent + (uint32_t)checkResult,
3419 (HW_RD_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKEVT1SEL1 +
3420 (uint32_t)checkEvent + (uint32_t)checkResult) |
3421 (1UL << (uint32_t)checkerNumber)));
3422
3423 }
3424
3425 //*****************************************************************************
3426 //
3452 //
3453 //*****************************************************************************
3454 static inline void
3455 ADC_disableSafetyCheckEvt(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3456 ADC_SafetyCheckEvent checkEvent, ADC_SafetyCheckResult checkResult)
3457 {
3458
3459 //
3460 // Disables the safety checker event source.
3461 //
3462 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKEVT1SEL1 +
3463 (uint32_t)checkEvent + (uint32_t)checkResult,
3464 (HW_RD_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKEVT1SEL1 +
3465 (uint32_t)checkEvent + (uint32_t)checkResult) &
3466 ~(1UL << (uint32_t)checkerNumber)));
3467
3468 }
3469
3470 //*****************************************************************************
3471 //
3492 //
3493 //*****************************************************************************
3494 static inline void
3495 ADC_enableSafetyCheckInt(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3496 ADC_SafetyCheckResult checkResult)
3497 {
3498
3499 //
3500 // Enables the safety checker interrupt source.
3501 //
3502 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKINTSEL1 +
3503 (uint32_t)checkResult,(HW_RD_REG32(scIntEvtBase +
3504 CSL_ADC_SAFETY_AGGR_CHECKINTSEL1 + (uint32_t)checkResult) |
3505 (1UL << (uint32_t)checkerNumber)));
3506
3507 }
3508
3509 //*****************************************************************************
3510 //
3531 //
3532 //*****************************************************************************
3533 static inline void
3534 ADC_disableSafetyCheckInt(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3535 ADC_SafetyCheckResult checkResult)
3536 {
3537
3538 //
3539 // Enables the safety checker interrupt source.
3540 //
3541 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKINTSEL1 +
3542 (uint32_t)checkResult,(HW_RD_REG32(scIntEvtBase +
3543 CSL_ADC_SAFETY_AGGR_CHECKINTSEL1 + (uint32_t)checkResult) &
3544 ~(1UL << (uint32_t)checkerNumber)));
3545
3546 }
3547
3548 //*****************************************************************************
3549 //
3571 //
3572 //*****************************************************************************
3573 static inline bool
3574 ADC_getSafetyCheckStatus(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3575 ADC_SafetyCheckFlag checkerFlag)
3576 {
3577
3578 //
3579 // Get the specified safety checker event status.
3580 //
3581 return(HW_RD_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_OOTFLG +
3582 (uint32_t)checkerFlag) & (1U << (uint32_t)checkerNumber));
3583
3584 }
3585
3586 //*****************************************************************************
3587 //
3607 //
3608 //*****************************************************************************
3609 static inline void
3610 ADC_clearSafetyCheckStatus(uint32_t scIntEvtBase, ADC_Checker checkerNumber,
3611 ADC_SafetyCheckFlag checkerFlag)
3612 {
3613
3614 //
3615 // Clear the specified safety checker event status.
3616 //
3617 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_OOTFLGCLR +
3618 (uint32_t)checkerFlag, (1UL << (uint32_t)checkerNumber));
3619
3620 }
3621
3622 //*****************************************************************************
3623 //
3632 //
3633 //*****************************************************************************
3634 static inline uint32_t
3635 ADC_getSafetyCheckIntStatus(uint32_t scIntEvtBase)
3636 {
3637
3638 //
3639 // Get the specified safety checker interrupt status.
3640 //
3641 return(HW_RD_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKINTFLG));
3642
3643 }
3644
3645 //*****************************************************************************
3646 //
3655 //
3656 //*****************************************************************************
3657 static inline void
3658 ADC_clearSafetyCheckIntStatus(uint32_t scIntEvtBase)
3659 {
3660
3661 //
3662 // Clear the specified safety checker interrupt status.
3663 //
3664 HW_WR_REG32(scIntEvtBase + CSL_ADC_SAFETY_AGGR_CHECKINTFLGCLR, 1U);
3665
3666 }
3667
3668 //*****************************************************************************
3669 //
3683 //
3684 //*****************************************************************************
3685 static inline void
3686 ADC_triggerRepeaterMode(uint32_t base, uint32_t repInstance, ADC_RepMode mode)
3687 {
3688 uint32_t regOffset;
3689
3690 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3691
3692 //
3693 // Set the specified repeater trigger source to modify.
3694 //
3695 HW_WR_REG32(regOffset + CSL_ADC_REP1CTL,
3696 ((HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) &
3697 ~CSL_ADC_REP1CTL_MODE_MASK) | (uint32_t)mode));
3698
3699 }
3700
3701 //*****************************************************************************
3702 //
3715 //
3716 //*****************************************************************************
3717 static inline bool
3718 ADC_triggerRepeaterActiveMode(uint32_t base, uint32_t repInstance)
3719 {
3720 uint32_t regOffset;
3721
3722 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3723
3724 //
3725 // get the specified repeater trigger active mode status.
3726 //
3727 return(HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) &
3728 (1U << CSL_ADC_REP1CTL_ACTIVEMODE_SHIFT));
3729
3730 }
3731
3732 //*****************************************************************************
3733 //
3746 //
3747 //*****************************************************************************
3748 static inline bool
3749 ADC_triggerRepeaterModuleBusy(uint32_t base, uint32_t repInstance)
3750 {
3751 uint32_t regOffset;
3752
3753 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3754
3755 //
3756 // get the specified repeater trigger active mode status.
3757 //
3758 return(HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) &
3759 (1U << CSL_ADC_REP1CTL_MODULEBUSY_SHIFT));
3760
3761 }
3762
3763 //*****************************************************************************
3764 //
3778 //
3779 //*****************************************************************************
3780 static inline void
3781 ADC_triggerRepeaterSelect(uint32_t base, uint16_t repInstance,
3782 ADC_Trigger trigger)
3783 {
3784 uint32_t regOffset;
3785
3786 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3787
3788 //
3789 // Set the specified repeater trigger source to modify.
3790 //
3791 HW_WR_REG32(regOffset + CSL_ADC_REP1CTL,
3792 ((HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) &
3793 ~CSL_ADC_REP1CTL_TRIGGER_MASK) |
3794 ((uint32_t)trigger << CSL_ADC_REP1CTL_TRIGGER_SHIFT)));
3795
3796 }
3797
3798 //*****************************************************************************
3799 //
3814 //
3815 //*****************************************************************************
3816 static inline void
3817 ADC_triggerRepeaterSyncIn(uint32_t base, uint16_t repInstance,
3818 ADC_SyncInput syncInput)
3819 {
3820 uint32_t regOffset;
3821
3822 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3823
3824 //
3825 // Set the specified trigger sync input.
3826 //
3827 HW_WR_REG32(regOffset + CSL_ADC_REP1CTL,
3828 ((HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) &
3829 ~CSL_ADC_REP1CTL_SYNCINSEL_MASK) |
3830 ((uint32_t)syncInput << CSL_ADC_REP1CTL_SYNCINSEL_SHIFT)));
3831
3832 }
3833
3834 //*****************************************************************************
3835 //
3848 //
3849 //*****************************************************************************
3850 static inline void
3851 ADC_forceRepeaterTriggerSync(uint32_t base, uint16_t repInstance)
3852 {
3853 uint32_t regOffset;
3854
3855 regOffset = base + (repInstance * (ADC_REPxCTL_STEP));
3856
3857 //
3858 // Force software sync for the trigger repeater block.
3859 //
3860 HW_WR_REG32(regOffset + CSL_ADC_REP1CTL,
3861 (HW_RD_REG32(regOffset + CSL_ADC_REP1CTL) |
3862 CSL_ADC_REP1CTL_SWSYNC_MASK));
3863
3864 }
3865
3866 //*****************************************************************************
3867 //
3890 //
3891 //*****************************************************************************
3892 static inline void
3893 ADC_triggerRepeaterCount(uint32_t base, uint16_t repInstance,
3894 uint16_t repCount)
3895 {
3896 uint32_t regOffset;
3897 //
3898 // Check the arguments.
3899 //
3900 DebugP_assert(repCount <= 127U);
3901
3902 regOffset = base + (repInstance * (ADC_REPxN_STEP));
3903
3904 //
3905 // Configure repeater count.
3906 //
3907 HW_WR_REG32(regOffset + CSL_ADC_REP1N,
3908 ((HW_RD_REG32(regOffset + CSL_ADC_REP1N) &
3909 ~CSL_ADC_REP1N_NSEL_MASK) | repCount));
3910
3911 }
3912
3913 //*****************************************************************************
3914 //
3932 //
3933 //*****************************************************************************
3934 static inline void
3935 ADC_triggerRepeaterPhase(uint32_t base, uint16_t repInstance,
3936 uint16_t repPhase)
3937 {
3938 uint32_t regOffset;
3939
3940 regOffset = base + (repInstance * (ADC_REPxPHASE_STEP));
3941
3942 //
3943 // Configure repeater phase.
3944 //
3945 HW_WR_REG32(regOffset + CSL_ADC_REP1PHASE,
3946 ((HW_RD_REG32(regOffset + CSL_ADC_REP1PHASE) &
3947 ~CSL_ADC_REP1PHASE_PHASE_MASK) | repPhase));
3948
3949 }
3950
3951 //*****************************************************************************
3952 //
3970 //
3971 //*****************************************************************************
3972 static inline void
3973 ADC_triggerRepeaterSpread(uint32_t base, uint16_t repInstance,
3974 uint16_t repSpread)
3975 {
3976 uint32_t regOffset;
3977
3978 regOffset = base + (repInstance * (ADC_REPxSPREAD_STEP));
3979
3980 //
3981 // Configure repeater spread.
3982 //
3983 HW_WR_REG32(regOffset + CSL_ADC_REP1SPREAD,
3984 ((HW_RD_REG32(regOffset + CSL_ADC_REP1SPREAD) &
3985 ~CSL_ADC_REP1SPREAD_SPREAD_MASK) | repSpread));
3986
3987 }
3988
3989 //
4009 //
4010 //*****************************************************************************
4011 extern void
4012 ADC_setMode(uint32_t base, ADC_Resolution resolution,
4013 ADC_SignalMode signalMode);
4014
4015 //*****************************************************************************
4016 //
4035 //
4036 //*****************************************************************************
4037 extern void
4038 ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber,
4039 int32_t tripHiLimit, int32_t tripLoLimit);
4040
4041 //*****************************************************************************
4042 //
4043 // Close the Doxygen group.
4045 //
4046 //*****************************************************************************
4047
4048 //*****************************************************************************
4049 //
4050 // Mark the end of the C bindings section for C++ compilers.
4051 //
4052 //*****************************************************************************
4053 #ifdef __cplusplus
4054 }
4055 #endif
4056
4057 #endif // ADC_V1_H_
ADC_SOC_NUMBER7
@ ADC_SOC_NUMBER7
SOC/EOC number 7.
Definition: adc/v2/adc.h:416
ADC_Resolution
ADC_Resolution
Definition: adc/v2/adc.h:204
ADC_SOC_NUMBER15
@ ADC_SOC_NUMBER15
SOC/EOC number 15.
Definition: adc/v2/adc.h:424
ADC_SAFETY_CHECKER_INPUT_SOCx
@ ADC_SAFETY_CHECKER_INPUT_SOCx
Safety checker i/p is SOCx.
Definition: adc/v2/adc.h:682
ADC_SYNCIN_EPWM22SYNCOUT
@ ADC_SYNCIN_EPWM22SYNCOUT
ADC Syncin is EPWM22SYNCOUT.
Definition: adc/v2/adc.h:532
ADC_SOC_NUMBER9
@ ADC_SOC_NUMBER9
SOC/EOC number 9.
Definition: adc/v2/adc.h:418
ADC_forceRepeaterTriggerSync
static void ADC_forceRepeaterTriggerSync(uint32_t base, uint16_t repInstance)
Definition: adc/v2/adc.h:3851
ADC_getSafetyCheckStatus
static bool ADC_getSafetyCheckStatus(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckFlag checkerFlag)
Definition: adc/v2/adc.h:3574
ADC_CH_ADCIN3_ADCIN2
@ ADC_CH_ADCIN3_ADCIN2
differential, ADCIN3 and ADCIN2
Definition: adc/v2/adc.h:344
ADC_TRIGGER_EPWM26_SOCA
@ ADC_TRIGGER_EPWM26_SOCA
ePWM26, ADCSOCA
Definition: adc/v2/adc.h:287
ADC_SYNCIN_EPWM12SYNCOUT
@ ADC_SYNCIN_EPWM12SYNCOUT
ADC Syncin is EPWM12SYNCOUT.
Definition: adc/v2/adc.h:522
ADC_SYNCIN_ECAP15SYNCOUT
@ ADC_SYNCIN_ECAP15SYNCOUT
ADC Syncin is ECAP15SYNCOUT.
Definition: adc/v2/adc.h:557
ADC_RepeaterConfig::repMode
ADC_RepMode repMode
Repeater Mode.
Definition: adc/v2/adc.h:797
ADC_TRIGGER_EPWM3_SOCA
@ ADC_TRIGGER_EPWM3_SOCA
ePWM3, ADCSOCA
Definition: adc/v2/adc.h:241
ADC_RESULT_ADCPPBxRESULT_STEP
#define ADC_RESULT_ADCPPBxRESULT_STEP
Register offset difference between 2 ADCPPBxRESULT registers.
Definition: adc/v2/adc.h:820
ADC_enableExtMuxPreselect
static void ADC_enableExtMuxPreselect(uint32_t base)
Definition: adc/v2/adc.h:1199
ADC_CLK_DIV_2_0
@ ADC_CLK_DIV_2_0
ADCCLK = (input clock) / 2.0.
Definition: adc/v2/adc.h:181
ADC_disablePPBEventInterrupt
static void ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags)
Definition: adc/v2/adc.h:1873
ADC_TRIGGER_EPWM14_SOCB
@ ADC_TRIGGER_EPWM14_SOCB
ePWM14, ADCSOCB
Definition: adc/v2/adc.h:264
ADC_OffsetTrim
ADC_OffsetTrim
Definition: adc/v2/adc.h:500
ADC_SYNCIN_EPWM2SYNCOUT
@ ADC_SYNCIN_EPWM2SYNCOUT
ADC Syncin is EPWM2SYNCOUT.
Definition: adc/v2/adc.h:512
ADC_RepeaterConfig::repCount
uint16_t repCount
Repeater trigger count.
Definition: adc/v2/adc.h:800
ADC_disablePPBTwosComplement
static void ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2859
ADC_ClkPrescale
ADC_ClkPrescale
Definition: adc/v2/adc.h:179
ADC_SYNCIN_INPUTXBAROUTPUT6
@ ADC_SYNCIN_INPUTXBAROUTPUT6
ADC Syncin is INPUTXBAROUTPUT6.
Definition: adc/v2/adc.h:558
ADC_RepInstance
ADC_RepInstance
Definition: adc/v2/adc.h:772
ADC_INT_NUMBER3
@ ADC_INT_NUMBER3
ADCINT3 Interrupt.
Definition: adc/v2/adc.h:380
ADC_OSDETECT_MODE_DISABLED
@ ADC_OSDETECT_MODE_DISABLED
Definition: adc/v2/adc.h:475
ADC_TRIGGER_ECAP8_SOCEVT
@ ADC_TRIGGER_ECAP8_SOCEVT
eCAP8, SOCEVT
Definition: adc/v2/adc.h:307
ADC_RESULT8
@ ADC_RESULT8
Select ADC Result 8.
Definition: adc/v2/adc.h:663
ADC_TRIGGER_EPWM24_SOCA
@ ADC_TRIGGER_EPWM24_SOCA
ePWM24, ADCSOCA
Definition: adc/v2/adc.h:283
ADC_CH_ADCIN2
@ ADC_CH_ADCIN2
single-ended, ADCIN2
Definition: adc/v2/adc.h:334
ADC_TRIGGER_EPWM23_SOCA
@ ADC_TRIGGER_EPWM23_SOCA
ePWM23, ADCSOCA
Definition: adc/v2/adc.h:281
ADC_SYNCIN_EPWM18SYNCOUT
@ ADC_SYNCIN_EPWM18SYNCOUT
ADC Syncin is EPWM18SYNCOUT.
Definition: adc/v2/adc.h:528
ADC_TRIGGER_EPWM11_SOCB
@ ADC_TRIGGER_EPWM11_SOCB
ePWM11, ADCSOCB
Definition: adc/v2/adc.h:258
ADC_disablePPBAbsoluteValue
static void ADC_disablePPBAbsoluteValue(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2277
ADC_ADCPPBxPCOUNT_STEP
#define ADC_ADCPPBxPCOUNT_STEP
Definition: adc/v2/adc.h:109
ADC_SYNCIN_EPWM11SYNCOUT
@ ADC_SYNCIN_EPWM11SYNCOUT
ADC Syncin is EPWM11SYNCOUT.
Definition: adc/v2/adc.h:521
ADC_CH_CAL1_CAL0
@ ADC_CH_CAL1_CAL0
differential, CAL1 and CAL0 Note : Not Valid for AM261x
Definition: adc/v2/adc.h:348
ADC_getPPBEventStatus
static uint16_t ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:1902
ADC_PULSE_END_OF_CONV
@ ADC_PULSE_END_OF_CONV
Occurs at the end of the conversion.
Definition: adc/v2/adc.h:364
ADC_clearInterruptOverflowStatus
static void ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:1504
ADC_REPINST2
@ ADC_REPINST2
Select ADC repeater instance 2.
Definition: adc/v2/adc.h:774
ADC_enableBurstMode
static void ADC_enableBurstMode(uint32_t base)
Definition: adc/v2/adc.h:1624
ADC_CH_ADCIN0
@ ADC_CH_ADCIN0
single-ended, ADCIN0
Definition: adc/v2/adc.h:332
ADC_3
@ ADC_3
Select ADC3 instance.
Definition: adc/v2/adc.h:643
ADC_SYNCIN_ECAP12SYNCOUT
@ ADC_SYNCIN_ECAP12SYNCOUT
ADC Syncin is ECAP12SYNCOUT.
Definition: adc/v2/adc.h:554
ADC_INT_TRIGGER_EOC9
@ ADC_INT_TRIGGER_EOC9
SOC/EOC9.
Definition: adc/v2/adc.h:606
ADC_PPB_OS_INT_1
@ ADC_PPB_OS_INT_1
PCount generates PPB interrupt.
Definition: adc/v2/adc.h:571
ADC_REPSTATUS_MASK
#define ADC_REPSTATUS_MASK
Definition: adc/v2/adc.h:124
ADC_SOC_NUMBER8
@ ADC_SOC_NUMBER8
SOC/EOC number 8.
Definition: adc/v2/adc.h:417
ADC_TRIGGER_EPWM9_SOCB
@ ADC_TRIGGER_EPWM9_SOCB
ePWM9, ADCSOCB
Definition: adc/v2/adc.h:254
ADC_TRIGGER_EPWM16_SOCA
@ ADC_TRIGGER_EPWM16_SOCA
ePWM16, ADCSOCA
Definition: adc/v2/adc.h:267
ADC_SAFETY_CHECK_EVENT3
@ ADC_SAFETY_CHECK_EVENT3
Safety Check Event 3.
Definition: adc/v2/adc.h:709
ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA
@ ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA
Definition: adc/v2/adc.h:485
ADC_SafetyCheckerInput
ADC_SafetyCheckerInput
Definition: adc/v2/adc.h:680
ADC_SOC_NUMBER1
@ ADC_SOC_NUMBER1
SOC/EOC number 1.
Definition: adc/v2/adc.h:410
ADC_PRI_THRU_SOC5_HIPRI
@ ADC_PRI_THRU_SOC5_HIPRI
SOC 0-5 hi pri, others in round robin.
Definition: adc/v2/adc.h:454
ADC_disablePPBEvent
static void ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v2/adc.h:1810
ADC_1
@ ADC_1
Select ADC1 instance.
Definition: adc/v2/adc.h:641
ADC_SYNCIN_EPWM7SYNCOUT
@ ADC_SYNCIN_EPWM7SYNCOUT
ADC Syncin is EPWM7SYNCOUT.
Definition: adc/v2/adc.h:517
ADC_INT_SOC_TRIGGER_ADCINT1
@ ADC_INT_SOC_TRIGGER_ADCINT1
ADCINT1 will trigger the SOC.
Definition: adc/v2/adc.h:436
ADC_getSafetyCheckIntStatus
static uint32_t ADC_getSafetyCheckIntStatus(uint32_t scIntEvtBase)
Definition: adc/v2/adc.h:3635
ADC_readPPBMinIndex
static uint16_t ADC_readPPBMinIndex(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2649
ADC_RESULT4
@ ADC_RESULT4
Select ADC Result 4.
Definition: adc/v2/adc.h:659
ADC_TRIGGER_EPWM2_SOCB
@ ADC_TRIGGER_EPWM2_SOCB
ePWM2, ADCSOCB
Definition: adc/v2/adc.h:240
ADC_INT_NUMBER4
@ ADC_INT_NUMBER4
ADCINT4 Interrupt.
Definition: adc/v2/adc.h:381
ADC_TRIGGER_EPWM27_SOCA
@ ADC_TRIGGER_EPWM27_SOCA
ePWM27, ADCSOCA
Definition: adc/v2/adc.h:289
ADC_OSDETECT_MODE_VSSA
@ ADC_OSDETECT_MODE_VSSA
Definition: adc/v2/adc.h:477
ADC_TRIGGER_REPEATER1
@ ADC_TRIGGER_REPEATER1
Repeater 1.
Definition: adc/v2/adc.h:319
ADC_SOC_NUMBER11
@ ADC_SOC_NUMBER11
SOC/EOC number 11.
Definition: adc/v2/adc.h:420
ADC_readPPBMaxIndex
static uint16_t ADC_readPPBMaxIndex(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2620
ADC_ADCINTSELxNy_STEP
#define ADC_ADCINTSELxNy_STEP
Register offset difference between 2 ADCINTSELxNy registers.
Definition: adc/v2/adc.h:813
ADC_INT_SOC_TRIGGER_NONE
@ ADC_INT_SOC_TRIGGER_NONE
No ADCINT will trigger the SOC.
Definition: adc/v2/adc.h:435
ADC_SYNCIN_DISABLE
@ ADC_SYNCIN_DISABLE
ADC Syncin is disabled.
Definition: adc/v2/adc.h:509
ADC_SAFETY_CHECK_EVENT2
@ ADC_SAFETY_CHECK_EVENT2
Safety Check Event 2.
Definition: adc/v2/adc.h:708
ADC_REPINST1
@ ADC_REPINST1
Select ADC repeater instance 1.
Definition: adc/v2/adc.h:773
ADC_SAFETY_CHECK_OOT_FLG
@ ADC_SAFETY_CHECK_OOT_FLG
Safety Check Out-of-Tolerance Flag.
Definition: adc/v2/adc.h:760
ADC_PRI_THRU_SOC14_HIPRI
@ ADC_PRI_THRU_SOC14_HIPRI
SOC 0-14 hi pri, SOC15 in round robin.
Definition: adc/v2/adc.h:463
ADC_getSafetyCheckerResult
static uint32_t ADC_getSafetyCheckerResult(uint32_t scBase, ADC_SafetyCheckInst checkInst)
Definition: adc/v2/adc.h:3369
ADC_MODE_SINGLE_ENDED
@ ADC_MODE_SINGLE_ENDED
Sample on single pin with VREFLO.
Definition: adc/v2/adc.h:216
ADC_TRIGGER_EPWM28_SOCA
@ ADC_TRIGGER_EPWM28_SOCA
ePWM28, ADCSOCA
Definition: adc/v2/adc.h:291
ADC_TRIGGER_EPWM6_SOCB
@ ADC_TRIGGER_EPWM6_SOCB
ePWM6, ADCSOCB
Definition: adc/v2/adc.h:248
ADC_TRIGGER_EPWM12_SOCB
@ ADC_TRIGGER_EPWM12_SOCB
ePWM12, ADCSOCB
Definition: adc/v2/adc.h:260
ADC_INT_TRIGGER_EOC12
@ ADC_INT_TRIGGER_EOC12
SOC/EOC12.
Definition: adc/v2/adc.h:609
ADC_INT_TRIGGER_OSINT2
@ ADC_INT_TRIGGER_OSINT2
OSINT2.
Definition: adc/v2/adc.h:614
ADC_TRIGGER_EPWM4_SOCA
@ ADC_TRIGGER_EPWM4_SOCA
ePWM4, ADCSOCA
Definition: adc/v2/adc.h:243
ADC_setSafetyCheckerTolerance
static void ADC_setSafetyCheckerTolerance(uint32_t scBase, uint32_t tolerance)
Definition: adc/v2/adc.h:3337
ADC_forceMultipleSOC
static void ADC_forceMultipleSOC(uint32_t base, uint16_t socMask)
Definition: adc/v2/adc.h:1393
ADC_CLK_DIV_4_0
@ ADC_CLK_DIV_4_0
ADCCLK = (input clock) / 4.0.
Definition: adc/v2/adc.h:185
ADC_TRIGGER_ECAP11_SOCEVT
@ ADC_TRIGGER_ECAP11_SOCEVT
eCAP11, SOCEVT
Definition: adc/v2/adc.h:310
ADC_PPBIntSrcSelect
ADC_PPBIntSrcSelect
Definition: adc/v2/adc.h:570
ADC_PulseMode
ADC_PulseMode
Definition: adc/v2/adc.h:360
ADC_INT_TRIGGER_EOC8
@ ADC_INT_TRIGGER_EOC8
SOC/EOC8.
Definition: adc/v2/adc.h:605
ADC_PPBCompSource
ADC_PPBCompSource
Definition: adc/v2/adc.h:626
ADC_TRIGGER_EPWM29_SOCB
@ ADC_TRIGGER_EPWM29_SOCB
ePWM29, ADCSOCB
Definition: adc/v2/adc.h:294
ADC_TRIGGER_ECAP3_SOCEVT
@ ADC_TRIGGER_ECAP3_SOCEVT
eCAP3, SOCEVT
Definition: adc/v2/adc.h:302
ADC_configOSDetectMode
static void ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal)
Definition: adc/v2/adc.h:1709
ADC_SYNCIN_EPWM8SYNCOUT
@ ADC_SYNCIN_EPWM8SYNCOUT
ADC Syncin is EPWM8SYNCOUT.
Definition: adc/v2/adc.h:518
ADC_SAFETY_CHECKER7
@ ADC_SAFETY_CHECKER7
Safety Checker7.
Definition: adc/v2/adc.h:744
ADC_ADCSOCxCTL_STEP
#define ADC_ADCSOCxCTL_STEP
Header Files.
Definition: adc/v2/adc.h:811
ADC_TRIGGER_EPWM27_SOCB
@ ADC_TRIGGER_EPWM27_SOCB
ePWM27, ADCSOCB
Definition: adc/v2/adc.h:290
ADC_RepeaterConfig::repPhase
uint16_t repPhase
Repeater trigger phase delay in sysclk cycles.
Definition: adc/v2/adc.h:801
ADC_enableSafetyChecker
static void ADC_enableSafetyChecker(uint32_t scBase)
Definition: adc/v2/adc.h:3202
ADC_CH_ADCINX_0
@ ADC_CH_ADCINX_0
ADCINX.0 is converted.
Definition: adc/v2/adc.h:583
ADC_TRIGGER_RTI7
@ ADC_TRIGGER_RTI7
RTI Timer 7.
Definition: adc/v2/adc.h:318
ADC_setInterruptPulseMode
static void ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode)
Definition: adc/v2/adc.h:1095
ADC_Select
ADC_Select
Definition: adc/v2/adc.h:639
ADC_PRI_THRU_SOC10_HIPRI
@ ADC_PRI_THRU_SOC10_HIPRI
SOC 0-10 hi pri, others in round robin.
Definition: adc/v2/adc.h:459
ADC_enablePPBExtendedLowLimit
static void ADC_enablePPBExtendedLowLimit(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2891
ADC_REPxN_STEP
#define ADC_REPxN_STEP
Definition: adc/v2/adc.h:101
ADC_SYNCIN_ECAP14SYNCOUT
@ ADC_SYNCIN_ECAP14SYNCOUT
ADC Syncin is ECAP14SYNCOUT.
Definition: adc/v2/adc.h:556
ADC_forcePPBSync
static void ADC_forcePPBSync(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2384
ADC_TRIGGER_ECAP1_SOCEVT
@ ADC_TRIGGER_ECAP1_SOCEVT
eCAP1, SOCEVT
Definition: adc/v2/adc.h:300
ADC_RESULT6
@ ADC_RESULT6
Select ADC Result 6.
Definition: adc/v2/adc.h:661
ADC_CH_ADCIN6
@ ADC_CH_ADCIN6
single-ended, ADCIN6 Note : only valid for AM261x
Definition: adc/v2/adc.h:338
ADC_TRIGGER_EPWM30_SOCB
@ ADC_TRIGGER_EPWM30_SOCB
ePWM30, ADCSOCB
Definition: adc/v2/adc.h:296
ADC_SYNCIN_EPWM23SYNCOUT
@ ADC_SYNCIN_EPWM23SYNCOUT
ADC Syncin is EPWM23SYNCOUT.
Definition: adc/v2/adc.h:533
ADC_selectPPBSyncInput
static void ADC_selectPPBSyncInput(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t syncInput)
Definition: adc/v2/adc.h:2351
ADC_RepeaterConfig::repTrigger
ADC_Trigger repTrigger
Repeater Trigger.
Definition: adc/v2/adc.h:798
ADC_INT_TRIGGER_EOC15
@ ADC_INT_TRIGGER_EOC15
SOC/EOC15.
Definition: adc/v2/adc.h:612
ADC_PRI_THRU_SOC11_HIPRI
@ ADC_PRI_THRU_SOC11_HIPRI
SOC 0-11 hi pri, others in round robin.
Definition: adc/v2/adc.h:460
ADC_PRI_THRU_SOC3_HIPRI
@ ADC_PRI_THRU_SOC3_HIPRI
SOC 0-3 hi pri, others in round robin.
Definition: adc/v2/adc.h:452
ADC_SAFETY_CHECK_RES2OVF_FLG
@ ADC_SAFETY_CHECK_RES2OVF_FLG
Safety Check Result2 Overflow Flag.
Definition: adc/v2/adc.h:762
ADC_TRIGGER_ECAP13_SOCEVT
@ ADC_TRIGGER_ECAP13_SOCEVT
eCAP13, SOCEVT
Definition: adc/v2/adc.h:312
ADC_Trigger
ADC_Trigger
Definition: adc/v2/adc.h:228
ADC_CLK_DIV_5_0
@ ADC_CLK_DIV_5_0
ADCCLK = (input clock) / 5.0.
Definition: adc/v2/adc.h:187
ADC_PRI_THRU_SOC4_HIPRI
@ ADC_PRI_THRU_SOC4_HIPRI
SOC 0-4 hi pri, others in round robin.
Definition: adc/v2/adc.h:453
ADC_INT_TRIGGER_EOC1
@ ADC_INT_TRIGGER_EOC1
SOC/EOC1.
Definition: adc/v2/adc.h:598
ADC_INT_TRIGGER_OSINT1
@ ADC_INT_TRIGGER_OSINT1
OSINT1.
Definition: adc/v2/adc.h:613
ADC_TRIGGER_ECAP15_SOCEVT
@ ADC_TRIGGER_ECAP15_SOCEVT
eCAP15, SOCEVT
Definition: adc/v2/adc.h:314
ADC_SAFETY_CHECKER4
@ ADC_SAFETY_CHECKER4
Safety Checker4.
Definition: adc/v2/adc.h:741
ADC_TRIGGER_EPWM2_SOCA
@ ADC_TRIGGER_EPWM2_SOCA
ePWM2, ADCSOCA
Definition: adc/v2/adc.h:239
ADC_readPPBPMin
static int32_t ADC_readPPBPMin(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2166
ADC_INT_TRIGGER_EOC4
@ ADC_INT_TRIGGER_EOC4
SOC/EOC4.
Definition: adc/v2/adc.h:601
ADC_PRI_THRU_SOC7_HIPRI
@ ADC_PRI_THRU_SOC7_HIPRI
SOC 0-7 hi pri, others in round robin.
Definition: adc/v2/adc.h:456
ADC_IntTrigger
ADC_IntTrigger
Definition: adc/v2/adc.h:596
ADC_selectPPBOSINTSource
static void ADC_selectPPBOSINTSource(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t osIntSrc)
Definition: adc/v2/adc.h:2418
ADC_TRIGGER_EPWM31_SOCA
@ ADC_TRIGGER_EPWM31_SOCA
ePWM31, ADCSOCA
Definition: adc/v2/adc.h:297
ADC_SYNCIN_EPWM0SYNCOUT
@ ADC_SYNCIN_EPWM0SYNCOUT
ADC Syncin is EPWM0SYNCOUT.
Definition: adc/v2/adc.h:510
ADC_SOCNumber
ADC_SOCNumber
Definition: adc/v2/adc.h:408
ADC_TRIGGER_REPEATER2
@ ADC_TRIGGER_REPEATER2
Repeater 2.
Definition: adc/v2/adc.h:320
ADC_CH_ADCIN1
@ ADC_CH_ADCIN1
single-ended, ADCIN1
Definition: adc/v2/adc.h:333
ADC_setBurstModeConfig
static void ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize)
Definition: adc/v2/adc.h:1586
ADC_OSDetectMode
ADC_OSDetectMode
Definition: adc/v2/adc.h:474
ADC_enableContinuousMode
static void ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:3087
ADC_INT_NUMBER1
@ ADC_INT_NUMBER1
ADCINT1 Interrupt.
Definition: adc/v2/adc.h:378
ADC_TRIGGER_EPWM7_SOCB
@ ADC_TRIGGER_EPWM7_SOCB
ePWM7, ADCSOCB
Definition: adc/v2/adc.h:250
ADC_disableSafetyCheckEvt
static void ADC_disableSafetyCheckEvt(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckEvent checkEvent, ADC_SafetyCheckResult checkResult)
Definition: adc/v2/adc.h:3455
ADC_getIntResultStatus
static bool ADC_getIntResultStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:1289
ADC_setInterruptSOCTrigger
static void ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, ADC_IntSOCTrigger trigger)
Definition: adc/v2/adc.h:1057
ADC_CH_CAL0
@ ADC_CH_CAL0
single-ended, CAL0
Definition: adc/v2/adc.h:339
ADC_TRIGGER_RTI1
@ ADC_TRIGGER_RTI1
RTI Timer 1.
Definition: adc/v2/adc.h:231
ADC_SOC_NUMBER3
@ ADC_SOC_NUMBER3
SOC/EOC number 3.
Definition: adc/v2/adc.h:412
ADC_getInterruptStatus
static bool ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:1420
ADC_ResultSelect
ADC_ResultSelect
Definition: adc/v2/adc.h:654
ADC_getPPBDelayTimeStamp
static uint16_t ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2702
ADC_SOC_NUMBER10
@ ADC_SOC_NUMBER10
SOC/EOC number 10.
Definition: adc/v2/adc.h:419
ADC_RESULT0
@ ADC_RESULT0
Select ADC Result 0.
Definition: adc/v2/adc.h:655
ADC_SYNCIN_EPWM15SYNCOUT
@ ADC_SYNCIN_EPWM15SYNCOUT
ADC Syncin is EPWM15SYNCOUT.
Definition: adc/v2/adc.h:525
ADC_INT_TRIGGER_EOC5
@ ADC_INT_TRIGGER_EOC5
SOC/EOC5.
Definition: adc/v2/adc.h:602
ADC_SAFETY_CHECK_OOT
@ ADC_SAFETY_CHECK_OOT
Safety Check OOT.
Definition: adc/v2/adc.h:724
ADC_RepMode
ADC_RepMode
Definition: adc/v2/adc.h:784
ADC_CH_ADCIN6_CAL0
@ ADC_CH_ADCIN6_CAL0
differential, ADCIN6 and CAL0 Note : only valid for AM261x
Definition: adc/v2/adc.h:350
ADC_configureSafetyChecker
static void ADC_configureSafetyChecker(uint32_t scBase, ADC_SafetyCheckInst checkInst, ADC_Select adcInst, ADC_ResultSelect adcResultInst)
Definition: adc/v2/adc.h:3307
ADC_TRIGGER_EPWM12_SOCA
@ ADC_TRIGGER_EPWM12_SOCA
ePWM12, ADCSOCA
Definition: adc/v2/adc.h:259
ADC_SYNCIN_EPWM31SYNCOUT
@ ADC_SYNCIN_EPWM31SYNCOUT
ADC Syncin is EPWM31SYNCOUT.
Definition: adc/v2/adc.h:541
ADC_PPBxTRIPLO_STEP
#define ADC_PPBxTRIPLO_STEP
Definition: adc/v2/adc.h:107
ADC_enableAltDMATiming
static void ADC_enableAltDMATiming(uint32_t base)
Definition: adc/v2/adc.h:1148
ADC_INT_TRIGGER_OSINT3
@ ADC_INT_TRIGGER_OSINT3
OSINT3.
Definition: adc/v2/adc.h:615
ADC_TRIGGER_EPWM9_SOCA
@ ADC_TRIGGER_EPWM9_SOCA
ePWM9, ADCSOCA
Definition: adc/v2/adc.h:253
ADC_TRIGGER_EPWM15_SOCB
@ ADC_TRIGGER_EPWM15_SOCB
ePWM15, ADCSOCB
Definition: adc/v2/adc.h:266
ADC_enablePPBEvent
static void ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v2/adc.h:1780
ADC_TRIGGER_EPWM17_SOCB
@ ADC_TRIGGER_EPWM17_SOCB
ePWM17, ADCSOCB
Definition: adc/v2/adc.h:270
ADC_SYNCIN_EPWM20SYNCOUT
@ ADC_SYNCIN_EPWM20SYNCOUT
ADC Syncin is EPWM20SYNCOUT.
Definition: adc/v2/adc.h:530
ADC_OFFSET_TRIM_COMMON
@ ADC_OFFSET_TRIM_COMMON
Definition: adc/v2/adc.h:501
ADC_SAFETY_CHECK_EVENT4
@ ADC_SAFETY_CHECK_EVENT4
Safety Check Event 4.
Definition: adc/v2/adc.h:710
ADC_PRI_THRU_SOC13_HIPRI
@ ADC_PRI_THRU_SOC13_HIPRI
SOC 0-13 hi pri, others in round robin.
Definition: adc/v2/adc.h:462
ADC_CLK_DIV_7_5
@ ADC_CLK_DIV_7_5
ADCCLK = (input clock) / 7.5.
Definition: adc/v2/adc.h:192
ADC_TRIGGER_EPWM29_SOCA
@ ADC_TRIGGER_EPWM29_SOCA
ePWM29, ADCSOCA
Definition: adc/v2/adc.h:293
ADC_SYNCIN_INPUTXBAROUTPUT7
@ ADC_SYNCIN_INPUTXBAROUTPUT7
ADC Syncin is INPUTXBAROUTPUT7.
Definition: adc/v2/adc.h:559
ADC_RepeaterConfig::repSyncin
ADC_SyncInput repSyncin
Repeater Syncin.
Definition: adc/v2/adc.h:799
ADC_getRepeaterStatus
static uint16_t ADC_getRepeaterStatus(uint32_t base, uint16_t repInstance)
Definition: adc/v2/adc.h:1017
ADC_triggerRepeaterCount
static void ADC_triggerRepeaterCount(uint32_t base, uint16_t repInstance, uint16_t repCount)
Definition: adc/v2/adc.h:3893
ADC_PRI_THRU_SOC6_HIPRI
@ ADC_PRI_THRU_SOC6_HIPRI
SOC 0-6 hi pri, others in round robin.
Definition: adc/v2/adc.h:455
ADC_INT_TRIGGER_EOC13
@ ADC_INT_TRIGGER_EOC13
SOC/EOC13.
Definition: adc/v2/adc.h:610
ADC_TRIGGER_ECAP7_SOCEVT
@ ADC_TRIGGER_ECAP7_SOCEVT
eCAP7, SOCEVT
Definition: adc/v2/adc.h:306
ADC_INT_TRIGGER_EOC7
@ ADC_INT_TRIGGER_EOC7
SOC/EOC7.
Definition: adc/v2/adc.h:604
ADC_setInterruptCycleOffset
static void ADC_setInterruptCycleOffset(uint32_t base, uint16_t cycleOffset)
Definition: adc/v2/adc.h:1126
ADC_SAFETY_CHECK2
@ ADC_SAFETY_CHECK2
Safety Check Result 2.
Definition: adc/v2/adc.h:696
ADC_SYNCIN_EPWM26SYNCOUT
@ ADC_SYNCIN_EPWM26SYNCOUT
ADC Syncin is EPWM26SYNCOUT.
Definition: adc/v2/adc.h:536
ADC_setPPBCalibrationOffset
static void ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, int16_t offset)
Definition: adc/v2/adc.h:2745
ADC_RESULT9
@ ADC_RESULT9
Select ADC Result 9.
Definition: adc/v2/adc.h:664
ADC_SYNCIN_EPWM29SYNCOUT
@ ADC_SYNCIN_EPWM29SYNCOUT
ADC Syncin is EPWM29SYNCOUT.
Definition: adc/v2/adc.h:539
ADC_TRIGGER_EPWM5_SOCB
@ ADC_TRIGGER_EPWM5_SOCB
ePWM5, ADCSOCB
Definition: adc/v2/adc.h:246
ADC_CLK_DIV_6_0
@ ADC_CLK_DIV_6_0
ADCCLK = (input clock) / 6.0.
Definition: adc/v2/adc.h:189
ADC_TRIGGER_EPWM25_SOCA
@ ADC_TRIGGER_EPWM25_SOCA
ePWM25, ADCSOCA
Definition: adc/v2/adc.h:285
ADC_OSDETECT_MODE_5BY12_VDDA
@ ADC_OSDETECT_MODE_5BY12_VDDA
Definition: adc/v2/adc.h:481
ADC_disableAltDMATiming
static void ADC_disableAltDMATiming(uint32_t base)
Definition: adc/v2/adc.h:1172
ADC_PPBNumber
ADC_PPBNumber
Definition: adc/v2/adc.h:391
ADC_RESULT7
@ ADC_RESULT7
Select ADC Result 7.
Definition: adc/v2/adc.h:662
ADC_SYNCIN_ECAP5SYNCOUT
@ ADC_SYNCIN_ECAP5SYNCOUT
ADC Syncin is ECAP5SYNCOUT.
Definition: adc/v2/adc.h:547
ADC_CLK_DIV_8_5
@ ADC_CLK_DIV_8_5
ADCCLK = (input clock) / 8.5.
Definition: adc/v2/adc.h:194
ADC_SAFECHECK_STATUS_MASK
#define ADC_SAFECHECK_STATUS_MASK
Definition: adc/v2/adc.h:134
ADC_TRIGGER_EPWM22_SOCB
@ ADC_TRIGGER_EPWM22_SOCB
ePWM22, ADCSOCB
Definition: adc/v2/adc.h:280
ADC_PRI_ALL_ROUND_ROBIN
@ ADC_PRI_ALL_ROUND_ROBIN
Round robin mode is used for all.
Definition: adc/v2/adc.h:448
ADC_TRIGGER_EPWM17_SOCA
@ ADC_TRIGGER_EPWM17_SOCA
ePWM17, ADCSOCA
Definition: adc/v2/adc.h:269
ADC_INT_TRIGGER_EOC11
@ ADC_INT_TRIGGER_EOC11
SOC/EOC11.
Definition: adc/v2/adc.h:608
ADC_TRIGGER_ECAP9_SOCEVT
@ ADC_TRIGGER_ECAP9_SOCEVT
eCAP9, SOCEVT
Definition: adc/v2/adc.h:308
ADC_SOC_NUMBER0
@ ADC_SOC_NUMBER0
SOC/EOC number 0.
Definition: adc/v2/adc.h:409
ADC_IntSOCTrigger
ADC_IntSOCTrigger
Definition: adc/v2/adc.h:434
ADC_SAFETY_CHECKER12
@ ADC_SAFETY_CHECKER12
Safety Checker12.
Definition: adc/v2/adc.h:749
ADC_setMode
void ADC_setMode(uint32_t base, ADC_Resolution resolution, ADC_SignalMode signalMode)
ADC_TRIGGER_EPWM28_SOCB
@ ADC_TRIGGER_EPWM28_SOCB
ePWM28, ADCSOCB
Definition: adc/v2/adc.h:292
ADC_PPB_NUMBER3
@ ADC_PPB_NUMBER3
Post-processing block 3.
Definition: adc/v2/adc.h:394
ADC_clearInterruptStatus
static void ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:1448
ADC_readPPBMax
static int32_t ADC_readPPBMax(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2562
ADC_PriorityMode
ADC_PriorityMode
Definition: adc/v2/adc.h:447
ADC_CLK_DIV_8_0
@ ADC_CLK_DIV_8_0
ADCCLK = (input clock) / 8.0.
Definition: adc/v2/adc.h:193
ADC_PRI_THRU_SOC8_HIPRI
@ ADC_PRI_THRU_SOC8_HIPRI
SOC 0-8 hi pri, others in round robin.
Definition: adc/v2/adc.h:457
ADC_RESULT10
@ ADC_RESULT10
Select ADC Result 10.
Definition: adc/v2/adc.h:665
ADC_enablePPBAbsoluteValue
static void ADC_enablePPBAbsoluteValue(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2243
ADC_ADCPPBxLIMIT_STEP
#define ADC_ADCPPBxLIMIT_STEP
Definition: adc/v2/adc.h:108
ADC_triggerRepeaterSpread
static void ADC_triggerRepeaterSpread(uint32_t base, uint16_t repInstance, uint16_t repSpread)
Definition: adc/v2/adc.h:3973
ADC_readPPBCount
static uint32_t ADC_readPPBCount(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2533
ADC_TRIGGER_EPWM1_SOCB
@ ADC_TRIGGER_EPWM1_SOCB
ePWM1, ADCSOCB
Definition: adc/v2/adc.h:238
ADC_SYNCIN_ECAP13SYNCOUT
@ ADC_SYNCIN_ECAP13SYNCOUT
ADC Syncin is ECAP13SYNCOUT.
Definition: adc/v2/adc.h:555
ADC_SYNCIN_EPWM9SYNCOUT
@ ADC_SYNCIN_EPWM9SYNCOUT
ADC Syncin is EPWM9SYNCOUT.
Definition: adc/v2/adc.h:519
ADC_SOC_NUMBER5
@ ADC_SOC_NUMBER5
SOC/EOC number 5.
Definition: adc/v2/adc.h:414
ADC_RESULT13
@ ADC_RESULT13
Select ADC Result 13.
Definition: adc/v2/adc.h:668
ADC_PPB_OS_INT_2
@ ADC_PPB_OS_INT_2
PCount/Sync generates PPB interrupt.
Definition: adc/v2/adc.h:572
ADC_triggerRepeaterSyncIn
static void ADC_triggerRepeaterSyncIn(uint32_t base, uint16_t repInstance, ADC_SyncInput syncInput)
Definition: adc/v2/adc.h:3817
ADC_CLK_DIV_6_5
@ ADC_CLK_DIV_6_5
ADCCLK = (input clock) / 6.5.
Definition: adc/v2/adc.h:190
ADC_SafetyCheckResult
ADC_SafetyCheckResult
Definition: adc/v2/adc.h:721
ADC_INT_SOC_TRIGGER_ADCINT2
@ ADC_INT_SOC_TRIGGER_ADCINT2
ADCINT2 will trigger the SOC.
Definition: adc/v2/adc.h:437
ADC_TRIGGER_EPWM6_SOCA
@ ADC_TRIGGER_EPWM6_SOCA
ePWM6, ADCSOCA
Definition: adc/v2/adc.h:247
ADC_enableConverter
static void ADC_enableConverter(uint32_t base)
Definition: adc/v2/adc.h:1316
ADC_setPPBCountLimit
static void ADC_setPPBCountLimit(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t limit)
Definition: adc/v2/adc.h:2024
ADC_disableSafetyCheckInt
static void ADC_disableSafetyCheckInt(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckResult checkResult)
Definition: adc/v2/adc.h:3534
ADC_PPB_NUMBER4
@ ADC_PPB_NUMBER4
Post-processing block 4.
Definition: adc/v2/adc.h:395
ADC_readPPBPMaxIndex
static uint16_t ADC_readPPBPMaxIndex(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2191
ADC_TRIGGER_EPWM13_SOCB
@ ADC_TRIGGER_EPWM13_SOCB
ePWM13, ADCSOCB
Definition: adc/v2/adc.h:262
ADC_readResult
static uint16_t ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber)
Definition: adc/v2/adc.h:1532
ADC_disablePPBEventCBCClear
static void ADC_disablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:1991
ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA
@ ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA
Definition: adc/v2/adc.h:487
ADC_CH_ADCIN5_ADCIN4
@ ADC_CH_ADCIN5_ADCIN4
differential, ADCIN5 and ADCIN4
Definition: adc/v2/adc.h:346
ADC_SYNCIN_EPWM5SYNCOUT
@ ADC_SYNCIN_EPWM5SYNCOUT
ADC Syncin is EPWM5SYNCOUT.
Definition: adc/v2/adc.h:515
ADC_TRIGGER_RTI6
@ ADC_TRIGGER_RTI6
RTI Timer 6.
Definition: adc/v2/adc.h:317
ADC_TRIGGER_ECAP6_SOCEVT
@ ADC_TRIGGER_ECAP6_SOCEVT
eCAP6, SOCEVT
Definition: adc/v2/adc.h:305
ADC_SYNCIN_EPWM27SYNCOUT
@ ADC_SYNCIN_EPWM27SYNCOUT
ADC Syncin is EPWM27SYNCOUT.
Definition: adc/v2/adc.h:537
ADC_SOC_NUMBER13
@ ADC_SOC_NUMBER13
SOC/EOC number 13.
Definition: adc/v2/adc.h:422
ADC_TRIGGER_ECAP2_SOCEVT
@ ADC_TRIGGER_ECAP2_SOCEVT
eCAP2, SOCEVT
Definition: adc/v2/adc.h:301
ADC_REPMODE_UNDERSAMPLING
@ ADC_REPMODE_UNDERSAMPLING
ADC repeater mode is undersampling.
Definition: adc/v2/adc.h:786
ADC_setInterruptSource
static void ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, uint16_t intTrigger)
Definition: adc/v2/adc.h:3044
ADC_CLK_DIV_3_5
@ ADC_CLK_DIV_3_5
ADCCLK = (input clock) / 3.5.
Definition: adc/v2/adc.h:184
ADC_SyncInput
ADC_SyncInput
Definition: adc/v2/adc.h:508
ADC_SYNCIN_EPWM10SYNCOUT
@ ADC_SYNCIN_EPWM10SYNCOUT
ADC Syncin is EPWM10SYNCOUT.
Definition: adc/v2/adc.h:520
ADC_PRI_THRU_SOC9_HIPRI
@ ADC_PRI_THRU_SOC9_HIPRI
SOC 0-9 hi pri, others in round robin.
Definition: adc/v2/adc.h:458
ADC_SYNCIN_ECAP6SYNCOUT
@ ADC_SYNCIN_ECAP6SYNCOUT
ADC Syncin is ECAP6SYNCOUT.
Definition: adc/v2/adc.h:548
ADC_readPPBPMax
static int32_t ADC_readPPBPMax(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2142
ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA
@ ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA
Definition: adc/v2/adc.h:489
ADC_INT_TRIGGER_EOC6
@ ADC_INT_TRIGGER_EOC6
SOC/EOC6.
Definition: adc/v2/adc.h:603
ADC_CH_ADCIN5
@ ADC_CH_ADCIN5
single-ended, ADCIN5
Definition: adc/v2/adc.h:337
ADC_SAFETY_CHECK1
@ ADC_SAFETY_CHECK1
Safety Check Result 1.
Definition: adc/v2/adc.h:695
ADC_TRIGGER_EPWM8_SOCA
@ ADC_TRIGGER_EPWM8_SOCA
ePWM8, ADCSOCA
Definition: adc/v2/adc.h:251
ADC_TRIGGER_ECAP5_SOCEVT
@ ADC_TRIGGER_ECAP5_SOCEVT
eCAP5, SOCEVT
Definition: adc/v2/adc.h:304
ADC_SafetyCheckFlag
ADC_SafetyCheckFlag
Definition: adc/v2/adc.h:759
ADC_enablePPBTwosComplement
static void ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2823
ADC_PPB_COMPSOURCE_RESULT
@ ADC_PPB_COMPSOURCE_RESULT
PPB compare source is ADCRESULT.
Definition: adc/v2/adc.h:627
ADC_SAFETY_CHECKER10
@ ADC_SAFETY_CHECKER10
Safety Checker10.
Definition: adc/v2/adc.h:747
ADC_SYNCIN_EPWM4SYNCOUT
@ ADC_SYNCIN_EPWM4SYNCOUT
ADC Syncin is EPWM4SYNCOUT.
Definition: adc/v2/adc.h:514
ADC_disableInterrupt
static void ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:3001
ADC_RESULT14
@ ADC_RESULT14
Select ADC Result 14.
Definition: adc/v2/adc.h:669
ADC_RESOLUTION_12BIT
@ ADC_RESOLUTION_12BIT
12-bit conversion resolution
Definition: adc/v2/adc.h:205
ADC_setupPPB
static void ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber)
Definition: adc/v2/adc.h:1746
ADC_getInterruptOverflowStatus
static bool ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:1476
ADC_PRI_THRU_SOC1_HIPRI
@ ADC_PRI_THRU_SOC1_HIPRI
SOC 0-1 hi pri, others in round robin.
Definition: adc/v2/adc.h:450
ADC_TRIGGER_ECAP10_SOCEVT
@ ADC_TRIGGER_ECAP10_SOCEVT
eCAP10, SOCEVT
Definition: adc/v2/adc.h:309
ADC_TRIGGER_RTI5
@ ADC_TRIGGER_RTI5
RTI Timer 5.
Definition: adc/v2/adc.h:316
ADC_TRIGGER_EPWM15_SOCA
@ ADC_TRIGGER_EPWM15_SOCA
ePWM15, ADCSOCA
Definition: adc/v2/adc.h:265
ADC_CH_ADCINX_2
@ ADC_CH_ADCINX_2
ADCINX.2 is converted.
Definition: adc/v2/adc.h:585
ADC_forceSOC
static void ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber)
Definition: adc/v2/adc.h:1363
ADC_selectSOCExtChannel
static void ADC_selectSOCExtChannel(uint32_t base, ADC_SOCNumber socNumber, uint16_t extChannel)
Definition: adc/v2/adc.h:946
ADC_TRIGGER_RTI4
@ ADC_TRIGGER_RTI4
RTI Timer 4.
Definition: adc/v2/adc.h:315
ADC_SAFETY_CHECKER1
@ ADC_SAFETY_CHECKER1
Safety Checker1.
Definition: adc/v2/adc.h:738
ADC_TRIGGER_ECAP12_SOCEVT
@ ADC_TRIGGER_ECAP12_SOCEVT
eCAP12, SOCEVT
Definition: adc/v2/adc.h:311
ADC_MODE_DIFFERENTIAL
@ ADC_MODE_DIFFERENTIAL
Sample on pair of pins.
Definition: adc/v2/adc.h:217
ADC_TRIGGER_EPWM10_SOCB
@ ADC_TRIGGER_EPWM10_SOCB
ePWM10, ADCSOCB
Definition: adc/v2/adc.h:256
ADC_disableConverter
static void ADC_disableConverter(uint32_t base)
Definition: adc/v2/adc.h:1337
ADC_clearSafetyCheckStatus
static void ADC_clearSafetyCheckStatus(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckFlag checkerFlag)
Definition: adc/v2/adc.h:3610
ADC_configSOCSafetyCheckerInput
static void ADC_configSOCSafetyCheckerInput(uint32_t base, ADC_SOCNumber socNumber, ADC_SafetyCheckerInput scInput)
Definition: adc/v2/adc.h:3171
ADC_CH_ADCINX_1
@ ADC_CH_ADCINX_1
ADCINX.1 is converted.
Definition: adc/v2/adc.h:584
ADC_enablePPBEventInterrupt
static void ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t intFlags)
Definition: adc/v2/adc.h:1841
ADC_readPPBPCount
static uint16_t ADC_readPPBPCount(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2093
ADC_TRIGGER_ECAP14_SOCEVT
@ ADC_TRIGGER_ECAP14_SOCEVT
eCAP14, SOCEVT
Definition: adc/v2/adc.h:313
ADC_disableSafetyChecker
static void ADC_disableSafetyChecker(uint32_t scBase)
Definition: adc/v2/adc.h:3225
ADC_PPB_COMPSOURCE_SUM
@ ADC_PPB_COMPSOURCE_SUM
PPB compare source is SUM.
Definition: adc/v2/adc.h:629
ADC_TRIGGER_EPWM10_SOCA
@ ADC_TRIGGER_EPWM10_SOCA
ePWM10, ADCSOCA
Definition: adc/v2/adc.h:255
ADC_SYNCIN_ECAP11SYNCOUT
@ ADC_SYNCIN_ECAP11SYNCOUT
ADC Syncin is ECAP11SYNCOUT.
Definition: adc/v2/adc.h:553
ADC_readPPBMin
static int32_t ADC_readPPBMin(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2591
ADC_PRI_THRU_SOC12_HIPRI
@ ADC_PRI_THRU_SOC12_HIPRI
SOC 0-12 hi pri, others in round robin.
Definition: adc/v2/adc.h:461
ADC_TRIGGER_EPWM31_SOCB
@ ADC_TRIGGER_EPWM31_SOCB
ePWM31, ADCSOCB
Definition: adc/v2/adc.h:298
ADC_SAFETY_CHECK_EVENT1
@ ADC_SAFETY_CHECK_EVENT1
Safety Check Event 1.
Definition: adc/v2/adc.h:707
ADC_RESULT5
@ ADC_RESULT5
Select ADC Result 5.
Definition: adc/v2/adc.h:660
ADC_SYNCIN_EPWM19SYNCOUT
@ ADC_SYNCIN_EPWM19SYNCOUT
ADC Syncin is EPWM19SYNCOUT.
Definition: adc/v2/adc.h:529
ADC_INT_TRIGGER_EOC10
@ ADC_INT_TRIGGER_EOC10
SOC/EOC10.
Definition: adc/v2/adc.h:607
ADC_CH_ADCIN4
@ ADC_CH_ADCIN4
single-ended, ADCIN4
Definition: adc/v2/adc.h:336
ADC_CLK_DIV_7_0
@ ADC_CLK_DIV_7_0
ADCCLK = (input clock) / 7.0.
Definition: adc/v2/adc.h:191
ADC_TRIGGER_EPWM19_SOCA
@ ADC_TRIGGER_EPWM19_SOCA
ePWM19, ADCSOCA
Definition: adc/v2/adc.h:273
ADC_disableContinuousMode
static void ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:3129
ADC_SYNCIN_EPWM6SYNCOUT
@ ADC_SYNCIN_EPWM6SYNCOUT
ADC Syncin is EPWM6SYNCOUT.
Definition: adc/v2/adc.h:516
ADC_SYNCIN_EPWM17SYNCOUT
@ ADC_SYNCIN_EPWM17SYNCOUT
ADC Syncin is EPWM17SYNCOUT.
Definition: adc/v2/adc.h:527
ADC_TRIGGER_ECAP4_SOCEVT
@ ADC_TRIGGER_ECAP4_SOCEVT
eCAP4, SOCEVT
Definition: adc/v2/adc.h:303
ADC_SYNCIN_EPWM25SYNCOUT
@ ADC_SYNCIN_EPWM25SYNCOUT
ADC Syncin is EPWM25SYNCOUT.
Definition: adc/v2/adc.h:535
ADC_selectPPBCompareSource
static void ADC_selectPPBCompareSource(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t compSrc)
Definition: adc/v2/adc.h:2461
ADC_SOC_NUMBER12
@ ADC_SOC_NUMBER12
SOC/EOC number 12.
Definition: adc/v2/adc.h:421
ADC_TRIGGER_EPWM7_SOCA
@ ADC_TRIGGER_EPWM7_SOCA
ePWM7, ADCSOCA
Definition: adc/v2/adc.h:249
ADC_SAFETY_CHECKER_INPUT_DISABLE
@ ADC_SAFETY_CHECKER_INPUT_DISABLE
Safety checker i/p disabled.
Definition: adc/v2/adc.h:681
ADC_TRIGGER_EPWM16_SOCB
@ ADC_TRIGGER_EPWM16_SOCB
ePWM16, ADCSOCB
Definition: adc/v2/adc.h:268
ADC_setPrescaler
static void ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale)
Definition: adc/v2/adc.h:850
ADC_SOC_NUMBER14
@ ADC_SOC_NUMBER14
SOC/EOC number 14.
Definition: adc/v2/adc.h:423
ADC_TRIGGER_EPWM30_SOCA
@ ADC_TRIGGER_EPWM30_SOCA
ePWM30, ADCSOCA
Definition: adc/v2/adc.h:295
ADC_PRI_THRU_SOC2_HIPRI
@ ADC_PRI_THRU_SOC2_HIPRI
SOC 0-2 hi pri, others in round robin.
Definition: adc/v2/adc.h:451
ADC_REPMODE_OVERSAMPLING
@ ADC_REPMODE_OVERSAMPLING
ADC repeater mode is oversampling.
Definition: adc/v2/adc.h:785
ADC_SYNCIN_EPWM30SYNCOUT
@ ADC_SYNCIN_EPWM30SYNCOUT
ADC Syncin is EPWM30SYNCOUT.
Definition: adc/v2/adc.h:540
ADC_INT_NUMBER2
@ ADC_INT_NUMBER2
ADCINT2 Interrupt.
Definition: adc/v2/adc.h:379
ADC_ADCPPBxPSUM_STEP
#define ADC_ADCPPBxPSUM_STEP
Definition: adc/v2/adc.h:111
ADC_SAFETY_CHECK_RES2OVF
@ ADC_SAFETY_CHECK_RES2OVF
Safety Check Result2 Overflow.
Definition: adc/v2/adc.h:723
ADC_SYNCIN_ECAP3SYNCOUT
@ ADC_SYNCIN_ECAP3SYNCOUT
ADC Syncin is ECAP3SYNCOUT.
Definition: adc/v2/adc.h:545
ADC_PULSE_END_OF_ACQ_WIN
@ ADC_PULSE_END_OF_ACQ_WIN
Occurs at the end of the acquisition window.
Definition: adc/v2/adc.h:362
ADC_SYNCIN_EPWM13SYNCOUT
@ ADC_SYNCIN_EPWM13SYNCOUT
ADC Syncin is EPWM13SYNCOUT.
Definition: adc/v2/adc.h:523
ADC_SAFETY_CHECKER5
@ ADC_SAFETY_CHECKER5
Safety Checker5.
Definition: adc/v2/adc.h:742
ADC_TRIGGER_ECAP0_SOCEVT
@ ADC_TRIGGER_ECAP0_SOCEVT
eCAP0, SOCEVT
Definition: adc/v2/adc.h:299
ADC_disablePPBExtendedLowLimit
static void ADC_disablePPBExtendedLowLimit(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2923
ADC_SAFETY_CHECKER6
@ ADC_SAFETY_CHECKER6
Safety Checker6.
Definition: adc/v2/adc.h:743
ADC_TRIGGER_EPWM18_SOCB
@ ADC_TRIGGER_EPWM18_SOCB
ePWM18, ADCSOCB
Definition: adc/v2/adc.h:272
ADC_triggerRepeaterMode
static void ADC_triggerRepeaterMode(uint32_t base, uint32_t repInstance, ADC_RepMode mode)
Definition: adc/v2/adc.h:3686
ADC_ADCPPBxPMINI_STEP
#define ADC_ADCPPBxPMINI_STEP
Definition: adc/v2/adc.h:115
ADC_SAFETY_CHECKER3
@ ADC_SAFETY_CHECKER3
Safety Checker3.
Definition: adc/v2/adc.h:740
ADC_CH_CAL0_ADCIN6
@ ADC_CH_CAL0_ADCIN6
differential, CAL0 and ADCIN6 Note : only valid for AM261x
Definition: adc/v2/adc.h:349
ADC_SYNCIN_ECAP2SYNCOUT
@ ADC_SYNCIN_ECAP2SYNCOUT
ADC Syncin is ECAP2SYNCOUT.
Definition: adc/v2/adc.h:544
ADC_CH_ADCIN2_ADCIN3
@ ADC_CH_ADCIN2_ADCIN3
differential, ADCIN2 and ADCIN3
Definition: adc/v2/adc.h:343
ADC_SYNCIN_EPWM1SYNCOUT
@ ADC_SYNCIN_EPWM1SYNCOUT
ADC Syncin is EPWM1SYNCOUT.
Definition: adc/v2/adc.h:511
ADC_clearSafetyCheckIntStatus
static void ADC_clearSafetyCheckIntStatus(uint32_t scIntEvtBase)
Definition: adc/v2/adc.h:3658
ADC_INT_TRIGGER_EOC3
@ ADC_INT_TRIGGER_EOC3
SOC/EOC3.
Definition: adc/v2/adc.h:600
DebugP.h
ADC_RESULT3
@ ADC_RESULT3
Select ADC Result 3.
Definition: adc/v2/adc.h:658
ADC_setPPBTripLimits
void ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, int32_t tripHiLimit, int32_t tripLoLimit)
ADC_SignalMode
ADC_SignalMode
Definition: adc/v2/adc.h:215
ADC_forceSafetyCheckerSync
static void ADC_forceSafetyCheckerSync(uint32_t scBase)
Definition: adc/v2/adc.h:3248
ADC_CH_ADCIN4_ADCIN5
@ ADC_CH_ADCIN4_ADCIN5
differential, ADCIN4 and ADCIN5
Definition: adc/v2/adc.h:345
ADC_SYNCIN_ECAP1SYNCOUT
@ ADC_SYNCIN_ECAP1SYNCOUT
ADC Syncin is ECAP1SYNCOUT.
Definition: adc/v2/adc.h:543
ADC_SYNCIN_ECAP7SYNCOUT
@ ADC_SYNCIN_ECAP7SYNCOUT
ADC Syncin is ECAP7SYNCOUT.
Definition: adc/v2/adc.h:549
ADC_TRIGGER_EPWM18_SOCA
@ ADC_TRIGGER_EPWM18_SOCA
ePWM18, ADCSOCA
Definition: adc/v2/adc.h:271
ADC_readPPBPSum
static int32_t ADC_readPPBPSum(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2118
ADC_SYNCIN_EPWM16SYNCOUT
@ ADC_SYNCIN_EPWM16SYNCOUT
ADC Syncin is EPWM16SYNCOUT.
Definition: adc/v2/adc.h:526
ADC_CLK_DIV_1_0
@ ADC_CLK_DIV_1_0
ADCCLK = (input clock) / 1.0.
Definition: adc/v2/adc.h:180
ADC_disableExtMuxPreselect
static void ADC_disableExtMuxPreselect(uint32_t base)
Definition: adc/v2/adc.h:1225
ADC_INT_TRIGGER_EOC0
@ ADC_INT_TRIGGER_EOC0
SOC/EOC0.
Definition: adc/v2/adc.h:597
ADC_CH_ADCINX_3
@ ADC_CH_ADCINX_3
ADCINX.3 is converted.
Definition: adc/v2/adc.h:586
ADC_TRIGGER_SW_ONLY
@ ADC_TRIGGER_SW_ONLY
Software only.
Definition: adc/v2/adc.h:229
ADC_SYNCIN_CPSW_CTPS_SYNC
@ ADC_SYNCIN_CPSW_CTPS_SYNC
ADC Syncin is CPSW_CTPS_SYNC.
Definition: adc/v2/adc.h:560
ADC_RESULT1
@ ADC_RESULT1
Select ADC Result 1.
Definition: adc/v2/adc.h:656
ADC_Checker
ADC_Checker
Definition: adc/v2/adc.h:737
ADC_ADCPPBxPMAX_STEP
#define ADC_ADCPPBxPMAX_STEP
Definition: adc/v2/adc.h:112
ADC_TRIGGER_INPUT_XBAR_OUT5
@ ADC_TRIGGER_INPUT_XBAR_OUT5
InputXBar.Out[5].
Definition: adc/v2/adc.h:234
ADC_SAFETY_CHECKER9
@ ADC_SAFETY_CHECKER9
Safety Checker9.
Definition: adc/v2/adc.h:746
ADC_RESULT15
@ ADC_RESULT15
Select ADC Result 15.
Definition: adc/v2/adc.h:670
ADC_SYNCIN_ECAP9SYNCOUT
@ ADC_SYNCIN_ECAP9SYNCOUT
ADC Syncin is ECAP9SYNCOUT.
Definition: adc/v2/adc.h:551
ADC_TRIGGER_EPWM11_SOCA
@ ADC_TRIGGER_EPWM11_SOCA
ePWM11, ADCSOCA
Definition: adc/v2/adc.h:257
ADC_RESULT2
@ ADC_RESULT2
Select ADC Result 2.
Definition: adc/v2/adc.h:657
ADC_OSDETECT_MODE_7BY12_VDDA
@ ADC_OSDETECT_MODE_7BY12_VDDA
Definition: adc/v2/adc.h:483
ADC_RepeaterConfig::repSpread
uint16_t repSpread
Repeater trigger spread in sysclk cycles.
Definition: adc/v2/adc.h:802
ADC_readPPBResult
static int32_t ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2678
ADC_TRIGGER_EPWM3_SOCB
@ ADC_TRIGGER_EPWM3_SOCB
ePWM3, ADCSOCB
Definition: adc/v2/adc.h:242
ADC_PRI_ALL_HIPRI
@ ADC_PRI_ALL_HIPRI
All priorities based on SOC number.
Definition: adc/v2/adc.h:464
ADC_triggerRepeaterModuleBusy
static bool ADC_triggerRepeaterModuleBusy(uint32_t base, uint32_t repInstance)
Definition: adc/v2/adc.h:3749
ADC_setPPBShiftValue
static void ADC_setPPBShiftValue(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t shiftVal)
Definition: adc/v2/adc.h:2310
ADC_PRI_SOC0_HIPRI
@ ADC_PRI_SOC0_HIPRI
SOC 0 hi pri, others in round robin.
Definition: adc/v2/adc.h:449
ADC_SAFETY_CHECKER11
@ ADC_SAFETY_CHECKER11
Safety Checker11.
Definition: adc/v2/adc.h:748
ADC_SYNCIN_ECAP10SYNCOUT
@ ADC_SYNCIN_ECAP10SYNCOUT
ADC Syncin is ECAP10SYNCOUT.
Definition: adc/v2/adc.h:552
ADC_SAFETY_CHECKER_INPUT_PPBSUMx
@ ADC_SAFETY_CHECKER_INPUT_PPBSUMx
Safety checker i/p is PPBSUMx.
Definition: adc/v2/adc.h:684
ADC_TRIGGER_EPWM0_SOCA
@ ADC_TRIGGER_EPWM0_SOCA
ePWM0, ADCSOCA
Definition: adc/v2/adc.h:235
ADC_CH_ADCIN0_ADCIN1
@ ADC_CH_ADCIN0_ADCIN1
differential, ADCIN0 and ADCIN1
Definition: adc/v2/adc.h:341
ADC_SOC_NUMBER6
@ ADC_SOC_NUMBER6
SOC/EOC number 6.
Definition: adc/v2/adc.h:415
ADC_INT_TRIGGER_EOC2
@ ADC_INT_TRIGGER_EOC2
SOC/EOC2.
Definition: adc/v2/adc.h:599
ADC_enableSafetyCheckInt
static void ADC_enableSafetyCheckInt(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckResult checkResult)
Definition: adc/v2/adc.h:3495
ADC_2
@ ADC_2
Select ADC2 instance.
Definition: adc/v2/adc.h:642
ADC_enableInterrupt
static void ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum)
Definition: adc/v2/adc.h:2961
ADC_TRIGGER_EPWM20_SOCB
@ ADC_TRIGGER_EPWM20_SOCB
ePWM20, ADCSOCB
Definition: adc/v2/adc.h:276
ADC_ExtChannel
ADC_ExtChannel
Definition: adc/v2/adc.h:582
ADC_TRIGGER_EPWM1_SOCA
@ ADC_TRIGGER_EPWM1_SOCA
ePWM1, ADCSOCA
Definition: adc/v2/adc.h:237
ADC_SOC_NUMBER4
@ ADC_SOC_NUMBER4
SOC/EOC number 4.
Definition: adc/v2/adc.h:413
ADC_REPxSPREAD_STEP
#define ADC_REPxSPREAD_STEP
Definition: adc/v2/adc.h:103
ADC_CH_ADCIN3
@ ADC_CH_ADCIN3
single-ended, ADCIN3
Definition: adc/v2/adc.h:335
ADC_SAFETY_CHECK_RES1OVF_FLG
@ ADC_SAFETY_CHECK_RES1OVF_FLG
Safety Check Result1 Overflow Flag.
Definition: adc/v2/adc.h:761
ADC_SAFETY_CHECKER8
@ ADC_SAFETY_CHECKER8
Safety Checker8.
Definition: adc/v2/adc.h:745
ADC_RESULT_ADCRESULTx_STEP
#define ADC_RESULT_ADCRESULTx_STEP
Register offset difference between 2 ADCRESULTx registers.
Definition: adc/v2/adc.h:823
ADC_TRIGGER_RTI2
@ ADC_TRIGGER_RTI2
RTI Timer 2.
Definition: adc/v2/adc.h:232
ADC_TRIGGER_EPWM19_SOCB
@ ADC_TRIGGER_EPWM19_SOCB
ePWM19, ADCSOCB
Definition: adc/v2/adc.h:274
ADC_TRIGGER_EPWM20_SOCA
@ ADC_TRIGGER_EPWM20_SOCA
ePWM20, ADCSOCA
Definition: adc/v2/adc.h:275
ADC_INT_TRIGGER_OSINT4
@ ADC_INT_TRIGGER_OSINT4
OSINT4.
Definition: adc/v2/adc.h:616
ADC_SYNCIN_EPWM28SYNCOUT
@ ADC_SYNCIN_EPWM28SYNCOUT
ADC Syncin is EPWM28SYNCOUT.
Definition: adc/v2/adc.h:538
ADC_ADCPPBxCONFIG2_STEP
#define ADC_ADCPPBxCONFIG2_STEP
Register offset difference between 2 ADCPPBxLIMIT registers.
Definition: adc/v2/adc.h:110
ADC_CLK_DIV_3_0
@ ADC_CLK_DIV_3_0
ADCCLK = (input clock) / 3.0.
Definition: adc/v2/adc.h:183
ADC_REPxPHASE_STEP
#define ADC_REPxPHASE_STEP
Definition: adc/v2/adc.h:102
ADC_REPxCTL_STEP
#define ADC_REPxCTL_STEP
Definition: adc/v2/adc.h:100
ADC_SYNCIN_EPWM21SYNCOUT
@ ADC_SYNCIN_EPWM21SYNCOUT
ADC Syncin is EPWM21SYNCOUT.
Definition: adc/v2/adc.h:531
ADC_enablePPBEventCBCClear
static void ADC_enablePPBEventCBCClear(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:1959
ADC_setSOCPriority
static void ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode)
Definition: adc/v2/adc.h:1686
ADC_PPB_COMPSOURCE_PSUM
@ ADC_PPB_COMPSOURCE_PSUM
PPB compare source is PSUM.
Definition: adc/v2/adc.h:628
ADC_SYNCIN_EPWM24SYNCOUT
@ ADC_SYNCIN_EPWM24SYNCOUT
ADC Syncin is EPWM24SYNCOUT.
Definition: adc/v2/adc.h:534
ADC_TRIGGER_EPWM23_SOCB
@ ADC_TRIGGER_EPWM23_SOCB
ePWM23, ADCSOCB
Definition: adc/v2/adc.h:282
ADC_readPPBPMinIndex
static uint16_t ADC_readPPBPMinIndex(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2216
ADC_RESULT11
@ ADC_RESULT11
Select ADC Result 11.
Definition: adc/v2/adc.h:666
ADC_disableBurstMode
static void ADC_disableBurstMode(uint32_t base)
Definition: adc/v2/adc.h:1648
ADC_isBusy
static bool ADC_isBusy(uint32_t base)
Definition: adc/v2/adc.h:1555
ADC_TRIGGER_RTI3
@ ADC_TRIGGER_RTI3
RTI Timer 3.
Definition: adc/v2/adc.h:233
ADC_setPPBReferenceOffset
static void ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t offset)
Definition: adc/v2/adc.h:2788
ADC_forceRepeaterTrigger
static void ADC_forceRepeaterTrigger(uint32_t base, uint16_t repInstance)
Definition: adc/v2/adc.h:987
ADC_RepeaterConfig
Definition: adc/v2/adc.h:796
ADC_triggerRepeaterActiveMode
static bool ADC_triggerRepeaterActiveMode(uint32_t base, uint32_t repInstance)
Definition: adc/v2/adc.h:3718
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:187
ADC_CH_ADCIN1_ADCIN0
@ ADC_CH_ADCIN1_ADCIN0
differential, ADCIN1 and ADCIN0
Definition: adc/v2/adc.h:342
ADC_TRIGGER_EPWM21_SOCA
@ ADC_TRIGGER_EPWM21_SOCA
ePWM21, ADCSOCA
Definition: adc/v2/adc.h:277
ADC_CLK_DIV_5_5
@ ADC_CLK_DIV_5_5
ADCCLK = (input clock) / 5.5.
Definition: adc/v2/adc.h:188
ADC_SYNCIN_ECAP4SYNCOUT
@ ADC_SYNCIN_ECAP4SYNCOUT
ADC Syncin is ECAP4SYNCOUT.
Definition: adc/v2/adc.h:546
ADC_SAFETY_CHECK_RES1OVF
@ ADC_SAFETY_CHECK_RES1OVF
Safety Check Result1 Overflow.
Definition: adc/v2/adc.h:722
ADC_ADCPPBx_STEP
#define ADC_ADCPPBx_STEP
Register offset difference between 2 ADCPPBxCONFIG registers.
Definition: adc/v2/adc.h:815
ADC_TRIGGER_EPWM22_SOCA
@ ADC_TRIGGER_EPWM22_SOCA
ePWM22, ADCSOCA
Definition: adc/v2/adc.h:279
ADC_4
@ ADC_4
Select ADC4 instance.
Definition: adc/v2/adc.h:644
ADC_SYNCIN_EPWM3SYNCOUT
@ ADC_SYNCIN_EPWM3SYNCOUT
ADC Syncin is EPWM3SYNCOUT.
Definition: adc/v2/adc.h:513
ADC_Channel
ADC_Channel
Definition: adc/v2/adc.h:331
ADC_CH_CAL1
@ ADC_CH_CAL1
single-ended, CAL1 Note : Not Valid for AM261x
Definition: adc/v2/adc.h:340
ADC_readPPBSum
static int32_t ADC_readPPBSum(uint32_t resultBase, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2504
ADC_CLK_DIV_4_5
@ ADC_CLK_DIV_4_5
ADCCLK = (input clock) / 4.5.
Definition: adc/v2/adc.h:186
ADC_getSafetyCheckerStatus
static uint16_t ADC_getSafetyCheckerStatus(uint32_t scBase)
Definition: adc/v2/adc.h:3276
ADC_OFFSET_TRIM_INDIVIDUAL
@ ADC_OFFSET_TRIM_INDIVIDUAL
Definition: adc/v2/adc.h:503
ADC_triggerRepeaterPhase
static void ADC_triggerRepeaterPhase(uint32_t base, uint16_t repInstance, uint16_t repPhase)
Definition: adc/v2/adc.h:3935
ADC_enableSafetyCheckEvt
static void ADC_enableSafetyCheckEvt(uint32_t scIntEvtBase, ADC_Checker checkerNumber, ADC_SafetyCheckEvent checkEvent, ADC_SafetyCheckResult checkResult)
Definition: adc/v2/adc.h:3410
ADC_PPB_NUMBER1
@ ADC_PPB_NUMBER1
Post-processing block 1.
Definition: adc/v2/adc.h:392
ADC_TRIGGER_EPWM8_SOCB
@ ADC_TRIGGER_EPWM8_SOCB
ePWM8, ADCSOCB
Definition: adc/v2/adc.h:252
ADC_SAFETY_CHECKER2
@ ADC_SAFETY_CHECKER2
Safety Checker2.
Definition: adc/v2/adc.h:739
ADC_SYNCIN_EPWM14SYNCOUT
@ ADC_SYNCIN_EPWM14SYNCOUT
ADC Syncin is EPWM14SYNCOUT.
Definition: adc/v2/adc.h:524
ADC_TRIGGER_EPWM0_SOCB
@ ADC_TRIGGER_EPWM0_SOCB
ePWM0, ADCSOCB
Definition: adc/v2/adc.h:236
ADC_TRIGGER_EPWM24_SOCB
@ ADC_TRIGGER_EPWM24_SOCB
ePWM24, ADCSOCB
Definition: adc/v2/adc.h:284
ADC_ADCPPBxPMAXI_STEP
#define ADC_ADCPPBxPMAXI_STEP
Definition: adc/v2/adc.h:113
ADC_ADCPPBxPMIN_STEP
#define ADC_ADCPPBxPMIN_STEP
Definition: adc/v2/adc.h:114
ADC_0
@ ADC_0
Select ADC0 instance.
Definition: adc/v2/adc.h:640
ADC_CLK_DIV_2_5
@ ADC_CLK_DIV_2_5
ADCCLK = (input clock) / 2.5.
Definition: adc/v2/adc.h:182
ADC_IntNumber
ADC_IntNumber
Definition: adc/v2/adc.h:377
ADC_SafetyCheckEvent
ADC_SafetyCheckEvent
Definition: adc/v2/adc.h:706
ADC_SYNCIN_ECAP0SYNCOUT
@ ADC_SYNCIN_ECAP0SYNCOUT
ADC Syncin is ECAP0SYNCOUT.
Definition: adc/v2/adc.h:542
ADC_CH_CAL0_CAL1
@ ADC_CH_CAL0_CAL1
differential, CAL0 and CAL1 Note : Not Valid for AM261x
Definition: adc/v2/adc.h:347
ADC_TRIGGER_EPWM13_SOCA
@ ADC_TRIGGER_EPWM13_SOCA
ePWM13, ADCSOCA
Definition: adc/v2/adc.h:261
ADC_getPPBCountLimit
static uint16_t ADC_getPPBCountLimit(uint32_t base, ADC_PPBNumber ppbNumber)
Definition: adc/v2/adc.h:2063
ADC_TRIGGER_EPWM5_SOCA
@ ADC_TRIGGER_EPWM5_SOCA
ePWM5, ADCSOCA
Definition: adc/v2/adc.h:245
ADC_SOC_NUMBER2
@ ADC_SOC_NUMBER2
SOC/EOC number 2.
Definition: adc/v2/adc.h:411
ADC_SafetyCheckInst
ADC_SafetyCheckInst
Definition: adc/v2/adc.h:694
ADC_TRIGGER_EPWM21_SOCB
@ ADC_TRIGGER_EPWM21_SOCB
ePWM21, ADCSOCB
Definition: adc/v2/adc.h:278
ADC_TRIGGER_EPWM25_SOCB
@ ADC_TRIGGER_EPWM25_SOCB
ePWM25, ADCSOCB
Definition: adc/v2/adc.h:286
ADC_clearPPBEventStatus
static void ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags)
Definition: adc/v2/adc.h:1927
ADC_TRIGGER_RTI0
@ ADC_TRIGGER_RTI0
RTI Timer 0.
Definition: adc/v2/adc.h:230
ADC_TRIGGER_EPWM14_SOCA
@ ADC_TRIGGER_EPWM14_SOCA
ePWM14, ADCSOCA
Definition: adc/v2/adc.h:263
ADC_INT_TRIGGER_EOC14
@ ADC_INT_TRIGGER_EOC14
SOC/EOC14.
Definition: adc/v2/adc.h:611
ADC_TRIGGER_EPWM26_SOCB
@ ADC_TRIGGER_EPWM26_SOCB
ePWM26, ADCSOCB
Definition: adc/v2/adc.h:288
ADC_PPB_NUMBER2
@ ADC_PPB_NUMBER2
Post-processing block 2.
Definition: adc/v2/adc.h:393
ADC_SYNCIN_ECAP8SYNCOUT
@ ADC_SYNCIN_ECAP8SYNCOUT
ADC Syncin is ECAP8SYNCOUT.
Definition: adc/v2/adc.h:550
ADC_setupSOC
static void ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, ADC_Channel channel, uint32_t sampleWindow)
Definition: adc/v2/adc.h:898
ADC_OSDETECT_MODE_VDDA
@ ADC_OSDETECT_MODE_VDDA
Definition: adc/v2/adc.h:479
ADC_selectOffsetTrimMode
static void ADC_selectOffsetTrimMode(uint32_t base, ADC_OffsetTrim mode)
Definition: adc/v2/adc.h:1257
ADC_RESULT12
@ ADC_RESULT12
Select ADC Result 12.
Definition: adc/v2/adc.h:667
ADC_TRIGGER_EPWM4_SOCB
@ ADC_TRIGGER_EPWM4_SOCB
ePWM4, ADCSOCB
Definition: adc/v2/adc.h:244
ADC_SAFETY_CHECKER_INPUT_PPBx
@ ADC_SAFETY_CHECKER_INPUT_PPBx
Safety checker i/p is PPBx.
Definition: adc/v2/adc.h:683
ADC_triggerRepeaterSelect
static void ADC_triggerRepeaterSelect(uint32_t base, uint16_t repInstance, ADC_Trigger trigger)
Definition: adc/v2/adc.h:3781