AM263Px MCU+ SDK: TI generic_phy PHY

| AM263Px MCU+ SDK 26.00.00 |

Functions | Macros
TI generic_phy PHY
APIs for Networking modules » APIs for Enet LLD » Ethernet PHY Driver

## Introduction

TI generic_phy RGMII Ethernet PHY.

## Functions
void | GenericPhy_reset (EthPhyDrv_Handle hPhy)
bool | GenericPhy_isResetComplete (EthPhyDrv_Handle hPhy)
int32_t | GenericPhy_readReg (EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *pVal)
int32_t | GenericPhy_writeReg (EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
int32_t | GenericPhy_readExtReg (EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t *val)
int32_t | GenericPhy_writeExtReg (EthPhyDrv_Handle hPhy, uint32_t reg, uint16_t val)
void | GenericPhy_printRegs (EthPhyDrv_Handle hPhy)
int32_t | GenericPhy_ctrlPowerDown (EthPhyDrv_Handle hPhy, bool control)
int32_t | GenericPhy_isPowerDownActive (EthPhyDrv_Handle hPhy, bool *pActive)
int32_t | GenericPhy_enableAdvertisement (EthPhyDrv_Handle hPhy, uint32_t advertisement)
int32_t | GenericPhy_disableAdvertisement (EthPhyDrv_Handle hPhy, uint32_t advertisement)
int32_t | GenericPhy_ctrlAutoNegotiation (EthPhyDrv_Handle hPhy, uint32_t control)
int32_t | GenericPhy_isLinkPartnerAutoNegotiationAble (EthPhyDrv_Handle hPhy, bool *pAble)
int32_t | GenericPhy_isAutoNegotiationEnabled (EthPhyDrv_Handle hPhy, bool *pEnabled)
int32_t | GenericPhy_isAutoNegotiationComplete (EthPhyDrv_Handle hPhy, bool *pCompleted)
int32_t | GenericPhy_isAutoNegotiationRestartComplete (EthPhyDrv_Handle hPhy, bool *pCompleted)
int32_t | GenericPhy_setSpeedDuplex (EthPhyDrv_Handle hPhy, uint32_t settings)
int32_t | GenericPhy_isLinkUp (EthPhyDrv_Handle hPhy, bool *pLinkUp)
int32_t | GenericPhy_getId (EthPhyDrv_Handle hPhy, uint32_t *pId)

## Macros
#define | PHY_BMCR (0x00U)
| Basic Mode Control Register (BMCR) More...
#define | PHY_BMSR (0x01U)
| Basic Mode Status Register (BMSR) More...
#define | PHY_PHYIDR1 (0x02U)
| PHY Identifier Register #1 (PHYIDR1) More...
#define | PHY_PHYIDR2 (0x03U)
| PHY Identifier Register #2 (PHYIDR2) More...
#define | PHY_ANAR (0x04U)
| Auto-Negotiation Advertisement Register (ANAR) More...
#define | PHY_ANLPAR (0x05U)
| Auto-Negotiation Link Partner Abilitiy Register (ANLPAR) More...
#define | PHY_ANER (0x06U)
| Auto-Negotiation Expansion Register (ANER) More...
#define | PHY_ANNPTR (0x07U)
| Auto-Negotiation NP TX Register (ANNPTR) More...
#define | PHY_ANNPRR (0x08U)
| Auto-Neg NP RX Register (ANNPRR) More...
#define | PHY_GIGCR (0x09U)
| 1000BASE-T Control Register (GIGCR) More...
#define | PHY_GIGSR (0x0AU)
| 1000BASE-T Status Register (GIGSR) More...
#define | PHY_MMD_CR (0x0DU)
| MMD Access Control Register. More...
#define | PHY_MMD_DR (0x0EU)
| MMD Access Data Register. More...
#define | PHY_GIGESR (0x0FU)
| 1000BASE-T Extended Status Register (GIGESR) More...
#define | BMCR_RESET PHY_BIT(15)
#define | BMCR_LOOPBACK PHY_BIT(14)
#define | BMCR_SPEED100 PHY_BIT(13)
#define | BMCR_ANEN PHY_BIT(12)
#define | BMCR_PWRDOWN PHY_BIT(11)
#define | BMCR_ISOLATE PHY_BIT(10)
#define | BMCR_ANRESTART PHY_BIT(9)
#define | BMCR_FD PHY_BIT(8)
#define | BMCR_SPEED1000 PHY_BIT(6)
#define | BMSR_100FD PHY_BIT(14)
#define | BMSR_100HD PHY_BIT(13)
#define | BMSR_10FD PHY_BIT(12)
#define | BMSR_10HD PHY_BIT(11)
#define | BMSR_GIGEXTSTS PHY_BIT(8)
#define | BMSR_ANCOMPLETE PHY_BIT(5)
#define | BMSR_ANCAPABLE PHY_BIT(3)
#define | BMSR_LINKSTS PHY_BIT(2)
#define | BMSR_EXTCAP PHY_BIT(0)
#define | PHYIDR1_OUI_OFFSET (6U)
#define | PHYIDR2_OUI_MASK (0xFC00U)
#define | PHYIDR2_VMDL_MASK (0x03F0U)
#define | PHYIDR2_VREV_MASK (0x000FU)
#define | PHYIDR2_OUI_OFFSET (10U)
#define | PHYIDR2_VMDL_OFFSET (4U)
#define | PHYIDR2_VREV_OFFSET (0U)
#define | ANAR_100FD PHY_BIT(8)
#define | ANAR_100HD PHY_BIT(7)
#define | ANAR_10FD PHY_BIT(6)
#define | ANAR_10HD PHY_BIT(5)
#define | ANAR_802P3 PHY_BIT(0)
#define | ANAR_100 (ANAR_100FD | ANAR_100HD)
#define | ANAR_10 (ANAR_10FD | ANAR_10HD)
#define | ANLPAR_100FD PHY_BIT(8)
#define | ANLPAR_100HD PHY_BIT(7)
#define | ANLPAR_10FD PHY_BIT(6)
#define | ANLPAR_10HD PHY_BIT(5)
#define | ANLPAR_100 (ANLPAR_100FD | ANLPAR_100HD)
#define | ANLPAR_10 (ANLPAR_10FD | ANLPAR_10HD)
#define | ANER_LPISANABLE PHY_BIT(0)
#define | GIGCR_MASTERCFG PHY_BIT(12)
#define | GIGCR_MASTEREN PHY_BIT(11)
#define | GIGCR_1000FD PHY_BIT(9)
#define | GIGCR_1000HD PHY_BIT(8)
#define | GIGCR_1000 (GIGCR_1000FD | GIGCR_1000HD)
#define | GIGSR_MASTERRES PHY_BIT(14)
#define | GIGSR_LOCALSTS PHY_BIT(13)
#define | GIGSR_LPARSTS PHY_BIT(12)
#define | GIGSR_1000FD PHY_BIT(11)
#define | GIGSR_1000HD PHY_BIT(10)
#define | GIGSR_1000 (GIGSR_1000FD | GIGSR_1000HD)
#define | MMD_CR_ADDR (0x0000U)
#define | MMD_CR_DATA_NOPOSTINC (0x4000U)
#define | MMD_CR_DATA_POSTINC_RW (0x8000U)
#define | MMD_CR_DATA_POSTINC_W (0xC000U)
#define | MMD_CR_DEVADDR (0x001FU)
#define | GIGESR_1000FD PHY_BIT(13)
#define | GIGESR_1000HD PHY_BIT(12)
#define | GIGESR_1000 (GIGESR_1000FD | GIGESR_1000HD)

## Macro Definition Documentation

## ◆ PHY_BMCR

#define PHY_BMCR (0x00U)

Basic Mode Control Register (BMCR)

## ◆ PHY_BMSR

#define PHY_BMSR (0x01U)

Basic Mode Status Register (BMSR)

## ◆ PHY_PHYIDR1

#define PHY_PHYIDR1 (0x02U)

PHY Identifier Register #1 (PHYIDR1)

## ◆ PHY_PHYIDR2

#define PHY_PHYIDR2 (0x03U)

PHY Identifier Register #2 (PHYIDR2)

## ◆ PHY_ANAR

#define PHY_ANAR (0x04U)

Auto-Negotiation Advertisement Register (ANAR)

## ◆ PHY_ANLPAR

#define PHY_ANLPAR (0x05U)

Auto-Negotiation Link Partner Abilitiy Register (ANLPAR)

## ◆ PHY_ANER

#define PHY_ANER (0x06U)

Auto-Negotiation Expansion Register (ANER)

## ◆ PHY_ANNPTR

#define PHY_ANNPTR (0x07U)

Auto-Negotiation NP TX Register (ANNPTR)

## ◆ PHY_ANNPRR

#define PHY_ANNPRR (0x08U)

Auto-Neg NP RX Register (ANNPRR)

## ◆ PHY_GIGCR

#define PHY_GIGCR (0x09U)

1000BASE-T Control Register (GIGCR)

## ◆ PHY_GIGSR

#define PHY_GIGSR (0x0AU)

1000BASE-T Status Register (GIGSR)

## ◆ PHY_MMD_CR

#define PHY_MMD_CR (0x0DU)

MMD Access Control Register.

## ◆ PHY_MMD_DR

#define PHY_MMD_DR (0x0EU)

MMD Access Data Register.

## ◆ PHY_GIGESR

#define PHY_GIGESR (0x0FU)

1000BASE-T Extended Status Register (GIGESR)

## ◆ BMCR_RESET

#define BMCR_RESET PHY_BIT(15)

## ◆ BMCR_LOOPBACK

#define BMCR_LOOPBACK PHY_BIT(14)

## ◆ BMCR_SPEED100

#define BMCR_SPEED100 PHY_BIT(13)

## ◆ BMCR_ANEN

#define BMCR_ANEN PHY_BIT(12)

## ◆ BMCR_PWRDOWN

#define BMCR_PWRDOWN PHY_BIT(11)

## ◆ BMCR_ISOLATE

#define BMCR_ISOLATE PHY_BIT(10)

## ◆ BMCR_ANRESTART

#define BMCR_ANRESTART PHY_BIT(9)

## ◆ BMCR_FD

#define BMCR_FD PHY_BIT(8)

## ◆ BMCR_SPEED1000

#define BMCR_SPEED1000 PHY_BIT(6)

## ◆ BMSR_100FD

#define BMSR_100FD PHY_BIT(14)

## ◆ BMSR_100HD

#define BMSR_100HD PHY_BIT(13)

## ◆ BMSR_10FD

#define BMSR_10FD PHY_BIT(12)

## ◆ BMSR_10HD

#define BMSR_10HD PHY_BIT(11)

## ◆ BMSR_GIGEXTSTS

#define BMSR_GIGEXTSTS PHY_BIT(8)

## ◆ BMSR_ANCOMPLETE

#define BMSR_ANCOMPLETE PHY_BIT(5)

## ◆ BMSR_ANCAPABLE

#define BMSR_ANCAPABLE PHY_BIT(3)

## ◆ BMSR_LINKSTS

#define BMSR_LINKSTS PHY_BIT(2)

## ◆ BMSR_EXTCAP

#define BMSR_EXTCAP PHY_BIT(0)

## ◆ PHYIDR1_OUI_OFFSET

#define PHYIDR1_OUI_OFFSET (6U)

## ◆ PHYIDR2_OUI_MASK

#define PHYIDR2_OUI_MASK (0xFC00U)

## ◆ PHYIDR2_VMDL_MASK

#define PHYIDR2_VMDL_MASK (0x03F0U)

## ◆ PHYIDR2_VREV_MASK

#define PHYIDR2_VREV_MASK (0x000FU)

## ◆ PHYIDR2_OUI_OFFSET

#define PHYIDR2_OUI_OFFSET (10U)

## ◆ PHYIDR2_VMDL_OFFSET

#define PHYIDR2_VMDL_OFFSET (4U)

## ◆ PHYIDR2_VREV_OFFSET

#define PHYIDR2_VREV_OFFSET (0U)

## ◆ ANAR_100FD

#define ANAR_100FD PHY_BIT(8)

## ◆ ANAR_100HD

#define ANAR_100HD PHY_BIT(7)

## ◆ ANAR_10FD

#define ANAR_10FD PHY_BIT(6)

## ◆ ANAR_10HD

#define ANAR_10HD PHY_BIT(5)

## ◆ ANAR_802P3

#define ANAR_802P3 PHY_BIT(0)

## ◆ ANAR_100

#define ANAR_100 (ANAR_100FD | ANAR_100HD)

## ◆ ANAR_10

#define ANAR_10 (ANAR_10FD | ANAR_10HD)

## ◆ ANLPAR_100FD

#define ANLPAR_100FD PHY_BIT(8)

## ◆ ANLPAR_100HD

#define ANLPAR_100HD PHY_BIT(7)

## ◆ ANLPAR_10FD

#define ANLPAR_10FD PHY_BIT(6)

## ◆ ANLPAR_10HD

#define ANLPAR_10HD PHY_BIT(5)

## ◆ ANLPAR_100

#define ANLPAR_100 (ANLPAR_100FD | ANLPAR_100HD)

## ◆ ANLPAR_10

#define ANLPAR_10 (ANLPAR_10FD | ANLPAR_10HD)

## ◆ ANER_LPISANABLE

#define ANER_LPISANABLE PHY_BIT(0)

## ◆ GIGCR_MASTERCFG

#define GIGCR_MASTERCFG PHY_BIT(12)

## ◆ GIGCR_MASTEREN

#define GIGCR_MASTEREN PHY_BIT(11)

## ◆ GIGCR_1000FD

#define GIGCR_1000FD PHY_BIT(9)

## ◆ GIGCR_1000HD

#define GIGCR_1000HD PHY_BIT(8)

## ◆ GIGCR_1000

#define GIGCR_1000 (GIGCR_1000FD | GIGCR_1000HD)

## ◆ GIGSR_MASTERRES

#define GIGSR_MASTERRES PHY_BIT(14)

## ◆ GIGSR_LOCALSTS

#define GIGSR_LOCALSTS PHY_BIT(13)

## ◆ GIGSR_LPARSTS

#define GIGSR_LPARSTS PHY_BIT(12)

## ◆ GIGSR_1000FD

#define GIGSR_1000FD PHY_BIT(11)

## ◆ GIGSR_1000HD

#define GIGSR_1000HD PHY_BIT(10)

## ◆ GIGSR_1000

#define GIGSR_1000 (GIGSR_1000FD | GIGSR_1000HD)

## ◆ MMD_CR_ADDR

#define MMD_CR_ADDR (0x0000U)

## ◆ MMD_CR_DATA_NOPOSTINC

#define MMD_CR_DATA_NOPOSTINC (0x4000U)

## ◆ MMD_CR_DATA_POSTINC_RW

#define MMD_CR_DATA_POSTINC_RW (0x8000U)

## ◆ MMD_CR_DATA_POSTINC_W

#define MMD_CR_DATA_POSTINC_W (0xC000U)

## ◆ MMD_CR_DEVADDR

#define MMD_CR_DEVADDR (0x001FU)

## ◆ GIGESR_1000FD

#define GIGESR_1000FD PHY_BIT(13)

## ◆ GIGESR_1000HD

#define GIGESR_1000HD PHY_BIT(12)

## ◆ GIGESR_1000

#define GIGESR_1000 (GIGESR_1000FD | GIGESR_1000HD)

## Function Documentation

## ◆ GenericPhy_reset()

void GenericPhy_reset | ( | EthPhyDrv_Handle | hPhy | ) |

## ◆ GenericPhy_isResetComplete()

bool GenericPhy_isResetComplete | ( | EthPhyDrv_Handle | hPhy | ) |

## ◆ GenericPhy_readReg()

int32_t GenericPhy_readReg | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | reg,
|  | uint16_t * | pVal
| ) |  |

## ◆ GenericPhy_writeReg()

int32_t GenericPhy_writeReg | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | reg,
|  | uint16_t | val
| ) |  |

## ◆ GenericPhy_readExtReg()

int32_t GenericPhy_readExtReg | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | reg,
|  | uint16_t * | val
| ) |  |

## ◆ GenericPhy_writeExtReg()

int32_t GenericPhy_writeExtReg | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | reg,
|  | uint16_t | val
| ) |  |

## ◆ GenericPhy_printRegs()

void GenericPhy_printRegs | ( | EthPhyDrv_Handle | hPhy | ) |

## ◆ GenericPhy_ctrlPowerDown()

int32_t GenericPhy_ctrlPowerDown | ( | EthPhyDrv_Handle | hPhy,
|  | bool | control
| ) |  |

## ◆ GenericPhy_isPowerDownActive()

int32_t GenericPhy_isPowerDownActive | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pActive
| ) |  |

## ◆ GenericPhy_enableAdvertisement()

int32_t GenericPhy_enableAdvertisement | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | advertisement
| ) |  |

## ◆ GenericPhy_disableAdvertisement()

int32_t GenericPhy_disableAdvertisement | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | advertisement
| ) |  |

## ◆ GenericPhy_ctrlAutoNegotiation()

int32_t GenericPhy_ctrlAutoNegotiation | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | control
| ) |  |

## ◆ GenericPhy_isLinkPartnerAutoNegotiationAble()

int32_t GenericPhy_isLinkPartnerAutoNegotiationAble | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pAble
| ) |  |

## ◆ GenericPhy_isAutoNegotiationEnabled()

int32_t GenericPhy_isAutoNegotiationEnabled | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pEnabled
| ) |  |

## ◆ GenericPhy_isAutoNegotiationComplete()

int32_t GenericPhy_isAutoNegotiationComplete | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pCompleted
| ) |  |

## ◆ GenericPhy_isAutoNegotiationRestartComplete()

int32_t GenericPhy_isAutoNegotiationRestartComplete | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pCompleted
| ) |  |

## ◆ GenericPhy_setSpeedDuplex()

int32_t GenericPhy_setSpeedDuplex | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t | settings
| ) |  |

## ◆ GenericPhy_isLinkUp()

int32_t GenericPhy_isLinkUp | ( | EthPhyDrv_Handle | hPhy,
|  | bool * | pLinkUp
| ) |  |

## ◆ GenericPhy_getId()

int32_t GenericPhy_getId | ( | EthPhyDrv_Handle | hPhy,
|  | uint32_t * | pId
| ) |  |