AM263Px MCU+ SDK: SDFM EPWM sync CPU read

| AM263Px MCU+ SDK 26.00.00 |

SDFM EPWM sync CPU read

# Introduction

A SDFM example that reads filter data from CPU

Figure 1a. Block diagram

In this example, SDFM filter data is read by CPU in SDFM ISR routine. The SDFM configuration is shown below:

- SDFM used in this example - SDFM0
- Input control mode selected - MODE0
- Comparator settings
  - Sinc3 filter selected
  - OSR = 32
  - HLT = 0x7FFF (Higher threshold setting)
  - LLT = 0x0000(Lower threshold setting)
- Data filter settings
  - All the 4 filter modules enabled
  - Sinc3 filter selected
  - OSR = 256
  - All the 4 filters are synchronized by using PWM
  - Filter output represented in 16 bit format
  - In order to convert 25 bit Data filter into 16 bit format user needs to right shift by 10 bits for Sinc3 filter with OSR = 256
- Interrupt module settings for SDFM filter
  - All the 4 higher threshold comparator interrupts disabled
  - All the 4 lower threshold comparator interrupts disabled
  - All the 4 modulator failure interrupts disabled
  - All the 4 filter will generate interrupt when a new filter data is available.

EPWM1 SOCA is used to synchronize all four filters. All 4 filters use SD1 (Filter1) clock.

EPWM0_B is used to generated a optional SDFM clock.

Watch Variables

- filter1Result - Output of filter 1
- filter2Result - Output of filter 2
- filter3Result - Output of filter 3
- filter4Result - Output of filter 4

Figure 1b. Implementation details

# External Connections

- Connect Sigma-Delta streams to SDFM0_CLK0, SDFM0_D0, SDFM0_D1, SDFM0_D2, SDFM0_D3

## AM263X-CC or AM263Px-CC or AM261x-SOM

When using with TMDSHSECDOCK (HSEC180 controlCARD Baseboard Docking Station)

- Connect Sigma-Delta data streams to

HSEC Pin 91 (SDFM0_D0), HSEC Pin 99 (SDFM0_D1), HSEC Pin 103 (SDFM0_D2), HSEC Pin 107 (SDFM0_D3).

- Connect Sigma-Delta clock to

HSEC Pin 72 (SDFM0_CLK0)

Alternate option: Use PWM waveform generated by AM263x as clock. Connect HSEC Pin 51 (Clock generated by EPWM0_B) to HSEC Pin 72

## AM263X-LP

This example is not supported on AM263X-LP

# Supported Combinations

Parameter | Value
--- | ---
CPU + OS | r5fss0-0 nortos
Toolchain | ti-arm-clang
Board | am263px-cc
Example folder | examples/drivers/sdfm/sdfm_epwm_sync_cpuread.c/

# Steps to Run the Example

- When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
- When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
- Establish connections as mentioned in External Connections section
- Launch a CCS debug session and run the executable, see CCS Launch, Load and Run
- View the UART console logs for results

# See Also

SDFM

# Sample Output

Shown below is a sample output when the application is run,

[Cortex_R5_0] SDFM EPWM Sync CPU Read Test Started ...
Please wait 100 seconds ...
SDFM ISR count: 0
Modulator operating normally
Filter 1 data : -2731
Filter 2 data : -2731
Filter 3 data : -2731
Filter 4 data : -2731
SDFM ISR count: 3057
Modulator operating normally
Filter 1 data : -2731
Filter 2 data : -2731
Filter 3 data : -2731
Filter 4 data : -2731
SDFM ISR count: 6114
Modulator operating normally
Filter 1 data : -2731
Filter 2 data : -2731
Filter 3 data : -2731
Filter 4 data : -2731
...
...
...
SDFM ISR count: 302692
Modulator operating normally
Filter 1 data : -2731
Filter 2 data : -2731
Filter 3 data : -2731
Filter 4 data : -2731
SDFM EPWM Sync CPU Read Test Passed!!
All tests have passed!!