AM263Px MCU+ SDK: sdl_ecc_soc.h Source File

| AM263Px MCU+ SDK 26.00.00 |

sdl_ecc_soc.h
Go to the documentation of this file.
1 /*
2 * SDL ECC
3 *
4 * Software Diagnostics Library module for ECC
5 *
6 * Copyright (c) Texas Instruments Incorporated 2022-2024
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the
18 * distribution.
19 *
20 * Neither the name of Texas Instruments Incorporated nor the names of
21 * its contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 *
36 */
37
52 #ifndef INCLUDE_SDL_ECC_SOC_H_
53 #define INCLUDE_SDL_ECC_SOC_H_
54
55 #include <stdint.h>
56 #include <sdl/sdl_ecc.h>
57 #include <sdl/ecc/sdl_ip_ecc.h>
58 #include <sdl/include/sdl_types.h>
59 #include <sdl/esm/soc/am263px/sdl_esm_core.h>
60 #include <sdl/ecc/sdl_ecc_priv.h>
61 #include <sdl/include/am263px/sdlr_soc_ecc_aggr.h>
62 #include <sdl/include/am263px/soc_config.h>
63 #include <sdl/include/am263px/sdlr_intr_esm0.h>
64 #include <sdl/include/am263px/sdlr_soc_baseaddress.h>
65 #include <sdl/include/am263px/sdlr_intr_r5fss0_core0.h>
66 #include <sdl/include/am263px/sdlr_intr_r5fss0_core1.h>
67 #include <sdl/include/am263px/sdlr_intr_r5fss1_core0.h>
68 #include <sdl/include/am263px/sdlr_intr_r5fss1_core1.h>
69 #include <sdl/include/am263px/sdlr_param_regs.h>
70
71 #define SDL_ECC_WIDTH_UNDEFINED 0x1
72
73 /* define Max memEntries for each aggregator (i.e. the number of RAM ID's with * Wrapper type) */
74 #define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (9U)
75 #define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
76 #define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
77 #define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
78 #define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (29U)
79 #define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (10U)
80 #define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (5U)
81 #define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
82 #define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
83 #define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
84 #define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
85 #define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
86 #define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
87 #define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
88 #define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
89 #define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
90 #define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (1U)
91 #define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES (8U)
92 #define SDL_ECC_Base_Address_TOTAL_ENTRIES (18U)
93
94 #define SDL_CPSW0_ECC_U_BASE (SDL_CPSW0_U_BASE + 0x3f000u)
95 #define SDL_OSPI_ECC_U_BASE (0x53807000u)
96 #define SDL_FOTA_ECC_U_BASE (0x5380F000u)
97
98 /* define parity control register addresses */
99 /* R5FSS0 */
100 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS (0x50D18104U)
101 #define SDL_R5FSS0_CORE0_TCM_ERR_STATUS_RAW (0x50D18108U)
102 #define SDL_R5SS0_TCM_ADDRPARITY_ERRFORCE (0x50D1813CU)
103
104 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS (0x50D18114U)
105 #define SDL_R5FSS0_CORE1_TCM_ERR_STATUS_RAW (0x50D18118U)
106 /* R5FSS1 */
107 #define SDL_R5FSS1_CORE0_TCM_ERR_STATUS (0x50D18144U)
108 #define SDL_R5FSS1_CORE0_TCM_ERR_STATUS_RAW (0x50D18148U)
109 #define SDL_R5SS1_TCM_ADDRPARITY_ERRFORCE (0x50D1817CU)
110
111 #define SDL_R5FSS1_CORE1_TCM_ERR_STATUS (0x50D18154U)
112 #define SDL_R5FSS1_CORE1_TCM_ERR_STATUS_RAW (0x50D18158U)
113
114 /* TPCC */
115 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_CTRL (0x50D18180U)
116 #define SDL_R5FSS0_CORE0_TPCC0_PARITY_STATUS (0x50D18184U)
117
118 #define SDL_TPCC0_ERRAGG_STATUS (0x50D18004U)
119 #define SDL_TPCC0_ERRAGG_MASK (0x50D18000U)
120
121 /* TMU */
122 #define SDL_TMU_R5SS0_CORE0_ROM_PARITY_CTRL (0x50D18188U)
123 #define SDL_TMU_R5SS0_CORE1_ROM_PARITY_CTRL (0x50D18190U)
124 #define SDL_TMU_R5SS1_CORE0_ROM_PARITY_CTRL (0x50D18198U)
125 #define SDL_TMU_R5SS1_CORE1_ROM_PARITY_CTRL (0x50D181A0U)
126 #define SDL_TMU0_ROM_PARITY_EN (0x1U)
127 #define SDL_TMU0_ROM_PARITY_FORCE_ERR (0x2U)
128 #define SDL_TMU0_ROM_PARITY_ERR_CLR (0x10000U)
129
130 /*param registers */
131 #define SDL_PARAM_REG_1 (SDL_PARAM_REG_SET0 + 0x20U)
132 #define SDL_PARAM_REG_2 (SDL_PARAM_REG_SET0 + 0x30U)
133
137 static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
138 {
139 { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID, 0x70000000u,
140 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_SIZE, 8u,
141 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
142 { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID, 0x70080000u,
143 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_SIZE, 8u,
144 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
145 { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID, 0x70100000u,
146 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_SIZE, 8u,
147 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
148 { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID, 0x70180000u,
149 SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_SIZE, 8u,
150 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
151 { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID, 0x72000000u,
152 SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_SIZE, 8u,
153 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
154 { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID, 0u,
155 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_SIZE, 8u,
156 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
157 { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID, 0u,
158 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_SIZE, 8u,
159 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
160 { SDL_SOC_ECC_AGGR_MSS_L2_SLV4_ECC_RAM_ID, 0x70200000u,
161 SDL_SOC_ECC_AGGR_MSS_L2_SLV4_ECC_RAM_SIZE, 8u,
162 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
163 { SDL_SOC_ECC_AGGR_MSS_L2_SLV5_ECC_RAM_ID, 0x70280000u,
164 SDL_SOC_ECC_AGGR_MSS_L2_SLV5_ECC_RAM_SIZE, 8u,
165 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
166 };
167
172 static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
173 {
174 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
175 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
176 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
177 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
178 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
179 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
180 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
181 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
182 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
183 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
184 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
185 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
186 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
187 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
188 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
189 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
190 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
191 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
192 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
193 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
194 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
195 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
196 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
197 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
198 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
199 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
200 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
201 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
202 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
203 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
204 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
205 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
206 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
207 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
208 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
209 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
210 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
211 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
212 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
213 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
214 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
215 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
216 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
217 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
218 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
219 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
220 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
221 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
222 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
223 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
224 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
225 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
226 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
227 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
228 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
229 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
230 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
231 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
232 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
233 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
234 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
235 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
236 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
237 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
238 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
239 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
240 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x0u,
241 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
242 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
243 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
244 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
245 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
246 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
247 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
248 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
249 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
250 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
251 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
252 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
253 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
254 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
255 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
256 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
257 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
258 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID, 0,
259 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_SIZE, 4u,
260 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
261 };
262
267 static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
268 {
269 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
270 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
271 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
272 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
273 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
274 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
275 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
276 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
277 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
278 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
279 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
280 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
281 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
282 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
283 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
284 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
285 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
286 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
287 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
288 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
289 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
290 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
291 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
292 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
293 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
294 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
295 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
296 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
297 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
298 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
299 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
300 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
301 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
302 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
303 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
304 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
305 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
306 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
307 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
308 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
309 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
310 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
311 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
312 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
313 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
314 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
315 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
316 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
317 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
318 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
319 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
320 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
321 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
322 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
323 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
324 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
325 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
326 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
327 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
328 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
329 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
330 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
331 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
332 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x00008000u,
333 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
334 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
335 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x00008000u,
336 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
337 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
338 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00088000u,
339 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
340 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
341 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00088000u,
342 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
343 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
344 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00088000u,
345 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
346 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
347 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00088000u,
348 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
349 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
350 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
351 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
352 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
353 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID, 0,
354 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_SIZE, 4u,
355 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
356 };
357
362 static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
363 {
364 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID, 0u,
365 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_SIZE, 4u,
366 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
367 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID, 0u,
368 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_SIZE, 4u,
369 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
370 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID, 0u,
371 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_SIZE, 4u,
372 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
373 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID, 0u,
374 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_SIZE, 4u,
375 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
376 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID, 0u,
377 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_SIZE, 8u,
378 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
379 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID, 0u,
380 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_SIZE, 8u,
381 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
382 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID, 0u,
383 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_SIZE, 8u,
384 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
385 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID, 0u,
386 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_SIZE, 8u,
387 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
388 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID, 0u,
389 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_SIZE, 4u,
390 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
391 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID, 0u,
392 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_SIZE, 4u,
393 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
394 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID, 0u,
395 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_SIZE, 4u,
396 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
397 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID, 0u,
398 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_SIZE, 4u,
399 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
400 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID, 0u,
401 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_SIZE, 4u,
402 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
403 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID, 0u,
404 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_SIZE, 4u,
405 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
406 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID, 0u,
407 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_SIZE, 4u,
408 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
409 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID, 0u,
410 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_SIZE, 4u,
411 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
412 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID, 0u,
413 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_SIZE, 4u,
414 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
415 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID, 0u,
416 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_SIZE, 4u,
417 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
418 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID, 0u,
419 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_SIZE, 4u,
420 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
421 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID, 0u,
422 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_SIZE, 4u,
423 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
424 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID, 0u,
425 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_SIZE, 4u,
426 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
427 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID, 0x0u,
428 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_SIZE, 4u,
429 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_WIDTH, ((bool)true) },
430 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID, 0x0u,
431 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_SIZE, 4u,
432 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_WIDTH, ((bool)true) },
433 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID, 0x00080000u,
434 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_SIZE, 4u,
435 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_WIDTH, ((bool)true) },
436 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID, 0x00080000u,
437 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_SIZE, 4u,
438 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_WIDTH, ((bool)true) },
439 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID, 0x00080000u,
440 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_SIZE, 4u,
441 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_WIDTH, ((bool)true) },
442 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID, 0x00080000u,
443 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_SIZE, 4u,
444 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_WIDTH, ((bool)true) },
445 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
446 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_SIZE, 4u,
447 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
448 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID, 0,
449 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_SIZE, 4u,
450 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
451 };
452
457 static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
458 {
459 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID, 0u,
460 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_SIZE, 4u,
461 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ROW_WIDTH, ((bool)false) },
462 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID, 0u,
463 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_SIZE, 4u,
464 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ROW_WIDTH, ((bool)false) },
465 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID, 0u,
466 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_SIZE, 4u,
467 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ROW_WIDTH, ((bool)false) },
468 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID, 0u,
469 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_SIZE, 4u,
470 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ROW_WIDTH, ((bool)false) },
471 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID, 0u,
472 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_SIZE, 8u,
473 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ROW_WIDTH, ((bool)false) },
474 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID, 0u,
475 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_SIZE, 8u,
476 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ROW_WIDTH, ((bool)false) },
477 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID, 0u,
478 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_SIZE, 8u,
479 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ROW_WIDTH, ((bool)false) },
480 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID, 0u,
481 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_SIZE, 8u,
482 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ROW_WIDTH, ((bool)false) },
483 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID, 0u,
484 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_SIZE, 4u,
485 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ROW_WIDTH, ((bool)false) },
486 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID, 0u,
487 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_SIZE, 4u,
488 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ROW_WIDTH, ((bool)false) },
489 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID, 0u,
490 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_SIZE, 4u,
491 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ROW_WIDTH, ((bool)false) },
492 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID, 0u,
493 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_SIZE, 4u,
494 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ROW_WIDTH, ((bool)false) },
495 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID, 0u,
496 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_SIZE, 4u,
497 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ROW_WIDTH, ((bool)false) },
498 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID, 0u,
499 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_SIZE, 4u,
500 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ROW_WIDTH, ((bool)false) },
501 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID, 0u,
502 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_SIZE, 4u,
503 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ROW_WIDTH, ((bool)false) },
504 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID, 0u,
505 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_SIZE, 4u,
506 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ROW_WIDTH, ((bool)false) },
507 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID, 0u,
508 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_SIZE, 4u,
509 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ROW_WIDTH, ((bool)false) },
510 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID, 0u,
511 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_SIZE, 4u,
512 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ROW_WIDTH, ((bool)false) },
513 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID, 0u,
514 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_SIZE, 4u,
515 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ROW_WIDTH, ((bool)false) },
516 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID, 0u,
517 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_SIZE, 4u,
518 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ROW_WIDTH, ((bool)false) },
519 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID, 0u,
520 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_SIZE, 4u,
521 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ROW_WIDTH, ((bool)false) },
522 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID, 0x00008000u,
523 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_SIZE, 4u,
524 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ROW_WIDTH, ((bool)true) },
525 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID, 0x00008000u,
526 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_SIZE, 4u,
527 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ROW_WIDTH, ((bool)true) },
528 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID, 0x00088000u,
529 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_SIZE, 4u,
530 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ROW_WIDTH, ((bool)true) },
531 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID, 0x00088000u,
532 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_SIZE, 4u,
533 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ROW_WIDTH, ((bool)true) },
534 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID, 0x00088000u,
535 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_SIZE, 4u,
536 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ROW_WIDTH, ((bool)true) },
537 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID, 0x00088000u,
538 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_SIZE, 4u,
539 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ROW_WIDTH, ((bool)true) },
540 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID, 0x50f02000u,
541 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_SIZE, 4u,
542 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ROW_WIDTH, ((bool)true) },
543 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID, 0,
544 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_SIZE, 4u,
545 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ROW_WIDTH, ((bool)false) },
546 };
547
552 static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
553 {
554 { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID, 0u,
555 SDL_HSM_ECC_AGGR_RAMB0_RAM_SIZE, 4u,
556 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
557 { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID, 0u,
558 SDL_HSM_ECC_AGGR_RAMB1_RAM_SIZE, 4u,
559 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
560 { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID, 0u,
561 SDL_HSM_ECC_AGGR_RAMB2_RAM_SIZE, 4u,
562 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
563 { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID, 0u,
564 SDL_HSM_ECC_AGGR_RAMB3_RAM_SIZE, 4u,
565 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
566 { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID, 0u,
567 SDL_HSM_ECC_AGGR_SECUREB4_RAM_SIZE, 4u,
568 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
569 { SDL_HSM_ECC_AGGR_MBOX_RAM_ID, 0u,
570 SDL_HSM_ECC_AGGR_MBOX_RAM_SIZE, 4u,
571 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
572 { SDL_HSM_ECC_AGGR_SECURE_RAM_ID, 0u,
573 SDL_HSM_ECC_AGGR_SECURE_RAM_SIZE, 4u,
574 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
575 { SDL_HSM_ECC_AGGR_ROM_RAM_ID, 0u,
576 SDL_HSM_ECC_AGGR_ROM_RAM_SIZE, 4u,
577 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
578 { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID, 0u,
579 SDL_HSM_ECC_AGGR_TPTC_A0_RAM_SIZE, 8u,
580 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
581 { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID, 0u,
582 SDL_HSM_ECC_AGGR_TPTC_A1_RAM_SIZE, 8u,
583 SDL_ECC_WIDTH_UNDEFINED, ((bool)false) },
584 };
585
590 static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
591 {
592 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID, 0x48000000u,
593 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_SIZE, 4u,
594 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ROW_WIDTH, ((bool)true) },
595 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID, 0x48002000u,
596 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_SIZE, 4u,
597 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ROW_WIDTH, ((bool)true) },
598 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID, 0x48034000u,
599 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_SIZE, 4u,
600 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ROW_WIDTH, ((bool)true) },
601 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID, 0x48038000u,
602 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_SIZE, 4u,
603 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ROW_WIDTH, ((bool)true) },
604 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID, 0x48010000u,
605 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_SIZE, 4u,
606 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ROW_WIDTH, ((bool)true) },
607 };
608
613 static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
614 {
615 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52600000u,
616 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
617 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
618 };
619
624 static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
625 {
626 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52610000u,
627 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
628 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
629 };
630
635 static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
636 {
637 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52620000u,
638 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
639 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
640 };
641
646 static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
647 {
648 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52630000u,
649 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
650 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
651 };
652
657 static const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
658 {
659 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52640000u,
660 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
661 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
662 };
663
668 static const SDL_MemConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
669 {
670 { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52650000u,
671 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
672 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
673 };
674
679 static const SDL_MemConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
680 {
681 { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52660000u,
682 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
683 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
684 };
685
690 static const SDL_MemConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
691 {
692 { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID, 0x52670000u,
693 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_SIZE, 4u,
694 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ROW_WIDTH, ((bool)true) },
695 };
696
701 static const SDL_MemConfig_t SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries[SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
702 {
703 { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID, 0x53807000u,
704 SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_SIZE, 4u,
705 SDL_FSS_OSPI_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
706 };
707
712 static const SDL_MemConfig_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
713 {
714 { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID, 0x5380f000u,
715 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_SIZE, 4u,
716 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ROW_WIDTH, ((bool)true) },
717 };
718
723 static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES] =
724 {
725 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID, 0x5283E000u,
726 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_SIZE, 71u,
727 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ROW_WIDTH, ((bool)true) },
728 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID, 0u,
729 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_SIZE, 32u,
730 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ROW_WIDTH, ((bool)false) },
731 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID, 0u,
732 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_SIZE, 32u,
733 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ROW_WIDTH, ((bool)false) },
734 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID, 0u,
735 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_SIZE, 32u,
736 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ROW_WIDTH, ((bool)false) },
737 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID, 0u,
738 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_SIZE, 32u,
739 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ROW_WIDTH, ((bool)false) },
740 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID, 0u,
741 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_SIZE, 32u,
742 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ROW_WIDTH, ((bool)false) },
743 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID, 0u,
744 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_SIZE, 32u,
745 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ROW_WIDTH, ((bool)false) },
746 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID, 0x52832000u,
747 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_SIZE, 4u,
748 SDL_ECC_WIDTH_UNDEFINED, ((bool)true) },
749 };
754 static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS] =
755 {
756 { SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_RAM_ID,
757 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_INJECT_TYPE,
758 SDL_SOC_ECC_AGGR_MSS_L2_SLV0_ECC_ECC_TYPE,
759 0u,
760 NULL },
761 { SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_RAM_ID,
762 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_INJECT_TYPE,
763 SDL_SOC_ECC_AGGR_MSS_L2_SLV1_ECC_ECC_TYPE,
764 0u,
765 NULL },
766 { SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_RAM_ID,
767 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_INJECT_TYPE,
768 SDL_SOC_ECC_AGGR_MSS_L2_SLV2_ECC_ECC_TYPE,
769 0u,
770 NULL },
771 { SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_RAM_ID,
772 SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_INJECT_TYPE,
773 SDL_SOC_ECC_AGGR_MSS_L2_SLV3_ECC_ECC_TYPE,
774 0u,
775 NULL },
776 { SDL_SOC_ECC_AGGR_MAILBOX_ECC_RAM_ID,
777 SDL_SOC_ECC_AGGR_MAILBOX_ECC_INJECT_TYPE,
778 SDL_SOC_ECC_AGGR_MAILBOX_ECC_ECC_TYPE,
779 0u,
780 NULL },
781 { SDL_SOC_ECC_AGGR_TPTC_A0_ECC_RAM_ID,
782 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_INJECT_TYPE,
783 SDL_SOC_ECC_AGGR_TPTC_A0_ECC_ECC_TYPE,
784 0u,
785 NULL },
786 { SDL_SOC_ECC_AGGR_TPTC_A1_ECC_RAM_ID,
787 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_INJECT_TYPE,
788 SDL_SOC_ECC_AGGR_TPTC_A1_ECC_ECC_TYPE,
789 0u,
790 NULL },
791 { SDL_SOC_ECC_AGGR_MSS_L2_SLV4_ECC_RAM_ID,
792 SDL_SOC_ECC_AGGR_MSS_L2_SLV4_ECC_INJECT_TYPE,
793 SDL_SOC_ECC_AGGR_MSS_L2_SLV4_ECC_ECC_TYPE,
794 0u,
795 NULL },
796 { SDL_SOC_ECC_AGGR_MSS_L2_SLV5_ECC_RAM_ID,
797 SDL_SOC_ECC_AGGR_MSS_L2_SLV5_ECC_INJECT_TYPE,
798 SDL_SOC_ECC_AGGR_MSS_L2_SLV5_ECC_ECC_TYPE,
799 0u,
800 NULL },
801 };
802
807 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS] =
808 {
809 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
810 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
811 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
812 0u,
813 NULL },
814 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
815 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
816 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
817 0u,
818 NULL },
819 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
820 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
821 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
822 0u,
823 NULL },
824 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
825 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
826 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
827 0u,
828 NULL },
829 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
830 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
831 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
832 0u,
833 NULL },
834 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
835 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
836 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
837 0u,
838 NULL },
839 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
840 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
841 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
842 0u,
843 NULL },
844 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
845 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
846 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
847 0u,
848 NULL },
849 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
850 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
851 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
852 0u,
853 NULL },
854 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
855 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
856 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
857 0u,
858 NULL },
859 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
860 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
861 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
862 0u,
863 NULL },
864 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
865 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
866 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
867 0u,
868 NULL },
869 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
870 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
871 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
872 0u,
873 NULL },
874 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
875 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
876 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
877 0u,
878 NULL },
879 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
880 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
881 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
882 0u,
883 NULL },
884 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
885 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
886 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
887 0u,
888 NULL },
889 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
890 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
891 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
892 0u,
893 NULL },
894 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
895 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
896 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
897 0u,
898 NULL },
899 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
900 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
901 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
902 0u,
903 NULL },
904 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
905 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
906 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
907 0u,
908 NULL },
909 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
910 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
911 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
912 0u,
913 NULL },
914 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
915 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
916 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
917 0u,
918 NULL },
919 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
920 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
921 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
922 0u,
923 NULL },
924 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
925 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
926 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
927 0u,
928 NULL },
929 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
930 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
931 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
932 0u,
933 NULL },
934 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
935 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
936 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
937 0u,
938 NULL },
939 { SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
940 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
941 SDL_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
942 0u,
943 NULL },
944 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
945 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
946 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
947 0u,
948 NULL },
949 { SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID,
950 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_INJECT_TYPE,
951 SDL_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ECC_TYPE,
952 0u,
953 NULL },
954 };
955
960 static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS] =
961 {
962 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
963 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
964 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
965 0u,
966 NULL },
967 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
968 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
969 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
970 0u,
971 NULL },
972 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
973 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
974 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
975 0u,
976 NULL },
977 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
978 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
979 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
980 0u,
981 NULL },
982 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
983 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
984 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
985 0u,
986 NULL },
987 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
988 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
989 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
990 0u,
991 NULL },
992 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
993 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
994 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
995 0u,
996 NULL },
997 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
998 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
999 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
1000 0u,
1001 NULL },
1002 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
1003 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
1004 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
1005 0u,
1006 NULL },
1007 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
1008 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
1009 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
1010 0u,
1011 NULL },
1012 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
1013 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
1014 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
1015 0u,
1016 NULL },
1017 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
1018 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
1019 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
1020 0u,
1021 NULL },
1022 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
1023 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
1024 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
1025 0u,
1026 NULL },
1027 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
1028 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
1029 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
1030 0u,
1031 NULL },
1032 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
1033 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
1034 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
1035 0u,
1036 NULL },
1037 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
1038 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
1039 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
1040 0u,
1041 NULL },
1042 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
1043 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
1044 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
1045 0u,
1046 NULL },
1047 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
1048 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
1049 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
1050 0u,
1051 NULL },
1052 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
1053 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
1054 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
1055 0u,
1056 NULL },
1057 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
1058 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
1059 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
1060 0u,
1061 NULL },
1062 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
1063 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
1064 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
1065 0u,
1066 NULL },
1067 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
1068 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
1069 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
1070 0u,
1071 NULL },
1072 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
1073 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
1074 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
1075 0u,
1076 NULL },
1077 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
1078 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
1079 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
1080 0u,
1081 NULL },
1082 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
1083 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
1084 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
1085 0u,
1086 NULL },
1087 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
1088 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
1089 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
1090 0u,
1091 NULL },
1092 { SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
1093 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
1094 SDL_R5FSS0_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
1095 0u,
1096 NULL },
1097 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
1098 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
1099 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
1100 0u,
1101 NULL },
1102 { SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID,
1103 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_INJECT_TYPE,
1104 SDL_R5FSS0_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ECC_TYPE,
1105 0u,
1106 NULL },
1107 };
1112 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS] =
1113 {
1114 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_RAM_ID,
1115 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
1116 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE,
1117 0u,
1118 NULL },
1119 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_RAM_ID,
1120 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
1121 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE,
1122 0u,
1123 NULL },
1124 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_RAM_ID,
1125 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
1126 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE,
1127 0u,
1128 NULL },
1129 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_RAM_ID,
1130 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
1131 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE,
1132 0u,
1133 NULL },
1134 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_RAM_ID,
1135 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
1136 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE,
1137 0u,
1138 NULL },
1139 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_RAM_ID,
1140 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
1141 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE,
1142 0u,
1143 NULL },
1144 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_RAM_ID,
1145 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
1146 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE,
1147 0u,
1148 NULL },
1149 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_RAM_ID,
1150 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
1151 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE,
1152 0u,
1153 NULL },
1154 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_RAM_ID,
1155 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
1156 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE,
1157 0u,
1158 NULL },
1159 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_RAM_ID,
1160 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
1161 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE,
1162 0u,
1163 NULL },
1164 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_RAM_ID,
1165 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
1166 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE,
1167 0u,
1168 NULL },
1169 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_RAM_ID,
1170 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
1171 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE,
1172 0u,
1173 NULL },
1174 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_RAM_ID,
1175 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
1176 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE,
1177 0u,
1178 NULL },
1179 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_RAM_ID,
1180 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
1181 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE,
1182 0u,
1183 NULL },
1184 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_RAM_ID,
1185 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
1186 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE,
1187 0u,
1188 NULL },
1189 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_RAM_ID,
1190 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
1191 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE,
1192 0u,
1193 NULL },
1194 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_RAM_ID,
1195 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
1196 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE,
1197 0u,
1198 NULL },
1199 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_RAM_ID,
1200 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
1201 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE,
1202 0u,
1203 NULL },
1204 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_RAM_ID,
1205 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
1206 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE,
1207 0u,
1208 NULL },
1209 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_RAM_ID,
1210 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
1211 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE,
1212 0u,
1213 NULL },
1214 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_RAM_ID,
1215 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
1216 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE,
1217 0u,
1218 NULL },
1219 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_RAM_ID,
1220 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
1221 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE,
1222 0u,
1223 NULL },
1224 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_RAM_ID,
1225 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
1226 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE,
1227 0u,
1228 NULL },
1229 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_RAM_ID,
1230 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
1231 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE,
1232 0u,
1233 NULL },
1234 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_RAM_ID,
1235 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
1236 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE,
1237 0u,
1238 NULL },
1239 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_RAM_ID,
1240 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
1241 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE,
1242 0u,
1243 NULL },
1244 { SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_RAM_ID,
1245 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
1246 SDL_R5FSS1_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE,
1247 0u,
1248 NULL },
1249 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_RAM_ID,
1250 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE,
1251 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE,
1252 0u,
1253 NULL },
1254 { SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_RAM_ID,
1255 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_INJECT_TYPE,
1256 SDL_R5FSS1_CORE0_ECC_AGGR_CPU0_KS_RL2_RAMECC_ECC_TYPE,
1257 0u,
1258 NULL },
1259 };
1260
1265 static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS] =
1266 {
1267 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_RAM_ID,
1268 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_INJECT_TYPE,
1269 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM0_ECC_TYPE,
1270 0u,
1271 NULL },
1272 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_RAM_ID,
1273 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_INJECT_TYPE,
1274 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM1_ECC_TYPE,
1275 0u,
1276 NULL },
1277 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_RAM_ID,
1278 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_INJECT_TYPE,
1279 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM2_ECC_TYPE,
1280 0u,
1281 NULL },
1282 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_RAM_ID,
1283 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_INJECT_TYPE,
1284 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_ITAG_RAM3_ECC_TYPE,
1285 0u,
1286 NULL },
1287 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_RAM_ID,
1288 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_INJECT_TYPE,
1289 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK0_ECC_TYPE,
1290 0u,
1291 NULL },
1292 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_RAM_ID,
1293 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_INJECT_TYPE,
1294 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK1_ECC_TYPE,
1295 0u,
1296 NULL },
1297 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_RAM_ID,
1298 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_INJECT_TYPE,
1299 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK2_ECC_TYPE,
1300 0u,
1301 NULL },
1302 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_RAM_ID,
1303 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_INJECT_TYPE,
1304 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_IDATA_BANK3_ECC_TYPE,
1305 0u,
1306 NULL },
1307 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_RAM_ID,
1308 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_INJECT_TYPE,
1309 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM0_ECC_TYPE,
1310 0u,
1311 NULL },
1312 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_RAM_ID,
1313 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_INJECT_TYPE,
1314 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM1_ECC_TYPE,
1315 0u,
1316 NULL },
1317 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_RAM_ID,
1318 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_INJECT_TYPE,
1319 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM2_ECC_TYPE,
1320 0u,
1321 NULL },
1322 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_RAM_ID,
1323 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_INJECT_TYPE,
1324 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DTAG_RAM3_ECC_TYPE,
1325 0u,
1326 NULL },
1327 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_RAM_ID,
1328 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_INJECT_TYPE,
1329 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDIRTY_RAM_ECC_TYPE,
1330 0u,
1331 NULL },
1332 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_RAM_ID,
1333 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_INJECT_TYPE,
1334 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM0_ECC_TYPE,
1335 0u,
1336 NULL },
1337 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_RAM_ID,
1338 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_INJECT_TYPE,
1339 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM1_ECC_TYPE,
1340 0u,
1341 NULL },
1342 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_RAM_ID,
1343 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_INJECT_TYPE,
1344 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM2_ECC_TYPE,
1345 0u,
1346 NULL },
1347 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_RAM_ID,
1348 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_INJECT_TYPE,
1349 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM3_ECC_TYPE,
1350 0u,
1351 NULL },
1352 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_RAM_ID,
1353 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_INJECT_TYPE,
1354 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM4_ECC_TYPE,
1355 0u,
1356 NULL },
1357 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_RAM_ID,
1358 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_INJECT_TYPE,
1359 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM5_ECC_TYPE,
1360 0u,
1361 NULL },
1362 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_RAM_ID,
1363 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_INJECT_TYPE,
1364 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM6_ECC_TYPE,
1365 0u,
1366 NULL },
1367 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_RAM_ID,
1368 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_INJECT_TYPE,
1369 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_DDATA_RAM7_ECC_TYPE,
1370 0u,
1371 NULL },
1372 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_RAM_ID,
1373 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_INJECT_TYPE,
1374 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK0_ECC_TYPE,
1375 0u,
1376 NULL },
1377 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_RAM_ID,
1378 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_INJECT_TYPE,
1379 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_ATCM1_BANK1_ECC_TYPE,
1380 0u,
1381 NULL },
1382 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_RAM_ID,
1383 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_INJECT_TYPE,
1384 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK0_ECC_TYPE,
1385 0u,
1386 NULL },
1387 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_RAM_ID,
1388 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_INJECT_TYPE,
1389 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B0TCM1_BANK1_ECC_TYPE,
1390 0u,
1391 NULL },
1392 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_RAM_ID,
1393 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_INJECT_TYPE,
1394 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK0_ECC_TYPE,
1395 0u,
1396 NULL },
1397 { SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_RAM_ID,
1398 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_INJECT_TYPE,
1399 SDL_R5FSS1_CORE1_ECC_AGGR_PULSAR_SL_B1TCM1_BANK1_ECC_TYPE,
1400 0u,
1401 NULL },
1402 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_RAM_ID,
1403 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_INJECT_TYPE,
1404 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_VIM_RAMECC_ECC_TYPE,
1405 0u,
1406 NULL },
1407 { SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_RAM_ID,
1408 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_INJECT_TYPE,
1409 SDL_R5FSS1_CORE1_ECC_AGGR_CPU1_KS_RL2_RAMECC_ECC_TYPE,
1410 0u,
1411 NULL },
1412 };
1413
1418 static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS] =
1419 {
1420 { SDL_HSM_ECC_AGGR_RAMB0_RAM_ID,
1421 SDL_HSM_ECC_AGGR_RAMB0_INJECT_TYPE,
1422 SDL_HSM_ECC_AGGR_RAMB0_ECC_TYPE,
1423 0u,
1424 NULL },
1425 { SDL_HSM_ECC_AGGR_RAMB1_RAM_ID,
1426 SDL_HSM_ECC_AGGR_RAMB1_INJECT_TYPE,
1427 SDL_HSM_ECC_AGGR_RAMB1_ECC_TYPE,
1428 0u,
1429 NULL },
1430 { SDL_HSM_ECC_AGGR_RAMB2_RAM_ID,
1431 SDL_HSM_ECC_AGGR_RAMB2_INJECT_TYPE,
1432 SDL_HSM_ECC_AGGR_RAMB2_ECC_TYPE,
1433 0u,
1434 NULL },
1435 { SDL_HSM_ECC_AGGR_RAMB3_RAM_ID,
1436 SDL_HSM_ECC_AGGR_RAMB3_INJECT_TYPE,
1437 SDL_HSM_ECC_AGGR_RAMB3_ECC_TYPE,
1438 0u,
1439 NULL },
1440 { SDL_HSM_ECC_AGGR_SECUREB4_RAM_ID,
1441 SDL_HSM_ECC_AGGR_SECUREB4_INJECT_TYPE,
1442 SDL_HSM_ECC_AGGR_SECUREB4_ECC_TYPE,
1443 0u,
1444 NULL },
1445 { SDL_HSM_ECC_AGGR_MBOX_RAM_ID,
1446 SDL_HSM_ECC_AGGR_MBOX_INJECT_TYPE,
1447 SDL_HSM_ECC_AGGR_MBOX_ECC_TYPE,
1448 0u,
1449 NULL },
1450 { SDL_HSM_ECC_AGGR_SECURE_RAM_ID,
1451 SDL_HSM_ECC_AGGR_SECURE_INJECT_TYPE,
1452 SDL_HSM_ECC_AGGR_SECURE_ECC_TYPE,
1453 0u,
1454 NULL },
1455 { SDL_HSM_ECC_AGGR_ROM_RAM_ID,
1456 SDL_HSM_ECC_AGGR_ROM_INJECT_TYPE,
1457 SDL_HSM_ECC_AGGR_ROM_ECC_TYPE,
1458 0u,
1459 NULL },
1460 { SDL_HSM_ECC_AGGR_TPTC_A0_RAM_ID,
1461 SDL_HSM_ECC_AGGR_TPTC_A0_INJECT_TYPE,
1462 SDL_HSM_ECC_AGGR_TPTC_A0_ECC_TYPE,
1463 0u,
1464 NULL },
1465 { SDL_HSM_ECC_AGGR_TPTC_A1_RAM_ID,
1466 SDL_HSM_ECC_AGGR_TPTC_A1_INJECT_TYPE,
1467 SDL_HSM_ECC_AGGR_TPTC_A1_ECC_TYPE,
1468 0u,
1469 NULL },
1470 };
1471
1476 static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS] =
1477 {
1478 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_RAM_ID,
1479 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_INJECT_TYPE,
1480 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM0_ECC_ECC_TYPE,
1481 0u,
1482 NULL },
1483 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_RAM_ID,
1484 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_INJECT_TYPE,
1485 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_DRAM1_ECC_ECC_TYPE,
1486 0u,
1487 NULL },
1488 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_RAM_ID,
1489 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_INJECT_TYPE,
1490 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP0_IRAM_ECC_ECC_TYPE,
1491 0u,
1492 NULL },
1493 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_RAM_ID,
1494 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_INJECT_TYPE,
1495 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_PR1_PDSP1_IRAM_ECC_ECC_TYPE,
1496 0u,
1497 NULL },
1498 { SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_RAM_ID,
1499 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_INJECT_TYPE,
1500 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_ICSS_G_CORE_RAM_ECC_ECC_TYPE,
1501 0u,
1502 NULL },
1503 };
1504
1509 static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1510 {
1511 { SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1512 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1513 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1514 0u,
1515 NULL }
1516 };
1517
1522 static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1523 {
1524 { SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1525 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1526 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1527 0u,
1528 NULL }
1529 };
1530
1535 static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1536 {
1537 { SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1538 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1539 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1540 0u,
1541 NULL }
1542 };
1543
1548 static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1549 {
1550 { SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1551 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1552 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1553 0u,
1554 NULL }
1555 };
1556
1561 static const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1562 {
1563 { SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1564 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1565 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1566 0u,
1567 NULL }
1568 };
1569
1574 static const SDL_RAMIdEntry_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1575 {
1576 { SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1577 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1578 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1579 0u,
1580 NULL }
1581 };
1582
1587 static const SDL_RAMIdEntry_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1588 {
1589 { SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1590 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1591 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1592 0u,
1593 NULL }
1594 };
1595
1600 static const SDL_RAMIdEntry_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS] =
1601 {
1602 { SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_RAM_ID,
1603 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_INJECT_TYPE,
1604 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MCANSS_MSGMEM_WRAP_MSGMEM_ECC_ECC_TYPE,
1605 0u,
1606 NULL }
1607 };
1608
1613 static const SDL_RAMIdEntry_t SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable[SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS] =
1614 {
1615 { SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_ID,
1616 SDL_FSS_OSPI_RAM_ECC_AGGR_INJECT_TYPE,
1617 SDL_FSS_OSPI_RAM_ECC_AGGR_ECC_TYPE,
1618 0u,
1619 NULL }
1620 };
1621
1626 static const SDL_RAMIdEntry_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS] =
1627 {
1628 { SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_ID,
1629 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_INJECT_TYPE,
1630 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_ECC_TYPE,
1631 0u,
1632 NULL }
1633 };
1634
1635
1640 static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS] =
1641 {
1642 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_RAM_ID,
1643 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_INJECT_TYPE,
1644 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_ALE_RAM_ECC_ECC_TYPE,
1645 0u,
1646 NULL },
1647 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_RAM_ID,
1648 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_INJECT_TYPE,
1649 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL1_ECC_ECC_TYPE,
1650 0u,
1651 NULL },
1652 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_RAM_ID,
1653 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_INJECT_TYPE,
1654 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL2_ECC_ECC_TYPE,
1655 0u,
1656 NULL },
1657 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_RAM_ID,
1658 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_INJECT_TYPE,
1659 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL3_ECC_ECC_TYPE,
1660 0u,
1661 NULL },
1662 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_RAM_ID,
1663 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_INJECT_TYPE,
1664 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL4_ECC_ECC_TYPE,
1665 0u,
1666 NULL },
1667 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_RAM_ID,
1668 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_INJECT_TYPE,
1669 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL5_ECC_ECC_TYPE,
1670 0u,
1671 NULL },
1672 { SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_RAM_ID,
1673 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_INJECT_TYPE,
1674 SDL_CPSW3GCSS_ECC_AGGR_CPSW_3GC_CORE_ECC_ECC_CTRL6_ECC_ECC_TYPE,
1675 0u,
1676 NULL },
1677 { SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_RAM_ID,
1678 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_INJECT_TYPE,
1679 SDL_CPSW3GCSS_ECC_AGGR_CPSW3GCSS_EST_RAM_ECC_ECC_TYPE,
1680 0u,
1681 NULL },
1682 };
1683
1684 static SDL_ecc_aggrRegs * const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES] =
1685 {
1686 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_TOP_U_BASE)),
1687 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE0_U_BASE)),
1688 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS0_CORE1_U_BASE)),
1689 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE0_U_BASE)),
1690 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ECC_AGG_R5SS1_CORE1_U_BASE )),
1691 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_HSM_ECC_AGGR_U_BASE)),
1692 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_ICSSM0_ECC_U_BASE)),
1693 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN0_ECC_U_BASE)),
1694 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN1_ECC_U_BASE)),
1695 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN2_ECC_U_BASE)),
1696 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN3_ECC_U_BASE)),
1697 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN4_ECC_U_BASE)),
1698 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN5_ECC_U_BASE)),
1699 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN6_ECC_U_BASE)),
1700 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_MCAN7_ECC_U_BASE)),
1701 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_OSPI_ECC_U_BASE)),
1702 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_FOTA_ECC_U_BASE)),
1703 ((SDL_ecc_aggrRegs *)((uintptr_t)SDL_CPSW0_ECC_U_BASE)),
1704 };
1705
1706 SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX];
1709 static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX] =
1710 {
1711
1712 /* Index: SDL_SOC_ECC_AGGR (0) */
1713 {
1714 SDL_SOC_ECC_AGGR_NUM_RAMS,
1715 SDL_SOC_ECC_AGGR_RamIdTable,
1716 SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1717 SDL_SOC_ECC_AGGR_MemEntries,
1718 SDL_ESM_INST_MAIN_ESM0,
1719 SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_CORR_LEVEL,
1720 SDL_ESM0_ECC_AGGREGATOR_SOC_ECCAGG_UNCORR_LEVEL
1721 },
1722 /* Index: SDL_R5FSS0_CORE0_ECC_AGGR (1) */
1723 {
1724 SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS,
1725 SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable,
1726 SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1727 SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1728 SDL_ESM_INST_MAIN_ESM0,
1729 SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0,
1730 SDL_ESM0_R5FSS0_CORE0_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0
1731 },
1732 /* Index: SDL_R5FSS0_CORE1_ECC_AGGR (2) */
1733 {
1734 SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS,
1735 SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable,
1736 SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1737 SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries,
1738 SDL_ESM_INST_MAIN_ESM0,
1739 SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_CORRECTED_LEVEL_0,
1740 SDL_ESM0_R5FSS0_CORE1_R5FSS0_CORE1_ECC_UNCORRECTED_LEVEL_0
1741 },
1742 /* Index: SDL_R5FSS1_CORE0_ECC_AGGR (3) */
1743 {
1744 SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS,
1745 SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable,
1746 SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1747 SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries,
1748 SDL_ESM_INST_MAIN_ESM0,
1749 SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_CORRECTED_LEVEL_0,
1750 SDL_ESM0_R5FSS1_CORE0_R5FSS1_CORE0_ECC_UNCORRECTED_LEVEL_0
1751 },
1752 /* Index: SDL_R5FSS1_CORE1_ECC_AGGR (4) */
1753 {
1754 SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS,
1755 SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable,
1756 SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1757 SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries,
1758 SDL_ESM_INST_MAIN_ESM0,
1759 SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_CORRECTED_LEVEL_0,
1760 SDL_ESM0_R5FSS1_CORE1_R5FSS1_CORE1_ECC_UNCORRECTED_LEVEL_0
1761 },
1762 /* Index: SDL_HSM_ECC_AGGR (5) */
1763 {
1764 SDL_HSM_ECC_AGGR_NUM_RAMS,
1765 SDL_HSM_ECC_AGGR_RamIdTable,
1766 SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1767 SDL_HSM_ECC_AGGR_MemEntries,
1768 SDL_ESM_INST_MAIN_ESM0,
1769 SDL_ESM0_HSM_ESM_HIGH_INTR,
1770 SDL_ESM0_HSM_ESM_LOW_INTR
1771 },
1772 /* Index: SDL_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR (6) */
1773 {
1774 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS,
1775 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable,
1776 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1777 SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries,
1778 SDL_ESM_INST_MAIN_ESM0,
1779 SDL_ESM0_PRU_ICSSM0_PR1_ECC_SEC_ERR_REQ,
1780 SDL_ESM0_PRU_ICSSM0_PR1_ECC_DED_ERR_REQ
1781 },
1782 /* Index: SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR (7) */
1783 {
1784 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1785 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1786 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1787 SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1788 SDL_ESM_INST_MAIN_ESM0,
1789 SDL_ESM0_MCAN0_MCAN0_ECC_CORR_LVL_INT,
1790 SDL_ESM0_MCAN0_MCAN0_ECC_UNCORR_LVL_INT
1791 },
1792 /* Index: SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR (8) */
1793 {
1794 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1795 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1796 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1797 SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1798 SDL_ESM_INST_MAIN_ESM0,
1799 SDL_ESM0_MCAN1_MCAN1_ECC_CORR_LVL_INT,
1800 SDL_ESM0_MCAN1_MCAN1_ECC_UNCORR_LVL_INT
1801 },
1802 /* Index: SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR (9) */
1803 {
1804 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1805 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1806 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1807 SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1808 SDL_ESM_INST_MAIN_ESM0,
1809 SDL_ESM0_MCAN2_MCAN2_ECC_CORR_LVL_INT,
1810 SDL_ESM0_MCAN2_MCAN2_ECC_UNCORR_LVL_INT
1811 },
1812 /* Index: SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR (10) */
1813 {
1814 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1815 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1816 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1817 SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1818 SDL_ESM_INST_MAIN_ESM0,
1819 SDL_ESM0_MCAN3_MCAN3_ECC_CORR_LVL_INT,
1820 SDL_ESM0_MCAN3_MCAN3_ECC_UNCORR_LVL_INT
1821 },
1822 /* Index: SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR (11) */
1823 {
1824 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1825 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1826 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1827 SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1828 SDL_ESM_INST_MAIN_ESM0,
1829 SDL_ESM0_MCAN4_MCAN4_ECC_CORR_PLS_INT,
1830 SDL_ESM0_MCAN4_MCAN4_ECC_UNCORR_LVL_INT
1831 },
1832 /* Index: SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR (12) */
1833 {
1834 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1835 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1836 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1837 SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1838 SDL_ESM_INST_MAIN_ESM0,
1839 SDL_ESM0_MCAN5_MCAN5_ECC_CORR_LVL_INT,
1840 SDL_ESM0_MCAN5_MCAN5_ECC_UNCORR_LVL_INT
1841 },
1842 /* Index: SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR (13) */
1843 {
1844 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1845 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1846 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1847 SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1848 SDL_ESM_INST_MAIN_ESM0,
1849 SDL_ESM0_MCAN6_MCAN6_ECC_CORR_LVL_INT,
1850 SDL_ESM0_MCAN6_MCAN6_ECC_UNCORR_LVL_INT
1851 },
1852 /* Index: SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR (14) */
1853 {
1854 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS,
1855 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable,
1856 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1857 SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries,
1858 SDL_ESM_INST_MAIN_ESM0,
1859 SDL_ESM0_MCAN7_MCAN7_ECC_CORR_LVL_INT,
1860 SDL_ESM0_MCAN7_MCAN7_ECC_UNCORR_LVL_INT
1861 },
1862 /* Index: SDL_FSS_OSPI_RAM_ECC_AGGR (15) */
1863 {
1864 SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS,
1865 SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable,
1866 SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1867 SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries,
1868 SDL_ESM_INST_MAIN_ESM0,
1869 SDL_ESM0_OSPI_ECC_CORR,
1870 SDL_ESM0_OSPI_ECC_UNCORR
1871 },
1872 /* Index: SDL_FSS_FOTA_8051_RAM_ECC_AGGR (16) */
1873 {
1874 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS,
1875 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable,
1876 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1877 SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries,
1878 SDL_ESM_INST_MAIN_ESM0,
1879 SDL_ESM0_OTFA_ECC_CORR,
1880 SDL_ESM0_OTFA_ECC_UNCORR
1881 },
1882 /* Index: SDL_CPSW3GCSS_ECC_AGGR (17) */
1883 {
1884 SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS,
1885 SDL_CPSW3GCSS_ECC_AGGR_RamIdTable,
1886 SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES,
1887 SDL_CPSW3GCSS_ECC_AGGR_MemEntries,
1888 SDL_ESM_INST_MAIN_ESM0,
1889 SDL_ESM0_CPSW3G_CPSW_ECC_SEC_PEND_INTR,
1890 SDL_ESM0_CPSW3G_CPSW_ECC_DED_PEND_INTR
1891 },
1892
1893
1894 };
1896 #endif /* INCLUDE_SDL_ECC_SOC_H_ */
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:88
SDL_CPSW0_ECC_U_BASE
#define SDL_CPSW0_ECC_U_BASE
Definition: sdl_ecc_soc.h:94
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:657
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:635
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:90
SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:78
SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:75
SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:172
SDL_ecc_aggrRegs
Definition: V1/sdlr_ecc.h:53
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1574
SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1112
SDL_ESM_INST_MAIN_ESM0
@ SDL_ESM_INST_MAIN_ESM0
Definition: sdl_esm_soc.h:66
SDL_ECC_aggrTransBaseAddressTable
SDL_ecc_aggrRegs * SDL_ECC_aggrTransBaseAddressTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1706
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_MemEntries[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:590
SDL_SOC_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_SOC_ECC_AGGR_MemEntries[SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:137
SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:77
SDL_ECC_WIDTH_UNDEFINED
#define SDL_ECC_WIDTH_UNDEFINED
Definition: sdl_ecc_soc.h:71
SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS0_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:267
SDL_SOC_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_SOC_ECC_AGGR_RamIdTable[SDL_SOC_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:754
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:82
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:83
SDL_CPSW3GCSS_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_CPSW3GCSS_ECC_AGGR_RamIdTable[SDL_CPSW3GCSS_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1640
SDL_ECC_aggrBaseAddressTable
static SDL_ecc_aggrRegs *const SDL_ECC_aggrBaseAddressTable[SDL_ECC_Base_Address_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:1684
SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:960
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:87
SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN2_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1535
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1561
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1587
sdl_ip_ecc.h
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_MemEntries[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:712
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:646
SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_FSS_OSPI_RAM_ECC_AGGR_MemEntries[SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:701
SDL_MemConfig_t
Definition: sdl_ecc_priv.h:88
SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_R5FSS0_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:76
SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS_OSPI_RAM_ECC_AGGR_RamIdTable[SDL_FSS_OSPI_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1613
SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE1_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE1_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:457
SDL_HSM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_HSM_ECC_AGGR_RamIdTable[SDL_HSM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1418
sdl_ecc.h
Header file contains enumerations, structure definitions and function.
SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_FSS_FOTA_8051_RAM_ECC_AGGR_RamIdTable[SDL_FSS_FOTA_8051_RAM_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1626
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1522
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:80
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:668
SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_FSS_OSPI_RAM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:89
SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_SOC_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:74
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:690
SDL_FOTA_ECC_U_BASE
#define SDL_FOTA_ECC_U_BASE
Definition: sdl_ecc_soc.h:96
SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_R5FSS1_CORE0_ECC_AGGR_MemEntries[SDL_R5FSS1_CORE0_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:362
SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN5_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:86
SDL_HSM_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_HSM_ECC_AGGR_MemEntries[SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:552
SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN4_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:85
SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_RamIdTable[SDL_PRU_ICSSM_ICSS_G_CORE_BORG_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1476
SDL_RAMIdEntry_t
Definition: sdl_ecc_priv.h:63
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:81
SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN1_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:624
SDL_ECC_aggrTable
static const SDL_EccAggrEntry_t SDL_ECC_aggrTable[SDL_ECC_MEMTYPE_MAX]
Definition: sdl_ecc_soc.h:1709
SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN6_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:679
SDL_EccAggrEntry_t
Definition: sdl_ecc_priv.h:104
SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS1_CORE1_ECC_AGGR_RamIdTable[SDL_R5FSS1_CORE1_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1265
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1509
SDL_CPSW3GCSS_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_CPSW3GCSS_ECC_AGGR_MemEntries[SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:723
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1548
SDL_OSPI_ECC_U_BASE
#define SDL_OSPI_ECC_U_BASE
Definition: sdl_ecc_soc.h:95
SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_HSM_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:79
SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_R5FSS0_CORE0_ECC_AGGR_RamIdTable[SDL_R5FSS0_CORE0_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:807
SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries
static const SDL_MemConfig_t SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_MemEntries[SDL_MCAN0_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES]
Definition: sdl_ecc_soc.h:613
sdl_ecc_priv.h
SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_CPSW3GCSS_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:91
SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable
static const SDL_RAMIdEntry_t SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_RamIdTable[SDL_MCAN7_MCANSS_MSGMEM_WRAP_ECC_AGGR_NUM_RAMS]
Definition: sdl_ecc_soc.h:1600
SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
#define SDL_MCAN3_MCANSS_MSGMEM_WRAP_ECC_AGGR_RAM_IDS_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:84
SDL_ECC_Base_Address_TOTAL_ENTRIES
#define SDL_ECC_Base_Address_TOTAL_ENTRIES
Definition: sdl_ecc_soc.h:92