AM263Px MCU+ SDK: cslr_soc_defines.h Source File

| AM263Px MCU+ SDK 26.00.00 |

cslr_soc_defines.h
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1 /*
2 * Copyright (C) 2020-25 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
34 #ifndef CSLR_SOC_DEFINES_H_
35 #define CSLR_SOC_DEFINES_H_
36
37 /* ========================================================================== */
38 /* Include Files */
39 /* ========================================================================== */
40 #include <stdint.h>
41
42
43
44 #ifdef __cplusplus
45 extern "C" {
46 #endif
47
48 /* ========================================================================== */
49 /* Macros & Typedefs */
50 /* ========================================================================== */
52 #define CSL_UART_PER_CNT (6U)
53
55 #define CSL_SPI_PER_CNT (8U)
56
58 #define CSL_LIN_PER_CNT (5U)
59
61 #define CSL_I2C_PER_CNT (4U)
62
64 #define CSL_MCAN_PER_CNT (8U)
65
67 #define CSL_ETPWM_PER_CNT (32U)
68
70 #define CSL_ECAP_PER_CNT (16U)
71
73 #define CSL_EQEP_PER_CNT (3U)
74
76 #define CSL_SDFM_PER_CNT (2U)
77
79 #define CSL_ADC_PER_CNT (5U)
80
82 #define CSL_CMPSSA_PER_CNT (10U)
83
85 #define CSL_CMPSSB_PER_CNT (10U)
86
88 #define SOC_EDMA_NUM_DMACH (64U)
89
90 #define SOC_EDMA_NUM_QDMACH (8U)
91
92 #define SOC_EDMA_NUM_PARAMSETS (256U)
93
94 #define SOC_EDMA_NUM_EVQUE (2U)
95
96 #define SOC_EDMA_CHMAPEXIST (1U)
97
98 #define SOC_EDMA_NUM_REGIONS (8U)
99
100 #define SOC_EDMA_MEMPROTECT (1U)
101
102 #define SOC_EDMA_NUM_TPTC (2U)
103
110 #define EDMA_TPCC_A_ERRINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT_MASK)
111 #define EDMA_TPCC_A_MPINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_MPINT_MASK)
112 #define EDMA_TPTC_A0_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_ERR_MASK)
113 #define EDMA_TPTC_A1_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_ERR_MASK)
114 #define EDMA_TPCC_A_PAR_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR_MASK)
115 #define EDMA_TPCC_A_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR_MASK)
116 #define EDMA_TPTC_A0_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR_MASK)
117 #define EDMA_TPTC_A1_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR_MASK)
118 #define EDMA_TPCC_A_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR_MASK)
119 #define EDMA_TPTC_A0_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR_MASK)
120 #define EDMA_TPTC_A1_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR_MASK)
121
123 #define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
124
126 #define MCAN_MAX_RX_DMA_BUFFERS (7U)
127
129 #define MCAN_MAX_TX_DMA_BUFFERS (4U)
130
132 #define FSI_MAX_TX_DMA_BUFFERS (2U)
133
135 #define FSI_MAX_RX_DMA_BUFFERS (2U)
136
138 #define MCSPI_DMA_IS_FIFO_SUPPORTED (1U)
139
146 #define CSL_CORE_ID_R5FSS0_0 (0U)
147 #define CSL_CORE_ID_R5FSS0_1 (1U)
148 #define CSL_CORE_ID_R5FSS1_0 (2U)
149 #define CSL_CORE_ID_R5FSS1_1 (3U)
150 #define CSL_CORE_ID_MAX (4U)
151
159 #define PRIV_ID_M4FSS0_0 (1U)
160 #define PRIV_ID_R5FSS0_0 (4U)
161 #define PRIV_ID_R5FSS0_1 (5U)
162 #define PRIV_ID_R5FSS1_0 (6U)
163 #define PRIV_ID_R5FSS1_1 (7U)
164 #define PRIV_ID_ICSSM (9U)
165 #define PRIV_ID_CPSW (10U)
166
169 /***********************************************************************
170 * MSS - CLOCK setting
171 ***********************************************************************/
172 /* Sys_vclk : 200MHz */
173 #define MSS_SYS_VCLK 200000000U
174 #define R5F_CLOCK_MHZ 400U
175
183 #define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
184
185 #define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
186
195 #define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
196
197 #define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
198
201 #define CSL_CORE_R5F_INTR_MAX (256U)
202
203 /***********************************************************************
204 * Cache line size definitions
205 ***********************************************************************/
206 /* Cache line size definitions */
207 #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
208 #define CSL_CACHE_L1P_LINESIZE (32U)
209 #define CSL_CACHE_L1D_LINESIZE (32U)
210 #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') /* M4F */
211 /* No cache support */
212 #endif
213
214 /* ========================================================================== */
215 /* Structures and Enums */
216 /* ========================================================================== */
217
218 /* None */
219
220 /* ========================================================================== */
221 /* Global Variables */
222 /* ========================================================================== */
223
224 /* None */
225
226 /* ========================================================================== */
227 /* Function Declarations */
228 /* ========================================================================== */
229
230 /* None */
231
232 #ifdef __cplusplus
233 }
234 #endif
235
236 #endif /* CSLR_SOC_DEFINES_H_ */