AM263Px MCU+ SDK: SDL DCC Example

| AM263Px MCU+ SDK 26.00.00 |

SDL DCC Example

# Introduction

This example demonstrates how to configure the DCC and use it to monitor clocks in the two supported modes (continuous and single-shot modes). It also demonstrates how to receive errors generated by DCC in the DSP and Main domain.

This example displays:

    * Initializing the ESM to detect the DCC error event(s)
    * Registration of application callback for notification of ESM error events for the MSS ESM instance
    * Configuration of one MSS DCC instance to monitor a single clock in continuous mode
    * Forcing of an error to create a DCC error event

The following methods can be used as a trigger for the DCC error event:

    * Change ratio criterion for stable clocks
    * Turn off power for the monitored input clock

## Use Cases

FOR MSS INSTANCES

Use Case | Reference Clock | Test Clock | Description
--- | --- | --- | ---
UC-0 | XTAL_CLK | "RCCLK32K" | Configuration of MSS DCCA instance in continuous mode and error event is forced
UC-1 | XTAL_CLK | "SYSCLK0" | Configuration of MSS DCCA instance in single-shot mode and completion with no errors
UC-2 | XTAL_CLK | "SYSCLK0" | Configuration of MSS DCCA instance in continuous mode and error event is forced
UC-3 | "RCCLK10M" | "SYS_CLK0" | Configuration of MSS DCCA instance in single-shot mode and completion with no errors
UC-4 | "RCCLK10M" | "RCCLK32K" | Configuration of MSS DCCD instance in continuous mode and error event is forced
UC-5 | "RCCLK10M" | "RCCLK32K" | Configuration of MSS DCCD instance in continuous mode and error event is forced
UC-6 | XTAL_CLK | "RCCLK32K" | Configuration of MSS DCCD instance in continuous mode and completion with no errors
UC-7 | XTAL_CLK | "MAIN_SYSCLK0" | Configuration of MSS DCCD instance in continuous mode and completion with no errors
UC-8 | "RCCLK10M" | "XTAL_CLK" | Configuration of MSS DCCA instance in continuous mode and completion with no errors

# Supported Combinations

Parameter | Value
--- | ---
CPU + OS | r5fss0-0 nortos
r5fss1-0 nortos
Toolchain | ti-arm-clang
Board | am263px-cc
Example folder | examples/sdl/dcc/dcc_modes1/

# Steps to Run the Example

- When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
- When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
- Launch a CCS debug session and run the executable, see CCS Launch, Load and Run

# See Also

DCC

# Sample Output

Shown below is a sample output when the application is run,

DCC Example Test Application
DCC_Test_init: Init ESM complete
USECASE: 0
Source clock: XTAL_CLK
Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Warning Seed value for valid count exceeds allowed range.
SDL DCC EXAMPLE TEST: Application will run with 0 allowed drift.
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-0 Completed Successfully
USECASE: 1
Source clock: XTAL_CLK
Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-1 Completed Successfully
USECASE: 2
Source clock: XTAL_CLK
Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
UC-2 Completed Successfully
USECASE: 3
Source clock: RCCLK10M
Test clock: SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: DCC Generated completion interrupt
SDL DCC EXAMPLE TEST: No Clock Drift was observed
UC-3 Completed Successfully
USECASE: 4
Source clock: RCCLK10M
Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Warning Seed value for valid count exceeds allowed range.
SDL DCC EXAMPLE TEST: Application will run with 0 allowed drift.
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-4 Completed Successfully
USECASE: 5
Source clock: RCCLK10M
Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Warning Seed value for valid count exceeds allowed range.
SDL DCC EXAMPLE TEST: Application will run with 0 allowed drift.
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-5 Completed Successfully
USECASE: 6
Source clock: XTAL_CLK
Test clock: RCCLK32K
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
UC-6 Completed Successfully
USECASE: 7
Source clock: XTAL_CLK
Test clock: MAIN_SYSCLK0
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and waiting for Error interrupt
SDL DCC EXAMPLE TEST: DCC Generated Error interrupt
SDL DCC EXAMPLE TEST: Indicating clock drift/change
UC-7 Completed Successfully
USECASE: 8
Source clock: RCCLK10M
Test clock: XTAL_CLK
SDL DCC EXAMPLE TEST: Seed values calculation done.
SDL DCC EXAMPLE TEST: Enabling DCC and running for some time
UC-8 Completed Successfully
All tests have passed.