AM263Px MCU+ SDK: sipc_notify_mailbox.h Source File

| AM263Px MCU+ SDK 26.00.00 |

sipc_notify_mailbox.h
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1 /*
2 * Copyright (C) 2022 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
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17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #ifndef SIPC_NOTIFY_MAILBOX_H_
34 #define SIPC_NOTIFY_MAILBOX_H_
35
36 #ifdef __cplusplus
37 extern "C" {
38 #endif
39
40 #include <stdint.h>
41 #include <stdlib.h>
42 #include <string.h>
43
44 /* this file has define's and inline function's to program the HW mailbox registers and SW queue structure */
45 #define MAILBOX_MAX_SW_QUEUE_STRUCT_SIZE (sizeof(SIPC_SwQueue))
46
47 /* The HW mailbox only allows to trigger a interrupt on another core,
48 * the SIPC Notify needs ability to pass x byte message along with a interrupt
49 *
50 * Basically this mimics the functionality of HW mailbox with HW FIFO in AM243x SOC
51 *
52 * This needs to be in sync with the addresses being set for SW queue memory in soc/{soc}/sipc_notify_cfg.c
53 *
54 * The new queue has two more parameters i.e EleSize = Size of 1 queue element in words
55 * Qlength = total length of this Queue */
56
62 typedef struct SIPC_SwQueue_
63 {
64 volatile uint32_t rdIdx;
65 volatile uint32_t wrIdx;
66 uint16_t EleSize ;
67 uint16_t Qlength ;
68 uint8_t *Qfifo;
69 } SIPC_SwQueue;
70
71 #if defined(__aarch64__) || defined(__arm__)
72 static inline void asm_dsb_memory(void)
73 {
74 __asm__ __volatile__( "dsb sy" "\n\t": : : "memory");
75 }
76
77 static inline void asm_isb_memory(void)
78 {
79 __asm__ __volatile__( "isb" "\n\t": : : "memory");
80 }
81 #endif
82
83 /* Read from SW fifo within a mailbox */
84 static inline int32_t SIPC_mailboxRead(SIPC_SwQueue *swQ, uint8_t *Buff)
85 {
86 int32_t status = SystemP_FAILURE;
87
88 uint32_t rdIdx = swQ->rdIdx;
89 uint32_t wrIdx = swQ->wrIdx;
90
91 if((rdIdx < swQ->Qlength) && (wrIdx < swQ->Qlength))
92 {
93 /* If this condition meets then it means there is something in the fifo*/
94 if( rdIdx != wrIdx)
95 {
96 /* Copy EleSize bytes from Queue memory to the buffer */
97 (void)memcpy(Buff, SOC_phyToVirt((uint64_t)(swQ->Qfifo + (swQ->EleSize*rdIdx))),swQ->EleSize);
98
99 rdIdx = (rdIdx+1U)%swQ->Qlength;
100
101 swQ->rdIdx = rdIdx;
102
103 rdIdx = swQ->rdIdx; /* read back to ensure the update has reached the memory */
104
105 if (rdIdx < swQ->rdIdx) /*To suppress MISRA warning*/
106 {
107 /*Do nothing*/
108 }
109 #if defined(__aarch64__) || defined(__arm__)
110 asm_dsb_memory();
111 asm_isb_memory();
112 #endif
113
114 status = SystemP_SUCCESS;
115 }
116 }
117
118 return status;
119 }
120
121 /* Write to SW fifo and trigger HW interrupt using HW mailbox */
122 static inline int32_t SIPC_mailboxWrite(uint32_t mailboxBaseAddr, uint32_t wrIntrBitPos, SIPC_SwQueue *swQ, uint8_t *Buff)
123 {
124 int32_t status = SystemP_FAILURE;
125
126 volatile uint32_t rdIdx = swQ->rdIdx;
127 volatile uint32_t wrIdx = swQ->wrIdx;
128
129 if((rdIdx < swQ->Qlength) && (wrIdx < swQ->Qlength))
130 {
131 if( ( (wrIdx+1U)%swQ->Qlength ) != rdIdx )
132 {
133 volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
134
135 /* There is some space in the FIFO */
136
137 (void)memcpy(SOC_phyToVirt((uint64_t)(swQ->Qfifo + (swQ->EleSize*wrIdx))),Buff,swQ->EleSize);
138
139 wrIdx = (wrIdx+1U)%swQ->Qlength;
140
141 swQ->wrIdx = wrIdx;
142
143 wrIdx = swQ->wrIdx; /* read back to ensure the update has reached the memory */
144
145 #if defined(__aarch64__) || defined(__arm__)
146 asm_dsb_memory();
147 asm_isb_memory();
148 #endif
149
150 /* Trigger interrupt to other core */
151 *addr = (1U << (wrIntrBitPos));
152
153 status = SystemP_SUCCESS;
154 }
155 }
156 return status;
157 }
158
159 static inline void SIPC_mailboxClearAllInt(uint32_t mailboxBaseAddr)
160 {
161 volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
162 *addr = 0x1111111U;
163 }
164
165 static inline uint32_t SIPC_mailboxGetPendingIntr(uint32_t mailboxBaseAddr)
166 {
167 volatile uint32_t *addr = (uint32_t *)mailboxBaseAddr;
168
169 return *addr;
170 }
171
172 static inline void SIPC_mailboxClearPendingIntr(uint32_t mailboxBaseAddr, uint32_t pendingIntr)
173 {
174 volatile uint32_t *addr = ( uint32_t *)mailboxBaseAddr;
175 *addr = pendingIntr;
176 }
177
178 static inline uint32_t SIPC_mailboxIsPendingIntr(uint32_t pendingIntr, uint32_t coreId)
179 {
180 extern uint32_t gSIPCCoreIntrBitPos[];
181
182 uint32_t isPending = 0;
183 isPending = pendingIntr & (1U << gSIPCCoreIntrBitPos[coreId]);
184 return isPending;
185 }
186
187 #ifdef __cplusplus
188 }
189 #endif
190
191 #endif /*SIPC_NOTIFY_MAILBOX_H_*/
192
SIPC_mailboxIsPendingIntr
static uint32_t SIPC_mailboxIsPendingIntr(uint32_t pendingIntr, uint32_t coreId)
Definition: sipc_notify_mailbox.h:178
SIPC_mailboxWrite
static int32_t SIPC_mailboxWrite(uint32_t mailboxBaseAddr, uint32_t wrIntrBitPos, SIPC_SwQueue *swQ, uint8_t *Buff)
Definition: sipc_notify_mailbox.h:122
SIPC_SwQueue::Qfifo
uint8_t * Qfifo
Definition: sipc_notify_mailbox.h:68
SIPC_mailboxGetPendingIntr
static uint32_t SIPC_mailboxGetPendingIntr(uint32_t mailboxBaseAddr)
Definition: sipc_notify_mailbox.h:165
SOC_phyToVirt
void * SOC_phyToVirt(uint64_t phyAddr)
Physical to Virtual (CPU) address translation function.
SIPC_SwQueue::Qlength
uint16_t Qlength
Definition: sipc_notify_mailbox.h:67
SIPC_SwQueue
SIPC swQ structure which holds the data pointer to a fifo Queue in HSM MBOX memory.
Definition: sipc_notify_mailbox.h:63
SystemP_SUCCESS
#define SystemP_SUCCESS
Return status when the API execution was successful.
Definition: SystemP.h:56
SIPC_SwQueue::rdIdx
volatile uint32_t rdIdx
Definition: sipc_notify_mailbox.h:64
SystemP_FAILURE
#define SystemP_FAILURE
Return status when the API execution was not successful due to a failure.
Definition: SystemP.h:61
SIPC_SwQueue::EleSize
uint16_t EleSize
Definition: sipc_notify_mailbox.h:66
SIPC_mailboxClearPendingIntr
static void SIPC_mailboxClearPendingIntr(uint32_t mailboxBaseAddr, uint32_t pendingIntr)
Definition: sipc_notify_mailbox.h:172
SIPC_mailboxClearAllInt
static void SIPC_mailboxClearAllInt(uint32_t mailboxBaseAddr)
Definition: sipc_notify_mailbox.h:159
SIPC_mailboxRead
static int32_t SIPC_mailboxRead(SIPC_SwQueue *swQ, uint8_t *Buff)
Definition: sipc_notify_mailbox.h:84
SIPC_SwQueue::wrIdx
volatile uint32_t wrIdx
Definition: sipc_notify_mailbox.h:65