AM263Px MCU+ SDK: Enet Layer 2 CPSW SWITCH Example

| AM263Px MCU+ SDK 26.00.00 |

Enet Layer 2 CPSW SWITCH Example

# Introduction

The layer 2 cpsw switch example is dedicated to demonstrate usage of Enet CPSW3G peripheral operation as a basic switch.

On AM263PX, we can do ethernet based communication using CPSW HW mechanism

- This is a standard ethernet switch + port HW

This example does the following:

- Target-side application running on a Cortex R5F core.
  - Target-side application running on a Cortex R5F core.
  - Application receives the broadcast packet for switch operation, copies the payload into a new packet which is then sent back out to the source port as well as to all the other ports on the device.
  - The application has a menu to enable/disable features, such as getting mac address and stats. This menu along with application logs are implemented via UART.
- Host-side functionality
  - Software applications like Colasoft Pkt Builder or packETH tool could be used to generate and send packets. Wireshark can be used to receive and verify packet contents.
- The data path enabled in this example is as follows:
  - Host side (PC) application sends a broadcast packet to MAC port.
  - Target side application receives the broadcast packet, updates the MAC addresses in the Layer-2 header and sends the packet out back out to the source port as well as to all the other ports on the device.
  - Application like Wireshark (PC) receives the packet and can be seen in the capture window.

# Supported Combinations

Parameter | Value
--- | ---
CPU + OS | r5fss0-0_freertos
Toolchain | ti-arm-clang
Boards | am263px-lp
Example folder | source/networking/enet/core/examples/enet_layer2_cpsw_switch/V1

# Packet pool configuration

To change packet pool configuration from syscfg, please refer to Ethernet Packet Pool Allocation Guidelines

# Steps to Run the Example

## Build the example

- When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
- When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)

## HW Setup

Note
  Make sure you have setup the EVM with cable connections as shown here, EVM Setup. In addition do below steps.

## Run the example

Attention
  If you need to reload and run again, a CPU power-cycle is MUST

- Launch a CCS debug session and run the example executable, see CCS Launch, Load and Run
- You will see logs in the UART terminal as shown in the next section.
- Launch a CCS debug session and run the example executable, see CCS Launch, Load and Run
- You will see logs in the UART terminal as shown in the next section.
- We can start sending multicast packets from Colasoft Pkt Builder or packETH tool.
  - In the Colasoft Pkt Builder, click on Add icon , select any layer2 Packet and click ok.
  - Edit the source and destination address in the decode editor.
  - Click on send icon and select the ethernet adapater.
  - Click start, packets will be send to the target.
- Capture the packets in Wireshark.

Colasoft Pkt Builder to generate and send packets.

## Sample output for Multiport example

==========================
Layer 2 CPSW SWITCH Test
==========================
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task
Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 2
Init all configs
----------------------------------------------
cpsw-3g: init config
Mdio_open:282
cpsw-3g: Open port 1
EnetPhy_bindDriver:1718
cpsw-3g: Open port 2
EnetPhy_bindDriver:1718
PHY 0 is alive
PHY 3 is alive
Attach core id 1 on all peripherals
----------------------------------------------
cpsw-3g: Attach core
cpsw-3g: Open DMA
initQs() txFreePktInfoQ initialized with 16 pkts
cpsw-3g: Waiting for link up...
Cpsw_handleLinkUp:1369
MAC Port 2: link up
Cpsw_handleLinkUp:1369
MAC Port 1: link up
cpsw-3g: Port 1 link is up
cpsw-3g: Port 2 link is up
cpsw-3g: MAC port addr: f4:84:4c:fd:a6:00
Enet L2 cpsw Menu:
's' - Print statistics
'r' - Reset statistics
'm' - Show allocated MAC addresses
'p' - Enable Policer for rate limiting
'x' - Stop the test
s
Print statistics
----------------------------------------------
cpsw-3g - Port 1 statistics
--------------------------------
cpsw-3g - Port 2 statistics
--------------------------------
p
Rate limiting Enabled port 1 on Src MAC 02:00:00:00:00:08
s
Print statistics
----------------------------------------------
rxGoodFrames = 100000
rxOctets = 101800000
txGoodFrames = 100000
txBcastFrames = 100000
txOctets = 101800000
octetsFrames512to1023 = 200000
netOctets = 203600000
txPri[0] = 100000
txPriBcnt[0] = 101800000
cpsw-3g - Port 1 statistics
--------------------------------
txGoodFrames = 150000
txBcastFrames = 100000
txOctets = 152700000
octetsFrames512to1023 = 150000
netOctets = 152700000
txPri[0] = 150000
txPriBcnt[0] = 152700000
rxGoodFrames = 100000
rxOctets = 101800000
txGoodFrames = 100000
txBcastFrames = 100000
txOctets = 101800000
octetsFrames512to1023 = 200000
netOctets = 203600000
txPri[0] = 100000
txPriBcnt[0] = 101800000
cpsw-3g - Port 2 statistics
--------------------------------
rxGoodFrames = 100000
rxBcastFrames = 100000
rxOctets = 101800000
txGoodFrames = 50000
txOctets = 50900000
octetsFrames512to1023 = 150000
netOctets = 152700000
aleUnknownBcast = 1
aleUnknownBcastBcnt = 1018
txPri[0] = 50000
txPriBcnt[0] = 50900000
�
Starting NULL Bootloader ...
DMSC Firmware Version 8.4.7--v08.04.07 (Jolly Jellyfi
DMSC Firmware revision 0x8
DMSC ABI revision 3.1
INFO: Bootloader_runCpu:155: CPU r5f1-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU r5f1-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runCpu:155: CPU m4f0-0 is initialized to 400000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-0 is initialized to 800000000 Hz !!!
INFO: Bootloader_loadSelfCpu:207: CPU r5f0-1 is initialized to 800000000 Hz !!!
INFO: Bootloader_runSelfCpu:217: All done, reseting self ...
==========================
Layer 2 CPSW SWITCH Test
==========================
Init all peripheral clocks
----------------------------------------------
Enabling clocks!
Create RX tasks
----------------------------------------------
cpsw-3g: Create RX task
Open all peripherals
----------------------------------------------
cpsw-3g: Open enet
EnetAppUtils_reduceCoreMacAllocation: Reduced Mac Address Allocation for CoreId:1 From 4 To 2
Init all configs
----------------------------------------------
cpsw-3g: init config
Mdio_open:282
cpsw-3g: Open port 1
EnetPhy_bindDriver:1718
cpsw-3g: Open port 2
EnetPhy_bindDriver:1718
PHY 0 is alive
PHY 3 is alive
Attach core id 1 on all peripherals
----------------------------------------------
cpsw-3g: Attach core
cpsw-3g: Open DMA
initQs() txFreePktInfoQ initialized with 16 pkts
cpsw-3g: Waiting for link up...
Cpsw_handleLinkUp:1369
Cpsw_handleLinkUp:1369
MAC Port 1: link up
MAC Port 2: link up
cpsw-3g: Port 1 link is up
cpsw-3g: Port 2 link is up
cpsw-3g: MAC port addr: f4:84:4c:fd:a6:00
Enet L2 cpsw Menu:
's' - Print statistics
'r' - Reset statistics
'm' - Show allocated MAC addresses
'p' - Enable Policer for rate limiting
'x' - Stop the test
s
Print statistics
----------------------------------------------
cpsw-3g - Port 1 statistics
--------------------------------
cpsw-3g - Port 2 statistics
--------------------------------
p
Rate limiting Enabled port 1 on Src MAC 02:00:00:00:00:08
s
Print statistics
----------------------------------------------
rxGoodFrames = 25000
rxOctets = 25450000
txGoodFrames = 25000
txBcastFrames = 25000
txOctets = 25450000
octetsFrames512to1023 = 50000
netOctets = 50900000
txPri[0] = 25000
txPriBcnt[0] = 25450000
cpsw-3g - Port 1 statistics
--------------------------------
rxGoodFrames = 50000
rxBcastFrames = 50000
rxOctets = 50900000
txGoodFrames = 25000
txOctets = 25450000
octetsFrames512to1023 = 75000
netOctets = 76350000
portMaskDrop = 25000
alePolicyMatch = 50000
alePolicyMatchRed = 25000
txPri[0] = 25000
txPriBcnt[0] = 25450000
rxGoodFrames = 25000
rxOctets = 25450000
txGoodFrames = 25000
txBcastFrames = 25000
txOctets = 25450000
octetsFrames512to1023 = 50000
netOctets = 50900000
txPri[0] = 25000
txPriBcnt[0] = 25450000
cpsw-3g - Port 2 statistics
--------------------------------
txGoodFrames = 25000
txBcastFrames = 25000
txOctets = 25450000
octetsFrames512to1023 = 25000
netOctets = 25450000
txPri[0] = 25000
txPriBcnt[0] = 25450000

- On Wireshark we can see the packets received:

Wireshark log for Layer 2 CPSW Example

## Testing Switch Policer configuration

- Enable the policer using 'p' option in target UART terminal menu option.
- Send Layer-2 packets with below configurations
  - source MAC address - 02:00:00:00:00:08
  - ingress port - PORT 1
  - Destination MAC address - any
  - Ether_type = 0x8600
  - Data rate - more than 25 mbps
- Observe that packets are switched by limiting data rate to 25 mpbs.
- Observe that the dropped packets are marked with 'alePolicyMatchRed' in CPSW statistics print.

## Troubleshooting issues

- To ensure compatibility with CPSW RGMII2 port on am263px-cc board, make sure that SW-15(switch) should be set to `LOW` for board versions(E2/A/B versions). This configuration ensures seamless out-of-box support and functionality with the CPSW RGMII2 port on the specified versions.

# See Also

Ethernet And Networking