AM263Px MCU+ SDK: sdl_ecc_bus_safety_soc.h Source File

| AM263Px MCU+ SDK 26.00.00 |

sdl_ecc_bus_safety_soc.h
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1 /*
2 * Copyright (c) 2022-25 Texas Instruments Incorporated
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the
14 * distribution.
15 *
16 * Neither the name of Texas Instruments Incorporated nor the names of
17 * its contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 *
32 */
33
39 #ifndef SDL_MSS_CR5_SOC_H_
40 #define SDL_MSS_CR5_SOC_H_
41
42 /* ========================================================================== */
43 /* Include Files */
44 /* ========================================================================== */
45
46 #include <sdl/include/am263px/sdlr_soc_baseaddress.h>
47 #include <sdl/include/am263px/sdlr_mss_ctrl.h>
48
49 #ifdef _cplusplus
50 extern "C" {
51 #endif
52
53 /* ========================================================================== */
54 /* Macros & Typedefs */
55 /* ========================================================================== */
56 #define SDL_ECC_BUS_SAFETY_MSS_BUS_CFG (uint32_t)SDL_MSS_CTRL_U_BASE
57 #define DWORD (0x20U)
58 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE (0x000000A0U)
59 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE (0x000000A4U)
60 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE (0x000000B0U)
61 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE (0x000000B4U)
62 #define SDL_MSS_CTRL_R5SS0_CORE0_AHB_END (SDL_MSS_CTRL_R5SS0_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE0_AHB_SIZE)
63 #define SDL_MSS_CTRL_R5SS1_CORE0_AHB_END (SDL_MSS_CTRL_R5SS1_CORE0_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE0_AHB_SIZE)
64 #define SDL_MSS_CTRL_R5SS0_CORE1_AHB_END (SDL_MSS_CTRL_R5SS0_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS0_CORE1_AHB_SIZE)
65 #define SDL_MSS_CTRL_R5SS1_CORE1_AHB_END (SDL_MSS_CTRL_R5SS1_CORE1_AHB_BASE + SDL_MSS_CTRL_R5SS1_CORE1_AHB_SIZE)
66
67 #define SDL_R5SS0_CORE0_TCMA_U_SIZE (0x000000020U)
68 #define SDL_R5SS0_CORE0_TCMB_U_SIZE (0x000000020U)
69 #define SDL_MSS_CR5A_TCM_U_BASE (SDL_R5SS0_CORE0_TCMA_U_BASE )
70 #define SDL_MSS_CR5B_TCM_U_BASE (SDL_R5SS0_CORE0_TCMB_U_BASE )
71 #define SDL_MSS_CR5A_TCM_U_END (SDL_R5SS0_CORE0_TCMA_U_BASE + SDL_R5SS0_CORE0_TCMA_U_SIZE)
72 #define SDL_MSS_CR5B_TCM_U_END (SDL_R5SS0_CORE0_TCMB_U_BASE + SDL_R5SS0_CORE0_TCMB_U_SIZE)
73 #define SDL_MBOX_SRAM_U_BASE_END (SDL_MBOX_SRAM_U_BASE + 100U)
74 #define SDL_MMC0_U_BASE_END (SDL_MMC0_U_BASE + 0X1FFCU-DWORD)
75 #define SDL_CORE_VBUSP_START (0x50800000U)
76 #define SDL_CORE_VBUSP_START_END (SDL_CORE_VBUSP_START + 0X1FFCU)
77 #define SDL_PERI_VBUSP_START (0x50200000U)
78 #define SDL_PERI_VBUSP_START_END (SDL_PERI_VBUSP_START + 0X7FFFFCU)
79 #define SDL_L2OCRAM_BANK0 (SDL_L2OCRAM_U_BASE)
80 #define SDL_L2OCRAM_BANK0_END (SDL_L2OCRAM_U_BASE + 0x80000U)
81 #define SDL_L2OCRAM_BANK1 (SDL_L2OCRAM_U_BASE + 0x80000U)
82 #define SDL_L2OCRAM_BANK1_END (SDL_L2OCRAM_U_BASE + 0x100000U)
83 #define SDL_L2OCRAM_BANK2 (SDL_L2OCRAM_U_BASE + 0x100000U)
84 #define SDL_L2OCRAM_BANK2_END (SDL_L2OCRAM_U_BASE + 0x100FFFU)
85 #define SDL_L2OCRAM_BANK3 (SDL_L2OCRAM_U_BASE + 0x180000U)
86 #define SDL_L2OCRAM_BANK3_END (SDL_L2OCRAM_U_BASE + 0x180FFFU)
87 #define SDL_L2OCRAM_BANK4 (SDL_L2OCRAM_U_BASE + 0x200000U)
88 #define SDL_L2OCRAM_BANK4_END (SDL_L2OCRAM_U_BASE + 0x280000U)
89 #define SDL_L2OCRAM_BANK5 (SDL_L2OCRAM_U_BASE + 0x280000U)
90 #define SDL_L2OCRAM_BANK5_END (SDL_L2OCRAM_U_BASE + 0x280FFFU)
91 #define SDL_MSS_MCRC_U_BASE (SDL_MCRC0_U_BASE)
92 #define SDL_MSS_MCRC_U_SIZE (0x000001E4U)
93 #define SDL_MSS_MCRC_U_END (SDL_MSS_MCRC_U_BASE + SDL_MSS_MCRC_U_SIZE)
94 #define SDL_MSS_STM_STIM_U_BASE (SDL_STM_STIM_U_BASE)
95 #define SDL_MSS_STM_STIM_U_SIZE (0x00FFFFFFU)
96 #define SDL_MSS_STM_STIM_U_END (SDL_MSS_STM_STIM_U_BASE + SDL_MSS_STM_STIM_U_SIZE)
97
98 #define SDL_MSS_CR5A_AXI_RD_START (0x35000000U)
99 #define SDL_MSS_CR5A_AXI_RD_END (0x350003FFU-8U)
100 #define SDL_MSS_CR5A_AXI_WR_START (0x35000000U)
101 #define SDL_MSS_CR5A_AXI_WR_END (0x350003FFU-8U)
102 #define SDL_MSS_CR5A_AXI_S_START SDL_R5SS0_CORE0_TCMB_U_BASE
103 #define SDL_MSS_CR5A_AXI_S_END (SDL_R5SS0_CORE0_TCMB_U_BASE + 0xFFFFU)
104
105 #define SDL_MSS_CR5B_AXI_RD_START (0x35000000U)
106 #define SDL_MSS_CR5B_AXI_RD_END (0x350003FFU-8U)
107 #define SDL_MSS_CR5B_AXI_WR_START (0x35000000U)
108 #define SDL_MSS_CR5B_AXI_WR_END (0x350003FFU-8U)
109 #define SDL_MSS_CR5B_AXI_S_START SDL_R5SS1_CORE0_TCMB_U_BASE
110 #define SDL_MSS_CR5B_AXI_S_END (SDL_R5SS1_CORE0_TCMB_U_BASE + 0xFFFFU)
111
112 #define SDL_MSS_CR5C_AXI_RD_START (0x35000000U)
113 #define SDL_MSS_CR5C_AXI_RD_END (0x350003FFU-8U)
114 #define SDL_MSS_CR5C_AXI_WR_START (0x35000000U)
115 #define SDL_MSS_CR5C_AXI_WR_END (0x350003FFU-8U)
116 #define SDL_MSS_CR5C_AXI_S_START SDL_R5SS0_CORE1_TCMB_U_BASE
117 #define SDL_MSS_CR5C_AXI_S_END (SDL_R5SS0_CORE1_TCMB_U_BASE + 0x7FFFU)
118
119 #define SDL_MSS_CR5D_AXI_RD_START (0x35000000U)
120 #define SDL_MSS_CR5D_AXI_RD_END (0x350003FFU-8U)
121 #define SDL_MSS_CR5D_AXI_WR_START (0x35000000U)
122 #define SDL_MSS_CR5D_AXI_WR_END (0x350003FFU-8U)
123 #define SDL_MSS_CR5D_AXI_S_START SDL_R5SS1_CORE1_TCMB_U_BASE
124 #define SDL_MSS_CR5D_AXI_S_END (SDL_R5SS1_CORE1_TCMB_U_BASE + 0x7FFFU)
125
126 #define SDL_MSS_CTRL_TPCC_A0_WR_BASE (0x52A40000U)
127 #define SDL_MSS_CTRL_TPCC_A0_WR_END (0x52A40400U-8U)
128
129 #define SDL_MSS_CTRL_TPCC_A1_WR_BASE (0x52A60000U)
130 #define SDL_MSS_CTRL_TPCC_A1_WR_END (0x52A60400U-8U)
131
132 #define SDL_MSS_CTRL_TPCC_A0_RD_BASE (0x52A40000U)
133 #define SDL_MSS_CTRL_TPCC_A0_RD_END (0x52A40400U-8U)
134
135 #define SDL_MSS_CTRL_TPCC_A1_RD_BASE (0x52A60000U)
136 #define SDL_MSS_CTRL_TPCC_A1_RD_END (0x52A60400U-8U)
137
138 #define SDL_MSS_VBUSP_BASE (0x35000000U)
139 #define SDL_MSS_VBUSP_BASE_END (0x350003FFU-8U)
140
141 #define SDL_MSS_VBUSP_PERI_BASE (0x35000000U)
142 #define SDL_MSS_VBUSP_PERI_BASE_END (0x350003FFU-8U)
143
144 #define SDL_MSS_CPSW_BASE (0x52800000U)
145 #define SDL_MSS_CPSW_BASE_END (0x52800400U-8U)
146
147 #define SDL_MCRC_U_BASE (0x35000000U)
148 #define SDL_MCRC_U_BASE_END (0x350003FFU-8U)
149
150 #define SDL_STIM_U_BASE (0x53500000U)
151 #define SDL_STIM_U_BASE_END (0x535001FFU-8U)
152
153 #define SDL_SCRP0_U_BASE (0x48000000U)
154 #define SDL_SCRP0_U_BASE_END (0x4803FFFFU-8U)
155
156 #define SDL_SCRP1_U_BASE (0x48000000U)
157 #define SDL_SCRP1_U_BASE_END (0x4803FFFFU-8U)
158
159 #define SDL_ICSSM_PDSP0_U_BASE 0x72000000U
160 #define SDL_ICSSM_PDSP0_U_BASE_END (0x72004000U - 8U)
161
162 #define SDL_ICSSM_PDSP1_U_BASE 0x72000000U
163 #define SDL_ICSSM_PDSP1_U_BASE_END (0x72004000U - 8U)
164
165 #define SDL_ICSSM_S_BASE (0x48000000U)
166 #define SDL_ICSSM_S_BASE_END (0x4803FFFFU-8U)
167
168 #define SDL_DAP_U_BASE SDL_TOP_RCM_U_BASE
169 #define SDL_DAP_U_BASE_END (SDL_TOP_RCM_U_BASE + (0x1FFFU-8U))
170
171 #define SDL_OSPI_U_BASE (SDL_OSPI0_U_BASE)
172 #define SDL_OSPI_U_BASE_SIZE (0x00200000U)
173 #define SDL_OSPI_U_BASE_END (SDL_OSPI_U_BASE + SDL_OSPI_U_BASE_SIZE)
174
175 #define SDL_ECC_BUS_SAFETY_MSS_READABLE_NODE 1U
176 #define SDL_ECC_BUS_SAFETY_MSS_WRITABLE_NODE 0U
177
178 #define SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE 6U
179 #define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE 32U
180 #define SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG1_SIZE 10U
181 #define SDL_MSS_CTRL_MSS_VBUSP_VBUSM_ERRAGG0_SIZE (SDL_MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG_SIZE + \
182 SDL_MSS_CTRL_MSS_VBUSM_SAFETY_ERRAGG0_SIZE)
183
184 /* nodeReadable1 and nodeReadable2 are arranged by bit field for */
185 /* each busSftyNode based on MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG, */
186 /* MSS_VBUSM_SAFETY_H_ERRAGG and MSS_VBUSM_SAFETY_L_ERRAGG */
187 /* For example 0xxxxxxC0U, here 'C(0x1100)' means 6th */
188 /* node(CR5A_AXI_RD) and 7th node(CR5B_AXI_RD) are readable */
189 #define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_1_MASK 0x440800C0U
190 #define SDL_ECC_BUS_SAFETY_MSS_NODE_READABLE_2_MASK 0x00300008U
191
192 /* Macro defines Ecc Bus Safety Nodes in the MSS Subsystem */
193
194 /* Aggregated_VBUSP_error_H nodes */
195 /* Listed as per MMR MSS_CTRL_MSS_VBUSP_SAFETY_H_ERRAGG */
196 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AHB 0U
197 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AHB 1U
198 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AHB 2U
199 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AHB 3U
200 #define SDL_ECC_BUS_SAFETY_MSS_MAIN_VBUSP 4U
201 #define SDL_ECC_BUS_SAFETY_MSS_PERI_VBUSP 5U
202
203 /* Aggregated_VBUSM_error_H and Aggregated_VBUSM_error_L nodes */
204 /* Listed as per MMR MSS_CTRL MSS_VBUSM_SAFETY_H_ERRAGG */
205 /* and MSS_VBUSM_SAFETY_L_ERRAGG 0 Register */
206 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD 6U
207 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_RD 7U
208 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_WR 8U
209 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_WR 9U
210 #define SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_S 10U
211 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_S 11U
212 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_RD 12U
213 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_RD 13U
214 #define SDL_ECC_BUS_SAFETY_MSS_CR5C_AXI_WR 14U
215 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_WR 15U
216 #define SDL_ECC_BUS_SAFETY_MSS_CR5B_AXI_S 16U
217 #define SDL_ECC_BUS_SAFETY_MSS_CR5D_AXI_S 17U
218 #define SDL_ECC_BUS_SAFETY_DAP 18U
219 #define SDL_ECC_BUS_SAFETY_HSM_M 19U
220 #define SDL_ECC_BUS_SAFETY_MSS_CPSW 20U
221 #define SDL_ECC_BUS_SAFETY_MSS_L2_A 21U
222 #define SDL_ECC_BUS_SAFETY_MSS_L2_B 22U
223 #define SDL_ECC_BUS_SAFETY_MSS_L2_C 23U
224 #define SDL_ECC_BUS_SAFETY_MSS_L2_D 24U
225 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_RD 25U
226 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_RD 26U
227 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A0_WR 27U
228 #define SDL_ECC_BUS_SAFETY_MSS_TPTC_A1_WR 28U
229 #define SDL_ECC_BUS_SAFETY_HSM_TPTC0_RD 29U
230 #define SDL_ECC_BUS_SAFETY_HSM_TPTC0_WR 30U
231 #define SDL_ECC_BUS_SAFETY_HSM_TPTC1_RD 31U
232 #define SDL_ECC_BUS_SAFETY_HSM_TPTC1_WR 32U
233 #define SDL_ECC_BUS_SAFETY_ICSSM_PDSP0 33U
234 #define SDL_ECC_BUS_SAFETY_ICSSM_PDSP1 34U
235 #define SDL_ECC_BUS_SAFETY_MSS_OSPI 35U
236 #define SDL_ECC_BUS_SAFETY_MSS_MCRC 36U
237 #define SDL_ECC_BUS_SAFETY_HSM_DTHE 37U
238
239 /* Listed as per MMR MSS_CTRL MSS_VBUSM_SAFETY_H_ERRAGG */
240 /* and MSS_VBUSM_SAFETY_L_ERRAGG 1 Register */
241 #define SDL_ECC_BUS_SAFETY_MSS_SCRP0 38U
242 #define SDL_ECC_BUS_SAFETY_MSS_SCRP1 39U
243 #define SDL_ECC_BUS_SAFETY_HSM_S 40U
244 #define SDL_ECC_BUS_SAFETY_ICSSM_S 41U
245 #define SDL_ECC_BUS_SAFETY_MSS_MBOX 42U
246 #define SDL_ECC_BUS_SAFETY_MSS_STM_STIM 43U
247 #define SDL_ECC_BUS_SAFETY_MSS_MMC 44U
248 #define SDL_ECC_BUS_SAFETY_MSS_NULL 45U
249 #define SDL_ECC_BUS_SAFETY_MSS_L2_E 46U
250 #define SDL_ECC_BUS_SAFETY_MSS_L2_F 47U
251
252 #define SDL_ECC_BUS_SAFETY_SEC_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)
253 #define SDL_ECC_BUS_SAFETY_SEC_END_NODE (SDL_ECC_BUS_SAFETY_MSS_L2_F)
254
255 #define SDL_ECC_BUS_SAFETY_DED_START_NODE (SDL_ECC_BUS_SAFETY_MSS_CR5A_AXI_RD)
256 #define SDL_ECC_BUS_SAFETY_DED_END_NODE (SDL_ECC_BUS_SAFETY_MSS_L2_F)
257
258 #ifdef _cplusplus
259 }
260
261 #endif /*extern "C" */
262
263 #endif
264