AM263Px MCU+ SDK: cslr_soc_defines.h File Reference

| AM263Px MCU+ SDK 26.00.00 |

Macros
cslr_soc_defines.h File Reference

Go to the source code of this file.

## Macros
#define | CSL_UART_PER_CNT (6U)
| Number of UART instances. More...
#define | CSL_SPI_PER_CNT (8U)
| Number of SPI instances. More...
#define | CSL_LIN_PER_CNT (5U)
| Number of LIN instances. More...
#define | CSL_I2C_PER_CNT (4U)
| Number of I2C instances. More...
#define | CSL_MCAN_PER_CNT (8U)
| Number of MCAN instances. More...
#define | CSL_ETPWM_PER_CNT (32U)
| Number of ETPWM instances. More...
#define | CSL_ECAP_PER_CNT (16U)
| Number of ECAP instances. More...
#define | CSL_EQEP_PER_CNT (3U)
| Number of EQEP instances. More...
#define | CSL_SDFM_PER_CNT (2U)
| Number of SDFM instances. More...
#define | CSL_ADC_PER_CNT (5U)
| Number of ADC instances. More...
#define | CSL_CMPSSA_PER_CNT (10U)
| Number of CMPSSA instances. More...
#define | CSL_CMPSSB_PER_CNT (10U)
| Number of CMPSSB instances. More...
#define | SOC_EDMA_NUM_DMACH (64U)
| Number of DMA Channels. More...
#define | SOC_EDMA_NUM_QDMACH (8U)
| Number of QDMA Channels. More...
#define | SOC_EDMA_NUM_PARAMSETS (256U)
| Number of PaRAM Sets available. More...
#define | SOC_EDMA_NUM_EVQUE (2U)
| Number of Event Queues available. More...
#define | SOC_EDMA_CHMAPEXIST (1U)
| Support for Channel to PaRAM Set mapping. More...
#define | SOC_EDMA_NUM_REGIONS (8U)
| Number of EDMA Regions. More...
#define | SOC_EDMA_MEMPROTECT (1U)
| Support for Memory Protection. More...
#define | SOC_EDMA_NUM_TPTC (2U)
| Number of Transfer Controllers available. More...
#define | MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)
#define | MCAN_MAX_RX_DMA_BUFFERS (7U)
| Maximum number of Rx Dma buffers. More...
#define | MCAN_MAX_TX_DMA_BUFFERS (4U)
| Maximum number of Tx Dma buffers. More...
#define | FSI_MAX_TX_DMA_BUFFERS (2U)
| Maximum number of FSI Tx Dma buffers. More...
#define | FSI_MAX_RX_DMA_BUFFERS (2U)
| Maximum number of FSI Rx Dma buffers. More...
#define | MCSPI_DMA_IS_FIFO_SUPPORTED (1U)
| Whether FIFO is supported in MCSPI DMA MODE. More...
#define | MSS_SYS_VCLK 200000000U
#define | R5F_CLOCK_MHZ 400U
#define | CSL_CORE_R5F_INTR_MAX (256U)
| Maximum number of interrupts for r5f interrupts for this device. More...
EDMA Error Definitions on this SOC
#define | EDMA_TPCC_A_ERRINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT_MASK)
#define | EDMA_TPCC_A_MPINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_MPINT_MASK)
#define | EDMA_TPTC_A0_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_ERR_MASK)
#define | EDMA_TPTC_A1_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_ERR_MASK)
#define | EDMA_TPCC_A_PAR_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR_MASK)
#define | EDMA_TPCC_A_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR_MASK)
#define | EDMA_TPTC_A0_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR_MASK)
#define | EDMA_TPTC_A1_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR_MASK)
#define | EDMA_TPCC_A_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR_MASK)
#define | EDMA_TPTC_A0_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR_MASK)
#define | EDMA_TPTC_A1_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR_MASK)
Core ID's of core or CPUs present on this SOC
#define | CSL_CORE_ID_R5FSS0_0 (0U)
#define | CSL_CORE_ID_R5FSS0_1 (1U)
#define | CSL_CORE_ID_R5FSS1_0 (2U)
#define | CSL_CORE_ID_R5FSS1_1 (3U)
#define | CSL_CORE_ID_MAX (4U)
Priv ID's of core or CPUs present on this SOC
#define | PRIV_ID_M4FSS0_0 (1U)
#define | PRIV_ID_R5FSS0_0 (4U)
#define | PRIV_ID_R5FSS0_1 (5U)
#define | PRIV_ID_R5FSS1_0 (6U)
#define | PRIV_ID_R5FSS1_1 (7U)
#define | PRIV_ID_ICSSM (9U)
#define | PRIV_ID_CPSW (10U)
R5 Cluster Group IDs
#define | CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)
| R5 Cluster Group ID0. More...
#define | CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)
| R5 Cluster Group ID1. More...
R5 Core IDs
#define | CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)
| R5 Core ID0. More...
#define | CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)
| R5 Core ID1. More...

## Macro Definition Documentation

## ◆ CSL_UART_PER_CNT

#define CSL_UART_PER_CNT (6U)

Number of UART instances.

## ◆ CSL_SPI_PER_CNT

#define CSL_SPI_PER_CNT (8U)

Number of SPI instances.

## ◆ CSL_LIN_PER_CNT

#define CSL_LIN_PER_CNT (5U)

Number of LIN instances.

## ◆ CSL_I2C_PER_CNT

#define CSL_I2C_PER_CNT (4U)

Number of I2C instances.

## ◆ CSL_MCAN_PER_CNT

#define CSL_MCAN_PER_CNT (8U)

Number of MCAN instances.

## ◆ CSL_ETPWM_PER_CNT

#define CSL_ETPWM_PER_CNT (32U)

Number of ETPWM instances.

## ◆ CSL_ECAP_PER_CNT

#define CSL_ECAP_PER_CNT (16U)

Number of ECAP instances.

## ◆ CSL_EQEP_PER_CNT

#define CSL_EQEP_PER_CNT (3U)

Number of EQEP instances.

## ◆ CSL_SDFM_PER_CNT

#define CSL_SDFM_PER_CNT (2U)

Number of SDFM instances.

## ◆ CSL_ADC_PER_CNT

#define CSL_ADC_PER_CNT (5U)

Number of ADC instances.

## ◆ CSL_CMPSSA_PER_CNT

#define CSL_CMPSSA_PER_CNT (10U)

Number of CMPSSA instances.

## ◆ CSL_CMPSSB_PER_CNT

#define CSL_CMPSSB_PER_CNT (10U)

Number of CMPSSB instances.

## ◆ SOC_EDMA_NUM_DMACH

#define SOC_EDMA_NUM_DMACH (64U)

Number of DMA Channels.

## ◆ SOC_EDMA_NUM_QDMACH

#define SOC_EDMA_NUM_QDMACH (8U)

Number of QDMA Channels.

## ◆ SOC_EDMA_NUM_PARAMSETS

#define SOC_EDMA_NUM_PARAMSETS (256U)

Number of PaRAM Sets available.

## ◆ SOC_EDMA_NUM_EVQUE

#define SOC_EDMA_NUM_EVQUE (2U)

Number of Event Queues available.

## ◆ SOC_EDMA_CHMAPEXIST

#define SOC_EDMA_CHMAPEXIST (1U)

Support for Channel to PaRAM Set mapping.

## ◆ SOC_EDMA_NUM_REGIONS

#define SOC_EDMA_NUM_REGIONS (8U)

Number of EDMA Regions.

## ◆ SOC_EDMA_MEMPROTECT

#define SOC_EDMA_MEMPROTECT (1U)

Support for Memory Protection.

## ◆ SOC_EDMA_NUM_TPTC

#define SOC_EDMA_NUM_TPTC (2U)

Number of Transfer Controllers available.

## ◆ EDMA_TPCC_A_ERRINT

#define EDMA_TPCC_A_ERRINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT_MASK)

## ◆ EDMA_TPCC_A_MPINT

#define EDMA_TPCC_A_MPINT (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_MPINT_MASK)

## ◆ EDMA_TPTC_A0_ERR

#define EDMA_TPTC_A0_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_ERR_MASK)

## ◆ EDMA_TPTC_A1_ERR

#define EDMA_TPTC_A1_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_ERR_MASK)

## ◆ EDMA_TPCC_A_PAR_ERR

#define EDMA_TPCC_A_PAR_ERR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR_MASK)

## ◆ EDMA_TPCC_A_WRITE_ACCESS_ERROR

#define EDMA_TPCC_A_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR_MASK)

## ◆ EDMA_TPTC_A0_WRITE_ACCESS_ERROR

#define EDMA_TPTC_A0_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR_MASK)

## ◆ EDMA_TPTC_A1_WRITE_ACCESS_ERROR

#define EDMA_TPTC_A1_WRITE_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR_MASK)

## ◆ EDMA_TPCC_A_READ_ACCESS_ERROR

#define EDMA_TPCC_A_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR_MASK)

## ◆ EDMA_TPTC_A0_READ_ACCESS_ERROR

#define EDMA_TPTC_A0_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR_MASK)

## ◆ EDMA_TPTC_A1_READ_ACCESS_ERROR

#define EDMA_TPTC_A1_READ_ACCESS_ERROR (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR_MASK)

## ◆ MCAN_MSG_RAM_MAX_WORD_COUNT

#define MCAN_MSG_RAM_MAX_WORD_COUNT (4352U)

## ◆ MCAN_MAX_RX_DMA_BUFFERS

#define MCAN_MAX_RX_DMA_BUFFERS (7U)

Maximum number of Rx Dma buffers.

## ◆ MCAN_MAX_TX_DMA_BUFFERS

#define MCAN_MAX_TX_DMA_BUFFERS (4U)

Maximum number of Tx Dma buffers.

## ◆ FSI_MAX_TX_DMA_BUFFERS

#define FSI_MAX_TX_DMA_BUFFERS (2U)

Maximum number of FSI Tx Dma buffers.

## ◆ FSI_MAX_RX_DMA_BUFFERS

#define FSI_MAX_RX_DMA_BUFFERS (2U)

Maximum number of FSI Rx Dma buffers.

## ◆ MCSPI_DMA_IS_FIFO_SUPPORTED

#define MCSPI_DMA_IS_FIFO_SUPPORTED (1U)

Whether FIFO is supported in MCSPI DMA MODE.

## ◆ CSL_CORE_ID_R5FSS0_0

#define CSL_CORE_ID_R5FSS0_0 (0U)

## ◆ CSL_CORE_ID_R5FSS0_1

#define CSL_CORE_ID_R5FSS0_1 (1U)

## ◆ CSL_CORE_ID_R5FSS1_0

#define CSL_CORE_ID_R5FSS1_0 (2U)

## ◆ CSL_CORE_ID_R5FSS1_1

#define CSL_CORE_ID_R5FSS1_1 (3U)

## ◆ CSL_CORE_ID_MAX

#define CSL_CORE_ID_MAX (4U)

## ◆ PRIV_ID_M4FSS0_0

#define PRIV_ID_M4FSS0_0 (1U)

## ◆ PRIV_ID_R5FSS0_0

#define PRIV_ID_R5FSS0_0 (4U)

## ◆ PRIV_ID_R5FSS0_1

#define PRIV_ID_R5FSS0_1 (5U)

## ◆ PRIV_ID_R5FSS1_0

#define PRIV_ID_R5FSS1_0 (6U)

## ◆ PRIV_ID_R5FSS1_1

#define PRIV_ID_R5FSS1_1 (7U)

## ◆ PRIV_ID_ICSSM

#define PRIV_ID_ICSSM (9U)

## ◆ PRIV_ID_CPSW

#define PRIV_ID_CPSW (10U)

## ◆ MSS_SYS_VCLK

#define MSS_SYS_VCLK 200000000U

## ◆ R5F_CLOCK_MHZ

#define R5F_CLOCK_MHZ 400U

## ◆ CSL_ARM_R5_CLUSTER_GROUP_ID_0

#define CSL_ARM_R5_CLUSTER_GROUP_ID_0 ((uint32_t) 0x00U)

R5 Cluster Group ID0.

## ◆ CSL_ARM_R5_CLUSTER_GROUP_ID_1

#define CSL_ARM_R5_CLUSTER_GROUP_ID_1 ((uint32_t) 0x01U)

R5 Cluster Group ID1.

## ◆ CSL_ARM_R5_CPU_ID_0

#define CSL_ARM_R5_CPU_ID_0 ((uint32_t) 0x00U)

R5 Core ID0.

## ◆ CSL_ARM_R5_CPU_ID_1

#define CSL_ARM_R5_CPU_ID_1 ((uint32_t) 0x01U)

R5 Core ID1.

## ◆ CSL_CORE_R5F_INTR_MAX

#define CSL_CORE_R5F_INTR_MAX (256U)

Maximum number of interrupts for r5f interrupts for this device.