AM263Px MCU+ SDK  11.00.00
v2/v2_0/sdlr_esm.h
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1 /*
2  * Copyright (C) 2024 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #ifndef SDLR_ESM_H_
34 #define SDLR_ESM_H_
35 
36 #ifdef __cplusplus
37 extern "C"
38 {
39 #endif
40 
41 #include <stdint.h>
42 
43 /**************************************************************************
44 * Module Base Offset Values
45 **************************************************************************/
46 
47 #define SDL_ESM_REGS_BASE (0x00000000U)
48 
49 
50 /**************************************************************************
51 * Hardware Region : ESM Registers
52 **************************************************************************/
53 
54 
55 /**************************************************************************
56 * Register Overlay Structure
57 **************************************************************************/
58 
59 typedef struct {
60  volatile uint32_t RAW; /* Config Error Raw Status/Set Register */
61  volatile uint32_t STS; /* Level Error Interrupt Enable Status/Clear Register */
62  volatile uint32_t INTR_EN_SET; /* Level Error Interrutp Enable Set Register */
63  volatile uint32_t INTR_EN_CLR; /* Level Error Interrupt Enabled Clear Register */
64  volatile uint32_t INT_PRIO; /* Level Error Interrupt Priority Register */
65  volatile uint32_t PIN_EN_SET; /* Level Error Interrupt Pin Influence Set Register */
66  volatile uint32_t PIN_EN_CLR; /* Level Error Interrupt Pin Influence Clear Register */
67  volatile uint8_t Resv_32[4]; /* 0x1C is reserved */
68 } SDL_esmRegs_ERR_GRP;
69 
70 typedef struct {
71  volatile uint32_t CRI_EN_SET; /* Level Critical Priority Interrupt Enabled Clear Register */
72  volatile uint32_t CRI_EN_CLR; /* Level Critical Priority Interrupt Enabled Clear Register */
73  volatile uint8_t Resv_32[24];
74 } SDL_esmRegs_ERR_EXT_GRP;
75 
76 
77 typedef struct {
78  volatile uint32_t PID; /* Revision Register */
79  volatile uint32_t INFO; /* Info Register */
80  volatile uint32_t EN; /* Global Enable Register */
81  volatile uint32_t SFT_RST; /* Global Soft Reset Register */
82  volatile uint32_t ERR_RAW; /* Config Error Raw Status/Set Register */
83  volatile uint32_t ERR_STS; /* Config Error Interrupt Enable Status/Clear Register */
84  volatile uint32_t ERR_EN_SET; /* Config Error Interrutp Enable Set Register */
85  volatile uint32_t ERR_EN_CLR; /* Config Error Interrupt Enabled Clear Register */
86  volatile uint32_t LOW_PRI; /* Low Priority Prioritized Register */
87  volatile uint32_t HI_PRI; /* High Priority Prioritized Register */
88  volatile uint32_t LOW; /* Low Priority Interrupt Status Register */
89  volatile uint32_t HI; /* High Priority Interrupt Status Register */
90  volatile uint32_t EOI; /* EOI Interrupt Register */
91  volatile uint8_t Resv_64[12];
92  volatile uint32_t PIN_CTRL; /* Error Pin Control Register */
93  volatile uint32_t PIN_STS; /* Error Pin Status Register */
94  volatile uint32_t PIN_CNTR; /* Error Counter Value Register */
95  volatile uint32_t PIN_CNTR_PRE; /* Error Counter Value Pre-Load Register */
96  volatile uint32_t PWMH_PIN_CNTR; /* Error PWM High Counter Value Register */
97  volatile uint32_t PWMH_PIN_CNTR_PRE; /* Error PWM High Counter Value Pre-Load Register */
98  volatile uint32_t PWML_PIN_CNTR; /* Error PWM Low Counter Value Register */
99  volatile uint32_t PWML_PIN_CNTR_PRE; /* Error PWM Low Counter Value Pre-Load Register */
100  volatile uint8_t Resv_1024[928];
101  SDL_esmRegs_ERR_GRP ERR_GRP[32];
102  SDL_esmRegs_ERR_EXT_GRP ERR_EXT_GRP[32];
103 } SDL_esmRegs;
104 
105 
106 /**************************************************************************
107 * Register Macros
108 **************************************************************************/
109 
110 #define SDL_ESM_PID (0x00000000U)
111 #define SDL_ESM_INFO (0x00000004U)
112 #define SDL_ESM_EN (0x00000008U)
113 #define SDL_ESM_SFT_RST (0x0000000CU)
114 #define SDL_ESM_ERR_RAW (0x00000010U)
115 #define SDL_ESM_ERR_STS (0x00000014U)
116 #define SDL_ESM_ERR_EN_SET (0x00000018U)
117 #define SDL_ESM_ERR_EN_CLR (0x0000001CU)
118 #define SDL_ESM_LOW_PRI (0x00000020U)
119 #define SDL_ESM_HI_PRI (0x00000024U)
120 #define SDL_ESM_LOW (0x00000028U)
121 #define SDL_ESM_HI (0x0000002CU)
122 #define SDL_ESM_EOI (0x00000030U)
123 #define SDL_ESM_PIN_CTRL (0x00000040U)
124 #define SDL_ESM_PIN_STS (0x00000044U)
125 #define SDL_ESM_PIN_CNTR (0x00000048U)
126 #define SDL_ESM_PIN_CNTR_PRE (0x0000004CU)
127 #define SDL_ESM_PWMH_PIN_CNTR (0x00000050U)
128 #define SDL_ESM_PWMH_PIN_CNTR_PRE (0x00000054U)
129 #define SDL_ESM_PWML_PIN_CNTR (0x00000058U)
130 #define SDL_ESM_PWML_PIN_CNTR_PRE (0x0000005CU)
131 #define SDL_ESM_CRITICAL_PRI_INT_DELAY_CNTR (0x00000060U)
132 #define SDL_ESM_CRITICAL_PRI_INT_DELAY_CNTR_PRE (0x00000064U)
133 #define SDL_ESM_ERR_GRP_RAW(ERR_GRP) (0x00000400U+((ERR_GRP)*0x20U))
134 #define SDL_ESM_ERR_GRP_STS(ERR_GRP) (0x00000404U+((ERR_GRP)*0x20U))
135 #define SDL_ESM_ERR_GRP_INTR_EN_SET(ERR_GRP) (0x00000408U+((ERR_GRP)*0x20U))
136 #define SDL_ESM_ERR_GRP_INTR_EN_CLR(ERR_GRP) (0x0000040CU+((ERR_GRP)*0x20U))
137 #define SDL_ESM_ERR_GRP_INT_PRIO(ERR_GRP) (0x00000410U+((ERR_GRP)*0x20U))
138 #define SDL_ESM_ERR_GRP_PIN_EN_SET(ERR_GRP) (0x00000414U+((ERR_GRP)*0x20U))
139 #define SDL_ESM_ERR_GRP_PIN_EN_CLR(ERR_GRP) (0x00000418U+((ERR_GRP)*0x20U))
140 #define SDL_ESM_ERR_GRP_CRITICAL_PRI_EN_SET(ERR_GRP) (0x00000800U+((ERR_GRP)*0x20U))
141 #define SDL_ESM_ERR_GRP_CRITICAL_PRI_EN_CLR(ERR_GRP) (0x00000804U+((ERR_GRP)*0x20U))
142 
143 /**************************************************************************
144 * Field Definition Macros
145 **************************************************************************/
146 
147 
148 /* RAW */
149 
150 #define SDL_ESM_ERR_GRP_RAW_STS_MASK (0xFFFFFFFFU)
151 #define SDL_ESM_ERR_GRP_RAW_STS_SHIFT (0x00000000U)
152 #define SDL_ESM_ERR_GRP_RAW_STS_MAX (0xFFFFFFFFU)
153 
154 /* STS */
155 
156 #define SDL_ESM_ERR_GRP_STS_MSK_MASK (0xFFFFFFFFU)
157 #define SDL_ESM_ERR_GRP_STS_MSK_SHIFT (0x00000000U)
158 #define SDL_ESM_ERR_GRP_STS_MSK_MAX (0xFFFFFFFFU)
159 
160 /* INTR_EN_SET */
161 
162 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MASK (0xFFFFFFFFU)
163 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_SHIFT (0x00000000U)
164 #define SDL_ESM_ERR_GRP_INTR_EN_SET_MSK_MAX (0xFFFFFFFFU)
165 
166 /* INTR_EN_CLR */
167 
168 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
169 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_SHIFT (0x00000000U)
170 #define SDL_ESM_ERR_GRP_INTR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
171 
172 /* INT_PRIO */
173 
174 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MASK (0xFFFFFFFFU)
175 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_SHIFT (0x00000000U)
176 #define SDL_ESM_ERR_GRP_INT_PRIO_MSK_MAX (0xFFFFFFFFU)
177 
178 /* PIN_EN_SET */
179 
180 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MASK (0xFFFFFFFFU)
181 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_SHIFT (0x00000000U)
182 #define SDL_ESM_ERR_GRP_PIN_EN_SET_MSK_MAX (0xFFFFFFFFU)
183 
184 /* PIN_EN_CLR */
185 
186 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MASK (0xFFFFFFFFU)
187 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_SHIFT (0x00000000U)
188 #define SDL_ESM_ERR_GRP_PIN_EN_CLR_MSK_MAX (0xFFFFFFFFU)
189 
190 /* PID */
191 
192 #define SDL_ESM_PID_MINOR_MASK (0x0000003FU)
193 #define SDL_ESM_PID_MINOR_SHIFT (0x00000000U)
194 #define SDL_ESM_PID_MINOR_MAX (0x0000003FU)
195 
196 #define SDL_ESM_PID_CUSTOM_MASK (0x000000C0U)
197 #define SDL_ESM_PID_CUSTOM_SHIFT (0x00000006U)
198 #define SDL_ESM_PID_CUSTOM_MAX (0x00000003U)
199 
200 #define SDL_ESM_PID_MAJOR_MASK (0x00000700U)
201 #define SDL_ESM_PID_MAJOR_SHIFT (0x00000008U)
202 #define SDL_ESM_PID_MAJOR_MAX (0x00000007U)
203 
204 #define SDL_ESM_PID_RTL_MASK (0x0000F800U)
205 #define SDL_ESM_PID_RTL_SHIFT (0x0000000BU)
206 #define SDL_ESM_PID_RTL_MAX (0x0000001FU)
207 
208 #define SDL_ESM_PID_FUNC_MASK (0x0FFF0000U)
209 #define SDL_ESM_PID_FUNC_SHIFT (0x00000010U)
210 #define SDL_ESM_PID_FUNC_MAX (0x00000FFFU)
211 
212 #define SDL_ESM_PID_BU_MASK (0x30000000U)
213 #define SDL_ESM_PID_BU_SHIFT (0x0000001CU)
214 #define SDL_ESM_PID_BU_MAX (0x00000003U)
215 
216 #define SDL_ESM_PID_SCHEME_MASK (0xC0000000U)
217 #define SDL_ESM_PID_SCHEME_SHIFT (0x0000001EU)
218 #define SDL_ESM_PID_SCHEME_MAX (0x00000003U)
219 
220 /* INFO */
221 
222 #define SDL_ESM_INFO_GROUPS_MASK (0x000000FFU)
223 #define SDL_ESM_INFO_GROUPS_SHIFT (0x00000000U)
224 #define SDL_ESM_INFO_GROUPS_MAX (0x000000FFU)
225 
226 #define SDL_ESM_INFO_PULSE_GROUPS_MASK (0x0000FF00U)
227 #define SDL_ESM_INFO_PULSE_GROUPS_SHIFT (0x00000008U)
228 #define SDL_ESM_INFO_PULSE_GROUPS_MAX (0x000000FFU)
229 
230 #define SDL_ESM_INFO_LAST_RESET_MASK (0x80000000U)
231 #define SDL_ESM_INFO_LAST_RESET_SHIFT (0x0000001FU)
232 #define SDL_ESM_INFO_LAST_RESET_MAX (0x00000001U)
233 
234 /* EN */
235 
236 #define SDL_ESM_EN_KEY_MASK (0x0000000FU)
237 #define SDL_ESM_EN_KEY_SHIFT (0x00000000U)
238 #define SDL_ESM_EN_KEY_MAX (0x0000000FU)
239 
240 /* SFT_RST */
241 
242 #define SDL_ESM_SFT_RST_KEY_MASK (0x0000000FU)
243 #define SDL_ESM_SFT_RST_KEY_SHIFT (0x00000000U)
244 #define SDL_ESM_SFT_RST_KEY_MAX (0x0000000FU)
245 
246 /* ERR_RAW */
247 
248 #define SDL_ESM_ERR_RAW_STS_MASK (0xFFFFFFFFU)
249 #define SDL_ESM_ERR_RAW_STS_SHIFT (0x00000000U)
250 #define SDL_ESM_ERR_RAW_STS_MAX (0xFFFFFFFFU)
251 
252 /* ERR_STS */
253 
254 #define SDL_ESM_ERR_STS_MSK_MASK (0xFFFFFFFFU)
255 #define SDL_ESM_ERR_STS_MSK_SHIFT (0x00000000U)
256 #define SDL_ESM_ERR_STS_MSK_MAX (0xFFFFFFFFU)
257 
258 /* ERR_EN_SET */
259 
260 #define SDL_ESM_ERR_EN_SET_MSK_MASK (0xFFFFFFFFU)
261 #define SDL_ESM_ERR_EN_SET_MSK_SHIFT (0x00000000U)
262 #define SDL_ESM_ERR_EN_SET_MSK_MAX (0xFFFFFFFFU)
263 
264 /* ERR_EN_CLR */
265 
266 #define SDL_ESM_ERR_EN_CLR_MSK_MASK (0xFFFFFFFFU)
267 #define SDL_ESM_ERR_EN_CLR_MSK_SHIFT (0x00000000U)
268 #define SDL_ESM_ERR_EN_CLR_MSK_MAX (0xFFFFFFFFU)
269 
270 /* LOW_PRI */
271 
272 #define SDL_ESM_LOW_PRI_PLS_MASK (0xFFFF0000U)
273 #define SDL_ESM_LOW_PRI_PLS_SHIFT (0x00000010U)
274 #define SDL_ESM_LOW_PRI_PLS_MAX (0x0000FFFFU)
275 
276 #define SDL_ESM_LOW_PRI_LVL_MASK (0x0000FFFFU)
277 #define SDL_ESM_LOW_PRI_LVL_SHIFT (0x00000000U)
278 #define SDL_ESM_LOW_PRI_LVL_MAX (0x0000FFFFU)
279 
280 /* HI_PRI */
281 
282 #define SDL_ESM_HI_PRI_PLS_MASK (0xFFFF0000U)
283 #define SDL_ESM_HI_PRI_PLS_SHIFT (0x00000010U)
284 #define SDL_ESM_HI_PRI_PLS_MAX (0x0000FFFFU)
285 
286 #define SDL_ESM_HI_PRI_LVL_MASK (0x0000FFFFU)
287 #define SDL_ESM_HI_PRI_LVL_SHIFT (0x00000000U)
288 #define SDL_ESM_HI_PRI_LVL_MAX (0x0000FFFFU)
289 
290 /* LOW */
291 
292 #define SDL_ESM_LOW_STS_MASK (0xFFFFFFFFU)
293 #define SDL_ESM_LOW_STS_SHIFT (0x00000000U)
294 #define SDL_ESM_LOW_STS_MAX (0xFFFFFFFFU)
295 
296 /* HI */
297 
298 #define SDL_ESM_HI_STS_MASK (0xFFFFFFFFU)
299 #define SDL_ESM_HI_STS_SHIFT (0x00000000U)
300 #define SDL_ESM_HI_STS_MAX (0xFFFFFFFFU)
301 
302 /* EOI */
303 
304 #define SDL_ESM_EOI_KEY_MASK (0x000007FFU)
305 #define SDL_ESM_EOI_KEY_SHIFT (0x00000000U)
306 #define SDL_ESM_EOI_KEY_MAX (0x000007FFU)
307 
308 /* PIN_CTRL */
309 
310 #define SDL_ESM_PIN_CTRL_KEY_MASK (0x0000000FU)
311 #define SDL_ESM_PIN_CTRL_KEY_SHIFT (0x00000000U)
312 #define SDL_ESM_PIN_CTRL_KEY_MAX (0x0000000FU)
313 
314 #define SDL_ESM_PIN_CTRL_PWM_EN_MASK (0x000000F0U)
315 #define SDL_ESM_PIN_CTRL_PWM_EN_SHIFT (0x00000004U)
316 #define SDL_ESM_PIN_CTRL_PWM_EN_MAX (0x0000000FU)
317 
318 /* PIN_STS */
319 
320 #define SDL_ESM_PIN_STS_VAL_MASK (0x00000001U)
321 #define SDL_ESM_PIN_STS_VAL_SHIFT (0x00000000U)
322 #define SDL_ESM_PIN_STS_VAL_MAX (0x00000001U)
323 
324 /* PIN_CNTR */
325 
326 #define SDL_ESM_PIN_CNTR_COUNT_MASK (0x00FFFFFFU)
327 #define SDL_ESM_PIN_CNTR_COUNT_SHIFT (0x00000000U)
328 #define SDL_ESM_PIN_CNTR_COUNT_MAX (0x00FFFFFFU)
329 
330 /* PIN_CNTR_PRE */
331 
332 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MASK (0x00FFFFFFU)
333 #define SDL_ESM_PIN_CNTR_PRE_COUNT_SHIFT (0x00000000U)
334 #define SDL_ESM_PIN_CNTR_PRE_COUNT_MAX (0x00FFFFFFU)
335 
336 #ifdef __cplusplus
337 }
338 #endif
339 #endif /* SDLR_ESM_ */
SDL_esmRegs_ERR_EXT_GRP::CRI_EN_SET
volatile uint32_t CRI_EN_SET
Definition: v2/v2_0/sdlr_esm.h:71
SDL_esmRegs
Definition: v0/v0_0/sdlr_esm.h:71
SDL_esmRegs_ERR_GRP
Definition: v0/v0_0/sdlr_esm.h:59
SDL_esmRegs_ERR_EXT_GRP::CRI_EN_CLR
volatile uint32_t CRI_EN_CLR
Definition: v2/v2_0/sdlr_esm.h:72
SDL_esmRegs_ERR_EXT_GRP
Definition: v2/v2_0/sdlr_esm.h:70