sipc_notify_cfg.h

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/*
 *  Copyright (C) 2022-23 Texas Instruments Incorporated
 *
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 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
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 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 */
#ifndef SIPC_NOTIFY_CFG_H_
#define SIPC_NOTIFY_CFG_H_
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <drivers/hw_include/am263x/cslr_soc.h>
#include <drivers/soc/am263x/soc.h>
#include <kernel/dpl/CpuIdP.h>
 
#define SIPC_MSG_SIZE              (13u)
 
/* Max number of interrupt configs possible for AM263x */
#define INTR_CFG_NUM_MAX           (1u)
 
/* If SIPC is compiled for R5 core then Max client ID = 32
 * Else for HSM its 2 */
 
 
 
/* HSM specific register addresses defined here to remove the dependency on CSL files */
#define HSM_SOC_CTRL_U_BASE                                       (0x40000000U)
#define HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK                       (0x00000048U)
#define HSM_SOC_CTRL_HSM_MBOX_READ_DONE                           (0x0000004CU)
 
/* R5 Register for sending and receiving IPC interrutps
 * As write DONE interrupt line is being used by regular IPC communication we will use READ_DONE_ACK
 * register to post the interrupt to receiving core and it will read READ_DONE register to process
 * that interrupt */
#define R5FSS0_0_MBOX_READ_DONE_ACK    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE_ACK)
#define R5FSS0_0_MBOX_READ_DONE        (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE0_MBOX_READ_DONE)
#define R5FSS0_1_MBOX_READ_DONE_ACK    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE_ACK)
#define R5FSS0_1_MBOX_READ_DONE        (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS0_CORE1_MBOX_READ_DONE)
#define R5FSS1_0_MBOX_READ_DONE_ACK    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE_ACK)
#define R5FSS1_0_MBOX_READ_DONE        (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE0_MBOX_READ_DONE)
#define R5FSS1_1_MBOX_READ_DONE_ACK    (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE_ACK)
#define R5FSS1_1_MBOX_READ_DONE        (CSL_MSS_CTRL_U_BASE + CSL_MSS_CTRL_R5SS1_CORE1_MBOX_READ_DONE)
 
/* HSM registers for sending and receiving IPC interrupts */
#define HSM0_0_MBOX_READ_DONE_ACK         (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE_ACK)
#define HSM0_0_MBOX_READ_DONE             (HSM_SOC_CTRL_U_BASE + HSM_SOC_CTRL_HSM_MBOX_READ_DONE)
 
/* CPU bit positions within the HSM mailbox registers for sending interrupt
 * HSM will write the READ_DONE_ACK register to raise an interrupt to R5 core */
#define R5FSS0_0_MBOX_WRITE_PROC_BIT_POS  ( 0U)
#define R5FSS0_1_MBOX_WRITE_PROC_BIT_POS  ( 4U)
#define R5FSS1_0_MBOX_WRITE_PROC_BIT_POS  ( 8U)
#define R5FSS1_1_MBOX_WRITE_PROC_BIT_POS  ( 12U)
 
/* Bitshift to raise an interrupt from R5 core to HSM */
#define HSM0_0_MBOX_WRITE_PROC_BIT_POS    ( 6U)
 
/* CPU bit positions within the mailbox registers for receiving interrupts */
#define R5FSS0_0_MBOX_READ_PROC_BIT_POS  ( 0U)
#define R5FSS0_1_MBOX_READ_PROC_BIT_POS  ( 4U)
#define R5FSS1_0_MBOX_READ_PROC_BIT_POS  ( 8U)
#define R5FSS1_1_MBOX_READ_PROC_BIT_POS  (12U)
#define HSM0_0_MBOX_READ_PROC_BIT_POS    (24U)
 
/* Mailbox interrupts numbers */
#define R5FSS0_0_MBOX_READ_ACK_INTR      ( 137U)
#define R5FSS0_1_MBOX_READ_ACK_INTR      ( 137U)
#define R5FSS1_0_MBOX_READ_ACK_INTR      ( 137U)
#define R5FSS1_1_MBOX_READ_ACK_INTR      ( 137U)
#define HSM0_0_MBOX_READ_ACK_INTR        ( 56U )
 
typedef enum SIPC_CoreId_
{
    CORE_ID_R5FSS0_0 = 0,
    CORE_ID_R5FSS0_1,
    CORE_ID_R5FSS1_0,
    CORE_ID_R5FSS1_1,
    CORE_ID_HSM0_0  ,
    CORE_ID_MAX
} SIPC_coreId;
 
typedef enum SIPC_SecCoreId_
{
    CORE_INDEX_SEC_MASTER_0 = 0,
    CORE_INDEX_SEC_MASTER_1 ,
    CORE_INDEX_HSM,
    MAX_SEC_CORES_WITH_HSM
}SIPC_SecCoreId;
 
#if defined(__ARM_ARCH_7R__)
 
/* If building for R5 then read selfcore ID from the Core Cluster register */
static uint32_t SIPC_readSelfCoreID(void)
{
    uint32_t coreId ;
    CSL_ArmR5CPUInfo cpuId = {0, 0};
    CSL_armR5GetCpuID(&cpuId);
    /* both cpuId and greId fields can be either 0 or 1
     * ex for R5FSS1-0 core grpId = 1 and cpu id = 0 */
    coreId = cpuId.cpuID | (cpuId.grpId) << 1 ;
    return coreId;
}
#define SELF_CORE_ID                  (SIPC_readSelfCoreID())
 
#define SIPC_CLIENT_ID_MAX            (5U)
 
#else
#define SIPC_CLIENT_ID_MAX            (2U)
#define SELF_CORE_ID                  (CORE_ID_HSM0_0)
#endif
 
/*
 *  Client ID used by HSM server's boot notify message
 */
#define SIPC_BOOT_NOTIFY_CLIENT_ID   (0U)
 
#ifdef __cplusplus
}
#endif
 
#endif