cslr_soc_defines.h

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/*
 *  Copyright (C) 2020-25 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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 */
 
#ifndef CSLR_SOC_DEFINES_H_
#define CSLR_SOC_DEFINES_H_
 
/* ========================================================================== */
/*                             Include Files                                  */
/* ========================================================================== */
#include <stdint.h>
 
 
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* ========================================================================== */
/*                           Macros & Typedefs                                */
/* ========================================================================== */
#define CSL_UART_PER_CNT                (6U)
 
#define CSL_SPI_PER_CNT                (8U)
 
#define CSL_LIN_PER_CNT                (5U)
 
#define CSL_I2C_PER_CNT                (4U)
 
#define CSL_MCAN_PER_CNT                (8U)
 
#define CSL_ETPWM_PER_CNT                (32U)
 
#define CSL_ECAP_PER_CNT                (16U)
 
#define CSL_EQEP_PER_CNT                (3U)
 
#define CSL_SDFM_PER_CNT                (2U)
 
#define CSL_ADC_PER_CNT                (5U)
 
#define CSL_CMPSSA_PER_CNT                (10U)
 
#define CSL_CMPSSB_PER_CNT                (10U)
 
#define SOC_EDMA_NUM_DMACH                 (64U)
 
#define SOC_EDMA_NUM_QDMACH                (8U)
 
#define SOC_EDMA_NUM_PARAMSETS             (256U)
 
#define SOC_EDMA_NUM_EVQUE                 (2U)
 
#define SOC_EDMA_CHMAPEXIST                (1U)
 
#define SOC_EDMA_NUM_REGIONS               (8U)
 
#define SOC_EDMA_MEMPROTECT                (1U)
 
#define SOC_EDMA_NUM_TPTC                  (2U)
 
#define EDMA_TPCC_A_ERRINT                (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_ERRINT_MASK)
#define EDMA_TPCC_A_MPINT                 (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_MPINT_MASK)
#define EDMA_TPTC_A0_ERR                  (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_ERR_MASK)
#define EDMA_TPTC_A1_ERR                  (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_ERR_MASK)
#define EDMA_TPCC_A_PAR_ERR               (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_PAR_ERR_MASK)
#define EDMA_TPCC_A_WRITE_ACCESS_ERROR    (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_WRITE_ACCESS_ERROR_MASK)
#define EDMA_TPTC_A0_WRITE_ACCESS_ERROR   (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_WRITE_ACCESS_ERROR_MASK)
#define EDMA_TPTC_A1_WRITE_ACCESS_ERROR   (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_WRITE_ACCESS_ERROR_MASK)
#define EDMA_TPCC_A_READ_ACCESS_ERROR     (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPCC_A_READ_ACCESS_ERROR_MASK)
#define EDMA_TPTC_A0_READ_ACCESS_ERROR    (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A0_READ_ACCESS_ERROR_MASK)
#define EDMA_TPTC_A1_READ_ACCESS_ERROR    (CSL_MSS_CTRL_TPCC0_ERRAGG_STATUS_TPTC_A1_READ_ACCESS_ERROR_MASK)
 
#define MCAN_MSG_RAM_MAX_WORD_COUNT     (4352U)
 
#define MCAN_MAX_RX_DMA_BUFFERS             (7U)
 
#define MCAN_MAX_TX_DMA_BUFFERS             (4U)
 
#define FSI_MAX_TX_DMA_BUFFERS              (2U)
 
#define FSI_MAX_RX_DMA_BUFFERS              (2U)
 
#define MCSPI_DMA_IS_FIFO_SUPPORTED          (1U)
 
#define CSL_CORE_ID_R5FSS0_0         (0U)
#define CSL_CORE_ID_R5FSS0_1         (1U)
#define CSL_CORE_ID_R5FSS1_0         (2U)
#define CSL_CORE_ID_R5FSS1_1         (3U)
#define CSL_CORE_ID_MAX              (4U)
 
#define PRIV_ID_M4FSS0_0         (1U)
#define PRIV_ID_R5FSS0_0         (4U)
#define PRIV_ID_R5FSS0_1         (5U)
#define PRIV_ID_R5FSS1_0         (6U)
#define PRIV_ID_R5FSS1_1         (7U)
#define PRIV_ID_ICSSM            (9U)
#define PRIV_ID_CPSW             (10U)
 
/***********************************************************************
 * MSS - CLOCK setting
 ***********************************************************************/
 /* Sys_vclk : 200MHz */
#define MSS_SYS_VCLK                  200000000U
#define R5F_CLOCK_MHZ                 400U
 
#define CSL_ARM_R5_CLUSTER_GROUP_ID_0                 ((uint32_t) 0x00U)
 
#define CSL_ARM_R5_CLUSTER_GROUP_ID_1                 ((uint32_t) 0x01U)
 
#define CSL_ARM_R5_CPU_ID_0                          ((uint32_t) 0x00U)
 
#define CSL_ARM_R5_CPU_ID_1                          ((uint32_t) 0x01U)
 
#define CSL_CORE_R5F_INTR_MAX  (256U)      
 
/***********************************************************************
 * Cache line size definitions
 ***********************************************************************/
/* Cache line size definitions  */
#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
#define CSL_CACHE_L1P_LINESIZE     (32U)
#define CSL_CACHE_L1D_LINESIZE     (32U)
#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') /* M4F */
/* No cache support */
#endif
 
/* ========================================================================== */
/*                         Structures and Enums                               */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                            Global Variables                                */
/* ========================================================================== */
 
/* None */
 
/* ========================================================================== */
/*                          Function Declarations                             */
/* ========================================================================== */
 
/* None */
 
#ifdef __cplusplus
}
#endif
 
#endif  /* CSLR_SOC_DEFINES_H_ */