Introduction
The example demonstrates the PMIC watchdog in Q&A mode which will generate a warm reset when the core fails to send the answers to the watchdog. The application configures the GPIO pins and the watchdog in the PMIC to send and receive the Q&A signals. It services the watchdog for few iterations and stops sending the answers. Then, the core will wait for sometime based on the reset threshold value configured in the watchdog for the warm reset to occur. If the warm reset occurs, the test passes else fails.
- Note
- This example won't work in the debug mode as the user must not service the watchdog while in debug mode. Flash the application to get the expected result.
Supported Combinations
| Parameter | Value |
| CPU + OS | r5fss0-0 freertos |
| r5fss0-0 nortos |
| Toolchain | ti-arm-clang |
| Boards | am263px-cc |
| Example folder | examples/drivers/pmic/pmic_qa_watchdog_reset |
Steps to Run the Example
- When using CCS projects to build, import the CCS project for the required combination and build it using the CCS project menu (see Using SDK with CCS Projects).
- When using makefiles to build, note the required combination and build using make command (see Using SDK with Makefiles)
- As it is a watchdog example, it cannot be loaded through CCS as it may fail in debug mode. It should be flashed and booted through SBL to get the expected results.
- Refer Flash a Hello World example for flashing the application.
- Set bootmode to UART BOOT MODE and flash the binary using the following command from {SDK_INSTALLTION_PATH}/tools/boot
- Modify the existing default_sbl_ospi.cfg with the correct path of the application image.
python uart_uniflash.py -p COM<x> --cfg=sbl_prebuilt/am261x-lp/default_sbl_ospi.cfg
- Power OFF and change the boot mode to OSPI BOOT MODE
- Logs should appear at the UART port
Sample Output
Shown below is a sample output when the application is run,
Starting Q&A watchdog reset example !!
Checking if prerequisites for configuring the WDG has been met...
Configure PMIC watchdog in Q&A mode... DONE
Started watchdog sequence... Sending answers to the PMIC...
Stopped sending watchdog answers... Waiting for the warm reset to occur...
Warm reset has occurred due to watchdog failure!!
All tests have passed!!