soc.h

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/*
 *  Copyright (C) 2021-2023 Texas Instruments Incorporated
 *
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 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
#ifndef SOC_AM263PX_H_
#define SOC_AM263PX_H_
 
#ifdef __cplusplus
extern "C"
{
#endif
 
#include <kernel/dpl/SystemP.h>
#include <drivers/hw_include/cslr_soc.h>
#include "soc_xbar.h"
#include "soc_rcm.h"
 
#define SOC_DOMAIN_ID_MAIN     (0U)
 
/*Control MMRs partition*/
#define MSS_CTRL_PARTITION0                                (1)
#define TOP_CTRL_PARTITION0                                (2)
#define CONTROLSS_CTRL_PARTITION0                          (3)
 
/*Clock and reset MMRs partition*/
#define MSS_RCM_PARTITION0                                 (4)
#define TOP_RCM_PARTITION0                                 (5)
 
/*Pinmux MMR*/
//#define IOMUX_PARTITION0                                   (6)
 
 
/* define the unlock and lock values for MSS_CTRL, TOP_CTRL, MSS_RCM, TOP_RCM*/
#define KICK_LOCK_VAL                           (0x00000000U)
#define KICK0_UNLOCK_VAL                        (0x01234567U)
#define KICK1_UNLOCK_VAL                        (0x0FEDCBA8U)
 
/* defines the Inputs to the SOC_selectAdcExtChXbarAPI for extChXbarIn param */
#define ADC0_EXTCHSEL_BIT0                       (0U)
#define ADC0_EXTCHSEL_BIT1                       (1U)
#define ADC1_EXTCHSEL_BIT0                       (2U)
#define ADC1_EXTCHSEL_BIT1                       (3U)
#define ADC2_EXTCHSEL_BIT0                       (4U)
#define ADC2_EXTCHSEL_BIT1                       (5U)
#define ADC3_EXTCHSEL_BIT0                       (6U)
#define ADC3_EXTCHSEL_BIT1                       (7U)
#define ADC4_EXTCHSEL_BIT0                       (8U)
#define ADC4_EXTCHSEL_BIT1                       (9U)
#define ADC_R0_EXTCHSEL_BIT0                     (10U)
#define ADC_R0_EXTCHSEL_BIT1                     (11U)
#define ADC_R1_EXTCHSEL_BIT0                     (12U)
#define ADC_R2_EXTCHSEL_BIT1                     (13U)
 
 
#define ADC_EXTCHSELCT_DELAY_3_CYCLES            (0U)
#define ADC_EXTCHSELCT_DELAY_6_CYCLES            (1U)
 
static inline int32_t MCSPI_lld_isBaseAddrValid(uint32_t baseAddr)
{
    int32_t status = (int32_t)-3;
 
    if ((baseAddr == CSL_MCSPI0_U_BASE) || \
        (baseAddr == CSL_MCSPI1_U_BASE) || \
        (baseAddr == CSL_MCSPI2_U_BASE) || \
        (baseAddr == CSL_MCSPI3_U_BASE) || \
        (baseAddr == CSL_MCSPI4_U_BASE) || \
        (baseAddr == CSL_MCSPI5_U_BASE) || \
        (baseAddr == CSL_MCSPI6_U_BASE) || \
        (baseAddr == CSL_MCSPI7_U_BASE) )
    {
        status = 0;
    }
 
    return status;
}
#define IS_I2C_BASE_ADDR_VALID(baseAddr)    ((baseAddr == CSL_I2C0_U_BASE) || \
                                             (baseAddr == CSL_I2C1_U_BASE) || \
                                             (baseAddr == CSL_I2C2_U_BASE) || \
                                             (baseAddr == CSL_I2C3_U_BASE))
 
int32_t SOC_moduleClockEnable(uint32_t moduleId, uint32_t enable);
 
int32_t SOC_moduleSetClockFrequency(uint32_t moduleId, uint32_t clkId, uint64_t clkRate);
 
const char *SOC_getCoreName(uint16_t coreId);
 
uint64_t SOC_getSelfCpuClk(void);
 
void SOC_controlModuleLockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_controlModuleUnlockMMR(uint32_t domainId, uint32_t partition);
 
void SOC_setEpwmTbClk(uint32_t epwmInstance, uint32_t enable);
 
void SOC_setMultipleEpwmTbClk(uint32_t epwmMask, uint32_t enable);
 
void SOC_enableAdcReference(uint32_t adcInstance);
void SOC_enableAdcOsdChannel(uint32_t adcInstance, uint32_t channel, uint32_t enable);
 
void SOC_setAdcOsdConfig(uint32_t adcInstance, uint32_t config);
 
void SOC_enableAdcGlobalForce(uint32_t adcInstance, uint32_t enable);
 
void SOC_adcSocGlobalForce(uint32_t socNumber);
void SOC_selectAdcExtChXbar(uint32_t extChXbarOut, uint32_t extChXbarIn);
 
void SOC_selextAdcExtChDelay(uint32_t delay);
 
void SOC_enableAdcDacLoopback(uint32_t enable);
 
void SOC_setEpwmGroup(uint32_t epwmInstance, uint32_t group);
 
void SOC_selectSdfm1Clk0Source(uint8_t source);
 
 
void SOC_sdfmClkLoopBackConfig(uint32_t sdfmInstance, uint32_t clkInstance, uint32_t defaultValue);
 
void SOC_gateEpwmClock(uint32_t epwmInstance);
 
void SOC_gateFsitxClock(uint32_t fsitxInstance);
 
void SOC_gateFsirxClock(uint32_t fsirxInstance);
 
void SOC_gateCmpssaClock(uint32_t cmpssaInstance);
 
void SOC_gateCmpssbClock(uint32_t cmpssbInstance);
 
void SOC_gateEcapClock(uint32_t ecapInstance);
 
void SOC_gateEqepClock(uint32_t eqepInstance);
 
void SOC_gateSdfmClock(uint32_t sdfmInstance);
 
void SOC_gateDacClock(void);
 
void SOC_gateAdcClock(uint32_t adcInstance);
 
void SOC_gateRdcClock(uint32_t rdcInstance);
 
void SOC_gateOttoClock(uint32_t ottoInstance);
 
void SOC_gateSdfmPllClock(uint32_t sdfmInstance);
 
void SOC_gateFsiPllClock(uint32_t fsiInstance);
 
void SOC_generateEpwmReset(uint32_t ePWMInstance);
 
void SOC_generateFsiTxReset(uint32_t fsitxInstance);
 
void SOC_generateFsiRxReset(uint32_t fsirxInstance);
 
void SOC_generateCmpssaReset(uint32_t cmpssaInstance);
 
void SOC_generateCmpssbReset(uint32_t cmpssbInstance);
 
void SOC_generateEcapReset(uint32_t ecapInstance);
 
void SOC_generateEqepReset(uint32_t eqepInstance);
 
void SOC_generateSdfmReset(uint32_t sdfmInstance);
 
void SOC_generateDacReset(void);
 
void SOC_generateAdcReset(uint32_t adcInstance);
 
void SOC_generateRdcReset(uint32_t rdcInstance);
 
void Soc_enableEPWMHalt (uint32_t epwmInstance);
 
void SOC_generateOttoReset(uint32_t ottoInstance);
 
void SOC_selectIcssGpiMux(uint8_t pru_instance, uint32_t mask);
 
uint64_t SOC_virtToPhy(void *virtAddr);
 
void *SOC_phyToVirt(uint64_t phyAddr);
 
uint32_t SOC_getFlashDataBaseAddr(void);
 
static inline int32_t UART_IsBaseAddrValid(uint32_t baseAddr)
{
    int32_t status = (int32_t)-3;
 
    if(((baseAddr == CSL_UART0_U_BASE) ||
        (baseAddr == CSL_UART1_U_BASE) ||
        (baseAddr == CSL_UART2_U_BASE) ||
        (baseAddr == CSL_UART3_U_BASE) ||
        (baseAddr == CSL_UART4_U_BASE) ||
        (baseAddr == CSL_UART5_U_BASE)))
    {
        status = 0;
    }
 
    return status;
}
 
#ifdef __cplusplus
}
#endif
 
#endif