AM263Px MCU+ SDK  09.02.00
resolver/v0/resolver.h
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1 /*
2  * Copyright (C) 2021 Texas Instruments Incorporated
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31  */
32 
42 #ifndef RESOLVER_V1_H_
43 #define RESOLVER_V1_H_
44 
45 //*****************************************************************************
46 //
47 // If building with a C++ compiler, make all of the definitions in this header
48 // have a C binding.
49 //
50 //*****************************************************************************
51 #ifdef __cplusplus
52 extern "C"
53 {
54 #endif
55 
56 //*****************************************************************************
57 //
59 //
60 //*****************************************************************************
61 #include <stdint.h>
62 #include <stdbool.h>
63 #include <drivers/hw_include/hw_types.h>
64 #include <drivers/hw_include/cslr_soc.h>
65 #include <kernel/dpl/DebugP.h>
66 #include <drivers/hw_include/cslr_resolver.h>
67 
68 //*****************************************************************************
69 //
70 // Defines for the API.
71 //
72 //*****************************************************************************
73 //*****************************************************************************
74 //
76 //
77 //*****************************************************************************
78 #define RDC_CORE_OFFSET (CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_1 - CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0)
79 
82 #define RDC_EXCITATION_FREQUENCY_MIN_PHASE (0U)
83 
85 #define RDC_EXCITATION_FREQUENCY_MAX_PHASE (7999U)
86 
89 #define RDC_MAX_EXCITATION_AMPLITUDE (249U)
90 
93 #define RDC_RESOLVER_CORE0 (0U)
94 
96 #define RDC_RESOLVER_CORE1 (1U)
97 
98 
99 #define RDC_ADC_CAL_CHANNEL0 (0U)
100 #define RDC_ADC_CAL_CHANNEL1 (1U)
101 #define RDC_ADC_CAL_CHANNEL2 (2U)
102 #define RDC_ADC_CAL_CHANNEL3 (3U)
103 
104 
105 #define RDC_DC_OFFSET_SIN_ESTIMATION (0U)
106 #define RDC_DC_OFFSET_COS_ESTIMATION (1U)
107 
108 
109 #define RDC_MIN_IDEAL_SAMPLE_PEAK_AVG_LIMIT (0U)
110 #define RDC_MAX_IDEAL_SAMPLE_PEAK_AVG_LIMIT (7U)
111 
112 #define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST (0x0000001FU)
113 
114 #define RDC_SINGALMODE_SINGLE_ENDED (0U)
115 #define RDC_SINGALMODE_DIFFERENTIAL_ENDED (1U)
116 
117 
118 //*****************************************************************************
119 //
123 //
124 //*****************************************************************************
127 #define RDC_ADC_BURST_COUNT_DISABLE (1U)
128 
130 #define RDC_ADC_BURST_COUNT_2 (2U)
131 
133 #define RDC_ADC_BURST_COUNT_4 (4U)
134 
136 #define RDC_ADC_BURST_COUNT_8 (8U)
137 
139 #define RDC_ADC_BURST_COUNT_16 (16U)
140 
142 #define RDC_ADC_BURST_COUNT_32 (32U)
143 
144 
145 //*****************************************************************************
146 //
150 //
152 //
153 //*****************************************************************************
157 #define RDC_SEQUENCER_MODE_0 (0U)
158 
161 #define RDC_SEQUENCER_MODE_1 (1U)
162 
166 #define RDC_SEQUENCER_MODE_2 (2U)
167 
174 #define RDC_SEQUENCER_MODE_3 (3U)
175 
182 #define RDC_SEQUENCER_MODE_4 (4U)
183 
189 #define RDC_SEQUENCER_MODE_5 (5U)
190 
191 
192 //*****************************************************************************
193 //
197 //
199 //
200 //*****************************************************************************
203 #define RDC_EXCITATION_FREQUENCY_5K (50)
204 
206 #define RDC_EXCITATION_FREQUENCY_10K (100)
207 
209 #define RDC_EXCITATION_FREQUENCY_20K (200)
210 
211 
212 //*****************************************************************************
213 //
217 //
219 //
220 //*****************************************************************************
225 #define OVERSAMPLING_RATIO_16 (8)
226 
230 #define OVERSAMPLING_RATIO_20 (10)
231 
232 //*****************************************************************************
233 //
238 //
241 //
242 //*****************************************************************************
247 #define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR (0x00000001U)
248 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR (0x00000002U)
249 #define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR (0x00000004U)
250 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR (0x00000008U)
251 #define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR (0x00000010U)
252 #define RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR (0x00000020U)
253 #define RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR (0x00000040U)
254 #define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR (0x00000080U)
255 #define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR (0x00000100U)
256 #define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR (0x00000200U)
257 #define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR (0x00000400U)
258 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR (0x00000800U)
259 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR (0x00001000U)
260 #define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR (0x00002000U)
261 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR (0x00004000U)
262 #define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR (0x00008000U)
263 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR (0x00010000U)
264 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR (0x00020000U)
265 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR (0x00040000U)
266 #define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR (0x00080000U)
267 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR (0x00100000U)
268 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR (0x00200000U)
269 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR (0x00400000U)
270 #define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR (0x00800000U)
271 #define RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR (0x01000000U)
272 
273 #define RDC_INTERRUPT_SOURCE_ALL (RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR | \
274  RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR | \
275  RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR | \
276  RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR | \
277  RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR | \
278  RDC_INTERRUPT_SOURCE_COS_MULTI_ZC_ERROR_ERR | \
279  RDC_INTERRUPT_SOURCE_SIN_MULTI_ZC_ERROR_ERR | \
280  RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR | \
281  RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR | \
282  RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR | \
283  RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR | \
284  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR | \
285  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR | \
286  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR | \
287  RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR | \
288  RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR | \
289  RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR | \
290  RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR | \
291  RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR | \
292  RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR | \
293  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR | \
294  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR | \
295  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR | \
296  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR | \
297  RDC_INTERRUPT_SOURCE_TRACK_LOCK_ERR)
298 
299 //*****************************************************************************
300 //
304 //
305 //*****************************************************************************
308 #define RDC_CAL_ADC0 (0U)
309 
311 #define RDC_CAL_ADC1 (1U)
312 
313 //*****************************************************************************
314 //
318 //
319 //*****************************************************************************
323 #define RDC_IDEAL_SAMPLE_TIME_MODE_0_AUTO_DETECT (0U)
324 
327 #define RDC_IDEAL_SAMPLE_TIME_MODE_1_AUTO_DETECT_ON_SIN (1U)
328 
331 #define RDC_IDEAL_SAMPLE_TIME_MODE_2_AUTO_DETECT_ON_COS (2U)
332 
335 #define RDC_IDEAL_SAMPLE_TIME_MODE_3_AUTO_DETECT_OFF (3U)
336 
337 //*****************************************************************************
338 //
342 //
343 //*****************************************************************************
344 
349 typedef struct
350 {
351  uint8_t kvelfilt;
352 } Track2Constants_t;
353 
354 //*****************************************************************************
355 //
360 //
361 //*****************************************************************************
366 typedef struct
367 {
368  int16_t offset_drift_threshold_hi;
369  int16_t offset_drift_threshold_lo;
370  bool offset_drift_cos_hi;
371  bool offset_drift_cos_lo;
372  bool offset_drift_sin_hi;
373  bool offset_drift_sin_lo;
374  bool offset_drift_en;
375 } Diag_Mon_SinCos_Offset_drift_data;
376 
377 //*****************************************************************************
378 //
383 //
384 //*****************************************************************************
389 typedef struct
390 {
391  int16_t gain_drift_threshold_hi;
392  int16_t gain_drift_threshold_lo;
393  uint8_t gain_drift_glitch_count;
394  bool gain_drift_cos_hi;
395  bool gain_drift_cos_lo;
396  bool gain_drift_sin_hi;
397  bool gain_drift_sin_lo;
398  bool gaindrift_en;
399 } Diag_Mon_SinCos_Gain_drift_data;
400 
401 //*****************************************************************************
402 //
407 //
408 //*****************************************************************************
413 typedef struct
414 {
415  int16_t phase_drift_threshold_hi;
416  int16_t phase_drift_threshold_lo;
417  uint8_t phase_drift_glitch_count;
418  bool phase_drift_cos_hi;
419  bool phase_drift_cos_lo;
420  bool phase_drift_en;
421 } Diag_Mon_Cos_Phase_drift_data;
422 
423 //*****************************************************************************
424 //
429 //
430 //*****************************************************************************
435 typedef struct
436 {
437  uint16_t excfreqdetected_sin;
438  uint16_t excfreqdetected_cos;
439  uint16_t excfreqdrift_threshold_hi;
440  uint16_t excfreqdrift_threshold_lo;
441  uint16_t excfreq_level;
442  uint8_t excfreqdrift_glitchcount;
443  bool excfreqdrift_hi;
444  bool excfreqdrift_cos_lo;
445  bool excfreqdrift_sin_lo;
446  bool excfreqdrift_en;
447 } Diag_Mon_ExcFreq_Degradataion_data;
448 
449 //*****************************************************************************
450 //
455 //
456 //*****************************************************************************
461 typedef struct
462 {
463  bool cos_neg_zc_peak_mismatch_err;
464  bool cos_pos_zc_peak_mismatch_err;
465  bool sin_neg_zc_peak_mismatch_err;
466  bool sin_pos_zc_peak_mismatch_err;
467  bool sin_multi_zc_error_err;
468  bool cos_multi_zc_error_err;
469  uint8_t cos_multi_zc_error_count;
470  uint8_t sin_multi_zc_error_count;
471  uint16_t rotpeak_level;
472  uint16_t rotfreq_level;
473  bool zero_cross_rot_en;
474 } Diag_Mon_Rotational_Signal_Integrity_data;
475 
476 
477 //*****************************************************************************
478 //
483 //
484 //*****************************************************************************
489 typedef struct
490 {
491  uint16_t sinsqcossq_threshold_hi;
492  uint16_t sinsqcossq_threshold_lo;
493  uint8_t sinsqcossq_glitchcount;
494  uint16_t sinsqcossq_cossq;
495  uint16_t sinsqcossq_sinsq;
496  bool sinsqcossq_hi;
497  bool sinsqcossq_lo;
498 } Diag_Mon_Signal_Integrity_SinSq_CosSq;
499 
500 //*****************************************************************************
501 //
506 //
507 //*****************************************************************************
512 typedef struct
513 {
514  uint16_t highAmplitude_threshold;
515  uint8_t highAmplitude_glitchcount;
516  int16_t highAmplitude_sin_value;
517  int16_t highAmplitude_cos_value;
518  bool highAmplitude_sin_error;
519  bool highAmplitude_cos_error;
520 } Diag_Mon_Sin_Cos_High_Amplitude;
521 
522 //*****************************************************************************
523 //
528 //
529 //*****************************************************************************
534 typedef struct
535 {
536  uint16_t lowAmplitude_threshold;
537  uint8_t lowAmplitude_glitchcount;
538  bool lowAmplitude_error;
539  int16_t lowAmplitude_sin_value;
540  int16_t lowAmplitude_cos_value;
541 } Diag_Mon_Sin_Cos_Weak_Amplitude;
542 
543 
544 //*****************************************************************************
545 //
550 //
551 //*****************************************************************************
563 typedef struct
564 {
565  int16_t cos_adc;
566  int16_t sin_adc;
567  int16_t cos_rec;
568  int16_t sin_rec;
569  int16_t cos_dc;
570  int16_t sin_dc;
571  int16_t cos_pgc;
572  int16_t sin_pgc;
573 } ADC_observationalData;
574 
575 
581 typedef struct
582 {
583  bool BpfDc_bpfEnable;
584  bool BpfDc_offsetCorrectionEnable;
585  uint8_t BpfDc_dcOffCal1;
586  uint8_t BpfDc_dcOffCal2;
587  int16_t BpfDc_manualSin;
588  int16_t BpfDc_manualCos;
589 
590  uint8_t IdealSample_overrideValue;
591  uint16_t IdealSample_absThresholdValue;
592  uint8_t IdealSample_sampleAdjustCount;
593  uint8_t IdealSample_mode;
594  bool IdealSample_bottomSampleEnable;
595 
596  bool Pg_estimationEnable;
597  uint8_t Pg_estimationLimit;
598 
599  bool Pg_correctionEnable;
600  bool Pg_autoCorrectionEnable;
601  int16_t Pg_sinGainBypassValue;
602  int16_t Pg_cosGainBypassValue;
603  int16_t Pg_cosPhaseBypassValue;
604 
605  Track2Constants_t track2Constants;
606 }Core_config_t;
607 
615 typedef struct
616 {
617  bool adv_config;
618  uint8_t Input_signalMode;
619  uint8_t Input_socWidth;
620  uint8_t Input_adcBurstCount;
621  uint8_t Input_resolverSequencerMode;
622 
623  uint8_t ExcFrq_freqSel;
624  uint16_t ExcFrq_phase;
625  uint8_t ExcFrq_amplitude;
626  bool ExcFrq_enableSyncIn;
627  uint16_t ExcFrq_socDelay;
628 
629  Core_config_t core0;
630  Core_config_t core1;
631 
632  bool Int_seqEnable;
633  uint32_t Int_core0Interrupts;
634  uint32_t Int_core1Interrupts;
635 
636 }RDC_configParams;
637 
643 typedef struct
644 {
645  uint8_t adcParam1;
646  uint8_t IdealParam2;
647  uint8_t DcParam3;
648  uint16_t PgParam4;
649  uint8_t t2Param5;
650  uint8_t t2Param6;
651  uint8_t t2Param7;
652  uint8_t t2Param8;
653  bool t2Param9;
654 }baselineParameters;
655 
656 //*****************************************************************************
657 //
661 //
662 //*****************************************************************************
669 typedef struct
670 {
671  uint8_t peakHistgoramBucket[20];
672 }PeakHistogram_observationalData;
673 
674 //*****************************************************************************
675 // GLOBAL CONFIGURATIONS
676 //*****************************************************************************
683  static inline void
684  RDC_setAdcSocWidth(uint32_t base, uint8_t socWidth)
685  {
686  HW_WR_REG32(
687  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
688  (HW_RD_REG32(
689  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
690  ~CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_MASK) |
691  (((uint8_t)socWidth) << CSL_RESOLVER_REGS_GLOBAL_CFG_SOC_WIDTH_SHIFT));
692  }
706  static inline void
707  RDC_setAdcBurstCount(uint32_t base, uint8_t burstCount)
708  {
709  HW_WR_REG32(
710  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
711  (HW_RD_REG32(
712  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
713  ~CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_MASK) |
714  ((uint32_t)(((uint8_t)burstCount) << CSL_RESOLVER_REGS_GLOBAL_CFG_BURST_CNT_SHIFT)));
715  }
716 
723  static inline void
724  RDC_enableAdcSingleEndedMode(uint32_t base)
725  {
726  HW_WR_REG32(
727  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
728  (HW_RD_REG32(
729  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
730  ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK) |
731  ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_SHIFT)));
732  }
733 
740  static inline void
741  RDC_disableAdcSingleEndedMode(uint32_t base)
742  {
743  HW_WR_REG32(
744  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
745  (HW_RD_REG32(
746  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
747  ~CSL_RESOLVER_REGS_GLOBAL_CFG_SINGLE_EN_MASK));
748  }
749 
750 
769  static inline uint32_t
770  RDC_getAdcSequencerOperationalMode(uint32_t base)
771  {
772  return ((HW_RD_REG32(
773  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
774  CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) >>
775  CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT);
776  }
777 
797  static inline void
798  RDC_setAdcSequencerOperationalMode(uint32_t base, uint8_t operationalMode)
799  {
800  DebugP_assert(
801  (operationalMode >= RDC_SEQUENCER_MODE_0) &&
802  (operationalMode <= RDC_SEQUENCER_MODE_5));
803 
804  HW_WR_REG32(
805  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
806  (HW_RD_REG32(
807  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
808  ~CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_MASK) |
809  ((uint32_t)((operationalMode) << CSL_RESOLVER_REGS_GLOBAL_CFG_MODE_SHIFT)));
810  }
817  static inline void
818  RDC_enableResolver(uint32_t base)
819  {
820  HW_WR_REG32(
821  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
822  (HW_RD_REG32(
823  base + CSL_RESOLVER_REGS_GLOBAL_CFG) &
824  ~CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) |
825  ((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
826  }
833  static inline void
834  RDC_disableResolver(uint32_t base)
835  {
836  HW_WR_REG32(
837  base + CSL_RESOLVER_REGS_GLOBAL_CFG,
838  (HW_RD_REG32(
839  base + CSL_RESOLVER_REGS_GLOBAL_CFG) |
840  CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_MASK) &
841  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_GLOBAL_CFG_MASTER_EN_SHIFT)));
842  }
843 
844 //*****************************************************************************
845 // EXCITATION FREQUENCY AND SAMPLING CONFIGURATIONS
846 //*****************************************************************************
847 
855  static inline void
856  RDC_setExcitationSignalPhase(uint32_t base, uint16_t phase)
857  {
858  DebugP_assert(
859  (phase >= RDC_EXCITATION_FREQUENCY_MIN_PHASE) && (phase <= RDC_EXCITATION_FREQUENCY_MAX_PHASE));
860  HW_WR_REG32(
861  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
862  (HW_RD_REG32(
863  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
864  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) |
865  ((uint32_t)(phase << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT)));
866  }
867 
875  static inline uint32_t
876  RDC_getExcitationSignalPhase(uint32_t base)
877  {
878  return (
879  (HW_RD_REG32(
880  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
881  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_MASK) >>
882  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_PHASE_CFG_SHIFT);
883  }
884 
894  static inline void
895  RDC_setExcitationSignalFrequencySelect(uint32_t base, uint8_t FrequencySel)
896  {
897  DebugP_assert(
898  (FrequencySel == RDC_EXCITATION_FREQUENCY_5K) ||
899  (FrequencySel == RDC_EXCITATION_FREQUENCY_10K) ||
900  (FrequencySel == RDC_EXCITATION_FREQUENCY_20K));
901  HW_WR_REG32(
902  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1,
903  (HW_RD_REG32(
904  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
905  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) |
906  ((uint32_t)(FrequencySel << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT)));
907  }
908 
918  static inline uint32_t
919  RDC_getExcitationSignalFrequencySelect(uint32_t base)
920  {
921  return (
922  (HW_RD_REG32(
923  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
924  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_MASK) >>
925  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_EXC_FREQ_SEL_SHIFT);
926  }
927 
934  static inline uint32_t
935  RDC_getAdcSampleRate(uint32_t base)
936  {
937  return (
938  (HW_RD_REG32(
939  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1) &
940  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_MASK) >>
941  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG1_ADC_SAMPLE_RATE_SHIFT);
942  }
943 
949  static inline void
950  RDC_enableExcitationSignalSyncIn(uint32_t base)
951  {
952  HW_WR_REG32(
953  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
954  (HW_RD_REG32(
955  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
956  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) |
957  ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
958  }
959 
965  static inline void
966  RDC_disableExcitationSignalSyncIn(uint32_t base)
967  {
968  HW_WR_REG32(
969  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
970  (HW_RD_REG32(
971  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) |
972  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_MASK) &
973  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EN_SHIFT)));
974  }
975 
986  static inline uint32_t
987  RDC_getExcitationSignalEventStatus(uint32_t base)
988  {
989  return (
990  (HW_RD_REG32(
991  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
992  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) >>
993  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT);
994  }
995 
1001  static inline void
1002  RDC_clearExcitationSignalEventStatus(uint32_t base)
1003  {
1004  HW_WR_REG32(
1005  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1006  (HW_RD_REG32(
1007  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1008  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_MASK) |
1009  ((uint32_t)((1U) << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_SYNC_IN_EVENT_SHIFT)));
1010  }
1011 
1019  static inline uint32_t
1020  RDC_getExcitationSignalPhaseInfo(uint32_t base)
1021  {
1022  return (
1023  (HW_RD_REG32(
1024  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1025  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_MASK) >>
1026  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_PHASE_INFO_SHIFT);
1027  }
1028 
1035  static inline void
1036  RDC_setExcitationSignalSocDelay(uint32_t base, uint16_t socDelay)
1037  {
1038  HW_WR_REG32(
1039  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2,
1040  (HW_RD_REG32(
1041  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2) &
1042  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_MASK) |
1043  ((uint32_t)(socDelay << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG2_PWM_TO_SOC_DLY_START_SHIFT)));
1044  }
1045 
1046 
1047 
1054  static inline void
1055  RDC_setExcitationSignalAmplitudeControl(uint32_t base, uint8_t amplitude)
1056  {
1057  DebugP_assert(amplitude <= RDC_MAX_EXCITATION_AMPLITUDE);
1058  HW_WR_REG32(
1059  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3,
1060  (HW_RD_REG32(
1061  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1062  ~CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) |
1063  ((uint32_t)(amplitude << CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT)));
1064  }
1065 
1072  static inline uint32_t
1073  RDC_getExcitationSignalAmplitudeControl(uint32_t base)
1074  {
1075  return (
1076  (HW_RD_REG32(
1077  base + CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3) &
1078  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_MASK) >>
1079  CSL_RESOLVER_REGS_EXCIT_SAMPLE_CFG3_EXC_AMP_CTRL_SHIFT);
1080  }
1081 
1082  //*****************************************************************************
1083  // INTERRUPT CONFIGURATIONS
1084  //*****************************************************************************
1085 
1091  static inline void
1092  RDC_enableSequencerInterrupt(uint32_t base)
1093  {
1094  HW_WR_REG32(
1095  base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1096  (HW_RD_REG32(
1097  base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1098  ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1099  ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1100  }
1101 
1107  static inline void
1108  RDC_disableSequencerInterrupt(uint32_t base)
1109  {
1110  HW_WR_REG32(
1111  base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS,
1112  (HW_RD_REG32(
1113  base + CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS) &
1114  ~CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_MASK) |
1115  ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_SEQ_ERR_SHIFT)));
1116  }
1117 
1123  static inline void
1124  RDC_clearSequencerInterrupt(uint32_t base)
1125  {
1126  HW_WR_REG32(
1127  base + CSL_RESOLVER_REGS_IRQSTATUS_SYS,
1128  (HW_RD_REG32(
1129  base + CSL_RESOLVER_REGS_IRQSTATUS_SYS) &
1130  ~CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_MASK) |
1131  ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_SYS_SEQ_ERR_SHIFT)));
1132  }
1133 
1139  static inline void
1140  RDC_forceSequencerInterrupt(uint32_t base)
1141  {
1142  HW_WR_REG32(
1143  base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS,
1144  (HW_RD_REG32(
1145  base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1146  ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1147  ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1148  }
1149 
1155  static inline uint32_t
1156  RDC_getSequencerInterruptStatus(uint32_t base)
1157  {
1158  return (
1159  (HW_RD_REG32(
1160  base + CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS) &
1161  ~CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_MASK) |
1162  ((uint32_t)((1U) << CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_SEQ_ERR_SHIFT)));
1163  }
1164 
1165 
1173  static inline void
1174  RDC_enableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1175  {
1176  DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1177  DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1178 
1179  uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1180 
1181  HW_WR_REG32(
1182  base + regOffset,
1183  HW_RD_REG32(
1184  base + regOffset) |
1185  ((uint32_t)interruptSource));
1186  }
1187 
1195  static inline uint32_t
1196  RDC_getCoreEnabledInterruptSources(uint32_t base, uint8_t ResolverCore)
1197  {
1198  uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_SET_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1199  return (
1200  HW_RD_REG32(
1201  base + regOffset));
1202  }
1203 
1211  static inline void
1212  RDC_disableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1213  {
1214  DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1215  DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1216 
1217  uint32_t regOffset = CSL_RESOLVER_REGS_IRQENABLE_CLR_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1218 
1219  HW_WR_REG32(
1220  base + regOffset,
1221  HW_RD_REG32(
1222  base + regOffset) |
1223  ((uint32_t)interruptSource));
1224  }
1225 
1233  static inline void
1234  RDC_clearCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1235  {
1236  DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1237  DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1238 
1239  uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1240 
1241  HW_WR_REG32(
1242  base + regOffset,
1243  (HW_RD_REG32(
1244  base + regOffset) &
1245  ~((uint32_t)RDC_INTERRUPT_SOURCE_ALL)) |
1246  interruptSource);
1247  }
1248 
1256  static inline void
1257  RDC_forceCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
1258  {
1259  DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1260  DebugP_assert((interruptSource & (~((uint32_t)RDC_INTERRUPT_SOURCE_ALL))) == 0);
1261 
1262  uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_RAW_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1263 
1264  HW_WR_REG32(
1265  base + regOffset,
1266  (HW_RD_REG32(
1267  base + regOffset) &
1268  ~((uint32_t)RDC_INTERRUPT_SOURCE_ALL)) |
1269  interruptSource);
1270  }
1271 
1278  static inline uint32_t
1279  RDC_getCoreInterruptStatus(uint32_t base, uint32_t ResolverCore)
1280  {
1281  DebugP_assert((ResolverCore == RDC_RESOLVER_CORE0) || (ResolverCore == RDC_RESOLVER_CORE1));
1282 
1283  uint32_t regOffset = CSL_RESOLVER_REGS_IRQSTATUS_SYS_0 + (ResolverCore * RDC_CORE_OFFSET);
1284 
1285  return (
1286  (HW_RD_REG32(
1287  base + regOffset) &
1288  ((uint32_t)RDC_INTERRUPT_SOURCE_ALL)));
1289  }
1290 
1291  //*****************************************************************************
1292  // CALIBRATION CONFIGURATIONS
1293  //*****************************************************************************
1294 
1301  static inline bool
1302  RDC_getCalibrationStatus(uint32_t base)
1303  {
1304  return (
1305  (((HW_RD_REG32(
1306  base + CSL_RESOLVER_REGS_CAL_CFG) &
1307  CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) >>
1308  CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT) &
1309  (1U)) != 0U);
1310  }
1311 
1317  static inline void
1318  RDC_clearCalibrationStatus(uint32_t base)
1319  {
1320  HW_WR_REG32(
1321  base + CSL_RESOLVER_REGS_CAL_CFG,
1322  (HW_RD_REG32(
1323  base + CSL_RESOLVER_REGS_CAL_CFG) &
1324  ~CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_MASK) |
1325  ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_DONE_SHIFT)));
1326  }
1327 
1334  static inline void
1335  RDC_selectCalibrationChannel(uint32_t base, uint8_t calChannel)
1336  {
1337  HW_WR_REG32(
1338  base + CSL_RESOLVER_REGS_CAL_CFG,
1339  (HW_RD_REG32(
1340  base + CSL_RESOLVER_REGS_CAL_CFG) &
1341  ~CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_MASK) |
1342  ((uint32_t)(calChannel << CSL_RESOLVER_REGS_CAL_CFG_CAL_CHSEL_SHIFT)));
1343  }
1344 
1350  static inline void
1351  RDC_enableCalibration(uint32_t base)
1352  {
1353  HW_WR_REG32(
1354  base + CSL_RESOLVER_REGS_CAL_CFG,
1355  (HW_RD_REG32(
1356  base + CSL_RESOLVER_REGS_CAL_CFG) &
1357  ~CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_MASK) |
1358  ((uint32_t)((1U) << CSL_RESOLVER_REGS_CAL_CFG_CAL_EN_SHIFT)));
1359  }
1360 
1368  static inline uint32_t
1369  RDC_getCalibrationData(uint32_t base, uint8_t CalAdc)
1370  {
1371  uint32_t regData = HW_RD_REG32(
1372  base + CSL_RESOLVER_REGS_CAL_OBS) &
1373  (CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK |
1374  CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK);
1375  if (CalAdc == RDC_CAL_ADC0)
1376  {
1377  return ((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_MASK) >>
1378  CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC0_DATA_SHIFT);
1379  }
1380  return ((regData & CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_MASK) >>
1381  CSL_RESOLVER_REGS_CAL_OBS_CAL_ADC1_DATA_SHIFT);
1382  }
1383 
1384  //*****************************************************************************
1385  // DC OFFSET AND BAND PASS FILTER CONFIGURATIONS
1386  //*****************************************************************************
1387 
1397  static inline void
1398  RDC_setDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t coef1, uint8_t coef2)
1399  {
1400  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1401  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1402  uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_MASK |
1403  CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_MASK);
1404 
1405  uint32_t value = (coef1 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF1_SHIFT) |
1406  (coef2 << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFF_CAL_COEF2_SHIFT);
1407  value &= mask;
1408 
1409  HW_WR_REG32(
1410  base + regOffset,
1411  (HW_RD_REG32(
1412  base + regOffset) &
1413  (~mask)) |
1414  value);
1415  }
1416 
1427  static inline void
1428  RDC_enableBPF(uint32_t base, uint8_t core)
1429  {
1430  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1431  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1432 
1433  HW_WR_REG32(
1434  base + regOffset,
1435  (HW_RD_REG32(
1436  base + regOffset) &
1437  ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) |
1438  ((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1439  }
1440 
1447  static inline void
1448  RDC_disableBPF(uint32_t base, uint8_t core)
1449  {
1450  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1451  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1452 
1453  HW_WR_REG32(
1454  base + regOffset,
1455  (HW_RD_REG32(
1456  base + regOffset) |
1457  CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_MASK) &
1458  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_BANDPASSFILTER_ON_SHIFT)));
1459  }
1460 
1469  static inline void
1470  RDC_disableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
1471  {
1472  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1473  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1474 
1475  HW_WR_REG32(
1476  base + regOffset,
1477  (HW_RD_REG32(
1478  base + regOffset) &
1479  ~CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK) |
1480  ((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_SHIFT)));
1481  }
1482 
1491  static inline void
1492  RDC_enableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
1493  {
1494  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1495  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG1_0 + (core * RDC_CORE_OFFSET);
1496 
1497  HW_WR_REG32(
1498  base + regOffset,
1499  (HW_RD_REG32(
1500  base + regOffset) |
1501  CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_MASK) &
1502  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DC_OFF_CFG1_0_OFFSET_CORR_ON_SHIFT)));
1503  }
1504 
1515  static inline void
1516  RDC_setDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t sin, int16_t cos)
1517  {
1518  DebugP_assert((core == RDC_RESOLVER_CORE0) || (core == RDC_RESOLVER_CORE1));
1519  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF_CFG2_0 + (core * RDC_CORE_OFFSET);
1520  uint32_t mask = (CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_MASK |
1521  CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_MASK);
1522 
1523  uint32_t value = (((uint32_t)((uint16_t)sin)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_SIN_MAN_OFF_ADJ_SHIFT) |
1524  (((uint32_t)((uint16_t)cos)) << CSL_RESOLVER_REGS_DC_OFF_CFG2_0_COS_MAN_OFF_ADJ_SHIFT);
1525  value &= mask;
1526 
1527  HW_WR_REG32(
1528  base + regOffset,
1529  (HW_RD_REG32(
1530  base + regOffset) &
1531  (~mask)) |
1532  value);
1533  }
1534 
1546  static inline int16_t
1547  RDC_getDcOffsetEstimatedValues(uint32_t base, uint8_t core, uint8_t sinCosValue)
1548  {
1549  uint32_t regOffset = CSL_RESOLVER_REGS_DC_OFF0 + (core * RDC_CORE_OFFSET);
1550  uint32_t mask = CSL_RESOLVER_REGS_DC_OFF0_SIN_OFFSET_MASK | CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_MASK;
1551  DebugP_assert((sinCosValue == RDC_DC_OFFSET_SIN_ESTIMATION) || (sinCosValue == RDC_DC_OFFSET_COS_ESTIMATION));
1552  return ((int16_t)(HW_RD_REG32(
1553  base + regOffset) &
1554  mask) >>
1555  (sinCosValue * CSL_RESOLVER_REGS_DC_OFF0_COS_OFFSET_SHIFT));
1556  }
1557 
1558  //*****************************************************************************
1559  // Ideal Sample Time Configurations
1560  //*****************************************************************************
1561 
1570  static inline void
1571  RDC_overrideIdealSampleTime(uint32_t base, uint8_t core, uint8_t overrideValue)
1572  {
1573  uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core * RDC_CORE_OFFSET);
1574  HW_WR_REG32(
1575  base + regOffset,
1576  (HW_RD_REG32(
1577  base + regOffset) &
1578  ~CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_MASK) |
1579  ((uint32_t)(overrideValue << CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_OVR_SHIFT)));
1580  }
1581 
1590  static inline uint8_t
1591  RDC_getIdealSampleTime(uint32_t base, uint8_t core)
1592  {
1593  uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG1_0 + (core * RDC_CORE_OFFSET);
1594  return (
1595  (HW_RD_REG32(
1596  base + regOffset) &
1597  CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_MASK) >>
1598  CSL_RESOLVER_REGS_SAMPLE_CFG1_0_IDEAL_SAMPLE_TIME_SHIFT);
1599  }
1600 
1612  static inline void
1613  RDC_setIdealSampleDetectionThreshold(uint32_t base, uint8_t core, uint16_t absThresholdValue)
1614  {
1615  uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1616  HW_WR_REG32(
1617  base + regOffset,
1618  (HW_RD_REG32(
1619  base + regOffset) &
1620  ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_MASK) |
1621  ((uint32_t)(absThresholdValue << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_SAMPLE_DET_THRESHOLD_SHIFT)));
1622  }
1623 
1633  static inline void
1634  RDC_setIdealSampleBpfAdjust(uint32_t base, uint8_t core, uint8_t sampleAdjustCount)
1635  {
1636  uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1637  DebugP_assert(sampleAdjustCount <= RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST);
1638  HW_WR_REG32(
1639  base + regOffset,
1640  (HW_RD_REG32(
1641  base + regOffset) &
1642  ~CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_MASK) |
1643  ((uint32_t)(sampleAdjustCount << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_BANDPASSFILTERSAMPLEADJUST_SHIFT)));
1644  }
1645 
1655  static inline bool
1656  RDC_getIdealSamplePeakAvgLimitStatus(uint32_t base, uint8_t core)
1657  {
1658  uint32_t regOffset = CSL_RESOLVER_REGS_SAMPLE_CFG2_0 + (core * RDC_CORE_OFFSET);
1659  return (
1660  ((HW_RD_REG32(
1661  base + regOffset) &
1662  CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_MASK) &
1663  ((uint32_t)((1U) << CSL_RESOLVER_REGS_SAMPLE_CFG2_0_PEAK_AVG_LIMIT_DONE_SHIFT))) != 0U);
1664  }
1665 
1678  static inline void
1679  RDC_setIdealSampleMode(uint32_t base, uint8_t core, uint8_t mode)
1680  {
1681  uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1682  DebugP_assert(
1683  (mode & ~(CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MAX)) == 0U);
1684  HW_WR_REG32(
1685  base + regOffset,
1686  (HW_RD_REG32(
1687  base + regOffset) &
1688  ~CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_MASK) |
1689  ((uint32_t)(mode << CSL_RESOLVER_REGS_DEC_GF_CFG0_IDEAL_SAMPLE_MODE_SHIFT)));
1690  }
1691 
1701  static inline void
1702  RDC_enableIdealSampleBottomSampling(uint32_t base, uint8_t core)
1703  {
1704  uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1705  HW_WR_REG32(
1706  base + regOffset,
1707  (HW_RD_REG32(
1708  base + regOffset) &
1709  ~CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) |
1710  ((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
1711  }
1712 
1720  static inline void
1721  RDC_disableIdealSampleBottomSampling(uint32_t base, uint8_t core)
1722  {
1723  uint32_t regOffset = CSL_RESOLVER_REGS_DEC_GF_CFG0 + (core * RDC_CORE_OFFSET);
1724  HW_WR_REG32(
1725  base + regOffset,
1726  (HW_RD_REG32(
1727  base + regOffset) |
1728  CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_MASK) &
1729  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_DEC_GF_CFG0_ENABLE_BOTTOM_SHIFT)));
1730  }
1731 
1732  //*****************************************************************************
1733  // PHASE GAIN ESTIMATION AND CORRECTION CONFIGURAITONS
1734  //*****************************************************************************
1735 
1745  static inline bool
1746  RDC_getPhaseGainEstimationStatus(uint32_t base, uint8_t core)
1747  {
1748  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
1749  return (
1750  ((HW_RD_REG32(
1751  base + regOffset) &
1752  CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_MASK) &
1753  ((uint32_t)((1U) << CSL_RESOLVER_REGS_PG_EST_CFG1_0_AUTOPHASEGAINREADYDONE_SHIFT))) != 0U);
1754  }
1755 
1765  static inline void
1766  RDC_setPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core, uint8_t pgEstimationLimit)
1767  {
1768  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG1_0 + (core * RDC_CORE_OFFSET);
1769  DebugP_assert(pgEstimationLimit <= CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MAX);
1770  HW_WR_REG32(
1771  base + regOffset,
1772  (HW_RD_REG32(
1773  base + regOffset) &
1774  ~CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_MASK) |
1775  ((uint32_t)(pgEstimationLimit << CSL_RESOLVER_REGS_PG_EST_CFG1_0_PG_TRAIN_LIMIT_SHIFT)));
1776  }
1777 
1787  static inline void
1788  RDC_setCosPhaseBypass(uint32_t base, uint8_t core, int16_t cosPhaseBypass)
1789  {
1790  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1791  DebugP_assert((cosPhaseBypass & (~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MAX)) == 0U);
1792  HW_WR_REG32(
1793  base + regOffset,
1794  (HW_RD_REG32(
1795  base + regOffset) &
1796  ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_MASK) |
1797  ((uint32_t)(cosPhaseBypass << CSL_RESOLVER_REGS_PG_EST_CFG2_0_PHASECOSBYP0_SHIFT)));
1798  }
1799 
1807  static inline void
1808  RDC_enablePhaseGainEstimation(uint32_t base, uint8_t core)
1809  {
1810  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1811  HW_WR_REG32(
1812  base + regOffset,
1813  (HW_RD_REG32(
1814  base + regOffset) |
1815  CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) &
1816  ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
1817 
1818  }
1819 
1827  static inline void
1828  RDC_disablePhaseGainEstimation(uint32_t base, uint8_t core)
1829  {
1830  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1831  HW_WR_REG32(
1832  base + regOffset,
1833  (HW_RD_REG32(
1834  base + regOffset) &
1835  ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_MASK) |
1836  ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_BYPASSPHASEGAINCORR0_SHIFT));
1837  }
1838 
1846  static inline void
1847  RDC_enablePhaseAutoCorrection(uint32_t base, uint8_t core)
1848  {
1849  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1850  HW_WR_REG32(
1851  base + regOffset,
1852  (HW_RD_REG32(
1853  base + regOffset) &
1854  ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) |
1855  ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
1856  }
1857 
1865  static inline void
1866  RDC_disablePhaseAutoCorrection(uint32_t base, uint8_t core)
1867  {
1868  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1869  HW_WR_REG32(
1870  base + regOffset,
1871  (HW_RD_REG32(
1872  base + regOffset) |
1873  CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_MASK) &
1874  ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOPHASECONTROL0_SHIFT));
1875  }
1876 
1884  static inline void
1885  RDC_enableGainAutoCorrection(uint32_t base, uint8_t core)
1886  {
1887  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1888  HW_WR_REG32(
1889  base + regOffset,
1890  (HW_RD_REG32(
1891  base + regOffset) &
1892  ~CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) |
1893  ((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
1894  }
1895 
1903  static inline void
1904  RDC_disableGainAutoCorrection(uint32_t base, uint8_t core)
1905  {
1906  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG2_0 + (core * RDC_CORE_OFFSET);
1907  HW_WR_REG32(
1908  base + regOffset,
1909  (HW_RD_REG32(
1910  base + regOffset) |
1911  CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_MASK) &
1912  ~((1U) << CSL_RESOLVER_REGS_PG_EST_CFG2_0_AUTOGAINCONTROL0_SHIFT));
1913  }
1914 
1924  static inline void
1925  RDC_setGainBypassValue(uint32_t base, uint8_t core, uint16_t sinGainBypass, uint16_t cosGainBypass)
1926  {
1927  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG3_0 + (core * RDC_CORE_OFFSET);
1928  DebugP_assert(sinGainBypass >= 16384U);
1929  uint32_t value = ((uint32_t)(((uint32_t)cosGainBypass) << 16)) | ((uint32_t)((uint16_t)sinGainBypass));
1930 
1931  HW_WR_REG32(
1932  base + regOffset, value);
1933  }
1934 
1944  static inline int16_t
1945  RDC_getPhaseEstimation(uint32_t base, uint8_t core)
1946  {
1947  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG4_0 + (core * RDC_CORE_OFFSET);
1948  return ((int16_t)
1949  (HW_RD_REG32(
1950  base + regOffset) &
1951  CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_MASK) >>
1952  CSL_RESOLVER_REGS_PG_EST_CFG4_0_PHASEESTIMATEFINAL_SHIFT);
1953  }
1954 
1964  static inline void
1965  RDC_getGainEstimation(uint32_t base, uint8_t core, int16_t *sinGainEstimate, int16_t *cosGainEstimate)
1966  {
1967  uint32_t regOffset = CSL_RESOLVER_REGS_PG_EST_CFG5_0 + (core * RDC_CORE_OFFSET);
1968  uint32_t value = HW_RD_REG32(base + regOffset);
1969 
1970  *cosGainEstimate = (int16_t)(value >> 16);
1971  *sinGainEstimate = (int16_t)value;
1972  }
1973 
1974  //*****************************************************************************
1975  // TRACK2 CONFIGURATIONS
1976  //*****************************************************************************
1977 
1978 
1989  static inline void
1990  RDC_setTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
1991  {
1992  uint8_t kvelfilt = track2Constants->kvelfilt;
1993  uint32_t cfg1 = (kvelfilt << CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_SHIFT);
1994 
1995  uint32_t mask_cfg1 = (CSL_RESOLVER_REGS_TRACK2_CFG1_0_KVELFILT_MASK);
1996 
1997  uint32_t regOffset_cfg1 = CSL_RESOLVER_REGS_TRACK2_CFG1_0 + (core * RDC_CORE_OFFSET);
1998  HW_WR_REG32(
1999  base + regOffset_cfg1,
2000  (HW_RD_REG32(
2001  base + regOffset_cfg1) &
2002  (~mask_cfg1)) |
2003  cfg1);
2004  }
2005 
2013  static inline void
2014  RDC_enableTrack2Boost(uint32_t base, uint8_t core)
2015  {
2016  uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core * RDC_CORE_OFFSET);
2017 
2018  HW_WR_REG32(
2019  base + regOffset,
2020  (HW_RD_REG32(
2021  base + regOffset) &
2022  ~CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) |
2023  ((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2024  }
2032  static inline void
2033  RDC_disableTrack2Boost(uint32_t base, uint8_t core)
2034  {
2035  uint32_t regOffset = CSL_RESOLVER_REGS_TRACK2_CFG2_0 + (core * RDC_CORE_OFFSET);
2036 
2037  HW_WR_REG32(
2038  base + regOffset,
2039  (HW_RD_REG32(
2040  base + regOffset) |
2041  CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_MASK) &
2042  ~((uint32_t)((1U) << CSL_RESOLVER_REGS_TRACK2_CFG2_0_BOOST_SHIFT)));
2043  }
2044 
2055  static inline int16_t
2056  RDC_getArcTanAngle(uint32_t base, uint8_t core)
2057  {
2058  uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_ARCTAN_0 + (core * RDC_CORE_OFFSET);
2059  return (
2060  (int16_t)HW_RD_REG16(
2061  base + regOffset));
2062  }
2063 
2073  static inline int16_t
2074  RDC_getTrack2Angle(uint32_t base, uint8_t core)
2075  {
2076  uint32_t regOffset = CSL_RESOLVER_REGS_ANGLE_TRACK2_0 + (core * RDC_CORE_OFFSET);
2077  return (
2078  (int16_t)HW_RD_REG16(
2079  base + regOffset));
2080  }
2081 
2092  static inline int32_t
2093  RDC_getTrack2Velocity(uint32_t base, uint8_t core)
2094  {
2095  uint32_t regOffset = CSL_RESOLVER_REGS_VELOCITY_TRACK2_0 + (core * RDC_CORE_OFFSET);
2096  return (
2097  (int32_t)HW_RD_REG32(
2098  base + regOffset));
2099  }
2100 
2101  //*****************************************************************************
2102  // DIAGNOSTIC RELATED APIS
2103  //*****************************************************************************
2104 
2119  static inline void
2120  RDC_getDiagnosticsSinCosOffsetDriftData(uint32_t base,
2121  uint8_t resolverCore,
2122  Diag_Mon_SinCos_Offset_drift_data *monitorData)
2123  {
2124  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (RDC_CORE_OFFSET * resolverCore);
2125  uint32_t value = HW_RD_REG32(base + regOffset);
2126  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2127  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2128 
2129  monitorData->offset_drift_threshold_hi = (int16_t)((uint16_t)((value &
2130  CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_MASK) >>
2131  CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT));
2132  monitorData->offset_drift_threshold_lo = (int16_t)((uint16_t)((value &
2133  CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_MASK) >>
2134  CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT));
2135 
2136  monitorData->offset_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR) != 0);
2137  monitorData->offset_drift_sin_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR) != 0);
2138  monitorData->offset_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR) != 0);
2139  monitorData->offset_drift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR) != 0);
2140  monitorData->offset_drift_en = ((enabledInterruptSources &
2141  (RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR |
2142  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR |
2143  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR |
2144  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR)) != 0);
2145  }
2146 
2161  static inline void
2162  RDC_setDiagnosticsSinCosOffsetDriftData(uint32_t base,
2163  uint8_t resolverCore,
2164  Diag_Mon_SinCos_Offset_drift_data *monitorData)
2165  {
2166  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG1_0 + (RDC_CORE_OFFSET * resolverCore);
2167  uint32_t value = (((uint32_t)((uint16_t)(monitorData->offset_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_HI_SHIFT) |
2168  (((uint32_t)((uint16_t)(monitorData->offset_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG1_0_OFFSETDRIFT_THRESHOLD_LO_SHIFT);
2169  uint32_t interruptSource = 0;
2170  /* if interrupt needs to be enabled */
2171  RDC_disableCoreInterrupt(base, resolverCore,
2172  (RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR |
2173  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR |
2174  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR |
2175  RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR));
2176 
2177  /* writing the "value" */
2178  HW_WR_REG32(
2179  base + regOffset, value);
2180 
2181  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2182 
2183  if (monitorData->offset_drift_en)
2184  {
2185  if (monitorData->offset_drift_cos_hi)
2186  {
2187  interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR;
2188  }
2189 
2190  if (monitorData->offset_drift_sin_hi)
2191  {
2192  interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR;
2193  }
2194 
2195  if (monitorData->offset_drift_cos_lo)
2196  {
2197  interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR;
2198  }
2199 
2200  if (monitorData->offset_drift_sin_lo)
2201  {
2202  interruptSource |= RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR;
2203  }
2204 
2205  RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2206  }
2207  }
2208 
2224  static inline void
2225  RDC_getDiagnosticsSinCosGainDriftData(uint32_t base,
2226  uint8_t resolverCore,
2227  Diag_Mon_SinCos_Gain_drift_data *monitorData)
2228  {
2229  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (RDC_CORE_OFFSET * resolverCore);
2230 
2231  uint32_t value = HW_RD_REG32(base + regOffset);
2232 
2233  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2234  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2235 
2236  monitorData->gain_drift_threshold_hi = (int16_t)((uint16_t)((value &
2237  CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_MASK) >>
2238  CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT));
2239  monitorData->gain_drift_threshold_lo = (int16_t)((uint16_t)((value &
2240  CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_MASK) >>
2241  CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT));
2242 
2243  monitorData->gain_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR) != 0);
2244  monitorData->gain_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR) != 0);
2245  monitorData->gain_drift_sin_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR) != 0);
2246  monitorData->gain_drift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR) != 0);
2247 
2248  /* getting the glitch count value*/
2249  regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (RDC_CORE_OFFSET * resolverCore);
2250  monitorData->gain_drift_glitch_count = (uint8_t)HW_RD_REG32(base + regOffset);
2251 
2252  monitorData->gaindrift_en = ((enabledInterruptSources &
2253  (RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR |
2254  RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR |
2255  RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR |
2256  RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR)) != 0);
2257  }
2258 
2274  static inline void
2275  RDC_setDiagnosticsSinCosGainDriftData(uint32_t base,
2276  uint8_t resolverCore,
2277  Diag_Mon_SinCos_Gain_drift_data *monitorData)
2278  {
2279  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG14_0 + (RDC_CORE_OFFSET * resolverCore);
2280  uint32_t value = (((uint32_t)((uint16_t)(monitorData->gain_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_HI_SHIFT) |
2281  (((uint32_t)((uint16_t)(monitorData->gain_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG14_0_GAINDRIFT_THRESHOLD_LO_SHIFT);
2282 
2283  uint32_t interruptSource = 0;
2284 
2285  /* if interrupt needs to be enabled */
2286  RDC_disableCoreInterrupt(base, resolverCore,
2287  (RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR |
2288  RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR |
2289  RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR |
2290  RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR));
2291 
2292  /* setting the glitch count value */
2293  regOffset = CSL_RESOLVER_REGS_DIAG15_0 + (RDC_CORE_OFFSET * resolverCore);
2294  HW_WR_REG32(
2295  base + regOffset, monitorData->gain_drift_glitch_count);
2296 
2297  /* writing the "value" */
2298  HW_WR_REG32(
2299  base + regOffset, value);
2300 
2301  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2302 
2303  if (monitorData->gaindrift_en)
2304  {
2305  if (monitorData->gain_drift_cos_hi)
2306  {
2307  interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR;
2308  }
2309 
2310  if (monitorData->gain_drift_sin_hi)
2311  {
2312  interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR;
2313  }
2314 
2315  if (monitorData->gain_drift_cos_lo)
2316  {
2317  interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR;
2318  }
2319 
2320  if (monitorData->gain_drift_sin_lo)
2321  {
2322  interruptSource |= RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR;
2323  }
2324 
2325  RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2326  }
2327  }
2328 
2329 
2343  static inline void
2344  RDC_getDiagnosticsCosPhaseDriftData(uint32_t base,
2345  uint8_t resolverCore,
2346  Diag_Mon_Cos_Phase_drift_data *monitorData)
2347  {
2348  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (RDC_CORE_OFFSET * resolverCore);
2349 
2350  uint32_t value = HW_RD_REG32(base + regOffset);
2351 
2352  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2353  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2354 
2355  monitorData->phase_drift_threshold_hi = (int16_t)((uint16_t)((value &
2356  CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_MASK) >>
2357  CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT));
2358  monitorData->phase_drift_threshold_lo = (int16_t)((uint16_t)((value &
2359  CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_MASK) >>
2360  CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT));
2361 
2362  monitorData->phase_drift_cos_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR) != 0);
2363  monitorData->phase_drift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR) != 0);
2364 
2365  /* getting the glitch count value*/
2366  regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (RDC_CORE_OFFSET * resolverCore);
2367  monitorData->phase_drift_glitch_count = (uint8_t)HW_RD_REG32(base + regOffset);
2368 
2369  monitorData->phase_drift_en = ((enabledInterruptSources &
2370  (RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR |
2371  RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR)) != 0);
2372  }
2373 
2387  static inline void
2388  RDC_setDiagnosticsCosPhaseDriftData(uint32_t base,
2389  uint8_t resolverCore,
2390  Diag_Mon_Cos_Phase_drift_data *monitorData)
2391  {
2392  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG16_0 + (RDC_CORE_OFFSET * resolverCore);
2393  uint32_t value = (((uint32_t)((uint16_t)(monitorData->phase_drift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_HI_SHIFT) |
2394  (((uint32_t)((uint16_t)(monitorData->phase_drift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG16_0_PHASEDRIFT_THRESHOLD_LO_SHIFT);
2395 
2396  uint32_t interruptSource = 0;
2397  /* if interrupt needs to be enabled */
2398  RDC_disableCoreInterrupt(base, resolverCore,
2399  (RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR |
2400  RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR));
2401  /* writing the glitch count value */
2402  regOffset = CSL_RESOLVER_REGS_DIAG17_0 + (RDC_CORE_OFFSET * resolverCore);
2403  HW_WR_REG32(
2404  base + regOffset, monitorData->phase_drift_glitch_count);
2405 
2406  /* writing the "value" */
2407  HW_WR_REG32(
2408  base + regOffset, value);
2409 
2410  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2411 
2412  if (monitorData->phase_drift_en)
2413  {
2414  if (monitorData->phase_drift_cos_hi)
2415  {
2416  interruptSource |= RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR;
2417  }
2418 
2419  if (monitorData->phase_drift_cos_lo)
2420  {
2421  interruptSource |= RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR;
2422  }
2423 
2424  RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2425  }
2426  }
2427 
2428 
2429 
2447  static inline void
2448  RDC_getDiagnosticsExcFreqDegradationData(uint32_t base,
2449  uint8_t resolverCore,
2450  Diag_Mon_ExcFreq_Degradataion_data *monitorData)
2451  {
2452  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG2_0 + (RDC_CORE_OFFSET * resolverCore);
2453 
2454  uint32_t value = HW_RD_REG32(base + regOffset);
2455 
2456  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2457  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2458 
2459  monitorData->excfreqdetected_sin = ((uint16_t)((value &
2460  CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_MASK) >>
2461  CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_SIN_SHIFT));
2462  monitorData->excfreqdetected_cos = ((uint16_t)((value &
2463  CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_MASK) >>
2464  CSL_RESOLVER_REGS_DIAG2_0_EXCFREQDETECTED_COS_SHIFT));
2465 
2466  regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (RDC_CORE_OFFSET * resolverCore);
2467  value = HW_RD_REG32(base + regOffset);
2468 
2469  monitorData->excfreqdrift_threshold_hi = ((uint16_t)((value &
2470  CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_MASK) >>
2471  CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT));
2472  monitorData->excfreqdrift_threshold_lo = ((uint16_t)((value &
2473  CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_MASK) >>
2474  CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT));
2475 
2476  regOffset = CSL_RESOLVER_REGS_DIAG4_0 + (RDC_CORE_OFFSET * resolverCore);
2477  value = HW_RD_REG32(base + regOffset);
2478 
2479  monitorData->excfreq_level = ((uint16_t)((value &
2480  CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_MASK) >>
2481  CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT));
2482  monitorData->excfreqdrift_glitchcount = ((uint8_t)((value &
2483  CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_MASK) >>
2484  CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT));
2485 
2486  monitorData->excfreqdrift_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR) != 0);
2487  monitorData->excfreqdrift_cos_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR) != 0);
2488  monitorData->excfreqdrift_sin_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR) != 0);
2489 
2490  monitorData->excfreqdrift_en = ((enabledInterruptSources &
2491  (RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR |
2492  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR |
2493  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR)) != 0);
2494  }
2495 
2513  static inline void
2514  RDC_setDiagnosticsExcFreqDegradationData(uint32_t base,
2515  uint8_t resolverCore,
2516  Diag_Mon_ExcFreq_Degradataion_data *monitorData)
2517  {
2518  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG2_0 + (RDC_CORE_OFFSET * resolverCore);
2519  uint32_t value = (((uint32_t)((uint16_t)(monitorData->excfreqdrift_threshold_hi))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_HI_SHIFT) |
2520  (((uint32_t)((uint16_t)(monitorData->excfreqdrift_threshold_lo))) << CSL_RESOLVER_REGS_DIAG3_0_EXCFREQDRIFT_THRESHOLD_LO_SHIFT);
2521  uint32_t interruptSource = 0;
2522 
2523  RDC_disableCoreInterrupt(base, resolverCore,
2524  (RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR |
2525  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR |
2526  RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR));
2527 
2528  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2529 
2530  HW_WR_REG32(
2531  base + regOffset, value);
2532 
2533  regOffset = CSL_RESOLVER_REGS_DIAG3_0 + (RDC_CORE_OFFSET * resolverCore);
2534  value = (((uint32_t)((uint16_t)(monitorData->excfreq_level))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQ_LEVEL_SHIFT) |
2535  (((uint32_t)((uint16_t)(monitorData->excfreqdrift_glitchcount))) << CSL_RESOLVER_REGS_DIAG4_0_EXCFREQDRIFT_GLITCHCOUNT_SHIFT);
2536 
2537  HW_WR_REG32(
2538  base + regOffset, value);
2539 
2540  if (monitorData->excfreqdrift_en)
2541  {
2542  if (monitorData->excfreqdrift_hi)
2543  {
2544  interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR;
2545  }
2546 
2547  if (monitorData->excfreqdrift_cos_lo)
2548  {
2549  interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR;
2550  }
2551 
2552  if (monitorData->excfreqdrift_sin_lo)
2553  {
2554  interruptSource |= RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR;
2555  }
2556  RDC_enableCoreInterrupt(base, resolverCore, (interruptSource | enabledInterruptSources));
2557  }
2558  }
2559 
2577  static inline void
2578  RDC_getDiagnosticsRotationalSignalIntegrityData(uint32_t base,
2579  uint8_t resolverCore,
2580  Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
2581  {
2582  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG13_0 + (RDC_CORE_OFFSET * resolverCore);
2583  uint32_t value = HW_RD_REG32(
2584  base + regOffset);
2585 
2586  monitorData->sin_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_SIN_MULTI_ZC_ERROR_COUNT_SHIFT);
2587 
2588  monitorData->cos_multi_zc_error_count = (uint8_t)((value & CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_MASK) >> CSL_RESOLVER_REGS_DIAG13_0_COS_MULTI_ZC_ERROR_COUNT_SHIFT);
2589 
2590  regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (RDC_CORE_OFFSET * resolverCore);
2591  value = HW_RD_REG32(
2592  base + regOffset);
2593  monitorData->rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT;
2594  monitorData->rotpeak_level = (value & CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_MASK) >> CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT;
2595 
2596  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2597  monitorData->cos_neg_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR) != 0);
2598  monitorData->cos_pos_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR) != 0);
2599  monitorData->sin_neg_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR) != 0);
2600  monitorData->sin_pos_zc_peak_mismatch_err = ((interruptStatus & RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR) != 0);
2601 
2602 
2603  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2604  monitorData->zero_cross_rot_en = (enabledInterruptSources & (RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR |
2605  RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR |
2606  RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR |
2607  RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR)) != 0;
2608  }
2609 
2627  static inline void
2628  RDC_setDiagnosticsRotationalSignalIntegrityData(uint32_t base,
2629  uint8_t resolverCore,
2630  Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
2631  {
2632  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG12_0 + (RDC_CORE_OFFSET * resolverCore);
2633  uint32_t value = (((uint32_t)((uint16_t)(monitorData->rotpeak_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTPEAK_LEVEL_SHIFT) |
2634  (((uint32_t)((uint16_t)(monitorData->rotfreq_level))) << CSL_RESOLVER_REGS_DIAG12_0_ROTFREQ_LEVEL_SHIFT);
2635  HW_WR_REG32(
2636  base + regOffset,
2637  value);
2638  RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR | RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR));
2639  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2640  uint32_t interruptSources = 0;
2641 
2642  if (monitorData->zero_cross_rot_en)
2643  {
2644  if (monitorData->cos_neg_zc_peak_mismatch_err)
2645  {
2646  interruptSources |= RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR;
2647  }
2648 
2649  if (monitorData->cos_pos_zc_peak_mismatch_err)
2650  {
2651  interruptSources |= RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR;
2652  }
2653 
2654  if (monitorData->sin_neg_zc_peak_mismatch_err)
2655  {
2656  interruptSources |= RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR;
2657  }
2658 
2659  if (monitorData->sin_pos_zc_peak_mismatch_err)
2660  {
2661  interruptSources |= RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR;
2662  }
2663 
2664  RDC_enableCoreInterrupt(base, resolverCore, (interruptSources | enabledInterruptSources));
2665  }
2666  }
2667 
2681  static inline void
2682  RDC_getDiagnosticsSignalIntegritySquareSumData(
2683  uint32_t base,
2684  uint32_t resolverCore,
2685  Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
2686  {
2687  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore * RDC_CORE_OFFSET);
2688  uint32_t value = HW_RD_REG32(
2689  base + regOffset);
2690 
2691  monitorData->sinsqcossq_threshold_hi = (value & CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_MASK) >>
2692  CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT;
2693  monitorData->sinsqcossq_threshold_lo = (value & CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_MASK) >>
2694  CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT;
2695 
2696  regOffset = CSL_RESOLVER_REGS_DIAG10_0 + (resolverCore * RDC_CORE_OFFSET);
2697  value = HW_RD_REG32(
2698  base + regOffset);
2699 
2700  monitorData->sinsqcossq_cossq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_MASK) >>
2701  CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_COSSQ_SHIFT;
2702  monitorData->sinsqcossq_sinsq = (value & CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_MASK) >>
2703  CSL_RESOLVER_REGS_DIAG10_0_SINSQCOSSQ_SINSQ_SHIFT;
2704 
2705  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2706 
2707  regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore * RDC_CORE_OFFSET);
2708  monitorData->sinsqcossq_glitchcount = (uint8_t)((HW_RD_REG32(
2709  base + regOffset) &
2710  CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_MASK) >>
2711  CSL_RESOLVER_REGS_DIAG11_0_SINSQCOSSQ_GLITCHCOUNT_SHIFT);
2712 
2713  monitorData->sinsqcossq_hi = ((interruptStatus & RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR) != 0);
2714  monitorData->sinsqcossq_lo = ((interruptStatus & RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR) != 0);
2715  }
2716 
2730  static inline void
2731  RDC_setDiagnosticsSignalIntegritySquareSumData(
2732  uint32_t base,
2733  uint32_t resolverCore,
2734  Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
2735  {
2736  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG9_0 + (resolverCore * RDC_CORE_OFFSET);
2737  uint32_t value = (((uint32_t)((uint16_t)(monitorData->sinsqcossq_threshold_hi))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_HI_SHIFT) |
2738  (((uint32_t)((uint16_t)(monitorData->sinsqcossq_threshold_lo))) << CSL_RESOLVER_REGS_DIAG9_0_SINSQCOSSQ_THRESHOLD_LO_SHIFT);
2739  HW_WR_REG32(
2740  base + regOffset, value);
2741 
2742  regOffset = CSL_RESOLVER_REGS_DIAG11_0 + (resolverCore * RDC_CORE_OFFSET);
2743  HW_WR_REG32(
2744  base + regOffset, (uint32_t)(monitorData->sinsqcossq_glitchcount));
2745 
2746  RDC_disableCoreInterrupt(base, resolverCore,
2747  (RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR | RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR));
2748  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2749  uint32_t interruptSources = 0;
2750 
2751  if (monitorData->sinsqcossq_hi)
2752  {
2753  interruptSources |= RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR;
2754  }
2755  if (monitorData->sinsqcossq_lo)
2756  {
2757  interruptSources |= RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR;
2758  }
2759  RDC_enableCoreInterrupt(base, resolverCore, (enabledInterruptSources | interruptSources));
2760  }
2761 
2762 
2763 
2776  static inline void
2777  RDC_getDiagnosticsHighAmplitudeData(
2778  uint32_t base,
2779  uint8_t resolverCore,
2780  Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
2781  {
2782  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore * RDC_CORE_OFFSET);
2783  uint32_t value = HW_RD_REG32(
2784  base + regOffset);
2785  uint32_t interruptStatus = RDC_getCoreInterruptStatus(base, resolverCore);
2786 
2787  monitorData->highAmplitude_glitchcount = (value & CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_GLITCHCOUNT_MASK) >>
2788  CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT;
2789 
2790  monitorData->highAmplitude_threshold = (value & CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_THRESHOLD_MASK) >>
2791  CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_THRESHOLD_SHIFT;
2792  regOffset = CSL_RESOLVER_REGS_DIAG8_0 + (resolverCore * RDC_CORE_OFFSET);
2793  value = HW_RD_REG32(
2794  base + regOffset);
2795 
2796  monitorData->highAmplitude_sin_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_SIN_MASK) >> \
2797  CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_SIN_SHIFT);
2798 
2799  monitorData->highAmplitude_cos_value = (int16_t) ((value & CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_COS_MASK) >> \
2800  CSL_RESOLVER_REGS_DIAG8_1_HIGHAMPLITUDE_COS_SHIFT);
2801  monitorData->highAmplitude_cos_error = ((interruptStatus & RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR) != 0);
2802  monitorData->highAmplitude_sin_error = ((interruptStatus & RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR) != 0);
2803  }
2804 
2817  static inline void
2818  RDC_setDiagnosticsHighAmplitudeData(
2819  uint32_t base,
2820  uint8_t resolverCore,
2821  Diag_Mon_Sin_Cos_High_Amplitude* monitorData)
2822  {
2823  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG7_0 + (resolverCore * RDC_CORE_OFFSET);
2824  uint32_t value = (((uint32_t)((uint16_t)(monitorData->highAmplitude_glitchcount))) << CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_GLITCHCOUNT_SHIFT) |
2825  (((uint32_t)((uint16_t)(monitorData->highAmplitude_threshold))) << CSL_RESOLVER_REGS_DIAG7_1_HIGHAMPLITUDE_THRESHOLD_SHIFT);
2826  uint32_t enabledInterruptSources = 0;
2827  uint32_t interruptSources = 0;
2828  HW_WR_REG32(
2829  base + regOffset,
2830  value);
2831  RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR | RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR));
2832  enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2833 
2834  if(monitorData->highAmplitude_cos_error)
2835  {
2836  interruptSources |= RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR;
2837  }
2838  if(monitorData->highAmplitude_sin_error)
2839  {
2840  interruptSources |= RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR;
2841  }
2842  RDC_enableCoreInterrupt(base, resolverCore, (interruptSources | enabledInterruptSources));
2843  }
2844 
2856  static inline void
2857  RDC_getDiagnosticsWeakAmplitudeData(
2858  uint32_t base,
2859  uint8_t resolverCore,
2860  Diag_Mon_Sin_Cos_Weak_Amplitude * monitorData
2861  )
2862  {
2863  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore * RDC_CORE_OFFSET);
2864  uint32_t interruptSources = RDC_getCoreInterruptStatus(base, resolverCore);
2865  uint32_t value = HW_RD_REG32(
2866  base + regOffset);
2867  monitorData->lowAmplitude_threshold = (value & CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_THRESHOLD_MASK) >>
2868  CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_THRESHOLD_SHIFT;
2869  monitorData->lowAmplitude_glitchcount = (value & CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_MASK) >>
2870  CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT;
2871 
2872  monitorData->lowAmplitude_error = ((interruptSources & RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR) != 0U);
2873 
2874  regOffset = CSL_RESOLVER_REGS_DIAG6_0 + (resolverCore * RDC_CORE_OFFSET);
2875  value = HW_RD_REG32(
2876  base + regOffset);
2877  monitorData->lowAmplitude_cos_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_COS_MASK) >>\
2878  CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_COS_SHIFT);
2879 
2880  monitorData->lowAmplitude_sin_value = (int16_t)((value & CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_SIN_MASK) >>\
2881  CSL_RESOLVER_REGS_DIAG6_1_LOWAMPLITUDE_SIN_SHIFT);
2882  }
2883 
2895  static inline void
2896  RDC_setDiagnosticsWeakAmplitudeData(
2897  uint32_t base,
2898  uint8_t resolverCore,
2899  Diag_Mon_Sin_Cos_Weak_Amplitude * monitorData
2900  )
2901  {
2902  uint32_t regOffset = CSL_RESOLVER_REGS_DIAG5_0 + (resolverCore * RDC_CORE_OFFSET);
2903  uint32_t value = ((uint32_t)(monitorData->lowAmplitude_glitchcount << CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT)) |
2904  ((uint32_t) (monitorData->lowAmplitude_threshold << CSL_RESOLVER_REGS_DIAG5_1_LOWAMPLITUDE_GLITCHCOUNT_SHIFT));
2905  uint32_t enabledInterruptSources = RDC_getCoreEnabledInterruptSources(base, resolverCore);
2906 
2907  HW_WR_REG32(
2908  base + regOffset, value);
2909 
2910  if(monitorData->lowAmplitude_error)
2911  {
2912  RDC_enableCoreInterrupt(base, resolverCore, (enabledInterruptSources | RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR));
2913  }
2914  else
2915  {
2916  RDC_disableCoreInterrupt(base, resolverCore, (RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR));
2917  }
2918  }
2919 
2920  //*****************************************************************************
2921  // Observational Data
2922  //*****************************************************************************
2923 
2938  static inline void
2939  RDC_getAdcObservationalData(
2940  uint32_t base,
2941  uint8_t resolverCore,
2942  ADC_observationalData * AdcData)
2943  {
2944  uint32_t regOffset = CSL_RESOLVER_REGS_OBS_ADC_0 + (resolverCore * RDC_CORE_OFFSET);
2945  uint32_t value = HW_RD_REG32(
2946  base + regOffset);
2947  AdcData->cos_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_COS_ADC_SHIFT);
2948  AdcData->sin_adc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_1_SIN_ADC_SHIFT);
2949 
2950  regOffset = CSL_RESOLVER_REGS_OBS_ADC_REC_0 + (resolverCore * RDC_CORE_OFFSET);
2951  value = HW_RD_REG32(
2952  base + regOffset);
2953  AdcData->cos_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_COS_REC_SHIFT);
2954  AdcData->sin_rec = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_REC_1_SIN_REC_SHIFT);
2955 
2956  regOffset = CSL_RESOLVER_REGS_OBS_ADC_DC_0 + (resolverCore * RDC_CORE_OFFSET);
2957  value = HW_RD_REG32(
2958  base + regOffset);
2959  AdcData->cos_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_COS_DC_SHIFT);
2960  AdcData->sin_dc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_DC_1_SIN_DC_SHIFT);
2961 
2962  regOffset = CSL_RESOLVER_REGS_OBS_ADC_PGC_0 + (resolverCore * RDC_CORE_OFFSET);
2963  value = HW_RD_REG32(
2964  base + regOffset);
2965  AdcData->cos_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_COS_PGC_SHIFT);
2966  AdcData->sin_pgc = (int16_t)((value & CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_MASK)>>CSL_RESOLVER_REGS_OBS_ADC_PGC_1_SIN_PGC_SHIFT);
2967  }
2968 
2976  static inline void
2977  RDC_getPeakHistogramObservationalData(uint32_t base, uint8_t resolverCore, PeakHistogram_observationalData* histogram)
2978  {
2979  uint32_t regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0 + (resolverCore * RDC_CORE_OFFSET);
2980  uint32_t value = HW_RD_REG32(
2981  base + regOffset);
2982  histogram->peakHistgoramBucket[0] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM0_0_SHIFT);
2983  histogram->peakHistgoramBucket[1] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM1_0_SHIFT);
2984  histogram->peakHistgoramBucket[2] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM2_0_SHIFT);
2985  histogram->peakHistgoramBucket[3] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM3_0_0_PEAKHISTOGRAM3_0_SHIFT);
2986 
2987  regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0 + (resolverCore * RDC_CORE_OFFSET);
2988  value = HW_RD_REG32(
2989  base + regOffset);
2990  histogram->peakHistgoramBucket[4] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM4_0_SHIFT);
2991  histogram->peakHistgoramBucket[5] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM5_0_SHIFT);
2992  histogram->peakHistgoramBucket[6] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM6_0_SHIFT);
2993  histogram->peakHistgoramBucket[7] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM7_4_0_PEAKHISTOGRAM7_0_SHIFT);
2994 
2995  regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0 + (resolverCore * RDC_CORE_OFFSET);
2996  value = HW_RD_REG32(
2997  base + regOffset);
2998  histogram->peakHistgoramBucket[8] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM8_0_SHIFT);
2999  histogram->peakHistgoramBucket[9] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM9_0_SHIFT);
3000  histogram->peakHistgoramBucket[10] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM10_0_SHIFT);
3001  histogram->peakHistgoramBucket[11] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM11_8_0_PEAKHISTOGRAM11_0_SHIFT);
3002 
3003  regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0 + (resolverCore * RDC_CORE_OFFSET);
3004  value = HW_RD_REG32(
3005  base + regOffset);
3006  histogram->peakHistgoramBucket[12] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM12_0_SHIFT);
3007  histogram->peakHistgoramBucket[13] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM13_0_SHIFT);
3008  histogram->peakHistgoramBucket[14] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM14_0_SHIFT);
3009  histogram->peakHistgoramBucket[15] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM15_12_0_PEAKHISTOGRAM15_0_SHIFT);
3010 
3011  regOffset = CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0 + (resolverCore * RDC_CORE_OFFSET);
3012  value = HW_RD_REG32(
3013  base + regOffset);
3014  histogram->peakHistgoramBucket[16] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM16_0_SHIFT);
3015  histogram->peakHistgoramBucket[17] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM17_0_SHIFT);
3016  histogram->peakHistgoramBucket[18] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM18_0_SHIFT);
3017  histogram->peakHistgoramBucket[19] = ((value & CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_MASK) >> CSL_RESOLVER_REGS_OBS_PEAKHISTOGRAM19_16_0_PEAKHISTOGRAM19_0_SHIFT);
3018  }
3019 
3025  extern void
3026  RDC_coreParamsInit(Core_config_t* coreParams);
3032  extern void
3033  RDC_paramsInit(RDC_configParams* params);
3040  extern void
3041  RDC_init(uint32_t base, RDC_configParams* params);
3047  extern void
3048  RDC_BaselineParametersInit(uint32_t base);
3049 //*****************************************************************************
3050 //
3051 // Close the Doxygen group.
3053 //
3054 //*****************************************************************************
3055 
3056 //*****************************************************************************
3057 //
3058 // Mark the end of the C bindings section for C++ compilers.
3059 //
3060 //*****************************************************************************
3061 #ifdef __cplusplus
3062 }
3063 #endif
3064 
3065 #endif // RESOLVER_V1_H_
Diag_Mon_SinCos_Gain_drift_data::gain_drift_threshold_lo
int16_t gain_drift_threshold_lo
Definition: resolver/v0/resolver.h:392
Core_config_t::Pg_correctionEnable
bool Pg_correctionEnable
Definition: resolver/v0/resolver.h:599
RDC_CAL_ADC0
#define RDC_CAL_ADC0
Macro used to specify Calibration data for ADC 0.
Definition: resolver/v0/resolver.h:308
RDC_getArcTanAngle
static int16_t RDC_getArcTanAngle(uint32_t base, uint8_t core)
Returns signed 16bit angle data from ArcTan. the data corresponds to -180 to +180 degrees angle in de...
Definition: resolver/v0/resolver.h:2056
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_error
bool lowAmplitude_error
Definition: resolver/v0/resolver.h:538
RDC_configParams::Input_signalMode
uint8_t Input_signalMode
Definition: resolver/v0/resolver.h:618
RDC_getDcOffsetEstimatedValues
static int16_t RDC_getDcOffsetEstimatedValues(uint32_t base, uint8_t core, uint8_t sinCosValue)
returns DC OFFSET estimation values
Definition: resolver/v0/resolver.h:1547
Diag_Mon_ExcFreq_Degradataion_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor excitation frequenc...
Definition: resolver/v0/resolver.h:436
RDC_DC_OFFSET_COS_ESTIMATION
#define RDC_DC_OFFSET_COS_ESTIMATION
Definition: resolver/v0/resolver.h:106
Diag_Mon_Cos_Phase_drift_data::phase_drift_en
bool phase_drift_en
Definition: resolver/v0/resolver.h:420
RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:261
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_cossq
uint16_t sinsqcossq_cossq
Definition: resolver/v0/resolver.h:494
RDC_coreParamsInit
void RDC_coreParamsInit(Core_config_t *coreParams)
Inits the Core Parameters for the resolver core.
Diag_Mon_ExcFreq_Degradataion_data::excfreqdetected_sin
uint16_t excfreqdetected_sin
Definition: resolver/v0/resolver.h:437
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_lo
bool sinsqcossq_lo
Definition: resolver/v0/resolver.h:497
RDC_EXCITATION_FREQUENCY_MIN_PHASE
#define RDC_EXCITATION_FREQUENCY_MIN_PHASE
Minimum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:82
RDC_setDiagnosticsSinCosOffsetDriftData
static void RDC_setDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Sets the Monitor Sin or Cos Offset Drift (DOS) diagnostics controls int16_t offset_drift_threshold_hi...
Definition: resolver/v0/resolver.h:2162
Diag_Mon_Cos_Phase_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Cos Phase drift (DO...
Definition: resolver/v0/resolver.h:414
Diag_Mon_SinCos_Gain_drift_data::gain_drift_sin_hi
bool gain_drift_sin_hi
Definition: resolver/v0/resolver.h:396
Diag_Mon_ExcFreq_Degradataion_data::excfreq_level
uint16_t excfreq_level
Definition: resolver/v0/resolver.h:441
RDC_clearSequencerInterrupt
static void RDC_clearSequencerInterrupt(uint32_t base)
Clear the Sequencer Error Interrupt status.
Definition: resolver/v0/resolver.h:1124
ADC_observationalData::cos_adc
int16_t cos_adc
Definition: resolver/v0/resolver.h:565
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:268
RDC_disablePhaseGainEstimation
static void RDC_disablePhaseGainEstimation(uint32_t base, uint8_t core)
Disbales Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:1828
RDC_setDcOffsetCalCoef
static void RDC_setDcOffsetCalCoef(uint32_t base, uint8_t core, uint8_t coef1, uint8_t coef2)
Sets the DC Offset Coefficients coef1, coef2.
Definition: resolver/v0/resolver.h:1398
baselineParameters::DcParam3
uint8_t DcParam3
Definition: resolver/v0/resolver.h:647
Core_config_t::BpfDc_offsetCorrectionEnable
bool BpfDc_offsetCorrectionEnable
Definition: resolver/v0/resolver.h:584
RDC_configParams::core1
Core_config_t core1
Definition: resolver/v0/resolver.h:630
ADC_observationalData::sin_adc
int16_t sin_adc
Definition: resolver/v0/resolver.h:566
RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_HI_ERR
Definition: resolver/v0/resolver.h:251
Diag_Mon_SinCos_Offset_drift_data::offset_drift_cos_lo
bool offset_drift_cos_lo
Definition: resolver/v0/resolver.h:371
RDC_getDiagnosticsRotationalSignalIntegrityData
static void RDC_getDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Returns the Monitor rotational signal integrity (DOS) diagnostics data bool cos_neg_zc_peak_mismatch_...
Definition: resolver/v0/resolver.h:2578
Core_config_t::Pg_sinGainBypassValue
int16_t Pg_sinGainBypassValue
Definition: resolver/v0/resolver.h:601
RDC_getCoreInterruptStatus
static uint32_t RDC_getCoreInterruptStatus(uint32_t base, uint32_t ResolverCore)
Returns Core interrupt Status.
Definition: resolver/v0/resolver.h:1279
RDC_getCoreEnabledInterruptSources
static uint32_t RDC_getCoreEnabledInterruptSources(uint32_t base, uint8_t ResolverCore)
returns enabled Interrupt Sources
Definition: resolver/v0/resolver.h:1196
RDC_setTrack2Constants
static void RDC_setTrack2Constants(uint32_t base, uint8_t core, Track2Constants_t *track2Constants)
sets up the Track2 loop constants the following are the constants that can be setup using this API
Definition: resolver/v0/resolver.h:1990
RDC_getDiagnosticsWeakAmplitudeData
static void RDC_getDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Returns the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics data uint16_t lowAmpli...
Definition: resolver/v0/resolver.h:2857
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_threshold_lo
uint16_t excfreqdrift_threshold_lo
Definition: resolver/v0/resolver.h:440
Diag_Mon_SinCos_Offset_drift_data::offset_drift_threshold_lo
int16_t offset_drift_threshold_lo
Definition: resolver/v0/resolver.h:369
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_en
bool excfreqdrift_en
Definition: resolver/v0/resolver.h:446
Diag_Mon_Rotational_Signal_Integrity_data::sin_pos_zc_peak_mismatch_err
bool sin_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:466
RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST
#define RDC_MAX_IDEAL_SAMPLE_BPF_ADJUST
Definition: resolver/v0/resolver.h:112
Core_config_t::BpfDc_manualCos
int16_t BpfDc_manualCos
Definition: resolver/v0/resolver.h:588
Diag_Mon_Cos_Phase_drift_data::phase_drift_cos_hi
bool phase_drift_cos_hi
Definition: resolver/v0/resolver.h:418
RDC_getAdcSampleRate
static uint32_t RDC_getAdcSampleRate(uint32_t base)
Gets the ADC Sampling Ratio.
Definition: resolver/v0/resolver.h:935
RDC_enableGainAutoCorrection
static void RDC_enableGainAutoCorrection(uint32_t base, uint8_t core)
Enable Gain Auto correction.
Definition: resolver/v0/resolver.h:1885
RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_COS_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:254
RDC_EXCITATION_FREQUENCY_MAX_PHASE
#define RDC_EXCITATION_FREQUENCY_MAX_PHASE
Maximum Phase value that can be programmed for the Excitation signal.
Definition: resolver/v0/resolver.h:85
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_cos_value
int16_t highAmplitude_cos_value
Definition: resolver/v0/resolver.h:517
Diag_Mon_Cos_Phase_drift_data::phase_drift_glitch_count
uint8_t phase_drift_glitch_count
Definition: resolver/v0/resolver.h:417
RDC_disableCoreInterrupt
static void RDC_disableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Disable Core Interrupt.
Definition: resolver/v0/resolver.h:1212
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_threshold
uint16_t highAmplitude_threshold
Definition: resolver/v0/resolver.h:514
RDC_init
void RDC_init(uint32_t base, RDC_configParams *params)
Configures the RDC based on the parameter values.
Core_config_t
Struct holds the Resolver Core Configurations Can be passed to RDC_coreParamsInit(Core_config_t* core...
Definition: resolver/v0/resolver.h:582
RDC_enableTrack2Boost
static void RDC_enableTrack2Boost(uint32_t base, uint8_t core)
enables the track2 Boost
Definition: resolver/v0/resolver.h:2014
RDC_getGainEstimation
static void RDC_getGainEstimation(uint32_t base, uint8_t core, int16_t *sinGainEstimate, int16_t *cosGainEstimate)
returns the Gain estimates for sin and cosine gain values
Definition: resolver/v0/resolver.h:1965
RDC_getIdealSamplePeakAvgLimitStatus
static bool RDC_getIdealSamplePeakAvgLimitStatus(uint32_t base, uint8_t core)
Gets the status if the Peak Averaging Limit is reached.
Definition: resolver/v0/resolver.h:1656
RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_PHASEDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:262
RDC_setIdealSampleBpfAdjust
static void RDC_setIdealSampleBpfAdjust(uint32_t base, uint8_t core, uint8_t sampleAdjustCount)
the BPF sample adjust when the BPF is turned on. This configuration takes effect only on the auto mod...
Definition: resolver/v0/resolver.h:1634
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_cos_lo
bool excfreqdrift_cos_lo
Definition: resolver/v0/resolver.h:444
Diag_Mon_Rotational_Signal_Integrity_data::cos_pos_zc_peak_mismatch_err
bool cos_pos_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:464
RDC_SEQUENCER_MODE_5
#define RDC_SEQUENCER_MODE_5
ADC0/1 Parallelly Sample Sin0, Cos0, Cos1, Sin1 Samples Sequentially For Core0/1. Both Sin(Cos) Sampl...
Definition: resolver/v0/resolver.h:189
RDC_getSequencerInterruptStatus
static uint32_t RDC_getSequencerInterruptStatus(uint32_t base)
Returns Sequencer interrupt Status.
Definition: resolver/v0/resolver.h:1156
RDC_getCalibrationData
static uint32_t RDC_getCalibrationData(uint32_t base, uint8_t CalAdc)
Returns the CAL ADC data for given ADC, if the mode permits.
Definition: resolver/v0/resolver.h:1369
Core_config_t::track2Constants
Track2Constants_t track2Constants
Definition: resolver/v0/resolver.h:605
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_HI_ERR
Definition: resolver/v0/resolver.h:260
RDC_overrideIdealSampleTime
static void RDC_overrideIdealSampleTime(uint32_t base, uint8_t core, uint8_t overrideValue)
sets the Override value for the Ideal Sample Time selection.
Definition: resolver/v0/resolver.h:1571
RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_SIN_FAULT_ERR
Definition: resolver/v0/resolver.h:249
Core_config_t::IdealSample_bottomSampleEnable
bool IdealSample_bottomSampleEnable
Definition: resolver/v0/resolver.h:594
RDC_RESOLVER_CORE0
#define RDC_RESOLVER_CORE0
Macro used to specify resolver core 0.
Definition: resolver/v0/resolver.h:93
baselineParameters::t2Param8
uint8_t t2Param8
Definition: resolver/v0/resolver.h:652
RDC_setIdealSampleMode
static void RDC_setIdealSampleMode(uint32_t base, uint8_t core, uint8_t mode)
Ideal Sample Time Computation Mode selection.
Definition: resolver/v0/resolver.h:1679
RDC_BaselineParametersInit
void RDC_BaselineParametersInit(uint32_t base)
Inits Baseline Parameter configurations.
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_threshold
uint16_t lowAmplitude_threshold
Definition: resolver/v0/resolver.h:536
Diag_Mon_Rotational_Signal_Integrity_data::cos_multi_zc_error_err
bool cos_multi_zc_error_err
Definition: resolver/v0/resolver.h:468
Core_config_t::BpfDc_bpfEnable
bool BpfDc_bpfEnable
Definition: resolver/v0/resolver.h:583
RDC_setGainBypassValue
static void RDC_setGainBypassValue(uint32_t base, uint8_t core, uint16_t sinGainBypass, uint16_t cosGainBypass)
Sets the Manual Gain Correction values for Sin and Cos.
Definition: resolver/v0/resolver.h:1925
RDC_getExcitationSignalAmplitudeControl
static uint32_t RDC_getExcitationSignalAmplitudeControl(uint32_t base)
returns the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1073
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_sin_error
bool highAmplitude_sin_error
Definition: resolver/v0/resolver.h:518
RDC_disableAdcSingleEndedMode
static void RDC_disableAdcSingleEndedMode(uint32_t base)
Disable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:741
RDC_configParams::Int_core1Interrupts
uint32_t Int_core1Interrupts
Definition: resolver/v0/resolver.h:634
RDC_configParams::adv_config
bool adv_config
Definition: resolver/v0/resolver.h:617
Diag_Mon_SinCos_Gain_drift_data::gaindrift_en
bool gaindrift_en
Definition: resolver/v0/resolver.h:398
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:269
Diag_Mon_SinCos_Gain_drift_data::gain_drift_sin_lo
bool gain_drift_sin_lo
Definition: resolver/v0/resolver.h:397
RDC_enableExcitationSignalSyncIn
static void RDC_enableExcitationSignalSyncIn(uint32_t base)
Enables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:950
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_glitchcount
uint8_t lowAmplitude_glitchcount
Definition: resolver/v0/resolver.h:537
Track2Constants_t
struct to hold the track2 constant data
Definition: resolver/v0/resolver.h:350
RDC_clearCoreInterrupt
static void RDC_clearCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Clear the Core Interrupt status.
Definition: resolver/v0/resolver.h:1234
RDC_CORE_OFFSET
#define RDC_CORE_OFFSET
Header Files.
Definition: resolver/v0/resolver.h:78
RDC_configParams::Input_adcBurstCount
uint8_t Input_adcBurstCount
Definition: resolver/v0/resolver.h:620
RDC_setDiagnosticsRotationalSignalIntegrityData
static void RDC_setDiagnosticsRotationalSignalIntegrityData(uint32_t base, uint8_t resolverCore, Diag_Mon_Rotational_Signal_Integrity_data *monitorData)
Sets the Monitor rotational signal integrity (DOS) diagnostics Controls bool cos_neg_zc_peak_mismatch...
Definition: resolver/v0/resolver.h:2628
Diag_Mon_Sin_Cos_High_Amplitude
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos saturati...
Definition: resolver/v0/resolver.h:513
RDC_selectCalibrationChannel
static void RDC_selectCalibrationChannel(uint32_t base, uint8_t calChannel)
Selects Calibration Channel for Cal sequence.
Definition: resolver/v0/resolver.h:1335
ADC_observationalData::cos_pgc
int16_t cos_pgc
Definition: resolver/v0/resolver.h:571
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_hi
bool sinsqcossq_hi
Definition: resolver/v0/resolver.h:496
Core_config_t::IdealSample_overrideValue
uint8_t IdealSample_overrideValue
Definition: resolver/v0/resolver.h:590
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_glitchcount
uint8_t excfreqdrift_glitchcount
Definition: resolver/v0/resolver.h:442
Diag_Mon_Cos_Phase_drift_data::phase_drift_cos_lo
bool phase_drift_cos_lo
Definition: resolver/v0/resolver.h:419
Diag_Mon_Sin_Cos_Weak_Amplitude
Structure to hold the control/status data for Diagnostics mentioned under Monitor weak Sin or Cos sig...
Definition: resolver/v0/resolver.h:535
RDC_RESOLVER_CORE1
#define RDC_RESOLVER_CORE1
Macro used to specify resolver core 1.
Definition: resolver/v0/resolver.h:96
RDC_configParams::Input_resolverSequencerMode
uint8_t Input_resolverSequencerMode
Definition: resolver/v0/resolver.h:621
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_sin_value
int16_t highAmplitude_sin_value
Definition: resolver/v0/resolver.h:516
RDC_disableGainAutoCorrection
static void RDC_disableGainAutoCorrection(uint32_t base, uint8_t core)
Disable Gain Auto Correction.
Definition: resolver/v0/resolver.h:1904
ADC_observationalData::sin_rec
int16_t sin_rec
Definition: resolver/v0/resolver.h:568
Diag_Mon_Rotational_Signal_Integrity_data::cos_neg_zc_peak_mismatch_err
bool cos_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:463
ADC_observationalData::cos_dc
int16_t cos_dc
Definition: resolver/v0/resolver.h:569
RDC_getExcitationSignalFrequencySelect
static uint32_t RDC_getExcitationSignalFrequencySelect(uint32_t base)
Returns the selected Excitation Signal Frequency select.
Definition: resolver/v0/resolver.h:919
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:270
RDC_configParams::core0
Core_config_t core0
Definition: resolver/v0/resolver.h:629
RDC_setExcitationSignalPhase
static void RDC_setExcitationSignalPhase(uint32_t base, uint16_t phase)
Sets the Phase value for the Excitation Signal. Phase values in the range [RDC_EXCITATION_FREQUENCY_M...
Definition: resolver/v0/resolver.h:856
Core_config_t::Pg_cosGainBypassValue
int16_t Pg_cosGainBypassValue
Definition: resolver/v0/resolver.h:602
PeakHistogram_observationalData
Struct to hold the peakHistogram Buckets for Ideal Sample Calculation by SW. once the auto ideal samp...
Definition: resolver/v0/resolver.h:670
RDC_enableBPF
static void RDC_enableBPF(uint32_t base, uint8_t core)
enables Band Pass Filter before DC Offset logic.
Definition: resolver/v0/resolver.h:1428
baselineParameters::t2Param6
uint8_t t2Param6
Definition: resolver/v0/resolver.h:650
RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR
#define RDC_INTERRUPT_SOURCE_LOWAMPLITUDE_ERR
Interrupt Sources Macros.
Definition: resolver/v0/resolver.h:247
RDC_setDiagnosticsHighAmplitudeData
static void RDC_setDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Sets the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics Controls uint16_t hig...
Definition: resolver/v0/resolver.h:2818
Diag_Mon_Rotational_Signal_Integrity_data::rotpeak_level
uint16_t rotpeak_level
Definition: resolver/v0/resolver.h:471
Diag_Mon_Rotational_Signal_Integrity_data::sin_neg_zc_peak_mismatch_err
bool sin_neg_zc_peak_mismatch_err
Definition: resolver/v0/resolver.h:465
RDC_disableSequencerInterrupt
static void RDC_disableSequencerInterrupt(uint32_t base)
Disable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1108
RDC_enableDcOffsetAutoCorrection
static void RDC_enableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Enables Auto DC Offset Correction from the estimated values Disables DC Offset Manual Correction logi...
Definition: resolver/v0/resolver.h:1492
RDC_setDiagnosticsSinCosGainDriftData
static void RDC_setDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Sets the Monitor Sin or Cos Gain drift (DOS) diagnostics Controls int16_t gain_drift_threshold_hi - t...
Definition: resolver/v0/resolver.h:2275
RDC_getPeakHistogramObservationalData
static void RDC_getPeakHistogramObservationalData(uint32_t base, uint8_t resolverCore, PeakHistogram_observationalData *histogram)
Returns the Peak Histogram Bucket data.
Definition: resolver/v0/resolver.h:2977
Core_config_t::Pg_cosPhaseBypassValue
int16_t Pg_cosPhaseBypassValue
Definition: resolver/v0/resolver.h:603
RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_HI_ERR
Definition: resolver/v0/resolver.h:264
Diag_Mon_Rotational_Signal_Integrity_data::sin_multi_zc_error_count
uint8_t sin_multi_zc_error_count
Definition: resolver/v0/resolver.h:470
RDC_forceSequencerInterrupt
static void RDC_forceSequencerInterrupt(uint32_t base)
Force the Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1140
RDC_configParams::ExcFrq_socDelay
uint16_t ExcFrq_socDelay
Definition: resolver/v0/resolver.h:627
RDC_configParams::Int_seqEnable
bool Int_seqEnable
Definition: resolver/v0/resolver.h:632
Diag_Mon_SinCos_Offset_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos offset d...
Definition: resolver/v0/resolver.h:367
baselineParameters::adcParam1
uint8_t adcParam1
Definition: resolver/v0/resolver.h:645
RDC_disableIdealSampleBottomSampling
static void RDC_disableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Disables Bottom Sampling.
Definition: resolver/v0/resolver.h:1721
RDC_setIdealSampleDetectionThreshold
static void RDC_setIdealSampleDetectionThreshold(uint32_t base, uint8_t core, uint16_t absThresholdValue)
sets Ideal Sample Detetction Threshold. validates the sample for the Ideal Sample time detection comp...
Definition: resolver/v0/resolver.h:1613
Diag_Mon_SinCos_Gain_drift_data::gain_drift_glitch_count
uint8_t gain_drift_glitch_count
Definition: resolver/v0/resolver.h:393
RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR
#define RDC_INTERRUPT_SOURCE_SINSQCOSSQ_LO_ERR
Definition: resolver/v0/resolver.h:250
RDC_getDiagnosticsHighAmplitudeData
static void RDC_getDiagnosticsHighAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_High_Amplitude *monitorData)
Returns the Monitor Sin or Cos saturation or very high amplitude (DOS) diagnostics data uint16_t high...
Definition: resolver/v0/resolver.h:2777
RDC_getPhaseEstimation
static int16_t RDC_getPhaseEstimation(uint32_t base, uint8_t core)
returns the Cos Phase Offset Estimation this can be used only if the RDC_getPhaseGainEstimationStatus...
Definition: resolver/v0/resolver.h:1945
RDC_enableCoreInterrupt
static void RDC_enableCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
enable Core Interrupt
Definition: resolver/v0/resolver.h:1174
RDC_enablePhaseAutoCorrection
static void RDC_enablePhaseAutoCorrection(uint32_t base, uint8_t core)
Enables Phase Auto Correction.
Definition: resolver/v0/resolver.h:1847
Diag_Mon_Signal_Integrity_SinSq_CosSq
Structure to hold the control/status data for Diagnostics mentioned under Monitor signal integrity by...
Definition: resolver/v0/resolver.h:490
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:259
RDC_getPhaseGainEstimationStatus
static bool RDC_getPhaseGainEstimationStatus(uint32_t base, uint8_t core)
Gets status if the Phase Gain Estimation is complete.
Definition: resolver/v0/resolver.h:1746
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_glitchcount
uint8_t highAmplitude_glitchcount
Definition: resolver/v0/resolver.h:515
Diag_Mon_SinCos_Offset_drift_data::offset_drift_sin_hi
bool offset_drift_sin_hi
Definition: resolver/v0/resolver.h:372
Diag_Mon_SinCos_Gain_drift_data::gain_drift_threshold_hi
int16_t gain_drift_threshold_hi
Definition: resolver/v0/resolver.h:391
Core_config_t::BpfDc_manualSin
int16_t BpfDc_manualSin
Definition: resolver/v0/resolver.h:587
Core_config_t::BpfDc_dcOffCal2
uint8_t BpfDc_dcOffCal2
Definition: resolver/v0/resolver.h:586
RDC_SEQUENCER_MODE_0
#define RDC_SEQUENCER_MODE_0
or returned by RDC_getAdcSequencerOperationalMode()
Definition: resolver/v0/resolver.h:157
RDC_getTrack2Angle
static int16_t RDC_getTrack2Angle(uint32_t base, uint8_t core)
Returns Signed 16 bit angle data from Track2 Loop. the data corresponds to -180 to 180 degrees angle ...
Definition: resolver/v0/resolver.h:2074
Core_config_t::Pg_estimationLimit
uint8_t Pg_estimationLimit
Definition: resolver/v0/resolver.h:597
baselineParameters::t2Param9
bool t2Param9
Definition: resolver/v0/resolver.h:653
RDC_paramsInit
void RDC_paramsInit(RDC_configParams *params)
Inits the resolver Configuration parameters.
Diag_Mon_Rotational_Signal_Integrity_data::rotfreq_level
uint16_t rotfreq_level
Definition: resolver/v0/resolver.h:472
RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_LO_ERR
Definition: resolver/v0/resolver.h:265
Track2Constants_t::kvelfilt
uint8_t kvelfilt
Definition: resolver/v0/resolver.h:351
Diag_Mon_ExcFreq_Degradataion_data::excfreqdetected_cos
uint16_t excfreqdetected_cos
Definition: resolver/v0/resolver.h:438
RDC_INTERRUPT_SOURCE_ALL
#define RDC_INTERRUPT_SOURCE_ALL
Definition: resolver/v0/resolver.h:273
baselineParameters::PgParam4
uint16_t PgParam4
Definition: resolver/v0/resolver.h:648
RDC_setDcOffsetManualCorrectionValue
static void RDC_setDcOffsetManualCorrectionValue(uint32_t base, uint8_t core, int16_t sin, int16_t cos)
Sets the Sin, Cosine Manual Correction values for the Dc Offset block in the given resolver core.
Definition: resolver/v0/resolver.h:1516
baselineParameters::t2Param5
uint8_t t2Param5
Definition: resolver/v0/resolver.h:649
ADC_observationalData::sin_dc
int16_t sin_dc
Definition: resolver/v0/resolver.h:570
Diag_Mon_Sin_Cos_High_Amplitude::highAmplitude_cos_error
bool highAmplitude_cos_error
Definition: resolver/v0/resolver.h:519
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_threshold_hi
uint16_t sinsqcossq_threshold_hi
Definition: resolver/v0/resolver.h:491
RDC_disableResolver
static void RDC_disableResolver(uint32_t base)
Disables the Resolver Operation.
Definition: resolver/v0/resolver.h:834
RDC_setExcitationSignalFrequencySelect
static void RDC_setExcitationSignalFrequencySelect(uint32_t base, uint8_t FrequencySel)
Sets the Excitation frequency value from the selected values.
Definition: resolver/v0/resolver.h:895
RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_COS_HI_ERR
Definition: resolver/v0/resolver.h:266
RDC_setDiagnosticsSignalIntegritySquareSumData
static void RDC_setDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Sets the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics Controls uint16_t ...
Definition: resolver/v0/resolver.h:2731
RDC_configParams::ExcFrq_freqSel
uint8_t ExcFrq_freqSel
Definition: resolver/v0/resolver.h:623
RDC_disableTrack2Boost
static void RDC_disableTrack2Boost(uint32_t base, uint8_t core)
disables the track2 Boost
Definition: resolver/v0/resolver.h:2033
RDC_clearCalibrationStatus
static void RDC_clearCalibrationStatus(uint32_t base)
Clears Calibration Status for re-enabling Calibration Sequence.
Definition: resolver/v0/resolver.h:1318
Diag_Mon_Cos_Phase_drift_data::phase_drift_threshold_hi
int16_t phase_drift_threshold_hi
Definition: resolver/v0/resolver.h:415
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_sinsq
uint16_t sinsqcossq_sinsq
Definition: resolver/v0/resolver.h:495
RDC_disablePhaseAutoCorrection
static void RDC_disablePhaseAutoCorrection(uint32_t base, uint8_t core)
Disables Phase Auto Correction.
Definition: resolver/v0/resolver.h:1866
RDC_getExcitationSignalPhase
static uint32_t RDC_getExcitationSignalPhase(uint32_t base)
Returns the Phase Value programmed for Excitation signal.
Definition: resolver/v0/resolver.h:876
RDC_setDiagnosticsCosPhaseDriftData
static void RDC_setDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Sets the Monitor Cos Phase drift (DOS) diagnostics Controls int16_t phase_drift_threshold_hi - the ph...
Definition: resolver/v0/resolver.h:2388
RDC_configParams::ExcFrq_phase
uint16_t ExcFrq_phase
Definition: resolver/v0/resolver.h:624
RDC_getAdcObservationalData
static void RDC_getAdcObservationalData(uint32_t base, uint8_t resolverCore, ADC_observationalData *AdcData)
Returns the Observational ADC data to struct type ADC_observationalData int16_t cos_adc - SW Observat...
Definition: resolver/v0/resolver.h:2939
RDC_enableAdcSingleEndedMode
static void RDC_enableAdcSingleEndedMode(uint32_t base)
Enable Single Ended Mode of operation.
Definition: resolver/v0/resolver.h:724
baselineParameters::t2Param7
uint8_t t2Param7
Definition: resolver/v0/resolver.h:651
RDC_configParams::Int_core0Interrupts
uint32_t Int_core0Interrupts
Definition: resolver/v0/resolver.h:633
RDC_enableIdealSampleBottomSampling
static void RDC_enableIdealSampleBottomSampling(uint32_t base, uint8_t core)
Enables bottom Sampling. twice the sampling rate than disabled. the track2 loop runs twice the speed ...
Definition: resolver/v0/resolver.h:1702
Diag_Mon_Cos_Phase_drift_data::phase_drift_threshold_lo
int16_t phase_drift_threshold_lo
Definition: resolver/v0/resolver.h:416
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_sin_lo
bool excfreqdrift_sin_lo
Definition: resolver/v0/resolver.h:445
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_glitchcount
uint8_t sinsqcossq_glitchcount
Definition: resolver/v0/resolver.h:493
RDC_getCalibrationStatus
static bool RDC_getCalibrationStatus(uint32_t base)
Returns the Calibration Status.
Definition: resolver/v0/resolver.h:1302
Diag_Mon_SinCos_Gain_drift_data::gain_drift_cos_lo
bool gain_drift_cos_lo
Definition: resolver/v0/resolver.h:395
DebugP.h
RDC_getDiagnosticsSinCosOffsetDriftData
static void RDC_getDiagnosticsSinCosOffsetDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Offset_drift_data *monitorData)
Returns the Monitor Sin or Cos Offset Drift (DOS) diagnostics data int16_t offset_drift_threshold_hi ...
Definition: resolver/v0/resolver.h:2120
RDC_enableCalibration
static void RDC_enableCalibration(uint32_t base)
Enables ADC Calibration.
Definition: resolver/v0/resolver.h:1351
Diag_Mon_SinCos_Gain_drift_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor Sin or Cos Gain dri...
Definition: resolver/v0/resolver.h:390
Core_config_t::IdealSample_absThresholdValue
uint16_t IdealSample_absThresholdValue
Definition: resolver/v0/resolver.h:591
RDC_disableExcitationSignalSyncIn
static void RDC_disableExcitationSignalSyncIn(uint32_t base)
Disables the Excitation Signal Sync In.
Definition: resolver/v0/resolver.h:966
ADC_observationalData::sin_pgc
int16_t sin_pgc
Definition: resolver/v0/resolver.h:572
Diag_Mon_Rotational_Signal_Integrity_data::zero_cross_rot_en
bool zero_cross_rot_en
Definition: resolver/v0/resolver.h:473
RDC_getDiagnosticsSinCosGainDriftData
static void RDC_getDiagnosticsSinCosGainDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_SinCos_Gain_drift_data *monitorData)
Returns the Monitor Sin or Cos Gain drift (DOS) diagnostics data int16_t gain_drift_threshold_hi - th...
Definition: resolver/v0/resolver.h:2225
RDC_setAdcSequencerOperationalMode
static void RDC_setAdcSequencerOperationalMode(uint32_t base, uint8_t operationalMode)
sets Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 SAM...
Definition: resolver/v0/resolver.h:798
RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_EXCFREQDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:258
RDC_enableResolver
static void RDC_enableResolver(uint32_t base)
Enables the Resolver Operation.
Definition: resolver/v0/resolver.h:818
RDC_setAdcBurstCount
static void RDC_setAdcBurstCount(uint32_t base, uint8_t burstCount)
sets the ADC Burst count, samples to be averaged.
Definition: resolver/v0/resolver.h:707
RDC_enableSequencerInterrupt
static void RDC_enableSequencerInterrupt(uint32_t base)
Enable Sequencer Error Interrupt.
Definition: resolver/v0/resolver.h:1092
RDC_getIdealSampleTime
static uint8_t RDC_getIdealSampleTime(uint32_t base, uint8_t core)
Returns the Ideal Sample Time esitimated by the resolver core.
Definition: resolver/v0/resolver.h:1591
RDC_configParams::Input_socWidth
uint8_t Input_socWidth
Definition: resolver/v0/resolver.h:619
RDC_setDiagnosticsExcFreqDegradationData
static void RDC_setDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Sets the Monitor excitation frequency degradation or loss (DOS) diagnostics Controls uint16_t excfreq...
Definition: resolver/v0/resolver.h:2514
Diag_Mon_SinCos_Offset_drift_data::offset_drift_sin_lo
bool offset_drift_sin_lo
Definition: resolver/v0/resolver.h:373
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_threshold_hi
uint16_t excfreqdrift_threshold_hi
Definition: resolver/v0/resolver.h:439
RDC_EXCITATION_FREQUENCY_20K
#define RDC_EXCITATION_FREQUENCY_20K
select 20KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:209
RDC_getDiagnosticsSignalIntegritySquareSumData
static void RDC_getDiagnosticsSignalIntegritySquareSumData(uint32_t base, uint32_t resolverCore, Diag_Mon_Signal_Integrity_SinSq_CosSq *monitorData)
Returns the Monitor signal integrity by checking Sin2+Cos2=Constant (DOS) diagnostics data uint16_t s...
Definition: resolver/v0/resolver.h:2682
RDC_DC_OFFSET_SIN_ESTIMATION
#define RDC_DC_OFFSET_SIN_ESTIMATION
Definition: resolver/v0/resolver.h:105
RDC_enablePhaseGainEstimation
static void RDC_enablePhaseGainEstimation(uint32_t base, uint8_t core)
Enables Phase Gain Estimation in the background.
Definition: resolver/v0/resolver.h:1808
RDC_MAX_EXCITATION_AMPLITUDE
#define RDC_MAX_EXCITATION_AMPLITUDE
Maximum Excitation Signal Amplitude.
Definition: resolver/v0/resolver.h:89
Diag_Mon_Rotational_Signal_Integrity_data
Structure to hold the control/status data for Diagnostics mentioned under Monitor rotational signal i...
Definition: resolver/v0/resolver.h:462
RDC_clearExcitationSignalEventStatus
static void RDC_clearExcitationSignalEventStatus(uint32_t base)
Clears SyncIn event status.
Definition: resolver/v0/resolver.h:1002
RDC_disableDcOffsetAutoCorrection
static void RDC_disableDcOffsetAutoCorrection(uint32_t base, uint8_t core)
Disbales Auto Offset correction from the estimated values Enables DC Offset Manual Correction logic.
Definition: resolver/v0/resolver.h:1470
RDC_setCosPhaseBypass
static void RDC_setCosPhaseBypass(uint32_t base, uint8_t core, int16_t cosPhaseBypass)
sets the Cos Phase Manual Bypass Value
Definition: resolver/v0/resolver.h:1788
baselineParameters::IdealParam2
uint8_t IdealParam2
Definition: resolver/v0/resolver.h:646
RDC_setPhaseGainEstimationTrainLimit
static void RDC_setPhaseGainEstimationTrainLimit(uint32_t base, uint8_t core, uint8_t pgEstimationLimit)
Sets the Phase Gain Estimation train limit. if the programmed value is x, 2^x rotations are considere...
Definition: resolver/v0/resolver.h:1766
RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_OFFSETDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:267
Core_config_t::BpfDc_dcOffCal1
uint8_t BpfDc_dcOffCal1
Definition: resolver/v0/resolver.h:585
RDC_forceCoreInterrupt
static void RDC_forceCoreInterrupt(uint32_t base, uint32_t ResolverCore, uint32_t interruptSource)
Force the Core Interrupt.
Definition: resolver/v0/resolver.h:1257
RDC_setExcitationSignalSocDelay
static void RDC_setExcitationSignalSocDelay(uint32_t base, uint16_t socDelay)
Sets the SOC Delay from the PWM Exciation Signal.
Definition: resolver/v0/resolver.h:1036
Core_config_t::IdealSample_sampleAdjustCount
uint8_t IdealSample_sampleAdjustCount
Definition: resolver/v0/resolver.h:592
RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_SIN_NEG_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:256
RDC_EXCITATION_FREQUENCY_5K
#define RDC_EXCITATION_FREQUENCY_5K
or returned by RDC_getExcitationSignalFrequencySelect()
Definition: resolver/v0/resolver.h:203
Diag_Mon_SinCos_Offset_drift_data::offset_drift_threshold_hi
int16_t offset_drift_threshold_hi
Definition: resolver/v0/resolver.h:368
RDC_getExcitationSignalPhaseInfo
static uint32_t RDC_getExcitationSignalPhaseInfo(uint32_t base)
Returns the latched value of the last pwm_sync_in rise event of the pwm phase. this is updated on eve...
Definition: resolver/v0/resolver.h:1020
baselineParameters
Struct holds the Baseline Parameter values Can be passed to RDC_BaselineParametersInit(uint32_t base)...
Definition: resolver/v0/resolver.h:644
Diag_Mon_Rotational_Signal_Integrity_data::cos_multi_zc_error_count
uint8_t cos_multi_zc_error_count
Definition: resolver/v0/resolver.h:469
Core_config_t::IdealSample_mode
uint8_t IdealSample_mode
Definition: resolver/v0/resolver.h:593
Diag_Mon_Rotational_Signal_Integrity_data::sin_multi_zc_error_err
bool sin_multi_zc_error_err
Definition: resolver/v0/resolver.h:467
Diag_Mon_Signal_Integrity_SinSq_CosSq::sinsqcossq_threshold_lo
uint16_t sinsqcossq_threshold_lo
Definition: resolver/v0/resolver.h:492
ADC_observationalData::cos_rec
int16_t cos_rec
Definition: resolver/v0/resolver.h:567
RDC_EXCITATION_FREQUENCY_10K
#define RDC_EXCITATION_FREQUENCY_10K
select 10KHz Excitation Sine Frequency
Definition: resolver/v0/resolver.h:206
RDC_getAdcSequencerOperationalMode
static uint32_t RDC_getAdcSequencerOperationalMode(uint32_t base)
returns Sequencer Operational Mode Valid values are RDC_SEQUENCER_MODE_0 - ADC0 SAMPLES SIN AND ADC1 ...
Definition: resolver/v0/resolver.h:770
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_cos_value
int16_t lowAmplitude_cos_value
Definition: resolver/v0/resolver.h:540
DebugP_assert
#define DebugP_assert(expression)
Function to call for assert check.
Definition: DebugP.h:177
Diag_Mon_ExcFreq_Degradataion_data::excfreqdrift_hi
bool excfreqdrift_hi
Definition: resolver/v0/resolver.h:443
Core_config_t::Pg_estimationEnable
bool Pg_estimationEnable
Definition: resolver/v0/resolver.h:596
RDC_getTrack2Velocity
static int32_t RDC_getTrack2Velocity(uint32_t base, uint8_t core)
Returns Signed 32 bit Velocity data from Track2 Loop.
Definition: resolver/v0/resolver.h:2093
PeakHistogram_observationalData::peakHistgoramBucket
uint8_t peakHistgoramBucket[20]
Definition: resolver/v0/resolver.h:671
RDC_disableBPF
static void RDC_disableBPF(uint32_t base, uint8_t core)
Disables Band Pass Filter Logic before DC Offset logic.
Definition: resolver/v0/resolver.h:1448
RDC_configParams::ExcFrq_enableSyncIn
bool ExcFrq_enableSyncIn
Definition: resolver/v0/resolver.h:626
RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_COS_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:255
RDC_setDiagnosticsWeakAmplitudeData
static void RDC_setDiagnosticsWeakAmplitudeData(uint32_t base, uint8_t resolverCore, Diag_Mon_Sin_Cos_Weak_Amplitude *monitorData)
Sets the Monitor weak Sin or Cos signal below a threshold (LOS) diagnostics Controls uint16_t lowAmpl...
Definition: resolver/v0/resolver.h:2896
RDC_setExcitationSignalAmplitudeControl
static void RDC_setExcitationSignalAmplitudeControl(uint32_t base, uint8_t amplitude)
set the Amplitude control for the excitation signal
Definition: resolver/v0/resolver.h:1055
RDC_setAdcSocWidth
static void RDC_setAdcSocWidth(uint32_t base, uint8_t socWidth)
sets the Start of Conversion Width for the ADC conversion
Definition: resolver/v0/resolver.h:684
RDC_getDiagnosticsExcFreqDegradationData
static void RDC_getDiagnosticsExcFreqDegradationData(uint32_t base, uint8_t resolverCore, Diag_Mon_ExcFreq_Degradataion_data *monitorData)
Returns the Monitor excitation frequency degradation or loss (DOS) diagnostics data uint16_t excfreqd...
Definition: resolver/v0/resolver.h:2448
Diag_Mon_Sin_Cos_Weak_Amplitude::lowAmplitude_sin_value
int16_t lowAmplitude_sin_value
Definition: resolver/v0/resolver.h:539
RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR
#define RDC_INTERRUPT_SOURCE_GAINDRIFT_SIN_LO_ERR
Definition: resolver/v0/resolver.h:263
RDC_configParams::ExcFrq_amplitude
uint8_t ExcFrq_amplitude
Definition: resolver/v0/resolver.h:625
RDC_getDiagnosticsCosPhaseDriftData
static void RDC_getDiagnosticsCosPhaseDriftData(uint32_t base, uint8_t resolverCore, Diag_Mon_Cos_Phase_drift_data *monitorData)
Returns the Monitor Cos Phase drift (DOS) diagnostics data int16_t phase_drift_threshold_hi - the con...
Definition: resolver/v0/resolver.h:2344
RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR
#define RDC_INTERRUPT_SOURCE_HIGHAMPLITUDE_COS_FAULT_ERR
Definition: resolver/v0/resolver.h:248
Diag_Mon_SinCos_Offset_drift_data::offset_drift_cos_hi
bool offset_drift_cos_hi
Definition: resolver/v0/resolver.h:370
RDC_getExcitationSignalEventStatus
static uint32_t RDC_getExcitationSignalEventStatus(uint32_t base)
returns if there is a sync in event after the RDC_enableResolver() has been called once this returns ...
Definition: resolver/v0/resolver.h:987
RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR
#define RDC_INTERRUPT_SOURCE_SIN_POS_ZC_PEAK_MISMATCH_ERR
Definition: resolver/v0/resolver.h:257
Core_config_t::Pg_autoCorrectionEnable
bool Pg_autoCorrectionEnable
Definition: resolver/v0/resolver.h:600
ADC_observationalData
Structure to hold the Observational Data reads int16_t cos_adc - SW Observational ADC data post latch...
Definition: resolver/v0/resolver.h:564
Diag_Mon_SinCos_Offset_drift_data::offset_drift_en
bool offset_drift_en
Definition: resolver/v0/resolver.h:374
RDC_configParams
Struct holds the RDC configurations Can be passed to RDC_paramsInit(RDC_configParams* params); RDC_in...
Definition: resolver/v0/resolver.h:616
Diag_Mon_SinCos_Gain_drift_data::gain_drift_cos_hi
bool gain_drift_cos_hi
Definition: resolver/v0/resolver.h:394