PSDK QNX API Guide
sciclient_fmwMsgParams.h
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1 /*
2  * Copyright (C) 2022 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  *
32  */
33 
44 #ifndef SCICLIENT_FMWMSGPARAMS_H_
45 #define SCICLIENT_FMWMSGPARAMS_H_
46 
47 /* ========================================================================== */
48 /* Include Files */
49 /* ========================================================================== */
50 
51 #include <stdint.h>
52 #include <ti/csl/soc.h>
53 
54 #ifdef __cplusplus
55 extern "C" {
56 #endif
57 
58 /* ========================================================================== */
59 /* Macros & Typedefs */
60 /* ========================================================================== */
61 
63 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU)
64 
71 /* ABI Major revision - Major revision changes
72 * indicate backward compatibility breakage */
73 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U)
74 /* ABI Minor revision - Minor revision changes
75 * indicate backward compatibility is maintained,
76 * however, new messages OR extensions to existing
77 * messages might have been adde */
78 #define SCICLIENT_FIRMWARE_ABI_MINOR (1U)
79 /* @} */
80 
88 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (0U)
90 #define SCICLIENT_CONTEXT_R5_SEC_0 (1U)
92 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (2U)
94 #define SCICLIENT_CONTEXT_R5_SEC_1 (3U)
96 #define SCICLIENT_CONTEXT_A72_SEC_0 (4U)
98 #define SCICLIENT_CONTEXT_A72_SEC_1 (5U)
100 #define SCICLIENT_CONTEXT_A72_NONSEC_0 (6U)
102 #define SCICLIENT_CONTEXT_A72_NONSEC_1 (7U)
104 #define SCICLIENT_CONTEXT_A72_NONSEC_2 (8U)
106 #define SCICLIENT_CONTEXT_A72_NONSEC_3 (9U)
108 #define SCICLIENT_CONTEXT_A72_NONSEC_4 (10U)
110 #define SCICLIENT_CONTEXT_A72_NONSEC_5 (11U)
112 #define SCICLIENT_CONTEXT_C7X_SEC_0 (12U)
114 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (13U)
116 #define SCICLIENT_CONTEXT_C7X_SEC_1 (14U)
118 #define SCICLIENT_CONTEXT_C7X_NONSEC_1 (15U)
120 #define SCICLIENT_CONTEXT_C7X_SEC_2 (16U)
122 #define SCICLIENT_CONTEXT_C7X_NONSEC_2 (17U)
124 #define SCICLIENT_CONTEXT_C7X_SEC_3 (18U)
126 #define SCICLIENT_CONTEXT_C7X_NONSEC_3 (19U)
128 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (20U)
130 #define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_0 (21U)
132 #define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_0 (22U)
134 #define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_1 (23U)
136 #define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_1 (24U)
138 #define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_0 (25U)
140 #define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_0 (26U)
142 #define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_1 (27U)
144 #define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_1 (28U)
146 #define SCICLIENT_CONTEXT_MAIN_2_R5_NONSEC_0 (29U)
148 #define SCICLIENT_CONTEXT_MAIN_2_R5_SEC_0 (30U)
150 #define SCICLIENT_CONTEXT_MAIN_2_R5_NONSEC_1 (31U)
152 #define SCICLIENT_CONTEXT_MAIN_2_R5_SEC_1 (32U)
154 #define SCICLIENT_CONTEXT_MAX_NUM (33U)
155 /* @} */
156 
166 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0 (0x20U)
167 
171 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE1_0 (0x21U)
172 
176 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE2_0 (0x22U)
177 
181 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE3_0 (0x23U)
182 
186 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0 (0x24U)
187 
191 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE1_0 (0x25U)
192 
196 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE2_0 (0x26U)
197 
201 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE3_0 (0x27U)
202 
206 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS0_CORE0_0 (0x30U)
207 
211 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS1_CORE0_0 (0x31U)
212 
216 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS2_CORE0_0 (0x32U)
217 
221 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS3_CORE0_0 (0x33U)
222 
226 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x01U)
227 
231 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1 (0x02U)
232 
236 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x06U)
237 
241 #define SCICLIENT_PROC_ID_R5FSS0_CORE1 (0x07U)
242 
246 #define SCICLIENT_PROC_ID_R5FSS1_CORE0 (0x08U)
247 
251 #define SCICLIENT_PROC_ID_R5FSS1_CORE1 (0x09U)
252 
256 #define SCICLIENT_PROC_ID_R5FSS2_CORE0 (0x0AU)
257 
261 #define SCICLIENT_PROC_ID_R5FSS2_CORE1 (0x0BU)
262 
266 #define SCICLIENT_PROC_ID_WKUP_HSM0 (0x80U)
267 
271 #define SCICLIENT_SOC_NUM_PROCESSORS (0x15U)
272 /* @} */
273 
279 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu)
283 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu)
290 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu)
296 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu)
302 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu)
308 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu)
313 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu)
314 
321 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu)
328 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu)
329 
337 #include <ti/drv/sciclient/soc/sysfw/include/j784s4/tisci_devices.h>
338 /* @} */
339 
346 #include <ti/drv/sciclient/soc/sysfw/include/j784s4/tisci_clocks.h>
347 /* @} */
348 
352 #define TISCI_ISC_CC_ID (160U)
353 
360 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U)
361 #define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U)
362 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U)
363 #define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U)
364 #define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U)
365 #define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U)
366 #define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1152U)
367 #define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1280U)
368 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (0U)
369 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (512U)
370 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (1024U)
371 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (1536U)
372 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (2048U)
373 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (2560U)
374 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (3072U)
375 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (3584U)
376 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (4096U)
377 /* @} */
378 
379 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U)
380 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U)
381 #define SCICLIENT_C7X_0_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_177)
382 #define SCICLIENT_C7X_0_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_179)
383 #define SCICLIENT_C7X_1_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_181)
384 #define SCICLIENT_C7X_1_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_183)
385 #define SCICLIENT_C7X_2_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_185)
386 #define SCICLIENT_C7X_2_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_187)
387 #define SCICLIENT_C7X_3_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_189)
388 #define SCICLIENT_C7X_3_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_191)
389 
396 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_MCU_R5FSS0_CORE0)
397 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_MCU_R5FSS0_CORE1)
398 /* @} */
399 
406 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \
407  (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0)
408 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \
409  (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1)
410 /* @} */
411 
413 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MCU_MSRAM_1MB0_RAM_BASE)
415 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END (CSL_MCU_MSRAM_1MB0_RAM_BASE + CSL_MCU_MSRAM_1MB0_RAM_SIZE)
416 
417 /* ========================================================================== */
418 /* Structure Declarations */
419 /* ========================================================================== */
420 
421 /* None */
422 
423 #ifdef __cplusplus
424 }
425 #endif
426 
427 #endif /* #ifndef SCICLIENT_FMWMSGPARAMS_H_ */
428