Files | |
file | udma_ch.h |
UDMA Channel related parameters and API. | |
Data Structures | |
struct | Udma_ChPrms |
UDMA channel open parameters. More... | |
struct | Udma_ChTxPrms |
UDMA TX channel parameters. More... | |
struct | Udma_ChRxPrms |
UDMA RX channel parameters. More... | |
struct | Udma_ChUtcPrms |
UDMA UTC channel parameters. More... | |
struct | Udma_ChPdmaPrms |
UDMA PDMA channel Static TR parameters. More... | |
struct | Udma_ChStats |
UDMA channel statistics. More... | |
struct | Udma_ChHandle |
UDMA channel object. More... | |
Macros | |
#define | UDMA_DMA_CH_INVALID ((uint32_t) 0xFFFF0000U) |
Macro used to specify that DMA Channel ID is invalid. Used in the API Udma_chOpen. More... | |
#define | UDMA_DMA_CH_ANY ((uint32_t) 0xFFFF0001U) |
Macro used to specify any available DMA Channel while requesting one. Used in the API Udma_chOpen. More... | |
#define | UDMA_DMA_CH_NA ((uint32_t) 0xFFFF0002U) |
Macro used to specify that the DMA Channel is not applicable for a particular mode. More... | |
#define | UDMA_UTC_ID_INVALID ((uint32_t) 0xFFFF0003U) |
Macro used to specify that the UTC ID is invalid. More... | |
#define | UDMA_MAPPED_GROUP_INVALID ((uint32_t) 0xFFFF0004U) |
Macro used to specify that the Mapped Channel Group is invalid. More... | |
#define | UDMA_DMSC_EXTENDED_CH_TYPE_BCDMA_BLK_CPY ((uint8_t) 1U) |
DMSC Extended Channel Type Flag for BCDMA Block Copy. More... | |
#define | UDMA_DMSC_EXTENDED_CH_TYPE_BCDMA_SPLIT_TR_TX ((uint8_t) 0U) |
DMSC Extended Channel Type Flag for BCDMA split TR TX channels. More... | |
UDMA PDMA element size | |
int32_t | Udma_chOpen (Udma_DrvHandle drvHandle, Udma_ChHandle chHandle, uint32_t chType, const Udma_ChPrms *chPrms) |
UDMA open channel. More... | |
int32_t | Udma_chClose (Udma_ChHandle chHandle) |
UDMA close channel. More... | |
int32_t | Udma_chConfigTx (Udma_ChHandle chHandle, const Udma_ChTxPrms *txPrms) |
UDMA configure TX channel. More... | |
int32_t | Udma_chConfigRx (Udma_ChHandle chHandle, const Udma_ChRxPrms *rxPrms) |
UDMA configure RX channel. More... | |
int32_t | Udma_chConfigUtc (Udma_ChHandle chHandle, const Udma_ChUtcPrms *utcPrms) |
UDMA configure UTC channel. More... | |
int32_t | Udma_chConfigPdma (Udma_ChHandle chHandle, const Udma_ChPdmaPrms *pdmaPrms) |
UDMA configure PDMA channel (peerChNum as part of Udma_ChPrms) paired with the UDMAP channel. More... | |
int32_t | Udma_chEnable (Udma_ChHandle chHandle) |
UDMA channel enable API. More... | |
int32_t | Udma_chDisable (Udma_ChHandle chHandle, uint32_t timeout) |
UDMA channel teardown and disable API. More... | |
int32_t | Udma_chPause (Udma_ChHandle chHandle) |
UDMA channel pause API. More... | |
int32_t | Udma_chResume (Udma_ChHandle chHandle) |
UDMA channel resume API. More... | |
uint32_t | Udma_chGetNum (Udma_ChHandle chHandle) |
Returns the channel number offset with in a channel type - TX, RX and External (UTC) channel types. More... | |
Udma_RingHandle | Udma_chGetFqRingHandle (Udma_ChHandle chHandle) |
Returns the default free ring handle of the channel. More... | |
Udma_RingHandle | Udma_chGetCqRingHandle (Udma_ChHandle chHandle) |
Returns the default completion ring handle of the channel. More... | |
Udma_RingHandle | Udma_chGetTdCqRingHandle (Udma_ChHandle chHandle) |
Returns the teardown completion ring handle of the channel. More... | |
uint16_t | Udma_chGetFqRingNum (Udma_ChHandle chHandle) |
Returns the default free ring number to be programmed in descriptor. More... | |
uint16_t | Udma_chGetCqRingNum (Udma_ChHandle chHandle) |
Returns the default completion ring number to be programmed in descriptor. More... | |
Udma_FlowHandle | Udma_chGetDefaultFlowHandle (Udma_ChHandle chHandle) |
Returns the default flow handle of the RX channel. More... | |
int32_t | Udma_chDequeueTdResponse (Udma_ChHandle chHandle, CSL_UdmapTdResponse *tdResponse) |
UDMA dequeue response from teardown completion ring. More... | |
uint32_t | Udma_chGetTriggerEvent (Udma_ChHandle chHandle, uint32_t trigger) |
Returns the global trigger event for the channel. More... | |
void * | Udma_chGetSwTriggerRegister (Udma_ChHandle chHandle) |
Returns the software trigger register address for the channel. More... | |
int32_t | Udma_chSetSwTrigger (Udma_ChHandle chHandle, uint32_t trigger) |
Sets the software trigger register based on the trigger mode provided. More... | |
int32_t | Udma_chSetChaining (Udma_ChHandle triggerChHandle, Udma_ChHandle chainedChHandle, uint32_t trigger) |
Chains the trigger channel with the chained channel. More... | |
int32_t | Udma_chBreakChaining (Udma_ChHandle triggerChHandle, Udma_ChHandle chainedChHandle) |
Breaks the chaining by resetting the trigger channel's OES. More... | |
void | UdmaChPrms_init (Udma_ChPrms *chPrms, uint32_t chType) |
Udma_ChPrms structure init function. More... | |
void | UdmaChTxPrms_init (Udma_ChTxPrms *txPrms, uint32_t chType) |
Udma_ChTxPrms structure init function. More... | |
void | UdmaChRxPrms_init (Udma_ChRxPrms *rxPrms, uint32_t chType) |
Udma_ChRxPrms structure init function. More... | |
void | UdmaChUtcPrms_init (Udma_ChUtcPrms *utcPrms) |
Udma_ChUtcPrms structure init function. More... | |
void | UdmaChPdmaPrms_init (Udma_ChPdmaPrms *pdmaPrms) |
Udma_ChPdmaPrms structure init function. More... | |
int32_t | Udma_chGetStats (Udma_ChHandle chHandle, Udma_ChStats *chStats) |
Get real-time channel statistics. More... | |
#define | UDMA_PDMA_ES_8BITS ((uint32_t) 0x00U) |
8-bits Element size More... | |
#define | UDMA_PDMA_ES_16BITS ((uint32_t) 0x01U) |
16-bits Element size More... | |
#define | UDMA_PDMA_ES_24BITS ((uint32_t) 0x02U) |
24-bits Element size More... | |
#define | UDMA_PDMA_ES_32BITS ((uint32_t) 0x03U) |
32-bits Element size More... | |
#define | UDMA_PDMA_ES_64BITS ((uint32_t) 0x04U) |
64-bits Element size More... | |
#define | UDMA_PDMA_ES_DONTCARE ((uint32_t) 0x00U) |
Set this for MCAN element size - not applicable. More... | |
UDMA Channel Flag | |
UDMA channel flags bit field used to form the channel type. | |
#define | UDMA_CH_FLAG_TX ((uint32_t) 0x0001U) |
TX channel flag. More... | |
#define | UDMA_CH_FLAG_RX ((uint32_t) 0x0002U) |
RX channel flag. More... | |
#define | UDMA_CH_FLAG_BLK_COPY ((uint32_t) 0x0004U) |
Block copy mode channel flag. More... | |
#define | UDMA_CH_FLAG_PDMA ((uint32_t) 0x0008U) |
PDMA channel flag. More... | |
#define | UDMA_CH_FLAG_PSIL ((uint32_t) 0x0010U) |
PSIL channel flag meant for periperals like Ethernet, SA2UL. More... | |
#define | UDMA_CH_FLAG_UTC ((uint32_t) 0x0020U) |
UTC channel flag. More... | |
#define | UDMA_CH_FLAG_HC ((uint32_t) 0x0040U) |
High capacity channel flag. More... | |
#define | UDMA_CH_FLAG_UHC ((uint32_t) 0x0080U) |
Ultra high capacity channel flag. More... | |
#define | UDMA_CH_FLAG_MAPPED ((uint32_t) 0x0100U) |
Mapped TX/RX channel flag. More... | |
UDMA Channel Type | |
UDMA channel type formed based on channel flags. | |
#define | UDMA_CH_TYPE_TR_BLK_COPY |
TR block copy type - TX/RX pair. More... | |
#define | UDMA_CH_TYPE_TR_BLK_COPY_HC |
High capacity TR block copy type - TX/RX pair. More... | |
#define | UDMA_CH_TYPE_TR_BLK_COPY_UHC |
Ultra high capacity TR block copy type - TX/RX pair. More... | |
#define | UDMA_CH_TYPE_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL) |
TX channel type. More... | |
#define | UDMA_CH_TYPE_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC) |
High capacity TX channel type. More... | |
#define | UDMA_CH_TYPE_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC) |
Ultra high capacity TX channel type. More... | |
#define | UDMA_CH_TYPE_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL) |
RX channel type. More... | |
#define | UDMA_CH_TYPE_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC) |
High capacity RX channel type. More... | |
#define | UDMA_CH_TYPE_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC) |
Ultra high capacity RX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA) |
PDMA TX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC) |
High capacity PDMA TX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC) |
Ultra high capacity PDMA TX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA) |
PDMA RX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC) |
High capacity PDMA RX channel type. More... | |
#define | UDMA_CH_TYPE_PDMA_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC) |
Ultra high capacity PDMA RX channel type. More... | |
#define | UDMA_CH_TYPE_TX_MAPPED (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED) |
Mapped TX channel. This could be different type of mapped TX channels. See Udma_MappedTxGrpSoc for differnt types of SOC specific mapped TX channels. More... | |
#define | UDMA_CH_TYPE_RX_MAPPED (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED) |
Mapped RX channel. This could be different type of mapped RX channels. See Udma_MappedRxGrpSoc for differnt types of SOC specific mapped RX channels. More... | |
#define | UDMA_CH_TYPE_UTC (UDMA_CH_FLAG_UTC) |
UTC channel. This could be. More... | |
This is UDMA driver channel related configuration parameters and API
#define UDMA_DMA_CH_INVALID ((uint32_t) 0xFFFF0000U) |
Macro used to specify that DMA Channel ID is invalid. Used in the API Udma_chOpen.
#define UDMA_DMA_CH_ANY ((uint32_t) 0xFFFF0001U) |
Macro used to specify any available DMA Channel while requesting one. Used in the API Udma_chOpen.
#define UDMA_DMA_CH_NA ((uint32_t) 0xFFFF0002U) |
Macro used to specify that the DMA Channel is not applicable for a particular mode.
#define UDMA_UTC_ID_INVALID ((uint32_t) 0xFFFF0003U) |
Macro used to specify that the UTC ID is invalid.
#define UDMA_MAPPED_GROUP_INVALID ((uint32_t) 0xFFFF0004U) |
Macro used to specify that the Mapped Channel Group is invalid.
#define UDMA_DMSC_EXTENDED_CH_TYPE_BCDMA_BLK_CPY ((uint8_t) 1U) |
DMSC Extended Channel Type Flag for BCDMA Block Copy.
#define UDMA_DMSC_EXTENDED_CH_TYPE_BCDMA_SPLIT_TR_TX ((uint8_t) 0U) |
DMSC Extended Channel Type Flag for BCDMA split TR TX channels.
#define UDMA_CH_FLAG_TX ((uint32_t) 0x0001U) |
TX channel flag.
#define UDMA_CH_FLAG_RX ((uint32_t) 0x0002U) |
RX channel flag.
#define UDMA_CH_FLAG_BLK_COPY ((uint32_t) 0x0004U) |
Block copy mode channel flag.
#define UDMA_CH_FLAG_PDMA ((uint32_t) 0x0008U) |
PDMA channel flag.
#define UDMA_CH_FLAG_PSIL ((uint32_t) 0x0010U) |
PSIL channel flag meant for periperals like Ethernet, SA2UL.
#define UDMA_CH_FLAG_UTC ((uint32_t) 0x0020U) |
UTC channel flag.
#define UDMA_CH_FLAG_HC ((uint32_t) 0x0040U) |
High capacity channel flag.
#define UDMA_CH_FLAG_UHC ((uint32_t) 0x0080U) |
Ultra high capacity channel flag.
#define UDMA_CH_FLAG_MAPPED ((uint32_t) 0x0100U) |
Mapped TX/RX channel flag.
#define UDMA_CH_TYPE_TR_BLK_COPY |
TR block copy type - TX/RX pair.
#define UDMA_CH_TYPE_TR_BLK_COPY_HC |
High capacity TR block copy type - TX/RX pair.
#define UDMA_CH_TYPE_TR_BLK_COPY_UHC |
Ultra high capacity TR block copy type - TX/RX pair.
#define UDMA_CH_TYPE_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL) |
TX channel type.
#define UDMA_CH_TYPE_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC) |
High capacity TX channel type.
#define UDMA_CH_TYPE_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC) |
Ultra high capacity TX channel type.
#define UDMA_CH_TYPE_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL) |
RX channel type.
#define UDMA_CH_TYPE_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_HC) |
High capacity RX channel type.
#define UDMA_CH_TYPE_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_UHC) |
Ultra high capacity RX channel type.
#define UDMA_CH_TYPE_PDMA_TX (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA) |
PDMA TX channel type.
#define UDMA_CH_TYPE_PDMA_TX_HC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC) |
High capacity PDMA TX channel type.
#define UDMA_CH_TYPE_PDMA_TX_UHC (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC) |
Ultra high capacity PDMA TX channel type.
#define UDMA_CH_TYPE_PDMA_RX (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA) |
PDMA RX channel type.
#define UDMA_CH_TYPE_PDMA_RX_HC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_HC) |
High capacity PDMA RX channel type.
#define UDMA_CH_TYPE_PDMA_RX_UHC (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PDMA | UDMA_CH_FLAG_UHC) |
Ultra high capacity PDMA RX channel type.
#define UDMA_CH_TYPE_TX_MAPPED (UDMA_CH_FLAG_TX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED) |
Mapped TX channel. This could be different type of mapped TX channels. See Udma_MappedTxGrpSoc for differnt types of SOC specific mapped TX channels.
#define UDMA_CH_TYPE_RX_MAPPED (UDMA_CH_FLAG_RX | UDMA_CH_FLAG_PSIL | UDMA_CH_FLAG_MAPPED) |
Mapped RX channel. This could be different type of mapped RX channels. See Udma_MappedRxGrpSoc for differnt types of SOC specific mapped RX channels.
#define UDMA_CH_TYPE_UTC (UDMA_CH_FLAG_UTC) |
UTC channel. This could be.
#define UDMA_PDMA_ES_8BITS ((uint32_t) 0x00U) |
8-bits Element size
#define UDMA_PDMA_ES_16BITS ((uint32_t) 0x01U) |
16-bits Element size
#define UDMA_PDMA_ES_24BITS ((uint32_t) 0x02U) |
24-bits Element size
#define UDMA_PDMA_ES_32BITS ((uint32_t) 0x03U) |
32-bits Element size
#define UDMA_PDMA_ES_64BITS ((uint32_t) 0x04U) |
64-bits Element size
#define UDMA_PDMA_ES_DONTCARE ((uint32_t) 0x00U) |
Set this for MCAN element size - not applicable.
int32_t Udma_chOpen | ( | Udma_DrvHandle | drvHandle, |
Udma_ChHandle | chHandle, | ||
uint32_t | chType, | ||
const Udma_ChPrms * | chPrms | ||
) |
UDMA open channel.
Opens the UDMA channel based on the channel parameters. This also does the PSILCFG pairing based on the peer thread ID provided.
Requirement: DOX_REQ_TAG(PDK-2578)
drvHandle | [IN] UDMA driver handle pointer passed during Udma_init |
chHandle | [IN/OUT] UDMA channel handle. The caller need to allocate memory for this object and pass this pointer to all further APIs. The caller should not change any parameters as this is owned and maintained by the driver. This parameter can't be NULL. |
chType | [IN] UDMA channel type. Refer Udma_ChType. |
chPrms | [IN] UDMA channel parameters. This parameter can't be NULL. |
int32_t Udma_chClose | ( | Udma_ChHandle | chHandle | ) |
UDMA close channel.
Closes the UDMA channel and frees all associated resources.
Requirement: DOX_REQ_TAG(PDK-2579)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
int32_t Udma_chConfigTx | ( | Udma_ChHandle | chHandle, |
const Udma_ChTxPrms * | txPrms | ||
) |
UDMA configure TX channel.
Configures the TX channel parameters. Note: This is applicable only when the channel type is TX
Note: This API can't be called after channel enable.
Requirement: DOX_REQ_TAG(PDK-2580)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
txPrms | [IN] UDMA TX channel parameter. Refer Udma_ChTxPrms. |
int32_t Udma_chConfigRx | ( | Udma_ChHandle | chHandle, |
const Udma_ChRxPrms * | rxPrms | ||
) |
UDMA configure RX channel.
Configures the RX channel parameters. Note: This is applicable only when the channel type is RX In case of BCDMA Block Copy, there is no need to configure RX Channel. Therfore the function returns gracefully, without doing anything.
Note: This API can't be called after channel enable.
Requirement: DOX_REQ_TAG(PDK-2581)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
rxPrms | [IN] UDMA RX channel parameter. Refer Udma_ChRxPrms. |
int32_t Udma_chConfigUtc | ( | Udma_ChHandle | chHandle, |
const Udma_ChUtcPrms * | utcPrms | ||
) |
UDMA configure UTC channel.
Configures the UTC channel parameters. Note: This is applicable only when the channel type is UTC
Note: This API can't be called after channel enable.
Requirement: DOX_REQ_TAG(PDK-2582)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
utcPrms | [IN] UDMA UTC channel parameter. Refer Udma_ChUtcPrms. |
int32_t Udma_chConfigPdma | ( | Udma_ChHandle | chHandle, |
const Udma_ChPdmaPrms * | pdmaPrms | ||
) |
UDMA configure PDMA channel (peerChNum as part of Udma_ChPrms) paired with the UDMAP channel.
This configures the PDMA channel static X,Y,Z parameters.
Requirement: DOX_REQ_TAG(PDK-2583)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
pdmaPrms | [IN] UDMA RX channel parameter. Refer Udma_ChPdmaPrms. |
int32_t Udma_chEnable | ( | Udma_ChHandle | chHandle | ) |
UDMA channel enable API.
This function will enable the UDMA channel.
Requirement: DOX_REQ_TAG(PDK-2584)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
int32_t Udma_chDisable | ( | Udma_ChHandle | chHandle, |
uint32_t | timeout | ||
) |
UDMA channel teardown and disable API.
This function will perform the channel teardown and eventually disables the UDMA channel. This initiates the force teardown sequence based on the channel type and wait for teardown to complete gracefully. If the teardown doesn't complete within the timeout provided, then this will initiate a force teardown sequence.
Caution: This API is blocking. Hence cannot be called from ISR context!!
Requirement: DOX_REQ_TAG(PDK-2585)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
timeout | [IN] Timeout in ms. Use UDMA_WAIT_FOREVER to wait forever. |
int32_t Udma_chPause | ( | Udma_ChHandle | chHandle | ) |
UDMA channel pause API.
This function will pause the UDMA channel by setting the pause bit of the UDMAP runtime register.
Requirement: DOX_REQ_TAG(PDK-2977)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
int32_t Udma_chResume | ( | Udma_ChHandle | chHandle | ) |
UDMA channel resume API.
This function will resume the UDMA channel by clearing the pause bit of the UDMAP runtime register.
Requirement: DOX_REQ_TAG(PDK-2977)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
uint32_t Udma_chGetNum | ( | Udma_ChHandle | chHandle | ) |
Returns the channel number offset with in a channel type - TX, RX and External (UTC) channel types.
In case of UTC type, this returns the relative offset from the start of UTC it belongs to (and not from the external channel start).
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
Udma_RingHandle Udma_chGetFqRingHandle | ( | Udma_ChHandle | chHandle | ) |
Returns the default free ring handle of the channel.
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
Udma_RingHandle Udma_chGetCqRingHandle | ( | Udma_ChHandle | chHandle | ) |
Returns the default completion ring handle of the channel.
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
Udma_RingHandle Udma_chGetTdCqRingHandle | ( | Udma_ChHandle | chHandle | ) |
Returns the teardown completion ring handle of the channel.
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
uint16_t Udma_chGetFqRingNum | ( | Udma_ChHandle | chHandle | ) |
Returns the default free ring number to be programmed in descriptor.
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
uint16_t Udma_chGetCqRingNum | ( | Udma_ChHandle | chHandle | ) |
Returns the default completion ring number to be programmed in descriptor.
Requirement: DOX_REQ_TAG(PDK-2586)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
Udma_FlowHandle Udma_chGetDefaultFlowHandle | ( | Udma_ChHandle | chHandle | ) |
Returns the default flow handle of the RX channel.
Requirement: TODO
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
int32_t Udma_chDequeueTdResponse | ( | Udma_ChHandle | chHandle, |
CSL_UdmapTdResponse * | tdResponse | ||
) |
UDMA dequeue response from teardown completion ring.
This function will pop the response from the teardown completion ring. This is non-blocking and will return timeout error UDMA_ETIMEOUT when the queue is empty. Note: When executing a teardown sequence, the teardown ring should be popped using this API to avoid ring overflow. Note: In case of devices like AM64x where there is no teardown function, this API is not supported and will return error.
Requirement: DOX_REQ_TAG(PDK-2589)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
tdResponse | [OUT] Teardown response received in the ring. |
uint32_t Udma_chGetTriggerEvent | ( | Udma_ChHandle | chHandle, |
uint32_t | trigger | ||
) |
Returns the global trigger event for the channel.
This function will return the appropriate global 0/1 trigger event for the channel.
Notes: Trigger is not supported for external channels and the function will return UDMA_EVENT_INVALID.
Requirement: DOX_REQ_TAG(PDK-2594)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
trigger | [IN] Global0 or Global 1 Trigger - refer CSL_UdmapTrFlagsTrigger |
void* Udma_chGetSwTriggerRegister | ( | Udma_ChHandle | chHandle | ) |
Returns the software trigger register address for the channel.
This function will return the appropriate SW trigger register. Incase of UDMAP channels, it returns the 32-bit TX SWTRIG register address. Incase of DRU channels, it returns the 64-bit DRU CHRT_SWTRIG register address.
Notes: SW trigger is not supported for RX channels. Incase of TX channels, only global trigger 0 is supported. Incase of DRU channels, global trigger 0/1 and local events are supported.
Requirement: DOX_REQ_TAG(PDK-2594)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
int32_t Udma_chSetSwTrigger | ( | Udma_ChHandle | chHandle, |
uint32_t | trigger | ||
) |
Sets the software trigger register based on the trigger mode provided.
This function will set the appropriate SW trigger register. Incase of UDMAP channels, it will set in the TX SWTRIG register. Incase of DRU channels, it will set in the DRU CHRT_SWTRIG register.
Notes: SW trigger is not supported for RX channels. Incase of TX channels, only global trigger 0 is supported. Incase of DRU channels, global trigger 0/1 and local events are supported.
Requirement: DOX_REQ_TAG(PDK-2594)
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
trigger | [IN] Global0 or Global 1 Trigger - refer CSL_UdmapTrFlagsTrigger |
int32_t Udma_chSetChaining | ( | Udma_ChHandle | triggerChHandle, |
Udma_ChHandle | chainedChHandle, | ||
uint32_t | trigger | ||
) |
Chains the trigger channel with the chained channel.
This programs the trigger channel TR event register (OES) to the global trigger (0 or 1) event of the chained channel.
Once this is done, the application should set the TR trigger (0 or 1) of the trigger channel while submitting TR to the trigger channel. Based on the trigger type (full, ICNT0, INCT1, ICNT3), the trigger channel will trigger the "chained" channel through the channel OES.
Note: Only global0 and global1 triggers are supported.
Requirement: TODO
triggerChHandle | [IN] UDMA channel handle which triggers the chain. This parameter can't be NULL. |
chainedChHandle | [IN] UDMA channel handle which gets triggered. This parameter can't be NULL. |
trigger | [IN] Global0 or Global 1 Trigger - refer CSL_UdmapTrFlagsTrigger |
int32_t Udma_chBreakChaining | ( | Udma_ChHandle | triggerChHandle, |
Udma_ChHandle | chainedChHandle | ||
) |
Breaks the chaining by resetting the trigger channel's OES.
Note: Only global0 and global1 triggers are supported.
Requirement: TODO
triggerChHandle | [IN] UDMA channel handle which triggers the chain. This parameter can't be NULL. |
chainedChHandle | [IN] UDMA channel handle which gets triggered. This parameter can't be NULL. |
void UdmaChPrms_init | ( | Udma_ChPrms * | chPrms, |
uint32_t | chType | ||
) |
Udma_ChPrms structure init function.
chPrms | [IN] Pointer to Udma_ChPrms structure. |
chType | [IN] UDMA channel type. Refer Udma_ChType. |
void UdmaChTxPrms_init | ( | Udma_ChTxPrms * | txPrms, |
uint32_t | chType | ||
) |
Udma_ChTxPrms structure init function.
txPrms | [IN] Pointer to Udma_ChTxPrms structure. |
chType | [IN] UDMA channel type. Refer Udma_ChType. |
void UdmaChRxPrms_init | ( | Udma_ChRxPrms * | rxPrms, |
uint32_t | chType | ||
) |
Udma_ChRxPrms structure init function.
rxPrms | [IN] Pointer to Udma_ChRxPrms structure. |
chType | [IN] UDMA channel type. Refer Udma_ChType. |
void UdmaChUtcPrms_init | ( | Udma_ChUtcPrms * | utcPrms | ) |
Udma_ChUtcPrms structure init function.
utcPrms | [IN] Pointer to Udma_ChUtcPrms structure. |
void UdmaChPdmaPrms_init | ( | Udma_ChPdmaPrms * | pdmaPrms | ) |
Udma_ChPdmaPrms structure init function.
pdmaPrms | [IN] Pointer to Udma_ChPdmaPrms structure. |
int32_t Udma_chGetStats | ( | Udma_ChHandle | chHandle, |
Udma_ChStats * | chStats | ||
) |
Get real-time channel statistics.
Requirement: PRSDK-5609
chHandle | [IN] UDMA channel handle. This parameter can't be NULL. |
chStats | [IN] Pointer to Udma_ChStats. This parameter can't be NULL. |
uint32_t Udma_ChPrms::chNum |
[IN] UDMAP channel to allocate.
Set to UDMA_DMA_CH_ANY if the channel to allocate and open could be any from the free pool. Set to the actual DMA channel when specific DMA channel need to be allocated. This channel number is relative to the channel type (TX, RX or External). The driver will internally calculate the respective offset to get the actual UDMAP channel number.
uint32_t Udma_ChPrms::peerChNum |
[IN] The peer channel to link the chNum using PSILCFG.
Incase of PDMA peripherals this represent the PDMA channel to which the UDMA channel should pair with. Refer Udma_PdmaCh macros.
Incase of other PSIL master peripherals this represent the thread ID to which the UDMA channel should pair with. Refer Udma_PsilCh macros.
Incase of Block copy channel type (UDMA_CH_TYPE_TR_BLK_COPY), set this to UDMA_DMA_CH_NA, as the corresponding RX channel (same index as TX channel) is assumed to be paired with and the driver internally sets this up. The UdmaChPrms_init API takes care of this.
Incase of UTC channel type (UDMA_CH_TYPE_UTC), set this to UDMA_DMA_CH_NA.
uint32_t Udma_ChPrms::utcId |
[IN] The UTC instance to use when channel type is UDMA_CH_TYPE_UTC. Refer Udma_UtcIdSoc macro for details.
For other channel type set to UDMA_UTC_ID_INVALID
uint32_t Udma_ChPrms::mappedChGrp |
[IN] The Mapped channel group to use when channel type is UDMA_CH_TYPE_TX_MAPPED or UDMA_CH_TYPE_RX_MAPPED. Refer Udma_MappedTxGrpSoc macro for details about mapped TX channel groups or Udma_MappedRxGrpSoc macro for details about mapped RX channel groups.
For other channel type set to UDMA_MAPPED_GROUP_INVALID
void* Udma_ChPrms::appData |
[IN] Application/caller context pointer passed back in all the channel callback functions. This could be used by the caller to identify the channel for which the callback is called. This can be set to NULL, if not required by caller.
Udma_RingPrms Udma_ChPrms::fqRingPrms |
[IN] Free queue ring params where descriptors are queued
Udma_RingPrms Udma_ChPrms::cqRingPrms |
[IN] Completion queue ring params where descriptors are dequeued This is not used for AM64x kind of devices, but even if the application sets this it will be ignored. But its not required to be set.
Udma_RingPrms Udma_ChPrms::tdCqRingPrms |
[IN] Teardown completion queue ring params where teardown response and TR response incase of direct TR mode are received from UDMA This is not used for AM64x kind of devices, but even if the application sets this it will be ignored. But its not required to be set.
uint8_t Udma_ChTxPrms::pauseOnError |
[IN] Bool: When set (UTRUE), pause channel on error
uint8_t Udma_ChTxPrms::filterEinfo |
[IN] Bool: When set (UTRUE), filter out extended info
uint8_t Udma_ChTxPrms::filterPsWords |
[IN] Bool: When set (UTRUE), filter out protocl specific words
uint8_t Udma_ChTxPrms::addrType |
[IN] Address type for this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype
uint8_t Udma_ChTxPrms::chanType |
[IN] Channel type. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type
uint16_t Udma_ChTxPrms::fetchWordSize |
[IN] Descriptor/TR Size in 32-bit words
uint8_t Udma_ChTxPrms::busPriority |
[IN] 3-bit priority value (0=highest, 7=lowest)
uint8_t Udma_ChTxPrms::busQos |
[IN] 3-bit qos value (0=highest, 7=lowest)
uint8_t Udma_ChTxPrms::busOrderId |
[IN] 4-bit orderid value
uint8_t Udma_ChTxPrms::dmaPriority |
[IN] This field selects which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority
uint8_t Udma_ChTxPrms::txCredit |
[IN] TX credit for external channels
uint16_t Udma_ChTxPrms::fifoDepth |
[IN] The fifo depth is used to specify how many FIFO data phases deep the Tx per channel FIFO will be for the channel. While the maximum depth of the Tx FIFO is set at design time, the FIFO depth can be artificially reduced in order to control the maximum latency which can be introduced due to buffering effects.
The maximum FIFO depth suppported depends on the channel type as given below: Normal Capacity Channel - CSL_NAVSS_UDMAP_TX_CHANS_FDEPTH (128 bytes) High Capacity Channel - CSL_NAVSS_UDMAP_TX_HC_CHANS_FDEPTH (1024 bytes) Ultra High Capacity Channel - CSL_NAVSS_UDMAP_TX_UHC_CHANS_FDEPTH (4096 bytes)
The default init API will set this paramater as per the channel type.
uint8_t Udma_ChTxPrms::burstSize |
[IN] Specifies the nominal burst size and alignment for data transfers on this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size. Note1: This parameter should be set less than or equal to the FIFO depth parameter set for UTC channel i.e. fifoDepth >= burstSize Note2: In case of packet mode TX channels, the Tx fifoDepth must be at least 2 PSI-L data phases (32 bytes) larger than the burst size given in this field in order to hold the packet info and extended packet info header which is placed at the front of the data packet in addition to the payload i.e. fifoDepth >= (burstSize + 32 bytes)
Below are the supported burst sizes for various channel types Normal Capacity Channel - 64 bytes High Capacity Channel - 64, 128 or 256 bytes Ultra High Capacity Channel - 64, 128 or 256 bytes
uint8_t Udma_ChTxPrms::supressTdCqPkt |
[IN] Bool: Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. UFALSE = TD packet is sent UTRUE = Suppress sending TD packet TODO: Should we allocate tdCq based on this flag?
uint8_t Udma_ChRxPrms::pauseOnError |
[IN] Bool: When set (UTRUE), pause channel on error
uint8_t Udma_ChRxPrms::addrType |
[IN] Address type for this channel. Refer tisci_msg_rm_udmap_rx_ch_cfg_req::rx_atype
uint8_t Udma_ChRxPrms::chanType |
[IN] Channel type. Refer tisci_msg_rm_udmap_rx_ch_cfg_req::rx_chan_type
uint16_t Udma_ChRxPrms::fetchWordSize |
[IN] Descriptor/TR Size in 32-bit words
uint8_t Udma_ChRxPrms::busPriority |
[IN] 3-bit priority value (0=highest, 7=lowest)
uint8_t Udma_ChRxPrms::busQos |
[IN] 3-bit qos value (0=highest, 7=lowest)
uint8_t Udma_ChRxPrms::busOrderId |
[IN] 4-bit orderid value
uint8_t Udma_ChRxPrms::dmaPriority |
[IN] This field selects which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. Refer tisci_msg_rm_udmap_rx_ch_cfg_req::rx_sched_priority
uint16_t Udma_ChRxPrms::flowIdFwRangeStart |
[IN] Starting flow ID value for firewall check
uint16_t Udma_ChRxPrms::flowIdFwRangeCnt |
[IN] Number of valid flow ID's starting from flowIdFwRangeStart for firewall check
uint8_t Udma_ChRxPrms::flowEInfoPresent |
[IN] default flow config parameter for EPIB Refer tisci_msg_rm_udmap_flow_cfg_req::rx_einfo_present
uint8_t Udma_ChRxPrms::flowPsInfoPresent |
[IN] default flow config parameter for psInfo Refer tisci_msg_rm_udmap_flow_cfg_req::rx_psinfo_present
uint8_t Udma_ChRxPrms::flowErrorHandling |
[IN] default flow config parameter for Error Handling Refer tisci_msg_rm_udmap_flow_cfg_req::rx_error_handling
uint8_t Udma_ChRxPrms::flowSopOffset |
[IN] default flow config parameter for SOP offset Refer tisci_msg_rm_udmap_flow_cfg_req::rx_sop_offset
uint8_t Udma_ChRxPrms::ignoreShortPkts |
[IN] Bool: This field controls whether or not short packets will be treated as exceptions (UFALSE) or ignored (UTRUE) for the channel. This field is only used when the channel is in split UTC mode.
uint8_t Udma_ChRxPrms::ignoreLongPkts |
[IN] Bool: This field controls whether or not long packets will be treated as exceptions (UFALSE) or ignored (UTRUE) for the channel. This field is only used when the channel is in split UTC mode.
uint32_t Udma_ChRxPrms::configDefaultFlow |
[IN] Bool: This field controls whether or not to program the default flow. UTRUE - Configures the default flow equal to the RX channel number UFALSE - Doesn't configure the default flow of channel. The caller can allocate and use other generic flows or get the default flow handle and configure the flow using Udma_flowConfig API at a later point of time
uint8_t Udma_ChRxPrms::burstSize |
[IN] Specifies the nominal burst size and alignment for data transfers on this channel. Refer tisci_msg_rm_udmap_rx_ch_cfg_req::rx_burst_size. Note1: This parameter should be set less than or equal to the FIFO depth parameter set for UTC channel i.e. fifoDepth >= burstSize Note2: In case of packet mode TX channels, the Tx fifoDepth must be at least 2 PSI-L data phases (32 bytes) larger than the burst size given in this field in order to hold the packet info and extended packet info header which is placed at the front of the data packet in addition to the payload i.e. fifoDepth >= (burstSize + 32 bytes)
Below are the supported burst sizes for various channel types Normal Capacity Channel - 64 bytes High Capacity Channel - 64, 128 or 256 bytes Ultra High Capacity Channel - 64, 128 or 256 bytes
uint8_t Udma_ChUtcPrms::pauseOnError |
[IN] Bool: When set (UTRUE), pause channel on error
uint8_t Udma_ChUtcPrms::addrType |
[IN] Address type for this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_atype
uint8_t Udma_ChUtcPrms::chanType |
[IN] Channel type. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_chan_type
uint16_t Udma_ChUtcPrms::fetchWordSize |
[IN] Descriptor/TR Size in 32-bit words
uint8_t Udma_ChUtcPrms::busPriority |
[IN] 3-bit priority value (0=highest, 7=lowest)
uint8_t Udma_ChUtcPrms::busQos |
[IN] 3-bit qos value (0=highest, 7=lowest)
uint8_t Udma_ChUtcPrms::busOrderId |
[IN] 4-bit orderid value
uint8_t Udma_ChUtcPrms::dmaPriority |
[IN] This field selects which scheduling bin the channel will be placed in for bandwidth allocation of the Tx DMA units. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_sched_priority
uint8_t Udma_ChUtcPrms::burstSize |
[IN] Specifies the nominal burst size and alignment for data transfers on this channel. Refer tisci_msg_rm_udmap_tx_ch_cfg_req::tx_burst_size. Note1: This parameter should be set less than or equal to the FIFO depth parameter set i.e. fifoDepth >= burstSize
Below are the supported burst sizes for various channel types Normal Capacity Channel - 64 or 128 bytes High Capacity Channel - 64, 128 or 256 bytes Ultra High Capacity Channel - 64, 128 or 256 bytes
uint8_t Udma_ChUtcPrms::supressTdCqPkt |
[IN] Bool: Specifies whether or not the channel should suppress sending the single data phase teardown packet when teardown is complete. UFALSE = TD packet is sent UTRUE = Suppress sending TD packet TODO: Should we allocate tdCq based on this flag?
uint32_t Udma_ChPdmaPrms::elemSize |
[IN] Element size. This field specifies how much data is transferred in each write which is performed by the PDMA. This is the X static TR parameter of PDMA.
In case of MCAN TX/RX PDMA channel, this is not used and should be set to 0.
Refer Udma_PdmaElemSize for supported values.
uint32_t Udma_ChPdmaPrms::elemCnt |
[IN] Element count. This field specifies how many elements to transfer each time a trigger is received on the PDMA channel. This is the Y static TR parameter of PDMA.
In case of MCAN PDMA channel, this represents the buffer size. In case of MCAN TX, this field specifies how many bytes should be written to an MCAN TX buffer. This field includes the 8 byte MCAN header on the initial packet fragment. The PDMA will break up the source packet into fragments of this buffer size, copying the 8 byte MCAN header for the initial fragment, and then skipping it for each additional fragment and thus reusing the header from the first fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72. In case of MCAN RX, this field specifies how many bytes should be read from an MCAN RX buffer. This field includes the 8 byte MCAN header on the initial packet fragment. A buffer size less than 16 is treated as 16, and a buffer size greater than 72 is treated as 72.
uint32_t Udma_ChPdmaPrms::fifoCnt |
[IN] FIFO count. This field specifies how many full FIFO operations comprise a complete packet. When the count has been reached, the PDMA will close the packet with an 'EOP' indication. If this parameter is set to 0, then no packet delineation is supplied by the PDMA and all framing is controlled via the UDMA TR.
This is the Z static TR parameter of PDMA. This is NA for TX and should be set to 0. In case of MCAN RX, this represents the buffer count. This field specifies how many MCAN RX buffers should be read before closing the CPPI packet with an 'EOP' indication. When this count is greater than 1, multiple MCAN RX buffers will be read into a single CPPI packet buffer. The 8 byte MCAN header will be skipped on subsequent MCAN buffer reads. Setting this field to NULL will suppress all packet delineation, and should be avoided.
uint32_t Udma_ChStats::packetCnt |
[OUT] Current completed packet count for the channel
uint32_t Udma_ChStats::completedByteCnt |
[OUT] Current completed payload byte count for the channel
uint32_t Udma_ChStats::startedByteCnt |
[OUT] Current started byte count for the channel
uint32_t Udma_ChHandle::chType |
UDMA channel type. Refer Udma_ChType.
Udma_ChPrms Udma_ChHandle::chPrms |
Object to store the channel params.
Udma_DrvHandle Udma_ChHandle::drvHandle |
Pointer to global driver handle.
uint32_t Udma_ChHandle::txChNum |
Allocated TX channel number - this is relative channel number from base TX channel. This is valid only when the channel is opened for TX and block copy mode
uint32_t Udma_ChHandle::rxChNum |
Allocated RX channel number - this is relative channel number from base RX channel. This is valid only when the channel is opened for RX and block copy mode
uint32_t Udma_ChHandle::extChNum |
Allocated Ext channel number - this is relative channel number from base External channel. This is valid only when the channel is opened for UTC mode
uint32_t Udma_ChHandle::pdmaChNum |
Allocated peer PDMA channel number. This is valid only when the channel is opened for PDMA mode
uint32_t Udma_ChHandle::peerThreadId |
Peer channel thread ID - this is or'ed with thread offset.
Udma_RingHandle Udma_ChHandle::fqRing |
Free queue ring handle
Udma_RingHandle Udma_ChHandle::cqRing |
Completion queue ring handle For AM64x kind of devices, where there is no seperate Completion queue, this points to fqRing itself.
Udma_RingHandle Udma_ChHandle::tdCqRing |
Teardown completion queue ring handle
struct Udma_RingObj Udma_ChHandle::fqRingObj |
Free queue ring object
struct Udma_RingObj Udma_ChHandle::cqRingObj |
Completion queue ring object Not used for AM64x kind of devices, where there is no seperate Completion queue.
struct Udma_RingObj Udma_ChHandle::tdCqRingObj |
Teardown completion queue ring object Not used for AM64x kind of devices, where teardown function is not present.
Udma_FlowHandle Udma_ChHandle::defaultFlow |
Default flow handle
struct Udma_FlowObj Udma_ChHandle::defaultFlowObj |
Default flow object - Flow ID equal to the RX channel is reserved as the default flow for the channel. This object is used for providing handle to the caller to re-program the default flow using the standard flow API's
Udma_ChTxPrms Udma_ChHandle::txPrms |
TX channel parameter passed during channel config.
Udma_ChRxPrms Udma_ChHandle::rxPrms |
RX channel parameter passed during channel config.
Udma_ChUtcPrms Udma_ChHandle::utcPrms |
UTC channel parameter passed during channel config.
uint32_t Udma_ChHandle::chInitDone |
Flag to set the channel object is init.
uint32_t Udma_ChHandle::chOesAllocDone |
Flag to check if the channel's OES is allocated. This is required because the channel OES is used for chaining as well as for TR event registeration. This allows to check for error when both are requested by user on the same channel
uint32_t Udma_ChHandle::trigger |
Channel trigger used when chaining channels - needed at the time of breaking the chaining