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file | ipc_soc.h |
| IPC Low Level Driver J784S4 SOC specific file.
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This is IPC documentation specific to J784S4 SoC
◆ IPC_VRING_BUFFER_SIZE
#define IPC_VRING_BUFFER_SIZE (0x3000000U) |
VRing Buffer Size required for all core combinations.
◆ IPC_MPU1_0
Core definitions.
ARM A72 - VM0
◆ IPC_MCU1_0
◆ IPC_MCU1_1
◆ IPC_MCU2_0
◆ IPC_MCU2_1
◆ IPC_MCU3_0
◆ IPC_MCU3_1
◆ IPC_MCU4_0
◆ IPC_MCU4_1
◆ IPC_C7X_1
◆ IPC_C7X_2
◆ IPC_C7X_3
◆ IPC_C7X_4
◆ IPC_MPU1_1
◆ IPC_MAX_PROCS
#define IPC_MAX_PROCS (14U) |
◆ IPC_MAILBOX_CLUSTER_CNT
#define IPC_MAILBOX_CLUSTER_CNT (18U) |
◆ IPC_MAILBOX_USER_CNT
#define IPC_MAILBOX_USER_CNT (4U) |
◆ MAIN_NAVSS_MAILBOX_INPUTINTR_MAX
#define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U) |
◆ MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX
#define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U) |
◆ NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET
#define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (105U) |
◆ NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET (457U) |
◆ NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET (400U) |
◆ NAVSS512_MCU1R5F0_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU1R5F0_INPUT_MAILBOX_VIM_OFFSET (376U) |
◆ NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET (404U) |
◆ NAVSS512_MCU1R5F1_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU1R5F1_INPUT_MAILBOX_VIM_OFFSET (380U) |
◆ NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET (219U) |
◆ NAVSS512_MCU2R5F0_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU2R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET (251U) |
◆ NAVSS512_MCU2R5F1_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU2R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET (283U) |
◆ NAVSS512_MCU3R5F0_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU3R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET (315U) |
◆ NAVSS512_MCU3R5F1_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU3R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_MCU4R5F0_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU4R5F0_INPUT_MAILBOX_OFFSET (347U) |
◆ NAVSS512_MCU4R5F0_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU4R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_MCU4R5F1_INPUT_MAILBOX_OFFSET
#define NAVSS512_MCU4R5F1_INPUT_MAILBOX_OFFSET (379U) |
◆ NAVSS512_MCU4R5F1_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_MCU4R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) |
◆ NAVSS512_C7X1_INPUT_MAILBOX_OFFSET
#define NAVSS512_C7X1_INPUT_MAILBOX_OFFSET (126U) |
◆ NAVSS512_C7X1_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_C7X1_INPUT_MAILBOX_VIM_OFFSET (511U) |
◆ NAVSS512_C7X2_INPUT_MAILBOX_OFFSET
#define NAVSS512_C7X2_INPUT_MAILBOX_OFFSET (147U) |
◆ NAVSS512_C7X2_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_C7X2_INPUT_MAILBOX_VIM_OFFSET (691U) |
◆ NAVSS512_C7X3_INPUT_MAILBOX_OFFSET
#define NAVSS512_C7X3_INPUT_MAILBOX_OFFSET (159U) |
◆ NAVSS512_C7X3_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_C7X3_INPUT_MAILBOX_VIM_OFFSET (703U) |
◆ NAVSS512_C7X4_INPUT_MAILBOX_OFFSET
#define NAVSS512_C7X4_INPUT_MAILBOX_OFFSET (171U) |
◆ NAVSS512_C7X4_INPUT_MAILBOX_VIM_OFFSET
#define NAVSS512_C7X4_INPUT_MAILBOX_VIM_OFFSET (715U) |
◆ IPC_MCU_NAVSS0_INTR0_CFG_BASE
#define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE) |
◆ C7X_CLEC_BASE_ADDR
#define C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE) |
◆ C7X_CLEC_OFFSET
#define C7X_CLEC_OFFSET (1024U - 32U) |
◆ IPC_C7X_MBINTR_OFFSET
#define IPC_C7X_MBINTR_OFFSET (59U) |