PSDK QNX API Guide
ipc_soc.h
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1 /*
2  * Copyright (c) Texas Instruments Incorporated 2022
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
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9  * Redistributions of source code must retain the above copyright
10  * notice, this list of conditions and the following disclaimer.
11  *
12  * Redistributions in binary form must reproduce the above copyright
13  * notice, this list of conditions and the following disclaimer in the
14  * documentation and/or other materials provided with the
15  * distribution.
16  *
17  * Neither the name of Texas Instruments Incorporated nor the names of
18  * its contributors may be used to endorse or promote products derived
19  * from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
47 #ifndef IPC_SOC_V4_H_
48 #define IPC_SOC_V4_H_
49 
51 
52 #ifdef __cplusplus
53 extern "C" {
54 #endif
55 
59 #define IPC_VRING_BUFFER_SIZE (0x3000000U)
60 
62 #define IPC_MPU1_0 (0U)
63 #define IPC_MCU1_0 (1U)
64 #define IPC_MCU1_1 (2U)
65 #define IPC_MCU2_0 (3U)
66 #define IPC_MCU2_1 (4U)
67 #define IPC_MCU3_0 (5U)
68 #define IPC_MCU3_1 (6U)
69 #define IPC_MCU4_0 (7U)
70 #define IPC_MCU4_1 (8U)
71 #define IPC_C7X_1 (9U)
72 #define IPC_C7X_2 (10U)
73 #define IPC_C7X_3 (11U)
74 #define IPC_C7X_4 (12U)
75 #define IPC_MPU1_1 (13U)
76 #define IPC_MAX_PROCS (14U)
78 #define IPC_MAILBOX_CLUSTER_CNT (18U)
79 #define IPC_MAILBOX_USER_CNT (4U)
80 #define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U)
81 #define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U)
82 
83 /* Refer to J784S4 interrupt mapping table and BoardCfg Resource allocation */
84 /* Note: In case of IPC_SUPPORT_SCICLIENT this is not actually used, since
85  * the range is returned from the BoardCfg */
86 #ifndef QNX_OS
87 #define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (105U)
88 #define NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET (457U)
89 #else
90 #define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (91U)
91 #define NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET (475U)
92 #endif
93 #define NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET (400U)
94 #define NAVSS512_MCU1R5F0_INPUT_MAILBOX_VIM_OFFSET (376U)
95 #define NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET (404U)
96 #define NAVSS512_MCU1R5F1_INPUT_MAILBOX_VIM_OFFSET (380U)
97 #define NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET (219U)
98 #define NAVSS512_MCU2R5F0_INPUT_MAILBOX_VIM_OFFSET (251U)
99 #define NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET (251U)
100 #define NAVSS512_MCU2R5F1_INPUT_MAILBOX_VIM_OFFSET (251U)
101 #define NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET (283U)
102 #define NAVSS512_MCU3R5F0_INPUT_MAILBOX_VIM_OFFSET (251U)
103 #define NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET (315U)
104 #define NAVSS512_MCU3R5F1_INPUT_MAILBOX_VIM_OFFSET (251U)
105 #define NAVSS512_MCU4R5F0_INPUT_MAILBOX_OFFSET (347U)
106 #define NAVSS512_MCU4R5F0_INPUT_MAILBOX_VIM_OFFSET (251U)
107 #define NAVSS512_MCU4R5F1_INPUT_MAILBOX_OFFSET (379U)
108 #define NAVSS512_MCU4R5F1_INPUT_MAILBOX_VIM_OFFSET (251U)
109 #define NAVSS512_C7X1_INPUT_MAILBOX_OFFSET (126U)
110 #define NAVSS512_C7X1_INPUT_MAILBOX_VIM_OFFSET (511U)
111 #define NAVSS512_C7X2_INPUT_MAILBOX_OFFSET (147U)
112 #define NAVSS512_C7X2_INPUT_MAILBOX_VIM_OFFSET (691U)
113 #define NAVSS512_C7X3_INPUT_MAILBOX_OFFSET (159U)
114 #define NAVSS512_C7X3_INPUT_MAILBOX_VIM_OFFSET (703U)
115 #define NAVSS512_C7X4_INPUT_MAILBOX_OFFSET (171U)
116 #define NAVSS512_C7X4_INPUT_MAILBOX_VIM_OFFSET (715U)
117 
118 #define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE)
119 
120 /* For C7x, DMSC does not configure or map CLEC router
121  * it must be done by C7x software.
122  */
123 #define C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE)
124 
125 /* CLEC Offset = 992:- soc_events_in #32 is connected to CLEC event #1024 */
126 /* CLEC is shared b/w all C7x cores and the offset can be common.
127  * ClecEvent # will be different for a particular C7x since the
128  * range is returned from BoardCfg based on core specific allocation */
129 #define C7X_CLEC_OFFSET (1024U - 32U)
130 
131 /* User selected IRQ number */
132 /* Start of C7x events associated to CLEC that IPC Driver will manage */
133 /* Events 0 - 15 : left for other drivers, Timer Interrupts etc.
134  * Events 16 - 47 : For routing DRU Local Events from CLEC (done by Vision Apps/TIDL)
135  * Events 48 - 58 : managed by UDMA for routing various UDMA events to C7x
136  * Events 59 - 63 : managed by IPC for routing various Mailbox events to C7x */
137 /* Even though same CLEC is shared b/w two C7x cores, CLEC can broadcast the
138  * event to any C7x core and CPU IRQ is core specific.
139  * Hence same Mailbox Interrupt offset can be used for both C7x cores. */
140 #define IPC_C7X_MBINTR_OFFSET (59U)
141 
142 /* ========================================================================== */
143 /* Include Files */
144 /* ========================================================================== */
145 
146 /* None */
147 
148 
149 /* ========================================================================== */
150 /* Macros & Typedefs */
151 /* ========================================================================== */
152 
153 
154 
155 /* @} */
156 
157 /* ========================================================================== */
158 /* Structure Declarations */
159 /* ========================================================================== */
160 /* None */
161 
162 /* ========================================================================== */
163 /* Function Declarations */
164 /* ========================================================================== */
165 
166 #if defined(BUILD_C7X)
167 uint32_t Ipc_configClecRouter(uint32_t coreEvent, uint32_t coreEventBase);
168 #endif
169 
170 #ifdef IPC_SUPPORT_SCICLIENT
171 int32_t Ipc_sciclientIrqRelease(uint16_t remoteId, uint32_t clusterId,
172  uint32_t userId, uint32_t intNumber);
173 int32_t Ipc_sciclientIrqSet(uint16_t remoteId, uint32_t clusterId,
174  uint32_t userId, uint32_t intNumber);
175 int32_t Ipc_getIntNumRange(uint32_t coreIndex, uint16_t *rangeStartP,
176  uint16_t *rangeNumP);
177 #endif
178 
179 /* ========================================================================== */
180 /* Static Function Definitions */
181 /* ========================================================================== */
182 
183 /* None */
184 
185 #ifdef __cplusplus
186 }
187 #endif
188 
189 #endif /* #ifndef IPC_SOC_V4_H_ */
190 
191 /* @} */
configurations for ipc module.