Brief: Parallel Interface related macro definitions
icss_pin_macros.inc time_macros.inc
Drive the RD_PIN low for RD_HIGH_LOW_TIME period and then make it high again
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
CLR(RD_PIN);
WAIT(RD_HIGH_LOW_TIME);
SET(RD_PIN);
WAIT(RD_HIGH_LOW_TIME);
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 16 data lines mapped to R31[15:0] ENDIAN = MSB => MSB bits are received first and are aligned to higher pin numbers Example: If receiving 10 bits = data[9:0], they should be available on R31[15:6]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 16 data lines mapped to R31[15:0] ENDIAN = LSB => LSB bits are received first and are aligned to lower pin numbers Example: If receiving 10 bits = data[9:0], they should be available on R31[9:0]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 8 data lines mapped to R31[7:0] ENDIAN = MSB => MSB bits are received first and are aligned to higher pin numbers Example: If receiving 4 bits = data[3:0], they should be available on R31[7:4]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 8 data lines mapped to R31[7:0] ENDIAN = LSB => LSB bits are received first and are aligned to lower pin numbers Example: If receiving 4 bits = data[3:0], they should be available on R31[3:0]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 16 data lines mapped to R31[15:0]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
ENDIAN | MSB : MSB Bits are transferred first LSB : LSB Bits are transferred first |
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read a data packet from parallel interface with 8 data lines mapped to R31[7:0]
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
ENDIAN | MSB : MSB Bits are transferred first LSB : LSB Bits are transferred first |
PACKETSIZE | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
RD_PIN | PRU Read Pin to trigger the adc to send data (similar to SCLK) |
Read as data packet from parallel interface with following configurations - INTERFACE, ENDIAN, DATAWIDTH
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
ENDIAN | MSB : MSB Bits are transferred first LSB : LSB Bits are transferred first |
INTERFACE | PARALLEL16 : 16 bit paralllel interface PARALLEL8 : 8 bit paralllel interface |
DATAWIDTH | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |
Read as data frame composed of data packets from parallel interface
PEAK cycles: ~ cycle - depends on configuration
Pseudo code:
data_reg = value;
ENDIAN | MSB : MSB Bits are transferred first LSB : LSB Bits are transferred first |
INTERFACE | PARALLEL16 : 16 bit paralllel interface PARALLEL8 : 8 bit paralllel interface |
DATAWIDTH | 1 to 32 |
RD_HIGH_LOW_TIME | Period to wait, in ns, after setting control (CS, RD) pins |
data_reg | Register to store read data packet (32 bit) |