Strucutre to store temporary registers for the Pru Ipc Instance
6 bytes
bufferBaseAddr | Stores base address for buffer buffers |
bufferOffset | Stores memory offset for TMP.bufferBaseAddr |
Initialization code when the Pru Ipc is started
PEAK cycles: 11 cycle
None
Pseudo code:
memcpy(offset(dataSize), PRU_IPC_CONFIG_MEM + DATASIZE_OFFSET, 1);
memcpy(offset(CFG.blockSize), PRU_IPC_CONFIG_MEM + BLOCKSIZE_OFFSET, 4);
ITR = 0;
dataSize | Size of the data packets (must dataSize = bx) |
baseMemAddr | register for storing BASE_MEM_ADDR in |
BASE_MEM_ADDR | Base addr of config memory Returns: None |
Sends the data packets to the shared memory for each Buffer Creates interrupt event for r5f core to read data packets.
PEAK cycles: (15 + 10*noOfBuffers) cycle
None
Pseudo code:
for (ITR.buffer = 0, TMP.bufferOffset = BUFFERBASE_OFFSET;
ITR.buffer < CFG.noOfBuffers;
ITR.buffer++, TMP.bufferOffset+=4) {
dataReg = *dataRegBaseAddr++;
memcpy(offset(TMP.bufferBaseAddr), PRU_IPC_CONFIG_MEM + TMP.bufferOffset, 4);
if (TMP.bufferBaseAddr == 0) continue;
memcpy(offset(dataReg), TMP.bufferBaseAddr + ITR.packet, dataSize);
}
ITR.packet += dataSize;
ITR.idxInBlock++;
if (ITR.idxInBlock == CFG.blockSize) {
memcpy(offset(ITR.block), PRU_IPC_CONFIG_MEM + BLOCKID_OFFSET, 1);
r31.b0 = INT_NUM; // generate interrupt
ITR.idxInBlock = 0;
ITR.block++;
if (ITR.block == CFG.noOfBlocks) {
ITR.block = 0
ITR.packet = 0
}
}
dataRegBaseAddr | (8 bits) Address of starting ADC data register (&ADC_DATA_REG_1) {ADC_DATA_REG_1, ADC_DATA_REG_2, .... ADC_DATA_REG_N} => register R1.bx must be used |
dataReg | Data stored in ADC_DATA_REG_X, Can pass ADC_DATA_REG_0 |
dataSize | Size of the data packets (must dataSize = bx) |
INTR_ENABLE | Enable interrupt trigger to specified event |
INTR_NUM | Interrupt value to write to R31 to trigger interrupt event |
None
Receives the data packets from the shared memory for each Buffer Handles interrupt event from r5f core, to read data packets.
PEAK cycles: (15 + 10*noOfBuffers) cycle
None
Pseudo code:
for (ITR.buffer = 0, TMP.bufferOffset = BUFFERBASE_OFFSET;
ITR.buffer < CFG.noOfBuffers;
ITR.buffer++, TMP.bufferOffset+=4) {
dataReg = *dataRegBaseAddr++;
memcpy(offset(TMP.bufferBaseAddr), PRU_IPC_CONFIG_MEM + TMP.bufferOffset, 4);
if (TMP.bufferBaseAddr == 0) continue;
memcpy(TMP.bufferBaseAddr + ITR.packet, offset(dataReg), dataSize);
}
ITR.packet += dataSize;
ITR.idxInBlock++;
if (ITR.idxInBlock == CFG.blockSize) {
memcpy(offset(ITR.block), PRU_IPC_CONFIG_MEM + BLOCKID_OFFSET, 1);
r31.b0 = INT_NUM; // generate interrupt
ITR.idxInBlock = 0;
ITR.block++;
if (ITR.block == CFG.noOfBlocks) {
ITR.block = 0
ITR.packet = 0
}
}
dataRegBaseAddr | (8 bits) Address of starting ADC data register (&ADC_DATA_REG_1) {ADC_DATA_REG_1, ADC_DATA_REG_2, .... ADC_DATA_REG_N} => register R1.bx must be used |
dataReg | Data stored in ADC_DATA_REG_X, Can pass ADC_DATA_REG_0 |
dataSize | Size of the data packets (must dataSize = bx) |
INTR_ENABLE | Enable interrupt trigger to specified event |
EVENT_NUM | Event number value on which interrupt will be generated |
None