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PSDK QNX API Guide
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Go to the documentation of this file. 44 #ifndef SCICLIENT_FMWMSGPARAMS_H_ 45 #define SCICLIENT_FMWMSGPARAMS_H_ 52 #include <ti/csl/soc.h> 63 #define TISCI_PARAM_UNDEF (0xFFFFFFFFU) 73 #define SCICLIENT_FIRMWARE_ABI_MAJOR (3U) 78 #define SCICLIENT_FIRMWARE_ABI_MINOR (1U) 88 #define SCICLIENT_CONTEXT_R5_NONSEC_0 (0U) 90 #define SCICLIENT_CONTEXT_R5_SEC_0 (1U) 92 #define SCICLIENT_CONTEXT_R5_NONSEC_1 (2U) 94 #define SCICLIENT_CONTEXT_R5_SEC_1 (3U) 96 #define SCICLIENT_CONTEXT_A72_SEC_0 (4U) 98 #define SCICLIENT_CONTEXT_A72_SEC_1 (5U) 100 #define SCICLIENT_CONTEXT_A72_NONSEC_0 (6U) 102 #define SCICLIENT_CONTEXT_A72_NONSEC_1 (7U) 104 #define SCICLIENT_CONTEXT_A72_NONSEC_2 (8U) 106 #define SCICLIENT_CONTEXT_A72_NONSEC_3 (9U) 108 #define SCICLIENT_CONTEXT_A72_NONSEC_4 (10U) 110 #define SCICLIENT_CONTEXT_A72_NONSEC_5 (11U) 112 #define SCICLIENT_CONTEXT_C7X_SEC_0 (12U) 114 #define SCICLIENT_CONTEXT_C7X_NONSEC_0 (13U) 116 #define SCICLIENT_CONTEXT_C7X_SEC_1 (14U) 118 #define SCICLIENT_CONTEXT_C7X_NONSEC_1 (15U) 120 #define SCICLIENT_CONTEXT_C7X_SEC_2 (16U) 122 #define SCICLIENT_CONTEXT_C7X_NONSEC_2 (17U) 124 #define SCICLIENT_CONTEXT_C7X_SEC_3 (18U) 126 #define SCICLIENT_CONTEXT_C7X_NONSEC_3 (19U) 128 #define SCICLIENT_CONTEXT_GPU_NONSEC_0 (20U) 130 #define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_0 (21U) 132 #define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_0 (22U) 134 #define SCICLIENT_CONTEXT_MAIN_0_R5_NONSEC_1 (23U) 136 #define SCICLIENT_CONTEXT_MAIN_0_R5_SEC_1 (24U) 138 #define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_0 (25U) 140 #define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_0 (26U) 142 #define SCICLIENT_CONTEXT_MAIN_1_R5_NONSEC_1 (27U) 144 #define SCICLIENT_CONTEXT_MAIN_1_R5_SEC_1 (28U) 146 #define SCICLIENT_CONTEXT_MAIN_2_R5_NONSEC_0 (29U) 148 #define SCICLIENT_CONTEXT_MAIN_2_R5_SEC_0 (30U) 150 #define SCICLIENT_CONTEXT_MAIN_2_R5_NONSEC_1 (31U) 152 #define SCICLIENT_CONTEXT_MAIN_2_R5_SEC_1 (32U) 154 #define SCICLIENT_CONTEXT_MAX_NUM (33U) 166 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE0_0 (0x20U) 171 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE1_0 (0x21U) 176 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE2_0 (0x22U) 181 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS0_CORE3_0 (0x23U) 186 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE0_0 (0x24U) 191 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE1_0 (0x25U) 196 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE2_0 (0x26U) 201 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_A72SS1_CORE3_0 (0x27U) 206 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS0_CORE0_0 (0x30U) 211 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS1_CORE0_0 (0x31U) 216 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS2_CORE0_0 (0x32U) 221 #define SCICLIENT_PROC_ID_COMPUTE_CLUSTER_J7AHP0_C71SS3_CORE0_0 (0x33U) 226 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0 (0x01U) 231 #define SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1 (0x02U) 236 #define SCICLIENT_PROC_ID_R5FSS0_CORE0 (0x06U) 241 #define SCICLIENT_PROC_ID_R5FSS0_CORE1 (0x07U) 246 #define SCICLIENT_PROC_ID_R5FSS1_CORE0 (0x08U) 251 #define SCICLIENT_PROC_ID_R5FSS1_CORE1 (0x09U) 256 #define SCICLIENT_PROC_ID_R5FSS2_CORE0 (0x0AU) 261 #define SCICLIENT_PROC_ID_R5FSS2_CORE1 (0x0BU) 266 #define SCICLIENT_PROC_ID_WKUP_HSM0 (0x80U) 271 #define SCICLIENT_SOC_NUM_PROCESSORS (0x15U) 279 #define TISCI_MSG_VALUE_RM_NULL_RING_TYPE (0xFFFFu) 283 #define TISCI_MSG_VALUE_RM_NULL_RING_INDEX (0xFFFFFFFFu) 290 #define TISCI_MSG_VALUE_RM_NULL_RING_ADDR (0xFFFFFFFFu) 296 #define TISCI_MSG_VALUE_RM_NULL_RING_COUNT (0xFFFFFFFFu) 302 #define TISCI_MSG_VALUE_RM_NULL_RING_MODE (0xFFu) 308 #define TISCI_MSG_VALUE_RM_NULL_RING_SIZE (0xFFu) 313 #define TISCI_MSG_VALUE_RM_NULL_ORDER_ID (0xFFu) 321 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_TYPE (0xFFu) 328 #define TISCI_MSG_VALUE_RM_UDMAP_NULL_CH_INDEX (0xFFFFFFFFu) 337 #include <ti/drv/sciclient/soc/sysfw/include/j784s4/tisci_devices.h> 346 #include <ti/drv/sciclient/soc/sysfw/include/j784s4/tisci_clocks.h> 352 #define TISCI_ISC_CC_ID (160U) 360 #define TISCI_RINGACC0_OES_IRQ_SRC_IDX_START (0U) 361 #define TISCI_RINGACC0_MON_IRQ_SRC_IDX_START (1024U) 362 #define TISCI_RINGACC0_EOES_IRQ_SRC_IDX_START (2048U) 363 #define TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START (0U) 364 #define TISCI_UDMAP0_TX_EOES_IRQ_SRC_IDX_START (512U) 365 #define TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START (1024U) 366 #define TISCI_UDMAP0_RX_EOES_IRQ_SRC_IDX_START (1152U) 367 #define TISCI_UDMAP0_RX_FLOW_EOES_IRQ_SRC_IDX_START (1280U) 368 #define TISCI_BCDMA0_BC_EOES_IRQ_SRC_IDX_START (0U) 369 #define TISCI_BCDMA0_BC_DC_OES_IRQ_SRC_IDX_START (512U) 370 #define TISCI_BCDMA0_BC_RC_OES_IRQ_SRC_IDX_START (1024U) 371 #define TISCI_BCDMA0_TX_EOES_IRQ_SRC_IDX_START (1536U) 372 #define TISCI_BCDMA0_TX_DC_OES_IRQ_SRC_IDX_START (2048U) 373 #define TISCI_BCDMA0_TX_RC_OES_IRQ_SRC_IDX_START (2560U) 374 #define TISCI_BCDMA0_RX_EOES_IRQ_SRC_IDX_START (3072U) 375 #define TISCI_BCDMA0_RX_DC_OES_IRQ_SRC_IDX_START (3584U) 376 #define TISCI_BCDMA0_RX_RC_OES_IRQ_SRC_IDX_START (4096U) 379 #define SCICLIENT_C7X_NON_SECURE_INTERRUPT_NUM (9U) 380 #define SCICLIENT_C7X_SECURE_INTERRUPT_NUM (10U) 381 #define SCICLIENT_C7X_0_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_177) 382 #define SCICLIENT_C7X_0_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_179) 383 #define SCICLIENT_C7X_1_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_181) 384 #define SCICLIENT_C7X_1_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_183) 385 #define SCICLIENT_C7X_2_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_185) 386 #define SCICLIENT_C7X_2_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_187) 387 #define SCICLIENT_C7X_3_0_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_189) 388 #define SCICLIENT_C7X_3_1_CLEC_EVENT_IN (CSLR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_IN_NAVSS0_INTR_0_OUTL_INTR_191) 396 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0 (TISCI_DEV_MCU_R5FSS0_CORE0) 397 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1 (TISCI_DEV_MCU_R5FSS0_CORE1) 406 #define SCICLIENT_DEV_MCU_R5FSS0_CORE0_PROCID \ 407 (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE0) 408 #define SCICLIENT_DEV_MCU_R5FSS0_CORE1_PROCID \ 409 (SCICLIENT_PROC_ID_MCU_R5FSS0_CORE1) 413 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_START (CSL_MCU_MSRAM_1MB0_RAM_BASE) 415 #define SCICLIENT_ALLOWED_BOARDCFG_BASE_END (CSL_MCU_MSRAM_1MB0_RAM_BASE + CSL_MCU_MSRAM_1MB0_RAM_SIZE)