59 #define IPC_VRING_BUFFER_SIZE (0x3000000U) 62 #define IPC_MPU1_0 (0U) 63 #define IPC_MCU1_0 (1U) 64 #define IPC_MCU1_1 (2U) 65 #define IPC_MCU2_0 (3U) 66 #define IPC_MCU2_1 (4U) 67 #define IPC_MCU3_0 (5U) 68 #define IPC_MCU3_1 (6U) 69 #define IPC_MCU4_0 (7U) 70 #define IPC_MCU4_1 (8U) 71 #define IPC_C7X_1 (9U) 72 #define IPC_C7X_2 (10U) 73 #define IPC_C7X_3 (11U) 74 #define IPC_C7X_4 (12U) 75 #define IPC_MPU1_1 (13U) 76 #define IPC_MAX_PROCS (14U) 78 #define IPC_MAILBOX_CLUSTER_CNT (18U) 79 #define IPC_MAILBOX_USER_CNT (4U) 80 #define MAIN_NAVSS_MAILBOX_INPUTINTR_MAX (440U) 81 #define MAIN_NAVSS_MAILBOX_OUTPUTINTR_MAX (512U) 87 #define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (105U) 88 #define NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET (457U) 90 #define NAVSS512_MPU1_0_INPUT_MAILBOX_OFFSET (91U) 91 #define NAVSS512_MPU1_0_INPUT_MAILBOX_VIM_OFFSET (475U) 93 #define NAVSS512_MCU1R5F0_INPUT_MAILBOX_OFFSET (400U) 94 #define NAVSS512_MCU1R5F0_INPUT_MAILBOX_VIM_OFFSET (376U) 95 #define NAVSS512_MCU1R5F1_INPUT_MAILBOX_OFFSET (404U) 96 #define NAVSS512_MCU1R5F1_INPUT_MAILBOX_VIM_OFFSET (380U) 97 #define NAVSS512_MCU2R5F0_INPUT_MAILBOX_OFFSET (219U) 98 #define NAVSS512_MCU2R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) 99 #define NAVSS512_MCU2R5F1_INPUT_MAILBOX_OFFSET (251U) 100 #define NAVSS512_MCU2R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) 101 #define NAVSS512_MCU3R5F0_INPUT_MAILBOX_OFFSET (283U) 102 #define NAVSS512_MCU3R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) 103 #define NAVSS512_MCU3R5F1_INPUT_MAILBOX_OFFSET (315U) 104 #define NAVSS512_MCU3R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) 105 #define NAVSS512_MCU4R5F0_INPUT_MAILBOX_OFFSET (347U) 106 #define NAVSS512_MCU4R5F0_INPUT_MAILBOX_VIM_OFFSET (251U) 107 #define NAVSS512_MCU4R5F1_INPUT_MAILBOX_OFFSET (379U) 108 #define NAVSS512_MCU4R5F1_INPUT_MAILBOX_VIM_OFFSET (251U) 109 #define NAVSS512_C7X1_INPUT_MAILBOX_OFFSET (126U) 110 #define NAVSS512_C7X1_INPUT_MAILBOX_VIM_OFFSET (511U) 111 #define NAVSS512_C7X2_INPUT_MAILBOX_OFFSET (147U) 112 #define NAVSS512_C7X2_INPUT_MAILBOX_VIM_OFFSET (691U) 113 #define NAVSS512_C7X3_INPUT_MAILBOX_OFFSET (159U) 114 #define NAVSS512_C7X3_INPUT_MAILBOX_VIM_OFFSET (703U) 115 #define NAVSS512_C7X4_INPUT_MAILBOX_OFFSET (171U) 116 #define NAVSS512_C7X4_INPUT_MAILBOX_VIM_OFFSET (715U) 118 #define IPC_MCU_NAVSS0_INTR0_CFG_BASE (CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE) 123 #define C7X_CLEC_BASE_ADDR (CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE) 129 #define C7X_CLEC_OFFSET (1024U - 32U) 140 #define IPC_C7X_MBINTR_OFFSET (59U) 166 #if defined(BUILD_C7X) 167 uint32_t Ipc_configClecRouter(uint32_t coreEvent, uint32_t coreEventBase);
170 #ifdef IPC_SUPPORT_SCICLIENT 171 int32_t Ipc_sciclientIrqRelease(uint16_t remoteId, uint32_t clusterId,
172 uint32_t userId, uint32_t intNumber);
173 int32_t Ipc_sciclientIrqSet(uint16_t remoteId, uint32_t clusterId,
174 uint32_t userId, uint32_t intNumber);
175 int32_t Ipc_getIntNumRange(uint32_t coreIndex, uint16_t *rangeStartP,
176 uint16_t *rangeNumP);
configurations for ipc module.