![]() |
![]() |
Jacinto 7 SoC (System on Chip) from Texas Instruments is targeted to address various ADAS (Advanced Driver Assistance Systems), In-Vehicle Infotainment (IVI) and Gateway markets. These devices are intended to be used in surround view systems, radar systems, vehicle compute, gateway (CAN to Ethernet, Ethernet to Ethernet), firewall and packet filtering use-cases.
Jacinto 7 family devices offer networking functionality through the Gigabit Ethernet MAC (MCU_CPSW0) and the Gigabit Ethernet Switch (CPSW0) subsystems. They provide Ethernet packet communication between the connected port(s) and the System on Chip. The total number of ports include host port which is an internal port providing the packet streaming interface to the device internal cores. The external ports are MAC ports supporting Media Independent Interface (MII) like MII, Gigabit Media Independent Interface (GMII), Reduced Media Independent Interface (RMII), Reduced Gigabit Media Independent Interface (RGMII), Serial Gigabit Media Independent Interface (SGMII) and Quad Serial Gigabit Media Independent Interface (QSGMII). The MII modes supported vary based on device variant.
MCU_CPSW0 is a two-port CPSW switch instance: one MAC port and a CPPI DMA host port. It's commonly referred to as CPSW2G.
CPSW0 is an integrated Ethernet switch IP with nine-port: eight MAC ports and a CPPI DMA host port. This CPSW instance is referred to as CPSW9G throughout most documentation and code. The CPSW9G switch facilitates the transfer of data between external ports along with internal traffic. Any core of Jacinto 7 devices can transmit/receive data to/from the switch.
CPSW9G is a shared resource and the Ethernet Switch Firmware is the software running on Main domain R5F of Jacinto 7, used for configuration, coordination and management of CPSW9G resources between internal processing cores and external ports. The Ethernet Switch Firmware software is mainly based on the PDK CPSW low-level driver (CPSW LLD), but also relies on other PDK drivers like UDMA for data transfers to the internal processing cores.
The diagram below show the comparison of a typical automotive system using an external switch and an MCU, with a similar system on Jacinto 7 with integrated Ethernet switch.
The diagram below shows the overall software architecture of the CPSW low-level driver. A top-level driver layer provides the interface that the applications can use to configure the switch and to send/receive Ethernet frames. The CPSW driver consists of several software submodules that mirror those of the CPSW hardware, like DMA, ALE, MAC port, host port, MDIO, etc. Additionally, the CPSW driver also includes PHY driver support as well as a resource manager to administrate the CPSW resources.
CPSW LLD relies on other PDK drivers like UDMA for data transfer to/from the CPSW host port to the other processing cores inside the Jacinto 7 devices. For the lower level access to the CPSW hardware register, the CPSW LLD relies on the Chip Support Library (CSL).
CPSW LLD comes with a set of examples demonstrating the usage of driver APIs. The examples are:
cpsw_loopback_test
: Internal (MAC port) or external loopback test.cpsw_nimu_example
: TCP/IP stack integration using TI NDK package.This example exercises the MAC loopback functionality of the hardware. The example is developed and tested on both bare metal and TI RTOS code base. The CPSW9G hardware is opened with default initialization parameters and the MAC loopback is enabled.
A Tx channel and a Rx flow are opened to enable data transfers. Packets are transmitted from the Switch R5F (Main R5F0_0) to the host port using the Tx channel. These packets are routed back to the host port by the switch hardware as the internal loopback feature is enabled. These packets are then transmitted to the Switch R5F by the Rx flow and the application is notified.
The Tx and Rx functions in the example are set to transmit and receive 10000 packets. After reaching the count of 10000, the application closes the Tx channel, Rx flow, CPSW and restarts the application for a configurable number of times. Restarting the loopback test application ensures that there aren’t any memory leaks, and the hardware is closed properly and can be reopened any time.
The Network Developer's Kit (NDK) is a platform for development and demonstration of network enabled applications on TI embedded processors. The NDK stack serves as a rapid prototyping platform for the development of network and packet processing applications. It can be used to add network connectivity to existing applications for communications, configuration, and control. Using the components provided in the NDK, developers can quickly move from development concepts to working implementations attached to the network.
Network Interface Management Unit (NIMU) acts as an intermediate layer between the CPSW LLD and the TI-NDK (NDK is TI’s TCP/IP stack with http server, telnet support, etc).
The NIMU example uses the NIMU layer present in the CPSW LLD and gets an IP address using the NDK stack and opens transmit and receive ports.
The send and receive functionalities of CPSW can be tested using the tools provided in NDK Winapps as follows:
cd ndk_<version>/packages/ti/ndk/winapps/ ./send.x86U <IP address>
cd ndk_<version>/packages/ti/ndk/winapps/ ./recv.x86U <IP address>
Where IP address
refers to the address of the Jacinto 7 processing core running the example, R5F or A72.
The CPSW LLD APIs can be broadly divided into two categories: control and data path. The control APIs can be used to configure all CPSW hardware submodules like ALE, MAC port, host port, MDIO, statistics, as well as PHY drivers and CPSW resource management. The data path APIs are exclusive for the UDMA-based data transfers between the Jacinto 7 processing cores and the CPSW peripheral.
The main APIs of the CPSW LLD are the following:
It's worth noting that the control path APIs are mainly IOCTL-based, and the data path APIs are direct functions in order to avoid any additional overhead associated with IOCTL calls as DMA data operations occur highly frequently.
IOCTLs are system calls that take an argument specifying the command code and can take none or additional parameters via Cpsw_IoctlPrms argument. IOCTL are used by all CPSW submodules except for DMA.
The Cpsw_IoctlPrms parameter structure consists of input and output argument pointers and their corresponding size. The following helper macros are provided to help construct the IOCTL params:
where prms
in a pointer to Cpsw_IoctlPrms variable, in
is the pointer to IOCTL input argument and out
is the pointer to IOCTL output argument.
Please refer to the individual IOCTL command to find out if it requires input and/or output parameters.
Developers who wish to add network connectivity to the applications running on Jacinto 7 SoC, will have to integrate CPSW LLD by following the below sequence.
Cpsw_Config structure includes configuration of various CPSW submodules as follows:
These parameters can be changed as needed for the application.
utilsPrms.printFxn = UART_printf; utilsPrms.traceFxn = UART_printf; utilsPrms.phyToVirtFxn = &CpswAppUtils_phyToVirtFxn; utilsPrms.virtToPhyFxn = &CpswAppUtils_virtToPhyFxn;
Cpsw_init(cpswType, &osalPrms, &utilsPrms);
CpswAppMemUtils
to take care of all memory allocation and freeing operations. The developer can take this as reference or can implement their own memory allocation functions.Forward
state using CPSW_ALE_IOCTL_SET_PORT_STATE IOCTL command.A template file to integrate NDK in an application is added into cpsw/docs/main_tirtos_template.c
, the developer can take this as reference.