Introduction
This example configures EPWM0/1/2 to generate symmetrical, Active-High Complementary (AHC) outputs using EPWM channels A and B:
- EPWM0/1/2 are synchronized using the daisy-chain connectivity between the EPWM modules. A Software Forced Synchronized Pulse is used at example initialization to simulate a hardware synchronization signal.
- The Duty Cycle for each EPWM output signal is updated every EPWM period via writes to the CMPA shadow registers in the EPWM ISR, where the Duty Cycle values are proportional to sinusoidal values computed in the ISR.
- The EPWMs are configured in Up-Down count mode to generate symmetrical outputs. The Deadband submodule is used to generate AHC outputs, where the channel A input is the source for both the rising-edge and falling-edge delays.
The following parameters are configurable at compile-time:
- EPWM output frequency: 4,8, or 16 kHz
- Initial Duty Cycle: 0.0 to 100.0 percent of EPWM period
- Time Base Phase on Sync In event: 0.0 to 100.0 percent of 1/2 EPWM period
- Deadband Rising Edge and Falling Edge delay
- Amplitude & frequency of sinusoids
- Duration of example execution
The following EPWM features are unused in this example:
- Chopper submodule
- Trip Zone submodule
- Event-Trigger submodule interrupt prescaling (every EPWM0 TBCNT=0 event triggers an interrupt)
AM62LX-EVM
- This example uses the user expansion connector (J2) in the board for testing on AM62LX-SK.
- All pin numbers are on the expansion connector in the board.
- The pins configured for the example is enabled on user expansion connector based on the FET selection switch(FET_SEL0).
- The SOC_VOUT0_DATAn are the input to FET switches. The pins that are configured for the example are pinmuxed with the FET switches.
- The S0 select pin decides if the configured pins (which is pinmuxed with SOC_VOUT0_DATAn) map to HDMI or USER EXP connector.
- The S0 pin is triggered to a high value in the software. When the S0 is high, the pin that is configured for the example (which is pinmuxed with SOC_VOUT0_DATAn) will be available on the user expansion connector.
The below diagram depicts the selection:
S2 | S1 | S0 | IP(nA)/OP(nB1 (Or) nB2) |
H | H | L | nA=nB1 -> SOC - HDMI |
H | H | H | nA=nB2 -> SOC - GPIO EXP CONN |
The table below shows the jumper pins where the EPWM outputs can be observed.
A debug GPIO is driven in the EPWM ISR to show the EPWM period timing. The GPIO output can be observed on the pins (below mentioned) of User Expansion Connector (J2) in the board.
EPWM | EPWM Signal | Pin Details |
0 | EPWM0_A | G22/GPIO0_28 (Pin_18) |
0 | EPWM0_B | F22/GPIO0_29 (Pin_7) |
1 | EPWM1_A | F23/GPIO0_30 (Pin_10) |
1 | EPWM1_B | L21/GPIO0_31 (Pin_5) |
Supported Combinations
Parameter | Value |
CPU + OS | a53ss0-0 nortos |
a53ss0-0 freertos |
Toolchain | arm.gnu.aarch64-none |
Board | am62lx-evm |
Example folder | examples/drivers/epwm/epwm_duty_cycle_sync/ |
Steps to Run the Example
See Also
EPWM
Sample Output
Shown below is a sample output when the application is run.
EPWM Duty Cycle Sync Test Started ...
Please refer to the EXAMPLES_DRIVERS_EPWM_DUTY_CYCLE_SYNC example user guide for the test setup to probe the EPWM signals.
App will wait for 60 seconds (using PWM period ISR) ...
EPWM Duty Cycle Sync Test Passed!!
All tests have passed!!