AM62Px MCU+ SDK  11.01.00
uart/v0/uart.h
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1 /*
2  * Copyright (C) 2021-2023 Texas Instruments Incorporated
3  *
4  * Redistribution and use in source and binary forms, with or without
5  * modification, are permitted provided that the following conditions
6  * are met:
7  *
8  * Redistributions of source code must retain the above copyright
9  * notice, this list of conditions and the following disclaimer.
10  *
11  * Redistributions in binary form must reproduce the above copyright
12  * notice, this list of conditions and the following disclaimer in the
13  * documentation and/or other materials provided with the
14  * distribution.
15  *
16  * Neither the name of Texas Instruments Incorporated nor the names of
17  * its contributors may be used to endorse or promote products derived
18  * from this software without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
48 #ifndef UART_V0_H_
49 #define UART_V0_H_
50 
51 /* ========================================================================== */
52 /* Include Files */
53 /* ========================================================================== */
54 
55 #include <stdint.h>
56 #include <kernel/dpl/SystemP.h>
57 #include <kernel/dpl/SemaphoreP.h>
58 #include <kernel/dpl/HwiP.h>
59 #include <drivers/hw_include/cslr.h>
60 #include <drivers/hw_include/cslr_uart.h>
61 #include <drivers/hw_include/hw_types.h>
62 
63 #ifdef __cplusplus
64 extern "C" {
65 #endif
66 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define UART_FIFO_SIZE (64U)
73 
79 #define UART_TRANSMITEMPTY_TRIALCOUNT (3000U)
80 
82 #define UART_ERROR_COUNT (0x00FFFFFFU)
83 
85 typedef void *UART_Handle;
86 
96 #define UART_TRANSFER_STATUS_SUCCESS (0U)
97 
98 #define UART_TRANSFER_STATUS_TIMEOUT (1U)
99 
100 #define UART_TRANSFER_STATUS_ERROR_BI (2U)
101 
102 #define UART_TRANSFER_STATUS_ERROR_FE (3U)
103 
104 #define UART_TRANSFER_STATUS_ERROR_PE (4U)
105 
106 #define UART_TRANSFER_STATUS_ERROR_OE (5U)
107 
108 #define UART_TRANSFER_STATUS_CANCELLED (6U)
109 
110 #define UART_TRANSFER_STATUS_STARTED (7U)
111 
112 #define UART_TRANSFER_STATUS_READ_TIMEOUT (8U)
113 
114 #define UART_TRANSFER_STATUS_ERROR_INUSE (9U)
115 
116 #define UART_TRANSFER_STATUS_ERROR_OTH (10U)
117 
138 #define UART_TRANSFER_MODE_BLOCKING (0U)
139 
143 #define UART_TRANSFER_MODE_CALLBACK (1U)
144 
166 #define UART_READ_RETURN_MODE_FULL (0U)
167 
170 #define UART_READ_RETURN_MODE_PARTIAL (1U)
171 
181 #define UART_LEN_5 (0U)
182 #define UART_LEN_6 (1U)
183 #define UART_LEN_7 (2U)
184 #define UART_LEN_8 (3U)
185 
195 #define UART_STOPBITS_1 (0U)
196 #define UART_STOPBITS_2 (1U)
197 
207 #define UART_PARITY_NONE (0x00U)
208 #define UART_PARITY_ODD (0x01U)
209 #define UART_PARITY_EVEN (0x03U)
210 #define UART_PARITY_FORCED0 (0x07U)
211 #define UART_PARITY_FORCED1 (0x05U)
212 
222 #define UART_FCTYPE_NONE (0x00U)
223 #define UART_FCTYPE_HW (0x02U)
224 
234 #define UART_FCPARAM_RXNONE (0x00U)
235 #define UART_FCPARAM_RXXONXOFF_2 (0x01U)
236 #define UART_FCPARAM_RXXONXOFF_1 (0x02U)
237 #define UART_FCPARAM_RXXONXOFF_12 (0x03U)
238 #define UART_FCPARAM_AUTO_RTS (0x40U)
239 
249 #define UART_FCPARAM_TXNONE (0x00U)
250 #define UART_FCPARAM_TXXONXOFF_2 (0x04U)
251 #define UART_FCPARAM_TXXONXOFF_1 (0x08U)
252 #define UART_FCPARAM_TXXONXOFF_12 (0x0CU)
253 #define UART_FCPARAM_AUTO_CTS (0x80U)
254 
264 #define UART_RXTRIGLVL_1 (1U)
265 #define UART_RXTRIGLVL_8 (8U)
266 #define UART_RXTRIGLVL_16 (16U)
267 #define UART_RXTRIGLVL_56 (56U)
268 #define UART_RXTRIGLVL_60 (60U)
269 
279 #define UART_TXTRIGLVL_1 (1U)
280 #define UART_TXTRIGLVL_8 (8U)
281 #define UART_TXTRIGLVL_16 (16U)
282 #define UART_TXTRIGLVL_32 (32U)
283 #define UART_TXTRIGLVL_56 (56U)
284 
294 #define UART_OPER_MODE_16X (0U)
295 #define UART_OPER_MODE_SIR (1U)
296 #define UART_OPER_MODE_16X_AUTO_BAUD (2U)
297 #define UART_OPER_MODE_13X (3U)
298 #define UART_OPER_MODE_MIR (4U)
299 #define UART_OPER_MODE_FIR (5U)
300 #define UART_OPER_MODE_CIR (6U)
301 #define UART_OPER_MODE_DISABLED (7U)
302 
313 #define UART_TX_FIFO_NOT_FULL ( \
314  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_0)
315 #define UART_TX_FIFO_FULL ( \
316  UART_SSR_TX_FIFO_FULL_TX_FIFO_FULL_VALUE_1)
317 
327 #define UART_INTID_MODEM_STAT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_0 \
328  << \
329  UART_IIR_IT_TYPE_SHIFT)
330 #define UART_INTID_TX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_1 \
331  << \
332  UART_IIR_IT_TYPE_SHIFT)
333 #define UART_INTID_RX_THRES_REACH (UART_IIR_IT_TYPE_IT_TYPE_VALUE_2 \
334  << \
335  UART_IIR_IT_TYPE_SHIFT)
336 #define UART_INTID_RX_LINE_STAT_ERROR (UART_IIR_IT_TYPE_IT_TYPE_VALUE_3 \
337  << \
338  UART_IIR_IT_TYPE_SHIFT)
339 #define UART_INTID_CHAR_TIMEOUT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_6 \
340  << \
341  UART_IIR_IT_TYPE_SHIFT)
342 #define UART_INTID_XOFF_SPEC_CHAR_DETECT (UART_IIR_IT_TYPE_IT_TYPE_VALUE_8 \
343  << \
344  UART_IIR_IT_TYPE_SHIFT)
345 #define UART_INTID_MODEM_SIG_STATE_CHANGE (UART_IIR_IT_TYPE_IT_TYPE_VALUE_10 \
346  << \
347  UART_IIR_IT_TYPE_SHIFT)
348 
350 #define UART_INTR_PENDING (0U)
351 #define UART_N0_INTR_PENDING (1U)
352 
361 #define UART_INTR_CTS (UART_IER_CTS_IT_MASK)
362 #define UART_INTR_RTS (UART_IER_RTS_IT_MASK)
363 #define UART_INTR_XOFF (UART_IER_XOFF_IT_MASK)
364 #define UART_INTR_SLEEPMODE (UART_IER_SLEEP_MODE_MASK)
365 #define UART_INTR_MODEM_STAT (UART_IER_MODEM_STS_IT_MASK)
366 #define UART_INTR_LINE_STAT (UART_IER_LINE_STS_IT_MASK)
367 #define UART_INTR_THR (UART_IER_THR_IT_MASK)
368 #define UART_INTR_RHR_CTI (UART_IER_RHR_IT_MASK)
369 
370 #define UART_INTR2_RX_EMPTY (UART_IER2_EN_RXFIFO_EMPTY_MASK)
371 #define UART_INTR2_TX_EMPTY (UART_IER2_EN_TXFIFO_EMPTY_MASK)
372 
381 #define UART_FIFO_PE_FE_BI_DETECTED (UART_LSR_RX_FIFO_STS_MASK)
382 #define UART_BREAK_DETECTED_ERROR (UART_LSR_RX_BI_MASK)
383 #define UART_FRAMING_ERROR (UART_LSR_RX_FE_MASK)
384 #define UART_PARITY_ERROR (UART_LSR_RX_PE_MASK)
385 #define UART_OVERRUN_ERROR (UART_LSR_RX_OE_MASK)
386 
395 #define UART_REG_CONFIG_MODE_A ((uint32_t) 0x0080)
396 #define UART_REG_CONFIG_MODE_B ((uint32_t) 0x00BF)
397 #define UART_REG_OPERATIONAL_MODE ((uint32_t) 0x007F)
398 
409 #define UART_CONFIG_MODE_POLLED (0x00U)
410 #define UART_CONFIG_MODE_INTERRUPT (0x01U)
411 #define UART_CONFIG_MODE_USER_INTR (0x02U)
412 #define UART_CONFIG_MODE_DMA (0x03U)
413 #define UART_DMA_MODE_PKTDMA (0x00U)
414 #define UART_DMA_MODE_BCDMA (0x01U)
415 
416 /* ========================================================================== */
417 /* Structures and Enums */
418 /* ========================================================================== */
419 
424 typedef struct
425 {
426  void *buf;
429  uint32_t count;
433  uint32_t timeout;
435  uint32_t status;
437  void *args;
440 
448 typedef void (*UART_CallbackFxn) (UART_Handle handle,
449  UART_Transaction *transaction);
450 
461 typedef struct
462 {
463  uint32_t baudRate;
465  uint32_t dataLength;
467  uint32_t stopBits;
469  uint32_t parityType;
471  uint32_t readMode;
473  uint32_t readReturnMode;
475  uint32_t writeMode;
481  uint32_t hwFlowControl;
486  /*
487  * Driver configuration
488  */
489  uint32_t transferMode;
491  uint32_t dmaMode;
493  uint32_t intrNum;
495  uint16_t eventId;
497  uint8_t intrPriority;
499  uint32_t skipIntrReg;
501  int32_t uartDmaIndex;
506  /*
507  * UART configuration
508  */
509  uint32_t operMode;
511  uint32_t rxTrigLvl;
513  uint32_t txTrigLvl;
515  uint32_t rxEvtNum;
517  uint32_t txEvtNum;
519 } UART_Params;
520 
522 typedef struct
523 {
524  /*
525  * SOC configuration
526  */
527  uint32_t baseAddr;
529  uint32_t inputClkFreq;
531 } UART_Attrs;
532 
533 /* ========================================================================== */
534 /* Internal/Private Structure Declarations */
535 /* ========================================================================== */
536 
540 typedef struct
541 {
542  /*
543  * User parameters
544  */
549  /*
550  * UART write variables
551  */
552  const void *writeBuf;
554  uint32_t writeCount;
558  /*
559  * UART receive variables
560  */
561  void *readBuf;
563  uint32_t readCount;
567  uint32_t rxTimeoutCnt;
569  uint32_t readErrorCnt;
571  /*
572  * UART ransaction status variables
573  */
578  /*
579  * State variables
580  */
581  uint32_t isOpen;
583  void *lock;
597  void *hwiHandle;
603 } UART_Object;
604 
611 typedef struct
612 {
617  uint32_t traceInstance;
619 } UART_Config;
620 
622 extern UART_Config gUartConfig[];
624 extern uint32_t gUartConfigNum;
625 
626 /* ========================================================================== */
627 /* Global Variables Declarations */
628 /* ========================================================================== */
629 
630 /* None */
631 
632 /* ========================================================================== */
633 /* Function Declarations */
634 /* ========================================================================== */
635 
639 void UART_init(void);
640 
644 void UART_deinit(void);
645 
662 UART_Handle UART_open(uint32_t index, const UART_Params *prms);
663 
673 void UART_close(UART_Handle handle);
674 
713 int32_t UART_write(UART_Handle handle, UART_Transaction *trans);
714 
749 int32_t UART_read(UART_Handle handle, UART_Transaction *trans);
750 
783 
816 
826 
837 
843 static inline void UART_Params_init(UART_Params *prms);
844 
851 static inline void UART_Transaction_init(UART_Transaction *trans);
852 
853 /* ========================================================================== */
854 /* Static Function Definitions */
855 /* ========================================================================== */
856 
857 static inline void UART_Params_init(UART_Params *prms)
858 {
859  if(prms != NULL)
860  {
861  prms->baudRate = 115200U;
862  prms->dataLength = UART_LEN_8;
863  prms->stopBits = UART_STOPBITS_1;
868  prms->readCallbackFxn = NULL;
869  prms->writeCallbackFxn = NULL;
870  prms->hwFlowControl = 0U;
872  prms->intrNum = 0xFFFF;
874  prms->intrPriority = 4U;
875  prms->skipIntrReg = 0U;
876  prms->uartDmaIndex = -1;
878  prms->rxTrigLvl = UART_RXTRIGLVL_8;
880  }
881 }
882 
883 static inline void UART_Transaction_init(UART_Transaction *trans)
884 {
885  if(trans != NULL)
886  {
887  trans->buf = NULL;
888  trans->count = 0U;
889  trans->timeout = SystemP_WAIT_FOREVER;
891  trans->args = NULL;
892  }
893 }
894 
895 /* ========================================================================== */
896 /* Advanced Function Declarations */
897 /* ========================================================================== */
906 uint32_t UART_getBaseAddr(UART_Handle handle);
907 
916 void UART_enableLoopbackMode(uint32_t baseAddr);
917 
926 void UART_disableLoopbackMode(uint32_t baseAddr);
927 
945 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx);
946 
961 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar);
962 
991 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag);
992 
1017 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag);
1018 
1037 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag);
1038 
1056 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag);
1057 
1083 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr);
1084 
1097 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr);
1098 
1113 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr);
1114 
1125 static inline uint32_t UART_readLineStatus(uint32_t baseAddr);
1126 
1140 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf);
1141 /* ========================================================================== */
1142 /* Advanced Function Definitions */
1143 /* ========================================================================== */
1144 static inline void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
1145 {
1146  /* Write the byte to the Transmit Holding Register(or TX FIFO). */
1147  HW_WR_REG32(baseAddr + UART_THR, (uint32_t) byteTx);
1148 }
1149 
1150 static inline uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
1151 {
1152  uint32_t lcrRegValue = 0U;
1153  uint32_t retVal = 0U;
1154 
1155  /* Preserving the current value of LCR. */
1156  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1157 
1158  /* Switching to Register Operational Mode of operation. */
1159  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1160  & 0x7FU);
1161 
1162  /* Checking if the RX FIFO(or RHR) has atleast one byte of data. */
1163  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1164  (HW_RD_REG32(baseAddr + UART_LSR) &
1165  UART_LSR_RX_FIFO_E_MASK))
1166  {
1167  uint32_t tempRetVal = HW_RD_REG32(baseAddr + UART_RHR);
1168  *pChar = (uint8_t)tempRetVal;
1169  retVal = 1U;
1170  }
1171 
1172  /* Restoring the value of LCR. */
1173  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1174 
1175  return retVal;
1176 }
1177 
1178 static inline void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
1179 {
1180  uint32_t enhanFnBitVal = 0U;
1181  uint32_t lcrRegValue = 0U;
1182 
1183  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1184  if ((intrFlag & 0xF0U) > 0U)
1185  {
1186  /* Preserving the current value of LCR. */
1187  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1188  /* Switching to Register Configuration Mode B. */
1189  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1190 
1191  /* Collecting the current value of EFR[4] and later setting it. */
1192  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1193 
1194  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1195  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1196 
1197  /* Restoring the value of LCR. */
1198  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1199 
1200  /* Preserving the current value of LCR. */
1201  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1202 
1203  /* Switching to Register Operational Mode of operation. */
1204  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1205  & 0x7FU);
1206 
1207  /*
1208  ** It is suggested that the System Interrupts for UART in the
1209  ** Interrupt Controller are enabled after enabling the peripheral
1210  ** interrupts of the UART using this API. If done otherwise, there
1211  ** is a risk of LCR value not getting restored and illicit characters
1212  ** transmitted or received from/to the UART. The situation is explained
1213  ** below.
1214  ** The scene is that the system interrupt for UART is already enabled
1215  ** and the current API is invoked. On enabling the interrupts
1216  ** corresponding to IER[7:4] bits below, if any of those interrupt
1217  ** conditions already existed, there is a possibility that the control
1218  ** goes to Interrupt Service Routine (ISR) without executing the
1219  ** remaining statements in this API. Executing the remaining statements
1220  ** is critical in that the LCR value is restored in them.
1221  ** However, there seems to be no risk in this API for enabling
1222  ** interrupts corresponding to IER[3:0] because it is done at the end
1223  ** and no statements follow that.
1224  */
1225 
1226  /************* ATOMIC STATEMENTS START *************************/
1227 
1228  /* Programming the bits IER[7:4]. */
1229  HW_WR_REG32(baseAddr + UART_IER, intrFlag & 0xF0U);
1230 
1231  /* Restoring the value of LCR. */
1232  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1233 
1234  /* Preserving the current value of LCR. */
1235  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1236  /* Switching to Register Configuration Mode B. */
1237  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1238 
1239  /* Restoring the value of EFR[4] to its original value. */
1240  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1241 
1242  /* Restoring the value of LCR. */
1243  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1244 
1245  /************** ATOMIC STATEMENTS END *************************/
1246  }
1247 
1248  /* Programming the bits IER[3:0]. */
1249  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) |
1250  (intrFlag & 0x0FU));
1251 }
1252 
1253 static inline void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
1254 {
1255  uint32_t enhanFnBitVal;
1256  uint32_t lcrRegValue;
1257 
1258  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1259  if((intrFlag & 0xF0U) > 0U)
1260  {
1261  /* Preserving the current value of LCR. */
1262  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1263  /* Switching to Register Configuration Mode B. */
1264  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1265 
1266  /* Collecting the current value of EFR[4] and later setting it. */
1267  enhanFnBitVal = HW_RD_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN);
1268 
1269  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN,
1270  UART_EFR_ENHANCED_EN_ENHANCED_EN_U_VALUE_1);
1271 
1272  /* Restoring the value of LCR. */
1273  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1274  }
1275 
1276  /* Preserving the current value of LCR. */
1277  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1278 
1279  /* Switching to Register Operational Mode of operation. */
1280  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1281  & 0x7FU);
1282 
1283  HW_WR_REG32(baseAddr + UART_IER, HW_RD_REG32(baseAddr + UART_IER) &
1284  ~(intrFlag & 0xFFU));
1285 
1286  /* Restoring the value of LCR. */
1287  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1288 
1289  /* Switch to mode B only when the upper 4 bits of IER needs to be changed */
1290  if((intrFlag & 0xF0U) > 0U)
1291  {
1292  /* Preserving the current value of LCR. */
1293  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1294  /* Switching to Register Configuration Mode B. */
1295  HW_WR_REG32(baseAddr + UART_LCR, UART_REG_CONFIG_MODE_B & 0xFFU);
1296 
1297  /* Restoring the value of EFR[4] to its original value. */
1298  HW_WR_FIELD32(baseAddr + UART_EFR, UART_EFR_ENHANCED_EN, enhanFnBitVal);
1299 
1300  /* Restoring the value of LCR. */
1301  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1302  }
1303 }
1304 
1305 static inline void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
1306 {
1307  /* Programming the bits IER2[1:0]. */
1308  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) |
1309  (intrFlag & 0x03U));
1310 }
1311 
1312 static inline void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
1313 {
1314  HW_WR_REG32(baseAddr + UART_IER2, HW_RD_REG32(baseAddr + UART_IER2) &
1315  ~(intrFlag & 0x3U));
1316 }
1317 
1318 static inline uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
1319 {
1320  uint32_t lcrRegValue = 0U;
1321  uint32_t retVal = 0U;
1322 
1323  /* Preserving the current value of LCR. */
1324  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1325 
1326  /* Switching to Register Operational Mode of operation. */
1327  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1328  & 0x7FU);
1329 
1330  retVal = HW_RD_REG32(baseAddr + UART_IIR) & UART_IIR_IT_TYPE_MASK;
1331 
1332  /* Restoring the value of LCR. */
1333  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1334 
1335  return retVal;
1336 }
1337 
1338 static inline uint32_t UART_getIntr2Status(uint32_t baseAddr)
1339 {
1340  uint32_t retVal = 0U;
1341 
1342  retVal = HW_RD_REG32(baseAddr + UART_ISR2) &
1343  (UART_IER2_EN_RXFIFO_EMPTY_MASK | UART_IER2_EN_TXFIFO_EMPTY_MASK);
1344 
1345  return retVal;
1346 }
1347 
1348 static inline uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
1349 {
1350  uint32_t lcrRegValue = 0;
1351  uint32_t retVal = 0U;
1352 
1353  /* Preserving the current value of LCR. */
1354  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1355 
1356  /* Switching to Register Operational Mode of operation. */
1357  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1358  & 0x7FU);
1359 
1360  /* Checking if the RHR(or RX FIFO) has atleast one byte to be read. */
1361  if ((uint32_t) UART_LSR_RX_FIFO_E_RX_FIFO_E_VALUE_0 !=
1362  (HW_RD_REG32(baseAddr + UART_LSR) &
1363  UART_LSR_RX_FIFO_E_MASK))
1364  {
1365  retVal = (uint32_t) TRUE;
1366  }
1367 
1368  /* Restoring the value of LCR. */
1369  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1370 
1371  return retVal;
1372 }
1373 
1374 static inline uint32_t UART_readLineStatus(uint32_t baseAddr)
1375 {
1376  uint32_t lcrRegValue = 0U;
1377  uint32_t retVal = 0U;
1378 
1379  /* Preserving the current value of LCR. */
1380  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1381 
1382  /* Switching to Register Operational Mode of operation. */
1383  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1384  & 0x7FU);
1385 
1386  retVal = HW_RD_REG32(baseAddr + UART_LSR);
1387 
1388  /* Restoring the value of LCR. */
1389  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1390 
1391  return retVal;
1392 }
1393 
1394 static inline uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
1395 {
1396  uint8_t readByte = 0;
1397  uint32_t waitCount = UART_ERROR_COUNT;
1398  uint32_t errorVal;
1399  uint32_t lcrRegValue = 0;
1400 
1401  /* Preserving the current value of LCR. */
1402  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1403 
1404  /* Switching to Register Operational Mode of operation. */
1405  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1406  & 0x7FU);
1407 
1408  /* Read Rx Error Status */
1409  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1410  (UART_LSR_RX_FIFO_STS_MASK |
1411  UART_LSR_RX_BI_MASK |
1412  UART_LSR_RX_FE_MASK |
1413  UART_LSR_RX_PE_MASK |
1414  UART_LSR_RX_OE_MASK);
1415 
1416  /* Restoring the value of LCR. */
1417  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1418 
1419  /* Read and throw Erroneous bytes from RxFIFO */
1420  while ((UART_LSR_RX_FIFO_STS_MASK |
1421  UART_LSR_RX_BI_MASK |
1422  UART_LSR_RX_FE_MASK |
1423  UART_LSR_RX_PE_MASK |
1424  UART_LSR_RX_OE_MASK) == errorVal)
1425  {
1426  readByte = (uint8_t) (HW_RD_REG32(baseAddr + UART_RHR) & 0xFFU);
1427  waitCount--;
1428  if (0U == waitCount)
1429  {
1430  break;
1431  }
1432 
1433  /* Preserving the current value of LCR. */
1434  lcrRegValue = HW_RD_REG32(baseAddr + UART_LCR);
1435 
1436  /* Switching to Register Operational Mode of operation. */
1437  HW_WR_REG32(baseAddr + UART_LCR, HW_RD_REG32(baseAddr + UART_LCR)
1438  & 0x7FU);
1439 
1440  /* Read Rx Error Status */
1441  errorVal = HW_RD_REG32(baseAddr + UART_LSR) &
1442  (UART_LSR_RX_FIFO_STS_MASK |
1443  UART_LSR_RX_BI_MASK |
1444  UART_LSR_RX_FE_MASK |
1445  UART_LSR_RX_PE_MASK |
1446  UART_LSR_RX_OE_MASK);
1447 
1448  /* Restoring the value of LCR. */
1449  HW_WR_REG32(baseAddr + UART_LCR, lcrRegValue);
1450  }
1451 
1452  /* Read non-erroneous byte from RxFIFO */
1453  readByte = (uint8_t) (HW_RD_REG32(baseAddr + UART_RHR) & 0xFFU);
1454 
1455  return readByte;
1456 }
1457 
1458 #ifdef __cplusplus
1459 }
1460 #endif
1461 
1462 #endif /* #ifndef UART_V0_H_ */
1463 
UART_enableLoopbackMode
void UART_enableLoopbackMode(uint32_t baseAddr)
Function to enable loopback mode. This function is for internal use. Not recommended for customers to...
UART_deinit
void UART_deinit(void)
This function de-initializes the UART module.
UART_Object::readTransferSem
void * readTransferSem
Definition: uart/v0/uart.h:587
UART_ERROR_COUNT
#define UART_ERROR_COUNT
Count Value to check error in the recieved byte
Definition: uart/v0/uart.h:82
UART_TRANSFER_MODE_BLOCKING
#define UART_TRANSFER_MODE_BLOCKING
UART read/write APIs blocks execution. This mode can only be used when called within a Task context.
Definition: uart/v0/uart.h:138
UART_Object::lockObj
SemaphoreP_Object lockObj
Definition: uart/v0/uart.h:585
UART_Transaction_init
static void UART_Transaction_init(UART_Transaction *trans)
Function to initialize the UART_Transaction struct to its defaults.
Definition: uart/v0/uart.h:883
UART_Object::readTransferSemObj
SemaphoreP_Object readTransferSemObj
Definition: uart/v0/uart.h:590
UART_REG_CONFIG_MODE_B
#define UART_REG_CONFIG_MODE_B
Definition: uart/v0/uart.h:396
UART_STOPBITS_1
#define UART_STOPBITS_1
Definition: uart/v0/uart.h:195
UART_TRANSFER_STATUS_SUCCESS
#define UART_TRANSFER_STATUS_SUCCESS
Transaction success.
Definition: uart/v0/uart.h:96
UART_Object::handle
UART_Handle handle
Definition: uart/v0/uart.h:545
UART_intr2Enable
static void UART_intr2Enable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1305
UART_Object::hwiHandle
void * hwiHandle
Definition: uart/v0/uart.h:597
index
uint16_t index
Definition: tisci_rm_proxy.h:3
UART_Object::writeBuf
const void * writeBuf
Definition: uart/v0/uart.h:552
SystemP.h
UART_Transaction::timeout
uint32_t timeout
Definition: uart/v0/uart.h:433
UART_Handle
void * UART_Handle
A handle that is returned from a UART_open() call.
Definition: uart/v0/uart.h:85
UART_Object::writeTrans
UART_Transaction * writeTrans
Definition: uart/v0/uart.h:576
NULL
#define NULL
Define NULL if not defined.
Definition: csl_types.h:100
UART_getHandle
UART_Handle UART_getHandle(uint32_t index)
Function to return a open'ed UART handle given a UART instance index.
UART_writeCancel
int32_t UART_writeCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current write transaction.
UART_Config
UART global configuration array.
Definition: uart/v0/uart.h:612
UART_Params::writeMode
uint32_t writeMode
Definition: uart/v0/uart.h:475
UART_getIntr2Status
static uint32_t UART_getIntr2Status(uint32_t baseAddr)
This API determines the UART Interrupt Status 2.
Definition: uart/v0/uart.h:1338
UART_Object::writeSizeRemaining
uint32_t writeSizeRemaining
Definition: uart/v0/uart.h:556
UART_CallbackFxn
void(* UART_CallbackFxn)(UART_Handle handle, UART_Transaction *transaction)
The definition of a callback function used by the UART driver when used in UART_TRANSFER_MODE_CALLBAC...
Definition: uart/v0/uart.h:448
UART_Params::eventId
uint16_t eventId
Definition: uart/v0/uart.h:495
UART_Params::dataLength
uint32_t dataLength
Definition: uart/v0/uart.h:465
SystemP_WAIT_FOREVER
#define SystemP_WAIT_FOREVER
Value to use when needing a timeout of infinity or wait forver until resource is available.
Definition: SystemP.h:83
UART_Params::intrPriority
uint8_t intrPriority
Definition: uart/v0/uart.h:497
UART_write
int32_t UART_write(UART_Handle handle, UART_Transaction *trans)
Function to perform UART write operation.
UART_Params::readMode
uint32_t readMode
Definition: uart/v0/uart.h:471
UART_RXTRIGLVL_8
#define UART_RXTRIGLVL_8
Definition: uart/v0/uart.h:265
SemaphoreP.h
UART_intrDisable
static void UART_intrDisable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1253
UART_disableLoopbackMode
void UART_disableLoopbackMode(uint32_t baseAddr)
Function to disable loopback mode. This function is for internal use. Not recommended for customers t...
UART_PARITY_NONE
#define UART_PARITY_NONE
Definition: uart/v0/uart.h:207
UART_Params::rxTrigLvl
uint32_t rxTrigLvl
Definition: uart/v0/uart.h:511
UART_getChar
static uint32_t UART_getChar(uint32_t baseAddr, uint8_t *pChar)
This API reads a byte from the Receiver Buffer Register (RBR). It checks once if any character is rea...
Definition: uart/v0/uart.h:1150
UART_close
void UART_close(UART_Handle handle)
Function to close a UART peripheral specified by the UART handle.
gUartConfig
UART_Config gUartConfig[]
Externally defined driver configuration array.
UART_getIntrIdentityStatus
static uint32_t UART_getIntrIdentityStatus(uint32_t baseAddr)
This API determines the UART Interrupt Status.
Definition: uart/v0/uart.h:1318
UART_Transaction::args
void * args
Definition: uart/v0/uart.h:437
UART_Params::uartDmaIndex
int32_t uartDmaIndex
Definition: uart/v0/uart.h:501
UART_Object::uartDmaHandle
void * uartDmaHandle
Definition: uart/v0/uart.h:601
UART_READ_RETURN_MODE_FULL
#define UART_READ_RETURN_MODE_FULL
Unblock/callback when buffer is full.
Definition: uart/v0/uart.h:166
UART_Params::dmaMode
uint32_t dmaMode
Definition: uart/v0/uart.h:491
UART_Object::isOpen
uint32_t isOpen
Definition: uart/v0/uart.h:581
UART_flushTxFifo
void UART_flushTxFifo(UART_Handle handle)
Function to flush a TX FIFO of peripheral specified by the UART handle.
UART_Params::transferMode
uint32_t transferMode
Definition: uart/v0/uart.h:489
UART_Params::skipIntrReg
uint32_t skipIntrReg
Definition: uart/v0/uart.h:499
UART_Config::attrs
UART_Attrs * attrs
Definition: uart/v0/uart.h:613
UART_Object::writeTransferSemObj
SemaphoreP_Object writeTransferSemObj
Definition: uart/v0/uart.h:595
UART_Object::lock
void * lock
Definition: uart/v0/uart.h:583
UART_Object::readCount
uint32_t readCount
Definition: uart/v0/uart.h:563
UART_Params::parityType
uint32_t parityType
Definition: uart/v0/uart.h:469
UART_Object::rxTimeoutCnt
uint32_t rxTimeoutCnt
Definition: uart/v0/uart.h:567
UART_putChar
static void UART_putChar(uint32_t baseAddr, uint8_t byteTx)
This API writes a byte to the Transmitter FIFO without checking for the emptiness of the Transmitter ...
Definition: uart/v0/uart.h:1144
UART_Object::writeCount
uint32_t writeCount
Definition: uart/v0/uart.h:554
UART_Params::hwFlowControl
uint32_t hwFlowControl
Definition: uart/v0/uart.h:481
UART_Object::readSizeRemaining
uint32_t readSizeRemaining
Definition: uart/v0/uart.h:565
UART_Params::readReturnMode
uint32_t readReturnMode
Definition: uart/v0/uart.h:473
HwiP.h
UART_init
void UART_init(void)
This function initializes the UART module.
UART_Params
UART Parameters.
Definition: uart/v0/uart.h:462
UART_readCancel
int32_t UART_readCancel(UART_Handle handle, UART_Transaction *trans)
Function to perform UART canceling of current read transaction.
UART_Params::baudRate
uint32_t baudRate
Definition: uart/v0/uart.h:463
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UART_CallbackFxn readCallbackFxn
Definition: uart/v0/uart.h:477
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uint32_t readErrorCnt
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void * writeTransferSem
Definition: uart/v0/uart.h:592
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uint32_t status
Definition: uart/v0/uart.h:435
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UART_Object * object
Definition: uart/v0/uart.h:615
UART_Transaction
Data structure used with UART_read() and UART_write()
Definition: uart/v0/uart.h:425
UART_getBaseAddr
uint32_t UART_getBaseAddr(UART_Handle handle)
Function to get base address of UART instance of a particular handle.
UART_Config::traceInstance
uint32_t traceInstance
Definition: uart/v0/uart.h:617
UART_LEN_8
#define UART_LEN_8
Definition: uart/v0/uart.h:184
UART_checkCharsAvailInFifo
static uint32_t UART_checkCharsAvailInFifo(uint32_t baseAddr)
This API checks if the RX FIFO (or RHR in non-FIFO mode) has atleast one byte of data to be read.
Definition: uart/v0/uart.h:1348
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uint32_t intrNum
Definition: uart/v0/uart.h:493
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uint32_t inputClkFreq
Definition: uart/v0/uart.h:529
UART_open
UART_Handle UART_open(uint32_t index, const UART_Params *prms)
This function opens a given UART peripheral.
UART_CONFIG_MODE_INTERRUPT
#define UART_CONFIG_MODE_INTERRUPT
Definition: uart/v0/uart.h:410
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UART_CallbackFxn writeCallbackFxn
Definition: uart/v0/uart.h:479
TRUE
#define TRUE
Definition: csl_types.h:61
HwiP_Object
Opaque Hwi object used with the Hwi APIs.
Definition: HwiP.h:93
UART_Object
UART driver object.
Definition: uart/v0/uart.h:541
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uint32_t hwFlowControlThr
Definition: uart/v0/uart.h:483
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UART_Transaction * readTrans
Definition: uart/v0/uart.h:574
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uint32_t stopBits
Definition: uart/v0/uart.h:467
UART_intr2Disable
static void UART_intr2Disable(uint32_t baseAddr, uint32_t intrFlag)
This API disables the specified interrupts in the UART mode of operation for IER2.
Definition: uart/v0/uart.h:1312
UART_Object::readBuf
void * readBuf
Definition: uart/v0/uart.h:561
UART_Params::rxEvtNum
uint32_t rxEvtNum
Definition: uart/v0/uart.h:515
UART_Params_init
static void UART_Params_init(UART_Params *prms)
Function to initialize the UART_Params struct to its defaults.
Definition: uart/v0/uart.h:857
gUartConfigNum
uint32_t gUartConfigNum
Externally defined driver configuration array size.
SemaphoreP_Object
Opaque semaphore object used with the semaphore APIs.
Definition: SemaphoreP.h:59
UART_read
int32_t UART_read(UART_Handle handle, UART_Transaction *trans)
Function to perform UART read operation.
UART_TXTRIGLVL_32
#define UART_TXTRIGLVL_32
Definition: uart/v0/uart.h:282
UART_OPER_MODE_16X
#define UART_OPER_MODE_16X
Definition: uart/v0/uart.h:294
UART_Attrs
UART instance attributes - used during init time.
Definition: uart/v0/uart.h:523
UART_RXTRIGLVL_16
#define UART_RXTRIGLVL_16
Definition: uart/v0/uart.h:266
UART_readLineStatus
static uint32_t UART_readLineStatus(uint32_t baseAddr)
This API reads the line status register value.
Definition: uart/v0/uart.h:1374
UART_Params::txEvtNum
uint32_t txEvtNum
Definition: uart/v0/uart.h:517
UART_getCharFifo
static uint8_t UART_getCharFifo(uint32_t baseAddr, uint8_t *readBuf)
This API reads the data present at the top of the RX FIFO, that is, the data in the Receive Holding R...
Definition: uart/v0/uart.h:1394
UART_Attrs::baseAddr
uint32_t baseAddr
Definition: uart/v0/uart.h:527
UART_Transaction::buf
void * buf
Definition: uart/v0/uart.h:426
UART_intrEnable
static void UART_intrEnable(uint32_t baseAddr, uint32_t intrFlag)
This API enables the specified interrupts in the UART mode of operation.
Definition: uart/v0/uart.h:1178
UART_Object::hwiObj
HwiP_Object hwiObj
Definition: uart/v0/uart.h:599
UART_Object::prms
UART_Params prms
Definition: uart/v0/uart.h:547
UART_Transaction::count
uint32_t count
Definition: uart/v0/uart.h:429
UART_Params::txTrigLvl
uint32_t txTrigLvl
Definition: uart/v0/uart.h:513
UART_Params::operMode
uint32_t operMode
Definition: uart/v0/uart.h:509