AM62Px MCU+ SDK  10.01.00
safety_checkers_soc.h
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1 /*
2  * Copyright (C) 2024 Texas Instruments Incorporated
3  *
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5  * modification, are permitted provided that the following conditions
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33 
46 #ifndef SAFETY_CHECKERS_SOC_H_
47 #define SAFETY_CHECKERS_SOC_H_
48 
49 /* ========================================================================== */
50 /* Include Files */
51 /* ========================================================================== */
52 
53 #include "safety_checkers_pm_soc.h"
54 #include "safety_checkers_rm_soc.h"
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
67 /* ========================================================================== */
68 /* Macros & Typedefs */
69 /* ========================================================================== */
70 
72 #define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS (0x400000UL)
73 #define SAFETY_CHECKERS_PM_PLL_CFG_BASE_ADDRESS (0x680000UL)
74 #define SAFETY_CHECKERS_PM_MCU_PLL_CFG_BASE_ADDRESS (0x4040000UL)
75 
77 #define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM (0x02U)
78 #define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM (0x0BU)
79 #define SAFETY_CHECKERS_PM_PD_STAT_NUM (0x16U)
80 #define SAFETY_CHECKERS_PM_MD_STAT_NUM (0x60U)
81 
83 #define SAFETY_CHECKERS_PM_PLL0_LENGTH (0xA8U)
84 #define SAFETY_CHECKERS_PM_PLL1_LENGTH (0x9CU)
85 #define SAFETY_CHECKERS_PM_PLL2_LENGTH (0xA8U)
86 #define SAFETY_CHECKERS_PM_PLL6_LENGTH (0x84U)
87 #define SAFETY_CHECKERS_PM_PLL8_LENGTH (0x84U)
88 #define SAFETY_CHECKERS_PM_PLL12_LENGTH (0x84U)
89 #define SAFETY_CHECKERS_PM_PLL15_LENGTH (0x8CU)
90 #define SAFETY_CHECKERS_PM_PLL16_LENGTH (0x84U)
91 #define SAFETY_CHECKERS_PM_PLL17_LENGTH (0x84U)
92 #define SAFETY_CHECKERS_PM_PLL18_LENGTH (0x84U)
93 #define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH (0x9CU)
94 
96 #define TIFS_CHECKER_FWL_MAX_NUM (0x16U)
97 
102 #define SAFETY_CHECKERS_PM_PSC_REGDUMP_SIZE (SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM + \
103  SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM + \
104  SAFETY_CHECKERS_PM_PD_STAT_NUM + \
105  SAFETY_CHECKERS_PM_MD_STAT_NUM)
106 
115 #define SAFETY_CHECKERS_PM_PLL_REGDUMP_SIZE (163U)
116 
123 #define SAFETY_CHECKERS_RM_REGDUMP_SIZE (3215U)
124 
126 #define SAFETY_CHECKERS_RM_BA0_IR (CSL_TIMESYNC_EVENT_INTROUTER0_INTR_ROUTER_CFG_BASE)
127 #define SAFETY_CHECKERS_RM_BA1_IR (CSL_WKUP_MCU_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
128 #define SAFETY_CHECKERS_RM_BA2_IR (CSL_MAIN_GPIOMUX_INTROUTER0_INTR_ROUTER_CFG_BASE)
129 
131 #define SAFETY_CHECKERS_RM_IR_REG0_NUM (26U)
132 #define SAFETY_CHECKERS_RM_IR_REG1_NUM (16U)
133 #define SAFETY_CHECKERS_RM_IR_REG2_NUM (36U)
134 
136 #define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM (2U)
137 
139 #define SAFETY_CHECKERS_RM_BA0_IA_IMAP (CSL_DMASS0_INTAGGR_IMAP_BASE)
140 #define SAFETY_CHECKERS_RM_BA1_IA_IMAP (CSL_DMASS1_INTAGGR_IMAP_BASE)
141 
143 #define SAFETY_CHECKERS_RM_REG0_IA_IMAP (1536U)
144 #define SAFETY_CHECKERS_RM_REG1_IA_IMAP (128U)
145 
147 #define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP (1U)
148 
150 #define SAFETY_CHECKERS_RM_BA0_RA (CSL_DMASS0_BCDMA_RING_BASE)
151 #define SAFETY_CHECKERS_RM_BA1_RA (CSL_DMASS0_PKTDMA_RING_BASE)
152 #define SAFETY_CHECKERS_RM_BA2_RA (CSL_DMASS0_RINGACC_CFG_BASE)
153 #define SAFETY_CHECKERS_RM_BA3_RA (CSL_DMASS1_BCDMA_RING_BASE)
154 
156 #define SAFETY_CHECKERS_RM_RA_REG0_NUM (82U)
157 #define SAFETY_CHECKERS_RM_RA_REG1_NUM (150U)
158 #define SAFETY_CHECKERS_RM_RA_REG2_NUM (20U)
159 #define SAFETY_CHECKERS_RM_RA_REG3_NUM (6U)
160 
162 #define SAFETY_CHECKERS_RM_SUBMOD0_RA (3U)
163 #define SAFETY_CHECKERS_RM_RA_SUBMOD1 (5U)
164 
166 #define SAFETY_CHECKERS_RM_BA0_UDMA_TX (CSL_DMASS0_BCDMA_TCHAN_BASE)
167 #define SAFETY_CHECKERS_RM_BA1_UDMA_TX (CSL_DMASS0_PKTDMA_TCHAN_BASE)
168 
170 #define SAFETY_CHECKERS_RM_REG0_UDMA_TX (25U)
171 #define SAFETY_CHECKERS_RM_REG1_UDMA_TX (29U)
172 
174 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX (5U)
175 
177 #define SAFETY_CHECKERS_RM_BA0_UDMA_RX (CSL_DMASS0_BCDMA_RCHAN_BASE)
178 #define SAFETY_CHECKERS_RM_BA1_UDMA_RX (CSL_DMASS0_PKTDMA_RCHAN_BASE)
179 #define SAFETY_CHECKERS_RM_BA2_UDMA_RX (CSL_DMASS1_BCDMA_RCHAN_BASE)
180 
182 #define SAFETY_CHECKERS_RM_REG0_UDMA_RX (25U)
183 #define SAFETY_CHECKERS_RM_REG1_UDMA_RX (24U)
184 #define SAFETY_CHECKERS_RM_REG2_UDMA_RX (6U)
185 
187 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX (4U)
188 
190 #define SAFETY_CHECKERS_RM_BA0_UDMA_FLW (CSL_DMASS0_PKTDMA_RFLOW_BASE)
191 
193 #define SAFETY_CHECKERS_RM_REG0_UDMA_FLW (51U)
194 
196 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW (1U)
197 
199 #define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG (CSL_DMASS0_BCDMA_GCFG_BASE)
200 #define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG (CSL_DMASS0_PKTDMA_GCFG_BASE)
201 #define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG (CSL_DMASS1_BCDMA_GCFG_BASE)
202 
204 #define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG (1U)
205 #define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG (1U)
206 #define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG (1U)
207 
209 #define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG (13U)
210 #define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG (14U)
211 #define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG (13U)
212 
222 /* ========================================================================== */
223 /* Global Variables */
224 /* ========================================================================== */
225 
232 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
233  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
234  0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U,
235  0xA8U};
236 
238 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
239  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
240  0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU};
241 
243 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
244  0x40U, 0x44U, 0x60U, 0x64U, 0x84U, 0x88U, 0x8CU,
245  0x90U, 0x94U, 0x98U, 0x9CU, 0xA0U, 0xA4U, 0xA8U};
246 
248 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
249  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
250 
252 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
253  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
254 
256 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
257  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
258 
260 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
261  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
262  0x8CU};
263 
265 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
266  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
267 
269 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
270  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
271 
273 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
274  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U};
275 
277 {0x00U, 0x08U, 0x20U, 0x24U, 0x30U, 0x34U, 0x38U,
278  0x40U, 0x44U, 0x60U, 0x64U, 0x80U, 0x84U, 0x88U,
279  0x8CU, 0x90U, 0x94U, 0x98U, 0x9CU};
280 
290 /* ========================================================================== */
291 /* Structure Declarations */
292 /* ========================================================================== */
293 
300 {
311 
313 };
314 
321 {
324 };
325 
332 {
333  {SAFETY_CHECKERS_RM_BA0_IR, SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM, SAFETY_CHECKERS_RM_IR_REG0_NUM,SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
334  {SAFETY_CHECKERS_RM_BA1_IR, SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM, SAFETY_CHECKERS_RM_IR_REG1_NUM,SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
335  {SAFETY_CHECKERS_RM_BA2_IR, SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM, SAFETY_CHECKERS_RM_IR_REG2_NUM,SAFETY_CHECKERS_RM_REG_HEX4, {0X0U, 0x4U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
336 
337  {SAFETY_CHECKERS_RM_BA0_IA_IMAP, SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP, SAFETY_CHECKERS_RM_REG0_IA_IMAP, SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
338  {SAFETY_CHECKERS_RM_BA1_IA_IMAP, SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP, SAFETY_CHECKERS_RM_REG1_IA_IMAP, SAFETY_CHECKERS_RM_REG_HEX8, {0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
339 
340  {SAFETY_CHECKERS_RM_BA0_RA, SAFETY_CHECKERS_RM_SUBMOD0_RA, SAFETY_CHECKERS_RM_RA_REG0_NUM, SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
341  {SAFETY_CHECKERS_RM_BA1_RA, SAFETY_CHECKERS_RM_SUBMOD0_RA, SAFETY_CHECKERS_RM_RA_REG1_NUM, SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
342  {SAFETY_CHECKERS_RM_BA2_RA, SAFETY_CHECKERS_RM_RA_SUBMOD1, SAFETY_CHECKERS_RM_RA_REG2_NUM, SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U, 0x4CU, 0x50U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
343  {SAFETY_CHECKERS_RM_BA3_RA, SAFETY_CHECKERS_RM_SUBMOD0_RA, SAFETY_CHECKERS_RM_RA_REG3_NUM, SAFETY_CHECKERS_RM_REG_HEX100, {0x40U, 0x44U, 0x48U,0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
344 
345  {SAFETY_CHECKERS_RM_BA0_UDMA_TX, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX, SAFETY_CHECKERS_RM_REG0_UDMA_TX, SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
346  {SAFETY_CHECKERS_RM_BA1_UDMA_TX, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX, SAFETY_CHECKERS_RM_REG1_UDMA_TX, SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x70U, 0x80U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
347 
348  {SAFETY_CHECKERS_RM_BA0_UDMA_RX, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX, SAFETY_CHECKERS_RM_REG0_UDMA_RX, SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
349  {SAFETY_CHECKERS_RM_BA1_UDMA_RX, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX, SAFETY_CHECKERS_RM_REG1_UDMA_RX, SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
350  {SAFETY_CHECKERS_RM_BA2_UDMA_RX, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX, SAFETY_CHECKERS_RM_REG2_UDMA_RX, SAFETY_CHECKERS_RM_REG_HEX100, {0x0U, 0x64U, 0x68U, 0x80U, 0X0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
351 
352  {SAFETY_CHECKERS_RM_BA0_UDMA_FLW, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW, SAFETY_CHECKERS_RM_REG0_UDMA_FLW, SAFETY_CHECKERS_RM_REG_HEX40, {0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
353 
354  {SAFETY_CHECKERS_RM_BA0_UDMA_GCFG, SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG, SAFETY_CHECKERS_RM_REG0_UDMA_GCFG, SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
355  {SAFETY_CHECKERS_RM_BA1_UDMA_GCFG, SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG, SAFETY_CHECKERS_RM_REG1_UDMA_GCFG, SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x88U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
356  {SAFETY_CHECKERS_RM_BA2_UDMA_GCFG, SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG, SAFETY_CHECKERS_RM_REG2_UDMA_GCFG, SAFETY_CHECKERS_RM_REG_HEX0, {0x0U, 0x04U, 0X08U, 0x10U, 0x20U, 0x24U, 0x28U, 0x2CU, 0x30U, 0x60U, 0x64U, 0x78U, 0x7CU, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U, 0x0U}},
357 };
358 
361 /* ========================================================================== */
362 /* Function Declarations */
363 /* ========================================================================== */
364 
365 /* None */
366 
367 /* ========================================================================== */
368 /* Static Function Definitions */
369 /* ========================================================================== */
370 
371 /* None */
372 
373 #ifdef __cplusplus
374 }
375 #endif
376 
377 #endif /* #ifndef SAFETY_CHECKERS_SOC_H_ */
gSafetyCheckers_PmPllRegOffset16
static uint32_t gSafetyCheckers_PmPllRegOffset16[]
Definition: safety_checkers_soc.h:264
SAFETY_CHECKERS_RM_BA0_UDMA_TX
#define SAFETY_CHECKERS_RM_BA0_UDMA_TX
RM UDMA TX module base addresses.
Definition: safety_checkers_soc.h:166
gSafetyCheckers_PmPllData
static SafetyCheckers_PmPllData gSafetyCheckers_PmPllData[]
Structure defines PLL register base address and the total length of registers.
Definition: safety_checkers_soc.h:299
SAFETY_CHECKERS_RM_REG2_UDMA_GCFG
#define SAFETY_CHECKERS_RM_REG2_UDMA_GCFG
Definition: safety_checkers_soc.h:206
SAFETY_CHECKERS_PM_PLL6_LENGTH
#define SAFETY_CHECKERS_PM_PLL6_LENGTH
Definition: safety_checkers_soc.h:86
SAFETY_CHECKERS_RM_IR_REG0_NUM
#define SAFETY_CHECKERS_RM_IR_REG0_NUM
Formula input of IR module to read relevant registers from register group.
Definition: safety_checkers_soc.h:131
gSafetyCheckers_PmPllRegOffset12
static uint32_t gSafetyCheckers_PmPllRegOffset12[]
Definition: safety_checkers_soc.h:255
gSafetyCheckers_PmPllRegOffset18
static uint32_t gSafetyCheckers_PmPllRegOffset18[]
Definition: safety_checkers_soc.h:272
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_GCFG
Number of registers in UDMA GCFG register group.
Definition: safety_checkers_soc.h:209
SAFETY_CHECKERS_PM_PD_STAT_NUM
#define SAFETY_CHECKERS_PM_PD_STAT_NUM
Definition: safety_checkers_soc.h:79
SAFETY_CHECKERS_RM_BA1_UDMA_TX
#define SAFETY_CHECKERS_RM_BA1_UDMA_TX
Definition: safety_checkers_soc.h:167
gSafetyCheckers_PmPllRegOffset6
static uint32_t gSafetyCheckers_PmPllRegOffset6[]
Definition: safety_checkers_soc.h:247
SAFETY_CHECKERS_RM_REG2_UDMA_RX
#define SAFETY_CHECKERS_RM_REG2_UDMA_RX
Definition: safety_checkers_soc.h:184
SafetyCheckers_PmPscData
Structure to hold the base address and the number of Module Domain(MD) stat and Power Domain(PD) stat...
Definition: safety_checkers_pm.h:126
gSafetyCheckers_RmRegData
static SafetyCheckers_RmRegData gSafetyCheckers_RmRegData[]
Structure defines RM module register base address and the total length of registers.
Definition: safety_checkers_soc.h:331
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_RX
Number of registers in UDMA RX register group.
Definition: safety_checkers_soc.h:187
SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP
#define SAFETY_CHECKERS_RM_SUBMOD0_IA_IMAP
Number of registers in IAIMAP register group.
Definition: safety_checkers_soc.h:147
SAFETY_CHECKERS_RM_REG0_UDMA_RX
#define SAFETY_CHECKERS_RM_REG0_UDMA_RX
Formula input of UDMA RX to read relevant registers from register group.
Definition: safety_checkers_soc.h:182
gSafetyCheckers_PmPllRegOffset0
static uint32_t gSafetyCheckers_PmPllRegOffset0[]
This defines the array holding register offset values for the each PLL's.
Definition: safety_checkers_soc.h:231
SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS
#define SAFETY_CHECKERS_PM_PLL_BASE_ADDRESS(i)
Each PLL base addresses.
Definition: safety_checkers_pm_soc.h:88
gSafetyCheckers_PmPllRegOffset2
static uint32_t gSafetyCheckers_PmPllRegOffset2[]
Definition: safety_checkers_soc.h:242
SAFETY_CHECKERS_RM_BA0_IA_IMAP
#define SAFETY_CHECKERS_RM_BA0_IA_IMAP
RM IAIMAP module base addresses.
Definition: safety_checkers_soc.h:139
SAFETY_CHECKERS_RM_REG0_UDMA_GCFG
#define SAFETY_CHECKERS_RM_REG0_UDMA_GCFG
Formula input of UDMA GCFG to read relevant registers from register group.
Definition: safety_checkers_soc.h:204
SAFETY_CHECKERS_PM_PLL2_LENGTH
#define SAFETY_CHECKERS_PM_PLL2_LENGTH
Definition: safety_checkers_soc.h:85
SAFETY_CHECKERS_RM_REG1_UDMA_GCFG
#define SAFETY_CHECKERS_RM_REG1_UDMA_GCFG
Definition: safety_checkers_soc.h:205
SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG
#define SAFETY_CHECKERS_RM_SUBMOD1_UDMA_GCFG
Definition: safety_checkers_soc.h:210
SAFETY_CHECKERS_RM_SUBMOD0_RA
#define SAFETY_CHECKERS_RM_SUBMOD0_RA
Number of registers in RA register group.
Definition: safety_checkers_soc.h:162
SAFETY_CHECKERS_RM_BA1_RA
#define SAFETY_CHECKERS_RM_BA1_RA
Definition: safety_checkers_soc.h:151
SAFETY_CHECKERS_RM_BA2_UDMA_RX
#define SAFETY_CHECKERS_RM_BA2_UDMA_RX
Definition: safety_checkers_soc.h:179
SAFETY_CHECKERS_RM_REG1_IA_IMAP
#define SAFETY_CHECKERS_RM_REG1_IA_IMAP
Definition: safety_checkers_soc.h:144
SAFETY_CHECKERS_RM_IR_REG2_NUM
#define SAFETY_CHECKERS_RM_IR_REG2_NUM
Definition: safety_checkers_soc.h:133
SAFETY_CHECKERS_PM_PLL1_LENGTH
#define SAFETY_CHECKERS_PM_PLL1_LENGTH
Definition: safety_checkers_soc.h:84
SAFETY_CHECKERS_PM_PLL18_LENGTH
#define SAFETY_CHECKERS_PM_PLL18_LENGTH
Definition: safety_checkers_soc.h:92
SAFETY_CHECKERS_RM_RA_REG1_NUM
#define SAFETY_CHECKERS_RM_RA_REG1_NUM
Definition: safety_checkers_soc.h:157
SAFETY_CHECKERS_RM_BA1_IR
#define SAFETY_CHECKERS_RM_BA1_IR
Definition: safety_checkers_soc.h:127
SafetyCheckers_PmPllData
Structure to hold the base address and the length of PLLs.
Definition: safety_checkers_pm.h:110
SAFETY_CHECKERS_PM_PLL17_LENGTH
#define SAFETY_CHECKERS_PM_PLL17_LENGTH
Definition: safety_checkers_soc.h:91
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_TX
Number of registers in UDMA TX register group.
Definition: safety_checkers_soc.h:174
SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM
#define SAFETY_CHECKERS_RM_IR_SUBMOD0_NUM
Number of registers in IR register group.
Definition: safety_checkers_soc.h:136
SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM
#define SAFETY_CHECKERS_PM_WKUP_MD_STAT_NUM
Definition: safety_checkers_soc.h:78
SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG
#define SAFETY_CHECKERS_RM_SUBMOD2_UDMA_GCFG
Definition: safety_checkers_soc.h:211
SAFETY_CHECKERS_PM_PLL15_LENGTH
#define SAFETY_CHECKERS_PM_PLL15_LENGTH
Definition: safety_checkers_soc.h:89
SAFETY_CHECKERS_PM_PLL12_LENGTH
#define SAFETY_CHECKERS_PM_PLL12_LENGTH
Definition: safety_checkers_soc.h:88
gSafetyCheckers_PmMcuPllRegOffset0
static uint32_t gSafetyCheckers_PmMcuPllRegOffset0[]
Definition: safety_checkers_soc.h:276
SAFETY_CHECKERS_RM_BA3_RA
#define SAFETY_CHECKERS_RM_BA3_RA
Definition: safety_checkers_soc.h:153
SAFETY_CHECKERS_RM_BA2_RA
#define SAFETY_CHECKERS_RM_BA2_RA
Definition: safety_checkers_soc.h:152
SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS
#define SAFETY_CHECKERS_PM_WKUP_PSC_BASE_ADDRESS
WKUP PSC base address.
Definition: safety_checkers_pm_soc.h:80
SAFETY_CHECKERS_RM_REG0_UDMA_TX
#define SAFETY_CHECKERS_RM_REG0_UDMA_TX
Formula input of UDMA TX to read relevant registers from register group.
Definition: safety_checkers_soc.h:170
SAFETY_CHECKERS_RM_REG1_UDMA_TX
#define SAFETY_CHECKERS_RM_REG1_UDMA_TX
Definition: safety_checkers_soc.h:171
SAFETY_CHECKERS_RM_BA1_UDMA_GCFG
#define SAFETY_CHECKERS_RM_BA1_UDMA_GCFG
Definition: safety_checkers_soc.h:200
SAFETY_CHECKERS_RM_RA_REG2_NUM
#define SAFETY_CHECKERS_RM_RA_REG2_NUM
Definition: safety_checkers_soc.h:158
SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM
#define SAFETY_CHECKERS_PM_WKUP_PD_STAT_NUM
PD STAT and MD STAT registers details for PSC.
Definition: safety_checkers_soc.h:77
SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS
#define SAFETY_CHECKERS_PM_PSC_BASE_ADDRESS
PLL and PSC base addresses.
Definition: safety_checkers_soc.h:72
SAFETY_CHECKERS_PM_MD_STAT_NUM
#define SAFETY_CHECKERS_PM_MD_STAT_NUM
Definition: safety_checkers_soc.h:80
SAFETY_CHECKERS_RM_BA0_UDMA_RX
#define SAFETY_CHECKERS_RM_BA0_UDMA_RX
RM UDMA RX module base addresses.
Definition: safety_checkers_soc.h:177
SAFETY_CHECKERS_RM_BA2_UDMA_GCFG
#define SAFETY_CHECKERS_RM_BA2_UDMA_GCFG
Definition: safety_checkers_soc.h:201
SAFETY_CHECKERS_RM_BA1_UDMA_RX
#define SAFETY_CHECKERS_RM_BA1_UDMA_RX
Definition: safety_checkers_soc.h:178
SafetyCheckers_RmRegData
Structure to hold the base address and the register details of RM control module registers.
Definition: safety_checkers_rm.h:110
SAFETY_CHECKERS_RM_BA2_IR
#define SAFETY_CHECKERS_RM_BA2_IR
Definition: safety_checkers_soc.h:128
SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS
#define SAFETY_CHECKERS_PM_MCU_PLL_BASE_ADDRESS(i)
Definition: safety_checkers_pm_soc.h:89
SAFETY_CHECKERS_RM_REG0_UDMA_FLW
#define SAFETY_CHECKERS_RM_REG0_UDMA_FLW
Formula input of UDMA FLOW to read relevant registers from register group.
Definition: safety_checkers_soc.h:193
SAFETY_CHECKERS_PM_PLL0_LENGTH
#define SAFETY_CHECKERS_PM_PLL0_LENGTH
PLL register details.
Definition: safety_checkers_soc.h:83
SAFETY_CHECKERS_RM_BA0_RA
#define SAFETY_CHECKERS_RM_BA0_RA
RM RA module base addresses.
Definition: safety_checkers_soc.h:150
SAFETY_CHECKERS_RM_REG_HEX8
#define SAFETY_CHECKERS_RM_REG_HEX8
Definition: safety_checkers_rm_soc.h:78
SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH
#define SAFETY_CHECKERS_PM_MCU_PLL0_LENGTH
Definition: safety_checkers_soc.h:93
SAFETY_CHECKERS_RM_BA1_IA_IMAP
#define SAFETY_CHECKERS_RM_BA1_IA_IMAP
Definition: safety_checkers_soc.h:140
SAFETY_CHECKERS_RM_REG_HEX100
#define SAFETY_CHECKERS_RM_REG_HEX100
Definition: safety_checkers_rm_soc.h:80
SAFETY_CHECKERS_RM_REG0_IA_IMAP
#define SAFETY_CHECKERS_RM_REG0_IA_IMAP
Formula input of IAIMAP module to read relevant registers from register group.
Definition: safety_checkers_soc.h:143
SAFETY_CHECKERS_PM_PLL8_LENGTH
#define SAFETY_CHECKERS_PM_PLL8_LENGTH
Definition: safety_checkers_soc.h:87
gSafetyCheckers_PmPscData
static SafetyCheckers_PmPscData gSafetyCheckers_PmPscData[]
Structure defines PSC register base address and the total length of registers.
Definition: safety_checkers_soc.h:320
SAFETY_CHECKERS_RM_REG_HEX40
#define SAFETY_CHECKERS_RM_REG_HEX40
Definition: safety_checkers_rm_soc.h:79
gSafetyCheckers_PmPllRegOffset8
static uint32_t gSafetyCheckers_PmPllRegOffset8[]
Definition: safety_checkers_soc.h:251
SAFETY_CHECKERS_RM_RA_SUBMOD1
#define SAFETY_CHECKERS_RM_RA_SUBMOD1
Definition: safety_checkers_soc.h:163
SAFETY_CHECKERS_RM_RA_REG3_NUM
#define SAFETY_CHECKERS_RM_RA_REG3_NUM
Definition: safety_checkers_soc.h:159
SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW
#define SAFETY_CHECKERS_RM_SUBMOD0_UDMA_FLW
Number of registers in UDMA FLOW register group.
Definition: safety_checkers_soc.h:196
gSafetyCheckers_PmPllRegOffset15
static uint32_t gSafetyCheckers_PmPllRegOffset15[]
Definition: safety_checkers_soc.h:259
safety_checkers_pm_soc.h
This file contains data structures for PM safety checker module.
SAFETY_CHECKERS_RM_RA_REG0_NUM
#define SAFETY_CHECKERS_RM_RA_REG0_NUM
Formula input of RA module to read relevant registers from register group.
Definition: safety_checkers_soc.h:156
SAFETY_CHECKERS_RM_REG_HEX4
#define SAFETY_CHECKERS_RM_REG_HEX4
Definition: safety_checkers_rm_soc.h:77
SAFETY_CHECKERS_RM_REG1_UDMA_RX
#define SAFETY_CHECKERS_RM_REG1_UDMA_RX
Definition: safety_checkers_soc.h:183
safety_checkers_rm_soc.h
This file contains data structures for RM safety checker module.
SAFETY_CHECKERS_RM_BA0_UDMA_GCFG
#define SAFETY_CHECKERS_RM_BA0_UDMA_GCFG
RM UDMA GCFG module base addresses.
Definition: safety_checkers_soc.h:199
SAFETY_CHECKERS_RM_REG_HEX0
#define SAFETY_CHECKERS_RM_REG_HEX0
Offsets for RM register blobs.
Definition: safety_checkers_rm_soc.h:76
SAFETY_CHECKERS_PM_PLL16_LENGTH
#define SAFETY_CHECKERS_PM_PLL16_LENGTH
Definition: safety_checkers_soc.h:90
gSafetyCheckers_PmPllRegOffset17
static uint32_t gSafetyCheckers_PmPllRegOffset17[]
Definition: safety_checkers_soc.h:268
SAFETY_CHECKERS_RM_BA0_UDMA_FLW
#define SAFETY_CHECKERS_RM_BA0_UDMA_FLW
RM UDMA FLOW module base addresses.
Definition: safety_checkers_soc.h:190
SAFETY_CHECKERS_RM_BA0_IR
#define SAFETY_CHECKERS_RM_BA0_IR
RM IR module base addresses.
Definition: safety_checkers_soc.h:126
gSafetyCheckers_PmPllRegOffset1
static uint32_t gSafetyCheckers_PmPllRegOffset1[]
Definition: safety_checkers_soc.h:237
SAFETY_CHECKERS_RM_IR_REG1_NUM
#define SAFETY_CHECKERS_RM_IR_REG1_NUM
Definition: safety_checkers_soc.h:132