MCUSW
Spi_Cfg.h
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62 
70  /*****************************************************************************
71  Project : j721e_spi
72  Date : 2024-10-22 14:02:42
73  SW Ver : 9.0.1
74  Module Rele Ver : AUTOSAR 4.3.1 0
75 
76  This file is generated by EB Tresos
77  Do not modify this file, otherwise the software may behave in unexpected way.
78  ******************************************************************************/
79 
87 #ifndef SPI_CFG_H_
88 #define SPI_CFG_H_
89 
90 /* ========================================================================== */
91 /* Include Files */
92 /* ========================================================================== */
93 #include "Os.h"
94 #include "Dem.h"
95 #include "Det.h"
96 #include "Spi_Cbk.h"
97 
98 #ifdef __cplusplus
99 extern "C" {
100 #endif
101 
107 #define SPI_VARIANT_POST_BUILD (STD_ON)
108 
117 #define SPI_ISR_VOID (0x00U)
118 
119 #define SPI_ISR_CAT1 (0x01U)
120 
121 #define SPI_ISR_CAT2 (0x02U)
122 /* @} */
123 
128 #define SPI_CORE_COUNT (1U)
129 
131 #define SPI_CHANNELBUFFERS (SPI_IB_EB)
132 
134 #define SPI_IB_MAX_LENGTH (64U)
135 
137 #define SPI_DEV_ERROR_DETECT (STD_ON)
138 
140 #define SPI_JOB_LOG (STD_OFF)
141 
143 #define SPI_MAX_JOB_LOG (100U)
144 
145 
146 
147 
148 
149 
150 
151 
152 
153 
154 
155 
157 #define SPI_MAX_HW_DMA_UNIT (0U)
158 
160 #define SPI_DMA_ENABLE (STD_OFF)
161 
162 /*
163  * Scalability levels
164  */
166 #define SPI_LEVEL_0 (0U)
167 
168 #define SPI_LEVEL_1 (1U)
169 
170 #define SPI_LEVEL_2 (2U)
171 
173 #define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)
174 
176 #define SPI_SCALEABILITY (SPI_LEVEL_2)
177 
179 #define SPI_VERSION_INFO_API (STD_ON)
180 
182 #define SPI_HW_STATUS_API (STD_ON)
183 
185 #define SPI_CANCEL_API (STD_ON)
186 
187 /*
188  * All below macros are used for static memory allocation and can be changed to
189  * match the usecase requirements.
190  */
192 #define SPI_MAX_CHANNELS_PER_JOB (1U)
193 
195 #define SPI_MAX_JOBS_PER_SEQ (1U)
196 
198 #define SPI_MAX_CHANNELS (1U)
199 
201 #define SPI_MAX_JOBS (1U)
202 
204 #define SPI_MAX_SEQ (1U)
205 
210 #define SPI_MAX_HW_UNIT (8U)
211 
215 #define SPI_MAX_EXT_DEV (11U)
216 
217 /*
218  All below macros are used for enabling the ISR for a particular hardware.
219  */
220 
223 #define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)
224 
227 #define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)
228 
231 #define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)
232 
235 #define SPI_UNIT_MCSPI0_ACTIVE (STD_ON)
236 
239 #define SPI_UNIT_MCSPI1_ACTIVE (STD_ON)
240 
243 #define SPI_UNIT_MCSPI2_ACTIVE (STD_ON)
244 
247 #define SPI_UNIT_MCSPI3_ACTIVE (STD_ON)
248 
249 
252 #define SPI_UNIT_MCSPI4_ACTIVE (STD_ON)
253 
256 #define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)
257 
260 #define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)
261 
264 #define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)
265 
266 
267 
268 
269 
270 
271 
272 
273 
274 
275 
276 
277 
279 #define SPI_ISR_TYPE (SPI_ISR_CAT1)
280 
282 #define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)
283 
289 #define SPI_TIMEOUT_DURATION (32000U)
290 
292 #define SPI_REGISTER_READBACK_API (STD_ON)
293 
294 
296 #define SpiConf_SpiChannel_SpiChannel_0 (0U)
297 
299 #define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)
300 
301 
303 #define SpiConf_SpiJob_SpiJob_0 (0U)
304 
306 #define SpiConf_SpiSequence_SpiSequence_0 (0U)
307 
308 
310 #define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)
311 
312 #define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)
313 
314 #define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)
315 
316 #define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)
317 
318 #define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)
319 
320 #define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)
321 
322 #define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)
323 
324 #define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)
325 
326 
334 #ifndef SPI_E_HARDWARE_ERROR
335 
336 #define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
337 #endif
338 
343 #define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)
344 
345 #define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)
346 
347 #define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)
348 
349 #define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)
350 
351 #define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)
352 
353 #define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)
354 
355 #define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)
356 
357 #define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)
358 
359 #define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)
360 
361 #define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)
362 
363 #define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)
364 /* @} */
365 
370 #define SPI_HW_UNIT_CNT (11U)
371 
372 extern const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT];
373 
374 /* @} */
375 
376 /* ========================================================================== */
377 /* Structures and Enums */
378 /* ========================================================================== */
379 
380 
381 
382 
387 typedef enum
388 {
389  CSIB0 = 0U,
391  CSIB1,
393  CSIB2,
395  CSIB3,
397  CSIB4,
399  CSIB5,
401  CSIB6,
403  CSIB7,
405  CSIB8,
407  CSIB9,
409  CSIB10,
412 
414 extern void SpiApp_wbInvCache(uint8 *buf, uint16 len);
416 extern void SpiApp_wbCache(uint8 *buf, uint16 len);
418 extern void SpiApp_invCache(uint8 *buf, uint16 len);
419 
420 
421 
423 extern const struct Spi_ConfigType_s SpiDriver;
424 
425 
426 /* ========================================================================== */
427 /* Function Declarations */
428 /* ========================================================================== */
435 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void);
436 
438 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(void);
439 
441 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(void);
442 
444 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi0TxRx(void);
445 
447 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi1TxRx(void);
448 
450 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi2TxRx(void);
451 
453 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(void);
454 
456 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(void);
457 
458 
459 
460 
461 
462 #ifdef __cplusplus
463 }
464 #endif
465 
466 #endif /* #ifndef SPI_CFG_H_ */
467 
468 /* @} */
CSIB1
@ CSIB1
Definition: Spi_Cfg.h:391
CSIB3
@ CSIB3
Definition: Spi_Cfg.h:395
Spi_HwUnitType
Spi_HwUnitType
This type defines a range of HW SPI Hardware microcontroller peripheral allocated to this Job.
Definition: Spi_Cfg.h:388
SpiApp_wbCache
void SpiApp_wbCache(uint8 *buf, uint16 len)
Cache write-back function.
CSIB6
@ CSIB6
Definition: Spi_Cfg.h:401
SpiDriver
const struct Spi_ConfigType_s SpiDriver
SPI Configuration struct declaration.
CSIB10
@ CSIB10
Definition: Spi_Cfg.h:409
SPI_HW_UNIT_CNT
#define SPI_HW_UNIT_CNT
Total HW units - used for array allocation. This should be +1 of the max unit number.
Definition: Spi_Cfg.h:370
CSIB4
@ CSIB4
Definition: Spi_Cfg.h:397
SpiApp_invCache
void SpiApp_invCache(uint8 *buf, uint16 len)
Cache invalidate function.
CSIB9
@ CSIB9
Definition: Spi_Cfg.h:407
CSIB5
@ CSIB5
Definition: Spi_Cfg.h:399
FUNC
FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void)
SPI Hwunit ISR.
CSIB8
@ CSIB8
Definition: Spi_Cfg.h:405
CSIB7
@ CSIB7
Definition: Spi_Cfg.h:403
CSIB2
@ CSIB2
Definition: Spi_Cfg.h:393
Spi_HwUnitBaseAddr
const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]
SpiApp_wbInvCache
void SpiApp_wbInvCache(uint8 *buf, uint16 len)
Cache write-back invalidate function.
CSIB0
@ CSIB0
Definition: Spi_Cfg.h:389