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107 #define SPI_VARIANT_POST_BUILD (STD_ON)
117 #define SPI_ISR_VOID (0x00U)
119 #define SPI_ISR_CAT1 (0x01U)
121 #define SPI_ISR_CAT2 (0x02U)
128 #define SPI_CORE_COUNT (1U)
131 #define SPI_CHANNELBUFFERS (SPI_IB_EB)
134 #define SPI_IB_MAX_LENGTH (64U)
137 #define SPI_DEV_ERROR_DETECT (STD_ON)
140 #define SPI_JOB_LOG (STD_OFF)
143 #define SPI_MAX_JOB_LOG (100U)
157 #define SPI_MAX_HW_DMA_UNIT (0U)
160 #define SPI_DMA_ENABLE (STD_OFF)
166 #define SPI_LEVEL_0 (0U)
168 #define SPI_LEVEL_1 (1U)
170 #define SPI_LEVEL_2 (2U)
173 #define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)
176 #define SPI_SCALEABILITY (SPI_LEVEL_2)
179 #define SPI_VERSION_INFO_API (STD_ON)
182 #define SPI_HW_STATUS_API (STD_ON)
185 #define SPI_CANCEL_API (STD_ON)
192 #define SPI_MAX_CHANNELS_PER_JOB (1U)
195 #define SPI_MAX_JOBS_PER_SEQ (1U)
198 #define SPI_MAX_CHANNELS (1U)
201 #define SPI_MAX_JOBS (1U)
204 #define SPI_MAX_SEQ (1U)
210 #define SPI_MAX_HW_UNIT (8U)
215 #define SPI_MAX_EXT_DEV (11U)
223 #define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)
227 #define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)
231 #define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)
235 #define SPI_UNIT_MCSPI0_ACTIVE (STD_ON)
239 #define SPI_UNIT_MCSPI1_ACTIVE (STD_ON)
243 #define SPI_UNIT_MCSPI2_ACTIVE (STD_ON)
247 #define SPI_UNIT_MCSPI3_ACTIVE (STD_ON)
252 #define SPI_UNIT_MCSPI4_ACTIVE (STD_ON)
256 #define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)
260 #define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)
264 #define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)
279 #define SPI_ISR_TYPE (SPI_ISR_CAT1)
282 #define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)
289 #define SPI_TIMEOUT_DURATION (32000U)
292 #define SPI_REGISTER_READBACK_API (STD_ON)
296 #define SpiConf_SpiChannel_SpiChannel_0 (0U)
299 #define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)
303 #define SpiConf_SpiJob_SpiJob_0 (0U)
306 #define SpiConf_SpiSequence_SpiSequence_0 (0U)
310 #define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)
312 #define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)
314 #define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)
316 #define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)
318 #define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)
320 #define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)
322 #define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)
324 #define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)
334 #ifndef SPI_E_HARDWARE_ERROR
336 #define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
343 #define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)
345 #define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)
347 #define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)
349 #define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)
351 #define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)
353 #define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)
355 #define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)
357 #define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)
359 #define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)
361 #define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)
363 #define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)
370 #define SPI_HW_UNIT_CNT (11U)
423 extern const struct Spi_ConfigType_s
SpiDriver;
435 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(
void);
438 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(
void);
441 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(
void);
444 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcspi0TxRx(
void);
447 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcspi1TxRx(
void);
450 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcspi2TxRx(
void);
453 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(
void);
456 FUNC(
void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(
void);
@ CSIB1
Definition: Spi_Cfg.h:391
@ CSIB3
Definition: Spi_Cfg.h:395
Spi_HwUnitType
This type defines a range of HW SPI Hardware microcontroller peripheral allocated to this Job.
Definition: Spi_Cfg.h:388
void SpiApp_wbCache(uint8 *buf, uint16 len)
Cache write-back function.
@ CSIB6
Definition: Spi_Cfg.h:401
const struct Spi_ConfigType_s SpiDriver
SPI Configuration struct declaration.
@ CSIB10
Definition: Spi_Cfg.h:409
#define SPI_HW_UNIT_CNT
Total HW units - used for array allocation. This should be +1 of the max unit number.
Definition: Spi_Cfg.h:370
@ CSIB4
Definition: Spi_Cfg.h:397
void SpiApp_invCache(uint8 *buf, uint16 len)
Cache invalidate function.
@ CSIB9
Definition: Spi_Cfg.h:407
@ CSIB5
Definition: Spi_Cfg.h:399
FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void)
SPI Hwunit ISR.
@ CSIB8
Definition: Spi_Cfg.h:405
@ CSIB7
Definition: Spi_Cfg.h:403
@ CSIB2
Definition: Spi_Cfg.h:393
const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]
void SpiApp_wbInvCache(uint8 *buf, uint16 len)
Cache write-back invalidate function.
@ CSIB0
Definition: Spi_Cfg.h:389