MCUSW
Spi_Cfg.h
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62 
70  /*****************************************************************************
71  Project : j721e_spi
72  Date : 2024-10-22 14:02:42
73  SW Ver : 9.0.1
74  Module Rele Ver : AUTOSAR 4.3.1 0
75 
76  This file is generated by EB Tresos
77  Do not modify this file, otherwise the software may behave in unexpected way.
78  ******************************************************************************/
79 
87 #ifndef SPI_CFG_H_
88 #define SPI_CFG_H_
89 
90 /* ========================================================================== */
91 /* Include Files */
92 /* ========================================================================== */
93 #include "Os.h"
94 #include "Dem.h"
95 #include "Det.h"
96 #include "Spi_Cbk.h"
97 
98 #ifdef __cplusplus
99 extern "C" {
100 #endif
101 
107 #define SPI_VARIANT_POST_BUILD (STD_ON)
108 
117 #define SPI_ISR_VOID (0x00U)
119 #define SPI_ISR_CAT1 (0x01U)
121 #define SPI_ISR_CAT2 (0x02U)
122 /* @} */
123 
130 #define SPI_CHANNELBUFFERS (SPI_IB_EB)
131 
133 #define SPI_IB_MAX_LENGTH (64U)
134 
136 #define SPI_DEV_ERROR_DETECT (STD_ON)
137 
139 #define SPI_JOB_LOG (STD_OFF)
140 
142 #define SPI_MAX_JOB_LOG (100U)
143 
144 
145 
146 
147 
148 
149 
150 
151 
152 
153 
154 
156 #define SPI_MAX_HW_DMA_UNIT (0U)
157 
159 #define SPI_DMA_ENABLE (STD_OFF)
160 
161 /*
162  * Scalability levels
163  */
165 #define SPI_LEVEL_0 (0U)
167 #define SPI_LEVEL_1 (1U)
169 #define SPI_LEVEL_2 (2U)
170 
172 #define SPI_SUPPORT_CONCURRENT_SYNC_TRANSMIT (STD_OFF)
173 
175 #define SPI_SCALEABILITY (SPI_LEVEL_2)
176 
178 #define SPI_VERSION_INFO_API (STD_ON)
179 
181 #define SPI_HW_STATUS_API (STD_ON)
182 
184 #define SPI_CANCEL_API (STD_ON)
185 
186 /*
187  * All below macros are used for static memory allocation and can be changed to
188  * match the usecase requirements.
189  */
191 #define SPI_MAX_CHANNELS_PER_JOB (1U)
192 
194 #define SPI_MAX_JOBS_PER_SEQ (1U)
195 
197 #define SPI_MAX_CHANNELS (1U)
198 
200 #define SPI_MAX_JOBS (1U)
201 
203 #define SPI_MAX_SEQ (1U)
204 
209 #define SPI_MAX_HW_UNIT (8U)
210 
214 #define SPI_MAX_EXT_DEV (11U)
215 
216 /*
217  All below macros are used for enabling the ISR for a particular hardware.
218  */
219 
222 #define SPI_UNIT_MCU_MCSPI0_ACTIVE (STD_ON)
223 
226 #define SPI_UNIT_MCU_MCSPI1_ACTIVE (STD_ON)
227 
230 #define SPI_UNIT_MCU_MCSPI2_ACTIVE (STD_ON)
231 
234 #define SPI_UNIT_MCSPI0_ACTIVE (STD_ON)
235 
238 #define SPI_UNIT_MCSPI1_ACTIVE (STD_ON)
239 
242 #define SPI_UNIT_MCSPI2_ACTIVE (STD_ON)
243 
246 #define SPI_UNIT_MCSPI3_ACTIVE (STD_ON)
247 
248 
251 #define SPI_UNIT_MCSPI4_ACTIVE (STD_ON)
252 
255 #define SPI_UNIT_MCSPI5_ACTIVE (STD_OFF)
256 
259 #define SPI_UNIT_MCSPI6_ACTIVE (STD_OFF)
260 
263 #define SPI_UNIT_MCSPI7_ACTIVE (STD_OFF)
264 
265 
266 
267 
268 
269 
270 
271 
272 
273 
274 
275 
276 
278 #define SPI_ISR_TYPE (SPI_ISR_CAT1)
279 
281 #define SPI_OS_COUNTER_ID ((CounterType)OsCounter_0)
282 
288 #define SPI_TIMEOUT_DURATION (32000U)
289 
291 #define SPI_REGISTER_READBACK_API (STD_ON)
292 
293 
295 #define SpiConf_SpiChannel_SpiChannel_0 (0U)
296 
298 #define SpiConf_SpiExternalDevice_CS0 (SPI_CS0)
299 
300 
302 #define SpiConf_SpiJob_SpiJob_0 (0U)
303 
305 #define SpiConf_SpiSequence_SpiSequence_0 (0U)
306 
307 
309 #define SpiConf_SpiExternalDevice_HwUnitId0 (CSIB0)
311 #define SpiConf_SpiExternalDevice_HwUnitId1 (CSIB1)
313 #define SpiConf_SpiExternalDevice_HwUnitId2 (CSIB2)
315 #define SpiConf_SpiExternalDevice_HwUnitId3 (CSIB3)
317 #define SpiConf_SpiExternalDevice_HwUnitId4 (CSIB4)
319 #define SpiConf_SpiExternalDevice_HwUnitId5 (CSIB5)
321 #define SpiConf_SpiExternalDevice_HwUnitId6 (CSIB6)
323 #define SpiConf_SpiExternalDevice_HwUnitId7 (CSIB7)
324 
325 
333 #ifndef SPI_E_HARDWARE_ERROR
335 #define SPI_E_HARDWARE_ERROR (DemConf_DemEventParameter_SPI_E_HARDWARE_ERROR)
336 #endif
342 #define SPI_UNIT_MCU_MCSPI0 ((Spi_HWUnitType) CSIB0)
344 #define SPI_UNIT_MCU_MCSPI1 ((Spi_HWUnitType) CSIB1)
346 #define SPI_UNIT_MCU_MCSPI2 ((Spi_HWUnitType) CSIB2)
348 #define SPI_UNIT_MCSPI0 ((Spi_HWUnitType) CSIB3)
350 #define SPI_UNIT_MCSPI1 ((Spi_HWUnitType) CSIB4)
352 #define SPI_UNIT_MCSPI2 ((Spi_HWUnitType) CSIB5)
354 #define SPI_UNIT_MCSPI3 ((Spi_HWUnitType) CSIB6)
356 #define SPI_UNIT_MCSPI4 ((Spi_HWUnitType) CSIB7)
358 #define SPI_UNIT_MCSPI5 ((Spi_HWUnitType) CSIB8)
360 #define SPI_UNIT_MCSPI6 ((Spi_HWUnitType) CSIB9)
362 #define SPI_UNIT_MCSPI7 ((Spi_HWUnitType) CSIB10)
363 /* @} */
364 
369 #define SPI_HW_UNIT_CNT (11U)
370 
371 extern const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT];
372 
373 /* @} */
374 
375 /* ========================================================================== */
376 /* Structures and Enums */
377 /* ========================================================================== */
378 
379 
380 
381 
386 typedef enum
387 {
388  CSIB0 = 0U,
390  CSIB1,
392  CSIB2,
394  CSIB3,
396  CSIB4,
398  CSIB5,
400  CSIB6,
402  CSIB7,
404  CSIB8,
406  CSIB9,
408  CSIB10,
411 
413 extern void SpiApp_wbInvCache(uint8 *buf, uint16 len);
415 extern void SpiApp_wbCache(uint8 *buf, uint16 len);
417 extern void SpiApp_invCache(uint8 *buf, uint16 len);
418 
419 
420 
422 extern const struct Spi_ConfigType_s SpiDriver;
423 
424 
425 /* ========================================================================== */
426 /* Function Declarations */
427 /* ========================================================================== */
434 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi0TxRx(void);
435 
437 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi1TxRx(void);
438 
440 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcuMcspi2TxRx(void);
441 
443 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi0TxRx(void);
444 
446 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi1TxRx(void);
447 
449 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi2TxRx(void);
450 
452 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi3TxRx(void);
453 
455 FUNC(void, SPI_CODE_FAST) Spi_IrqUnitMcspi4TxRx(void);
456 
457 
458 
459 
460 
461 #ifdef __cplusplus
462 }
463 #endif
464 
465 #endif /* #ifndef SPI_CFG_H_ */
466 
467 /* @} */
void Spi_IrqUnitMcspi4TxRx(void)
SPI MCSPI4 ISR.
void Spi_IrqUnitMcspi1TxRx(void)
SPI MCSPI1 ISR.
void Spi_IrqUnitMcuMcspi0TxRx(void)
SPI Hwunit ISR.
void Spi_IrqUnitMcuMcspi1TxRx(void)
SPI MCU_MCSPI1 ISR.
const uint32 Spi_HwUnitBaseAddr[SPI_HW_UNIT_CNT]
void SpiApp_wbCache(uint8 *buf, uint16 len)
Cache write-back function.
const struct Spi_ConfigType_s SpiDriver
SPI Configuration struct declaration.
void Spi_IrqUnitMcspi3TxRx(void)
SPI MCSPI3 ISR.
Spi_HwUnitType
This type defines a range of HW SPI Hardware microcontroller peripheral allocated to this Job.
Definition: Spi_Cfg.h:387
void Spi_IrqUnitMcspi0TxRx(void)
SPI MCSPI0 ISR.
void Spi_IrqUnitMcuMcspi2TxRx(void)
SPI MCU_MCSPI2 ISR.
void SpiApp_wbInvCache(uint8 *buf, uint16 len)
Cache write-back invalidate function.
void SpiApp_invCache(uint8 *buf, uint16 len)
Cache invalidate function.
#define SPI_HW_UNIT_CNT
Total HW units - used for array allocation. This should be +1 of the max unit number.
Definition: Spi_Cfg.h:369
void Spi_IrqUnitMcspi2TxRx(void)
SPI MCSPI2 ISR.
@ CSIB5
Definition: Spi_Cfg.h:398
@ CSIB8
Definition: Spi_Cfg.h:404
@ CSIB0
Definition: Spi_Cfg.h:388
@ CSIB4
Definition: Spi_Cfg.h:396
@ CSIB9
Definition: Spi_Cfg.h:406
@ CSIB2
Definition: Spi_Cfg.h:392
@ CSIB1
Definition: Spi_Cfg.h:390
@ CSIB3
Definition: Spi_Cfg.h:394
@ CSIB6
Definition: Spi_Cfg.h:400
@ CSIB10
Definition: Spi_Cfg.h:408
@ CSIB7
Definition: Spi_Cfg.h:402