MCUSW
Fls_NOR_Device.h
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62 
71  /*****************************************************************************
72  Project: FLS_J721E
73  Date : 2024-09-30 07:37:25
74  This file is generated by EB Tresos
75  Do not modify this file, otherwise the software may behave in unexpected way.
76  ******************************************************************************/
77 
78 #ifndef FLS_NOR_DEVICE_H_
79 #define FLS_NOR_DEVICE_H_
80 
81 /**************************************************************************
82  Macro Definitions
83  **************************************************************************/
86 #define EXT_ADDRESS_ENABLE (0U)
87 
88 /* Selected Flash M35XU512_3BYTE_ADDRESSING */
89 
90 
91 
92 /* NOR Block Size in bytes */
93 #define NOR_BLOCK_SIZE (131072U)
94 
95 /* NOR Sector Size in bytes */
96 #define NOR_UNIFORM_SECTOR_SIZE (4096U)
97 
98 /* NOR Hybrid Sector Size in bytes. Uniform Address space consists of all 256 KB Sectors */
99 #define NOR_SECTOR_SIZE (4096U)
100 
101 /* Total NOR Size in bytes */
102 #define NOR_SIZE (67108864U)
103 
104 /* Number of 4K sectors in the NOR flash */
105 #define NOR_NUM_4K_SECTORS (16384U)
106 
107 
108 /* Total number of sectors in the NOR flash */
109 #define NOR_NUM_SECTORS (NOR_SIZE / NOR_UNIFORM_SECTOR_SIZE)
110 
111 
112 /* Total number of blocks in the NOR flash */
113 #define NOR_NUM_BLOCKS (NOR_SIZE / NOR_BLOCK_SIZE)
114 
115 /* Page size of the NOR flash in bytes */
116 #define NOR_PAGE_SIZE (256U)
117 
118 /* Number of pages per sector */
119 #define NOR_NUM_PAGES_PER_SECTOR (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
120 
121 /* Number of pages per block */
122 #define NOR_NUM_PAGES_PER_BLOCK (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)
123 
124 /* Value of erased data */
125 #define NOR_ERASED_DATA (0xffU)
126 
127 /* Offset for the bottom of the 4K sector */
128 #define NOR_4K_SECT_BOT_END_OFFSET (0x0U)
129 
130 /* Number of sectors in the BE (Block Erase) region */
131 #define NOR_BE_SECTOR_NUM (-1U)
132 
133 /* Bulk Erase command for the NOR flash */
134 #define NOR_CMD_BULK_ERASE (0x60U)
135 
136 /* Write Register command */
137 #define NOR_CMD_WRREG (0x1U)
138 
139 /* Write Enable command */
140 #define NOR_CMD_WREN (0x6U)
141 
142 /* Write Disable command */
143 #define NOR_CMD_WRDIS (0x0U)
144 
145 /* Read Status Register command */
146 #define NOR_CMD_RDSR (0x5U)
147 
148 /* Read Status Register 2 command */
149 #define NOR_CMD_RDSR2 (0x0U)
150 
151 /* Register Read command */
152 #define NOR_CMD_RDREG (0x0U)
153 
154 /* Read Configuration Register command */
155 #define NOR_CMD_RDCR (0x0U)
156 
157 #define NOR_CMD_RDID (0x9fU)
158 
159 /* Software Reset Enable command */
160 #define NOR_CMD_SRSTE (0x66U)
161 
162 /* Software Reset command */
163 #define NOR_CMD_SFRST (0x99U)
164 
165 /* Block Erase command */
166 #define NOR_CMD_BLOCK_ERASE (0xd8U)
167 
168 /* Sector Erase command */
169 #define NOR_CMD_SECTOR_ERASE (0x20U)
170 
171 /* Standard Read command */
172 #define NOR_CMD_READ (0x3U)
173 
174 /* Fast Read command */
175 #define NOR_CMD_FAST_READ (0xbU)
176 
177 /* Octal Read command (calculated based on sector size) */
178 #define NOR_CMD_OCTAL_READ (0x8bU)
179 
180 /* Octal DDR Read command (calculated based on NOR size and sector size) */
181 #define NOR_CMD_OCTAL_DDR_READ (0x0U)
182 
183 /* Page Program command */
184 #define NOR_CMD_PAGE_PROG (0x2U)
185 
186 /* Octal Program command */
187 #define NOR_CMD_OCTAL_PROG (0x82U)
188 
189 /* Write VCR (Volatile Configuration Register) command */
190 #define NOR_CMD_WRITE_VCR (0x81U)
191 
192 /* Read VCR (Volatile Configuration Register) command */
193 #define NOR_CMD_READ_VCR (0x85U)
194 
195 /* Offset for the volatile register */
196 #define NOR_VREG_OFFSET (0x0U)
197 
198 /* Offset for the non-volatile register */
199 #define NOR_NVREG_OFFSET (0x0U)
200 
201 /* Non-Volatile Status Register 1 address */
202 #define NOR_STS1_NVREG_ADDR (0x0U)
203 
204 /* Non-Volatile Status Register 2 address */
205 #define NOR_STS2_NVREG_ADDR (0x0U)
206 
207 /* Non-Volatile Configuration Register 1 address */
208 #define NOR_CFG1_NVREG_ADDR (0x0U)
209 
210 /* Non-Volatile Configuration Register 2 address */
211 #define NOR_CFG2_NVREG_ADDR (0x0U)
212 
213 /* Non-Volatile Configuration Register 3 address */
214 #define NOR_CFG3_NVREG_ADDR (0x0U)
215 
216 /* Non-Volatile Configuration Register 4 address */
217 #define NOR_CFG4_NVREG_ADDR (0x0U)
218 
219 /* Non-Volatile Configuration Register 5 address */
220 #define NOR_CFG5_NVREG_ADDR (0x0U)
221 
222 /* Volatile Status Register 1 address */
223 #define NOR_STS1_VREG_ADDR (0x0U)
224 
225 /* Volatile Status Register 2 address */
226 #define NOR_STS2_VREG_ADDR (0x0U)
227 
228 /* Volatile Configuration Register 1 address */
229 #define NOR_CFG1_VREG_ADDR (0x0U)
230 
231 /* Volatile Configuration Register 2 address */
232 #define NOR_CFG2_VREG_ADDR (0x0U)
233 
234 /* Volatile Configuration Register 3 address */
235 #define NOR_CFG3_VREG_ADDR (0x0U)
236 
237 /* Volatile Configuration Register 4 address */
238 #define NOR_CFG4_VREG_ADDR (0x0U)
239 
240 /* Volatile Configuration Register 5 address */
241 #define NOR_CFG5_VREG_ADDR (0x0U)
242 
244 #define NOR_RDID_NUM_BYTES (0x3U)
245 #define NOR_MANF_ID (0x2cU) /* Manufacturer ID */
246 #define NOR_DEVICE_ID (0x5b1aU) /* Device ID */
247 
249 #define NOR_SR_WIP ((1U) << 0U)
250 
252 #define NOR_SR_WRPGEN ((1U) << 1U)
253 
255 #define NOR_CR_TBPARM ((1U) << 2U)
256 
257 #define NOR_CMD_RDCR_VOL (0x85U)
258 #define NOR_CMD_RDCR_NVOL (0xb5U)
259 #define NOR_CMD_OCTAL_O_FAST_RD (0x8bU)
260 #define NOR_CMD_OCTAL_IO_FAST_RD (0xcbU)
261 #define NOR_CMD_OCTAL_FAST_PROG (0x82U)
262 #define NOR_CMD_EXT_OCTAL_FAST_PROG (0xc2U)
263 #define NOR_CMD_QUAD_O_FAST_RD (0x6bU)
264 #define NOR_CMD_QUAD_IO_FAST_RD (0xebU)
265 #define NOR_CMD_QUAD_DDR_O_FAST_RD (0x6dU)
266 #define NOR_CMD_QUAD_FAST_PROG (0x32U)
267 #define NOR_CMD_EXT_QUAD_FAST_PROG (0x38U)
268 #define NOR_CMD_OCTAL_DDR_O_FAST_RD (0x9dU)
269 #define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xfdU)
270 
271 #define NOR_CMD_READ_ENVCR (0x65U)
272 
273 #define NOR_CMD_WRITE_NVCR (0xb1U)
274 #define NOR_CMD_READ_NVCR (0xb5U)
275 #define NOR_CMD_WRITE_ENVCR (0x61U)
276 
278 #define NOR_SINGLE_READ_DUMMY_CYCLE ((0U))
279 #define NOR_SINGLE_CMD_READ_DUMMY_CYCLE (1U)
280 #define NOR_OCTAL_SDR_CMD_READ_DUMMY_CYCLE (3U)
281 #define NOR_OCTAL_DDR_CMD_READ_DUMMY_CYCLE (4U)
282 #define NOR_OCTAL_READ_DUMMY_CYCLE (30U)
283 #define NOR_OCTAL_READ_DUMMY_CYCLE_LC (0x0U)
284 #define NOR_OCTAL_READ_DUMMY_CYCLE_INDAC (0U)
285 #define NOR_OCTAL_READ_DUMMY_CYCLE_LC_INDAC (0x0U)
286 #define NOR_QUAD_READ_DUMMY_CYCLE (10U)
287 
289 #define NOR_RDID_CMD_LENGTH_SINGLE (0U)
290 #define NOR_RDID_CMD_LENGTH_OCTAL (0U)
291 
293 #define NOR_PAGE_PROG_TIMEOUT (400U)
294 #define NOR_SECTOR_ERASE_TIMEOUT (600000U)
295 #define NOR_WRR_WRITE_TIMEOUT (600000U)
296 #define NOR_BULK_ERASE_TIMEOUT (110000000U)
297 
298 
299 #endif /* DEVICE_H_ */
300 
301 /* Nothing past this point */