88 #ifndef CDD_IPC_CFG_H_
89 #define CDD_IPC_CFG_H_
103 #include <CddIpc/ipc_baremetal_hw/include/ipc_config.h>
123 #define CDD_IPC_PRE_COMPILE_VARIANT (STD_ON)
132 #define CDD_IPC_ISR_VOID (0x00U)
134 #define CDD_IPC_ISR_CAT1 (0x01U)
136 #define CDD_IPC_ISR_CAT2 (0x02U)
145 #define CDD_IPC_DEV_ERROR_DETECT (STD_ON)
153 #define CDD_IPC_ISR_TYPE (CDD_IPC_ISR_CAT1)
166 #define CDD_IPC_VERSION_INFO_API (STD_ON)
174 #define CDD_IPC_DEINIT_API (STD_ON)
182 #define CDD_IPC_ANNOUNCE_API (STD_ON)
190 #define CDD_IPC_REGISTER_READBACK_API (STD_ON)
198 #define CDD_IPC_SAFETY_DIAGNOSTIC_API (STD_ON)
207 #define CDD_IPC_IS_INIT_DONE_API (STD_ON)
217 #define CDD_IPC_GET_MAX_MSG_SIZE_API (STD_ON)
233 #define CDD_IPC_OS_COUNTER_ID ((CounterType)OsCounter_0)
248 #ifndef CDD_IPC_E_HARDWARE_ERROR
250 #define CDD_IPC_E_HARDWARE_ERROR (DemConf_DemEventParameter_CDD_IPC_E_HARDWARE_ERROR)
264 #define CDD_IPC_CORE_MCU1_0 (1U)
266 #define CDD_IPC_CORE_MCU1_1 (2U)
268 #define CDD_IPC_CORE_MCU2_0 (3U)
270 #define CDD_IPC_CORE_MCU2_1 (4U)
272 #define CDD_IPC_CORE_MCU3_0 (5U)
274 #define CDD_IPC_CORE_MCU3_1 (6U)
276 #define CDD_IPC_CORE_C66X_1 (7U)
278 #define CDD_IPC_CORE_C66X_2 (8U)
280 #define CDD_IPC_CORE_C7X_1 (9U)
282 #define CDD_IPC_CORE_MAX_PROCS (11U)
286 #define CDD_IPC_OWN_CORE_ID (CDD_IPC_CORE_MCU1_0)
288 #define CDD_IPC_REMOTE_CORE_MCU2_0_USED
304 #define CDD_IPC_VERTIO_OBJECT_SIZE (0x1000U)
317 #define CddIpcConf_IpcComChanId_Cdd_IpcMcu20 (0U)
326 #define CDD_IPC_RPMSG_OBJ_SIZE (256U)
328 #define CDD_IPC_CH_0_BUFF_SIZE ((256U * (496U + 32U)) + CDD_IPC_RPMSG_OBJ_SIZE)
330 #define CDD_IPC_MAX_CHANNEL_CFG (2U)
337 #define IPC_VRING_BUFFER_SIZE (0x1C00000U)
340 #define IPC_MPU1_0 (0U)
341 #define IPC_MCU1_0 (1U)
342 #define IPC_MCU1_1 (2U)
343 #define IPC_MCU2_0 (3U)
344 #define IPC_MCU2_1 (4U)
345 #define IPC_MCU3_0 (5U)
346 #define IPC_MCU3_1 (6U)
347 #define IPC_C66X_1 (7U)
348 #define IPC_C66X_2 (8U)
349 #define IPC_C7X_1 (9U)
350 #define IPC_MPU1_1 (10U)
351 #define IPC_MAX_PROCS (11U)
355 #define CDD_IPC_CORE_ID_MAX (11U)
357 #define CDD_IPC_CORE_USED (1U)
358 #define IPC_MAILBOX_CLUSTER_CNT (12U)
397 #define CDD_IPC_NEW_MSG_NTFY_FXN Cdd_IpcNewMessageNotify
399 #if (STD_ON == CDD_IPC_ANNOUNCE_API)
413 #define CDD_IPC_NEW_CTRL_MSG_NTFY_FXN Cdd_IpcNewCtrlMessageNotify
#define IPC_MAX_PROCS
Definition: Cdd_IpcCfg.h:351
const uint32 IPC_Mailbox_BasePhyAddr[IPC_MAILBOX_CLUSTER_CNT]
#define IPC_MAILBOX_CLUSTER_CNT
Definition: Cdd_IpcCfg.h:358
void Cdd_IpcNewMessageNotify(void)
New Message notification function.
Ipc_MailboxInfo g_IPC_MailboxInfo[IPC_MAX_PROCS][IPC_MAX_PROCS]
void Cdd_IpcIrqMbxFromMcu_20(void)
A Mailbox can raise multiple interrupts. In this implementation, the Mailbox new message interrupt is...
#define CDD_IPC_VERTIO_OBJECT_SIZE
Definition: Cdd_IpcCfg.h:304
uint8 Cdd_IpcDrvVertIoObj[CDD_IPC_VERTIO_OBJECT_SIZE]
Communication Channels configured.
const struct Cdd_IpcConfigType_s CddIpcConfiguraions_PC
Ipc_ProcInfo g_Ipc_mp_procInfo[IPC_MAX_PROCS]
Processor IDs to name mapping for all processor in Jacinto7.
void Cdd_IpcNewCtrlMessageNotify(uint32 remoteProcId)
New Control Message notification function.