MCUSW
Eth_Cfg.h
Go to the documentation of this file.
1 /*
2 *
3 * Copyright (c) 2024 Texas Instruments Incorporated
4 *
5 * All rights reserved not granted herein.
6 *
7 * Limited License.
8 *
9 * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
10 * license under copyrights and patents it now or hereafter owns or controls to make,
11 * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
12 * terms herein. With respect to the foregoing patent license, such license is granted
13 * solely to the extent that any such patent is necessary to Utilize the software alone.
14 * The patent license shall not apply to any combinations which include this software,
15 * other than combinations with devices manufactured by or for TI ("TI Devices").
16 * No hardware patent is licensed hereunder.
17 *
18 * Redistributions must preserve existing copyright notices and reproduce this license
19 * (including the above copyright notice and the disclaimer and (if applicable) source
20 * code license limitations below) in the documentation and/or other materials provided
21 * with the distribution
22 *
23 * Redistribution and use in binary form, without modification, are permitted provided
24 * that the following conditions are met:
25 *
26 * * No reverse engineering, decompilation, or disassembly of this software is
27 * permitted with respect to any software provided in binary form.
28 *
29 * * any redistribution and use are licensed by TI for use only with TI Devices.
30 *
31 * * Nothing shall obligate TI to provide you with source code for the software
32 * licensed and provided to you in object code.
33 *
34 * If software source code is provided to you, modification and redistribution of the
35 * source code are permitted provided that the following conditions are met:
36 *
37 * * any redistribution and use of the source code, including any resulting derivative
38 * works, are licensed by TI for use only with TI Devices.
39 *
40 * * any redistribution and use of any object code compiled from the source code
41 * and any resulting derivative works, are licensed by TI for use only with TI Devices.
42 *
43 * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
44 *
45 * may be used to endorse or promote products derived from this software without
46 * specific prior written permission.
47 *
48 * DISCLAIMER.
49 *
50 * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
51 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
52 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
53 * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
54 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
55 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
56 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
57 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
58 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
59 * OF THE POSSIBILITY OF SUCH DAMAGE.
60 *
61 */
62 
69 /*******************************************************************************
70  Project : J721E
71  Date : 2025-04-18 12:22:03
72  SW Ver : 11.0.0
73  Module Rele Ver : AUTOSAR 4.3.1 0
74 
75  This file is generated by EB Tresos
76  Do not modify this file,otherwise the software may behave in unexpected way.
77 *******************************************************************************/
78 
86 #ifndef ETH_CFG_H_
87 #define ETH_CFG_H_
88 
89 /* ========================================================================== */
90 /* Include Files */
91 /* ========================================================================== */
92 #include "Os.h"
93 #include "Eth_LL_Types.h"
94 #include "Udma_Types.h"
95 #include "Eth_Rpc.h"
96 
97 #ifdef __cplusplus
98 extern "C" {
99 #endif
100 
101 /* ========================================================================== */
102 /* Macros & Typedefs */
103 /* ========================================================================== */
105 #define ETH_VERSION_INFO_API (STD_ON)
106 
108 #define ETH_GLOBALTIMESUPPORT_API (STD_ON)
109 
111 #define ETH_DEV_ERROR_DETECT (STD_ON)
112 
114 #define ETH_GET_COUNTER_VALUES_API (STD_ON)
115 
117 #define ETH_GET_RX_STATS_API (STD_ON)
118 
120 #define ETH_GET_TX_STATS_API (STD_ON)
121 
123 #define ETH_GET_TX_ERROR_COUNTERSVALUES_API (STD_ON)
124 
126 #define ETH_ZERO_COPY_API (STD_OFF)
127 
129 #define ETH_HEADER_ACCESS_API (STD_OFF)
130 
132 #define ETH_TRAFFIC_SHAPING_API (STD_OFF)
133 
135 #define ETH_GET_COUNTER_STATE_API (STD_OFF)
136 
137 
139 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_ICMP (STD_OFF)
140 
142 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_IPV4 (STD_OFF)
143 
145 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_TCP (STD_OFF)
146 
148 #define ETH_CTRL_ENABLE_OFFLOAD_CHECKSUM_UDP (STD_OFF)
149 
151 #define ETH_REGISTER_READBACK_API (STD_ON)
152 
154 #define ETH_TIMESTAMP_VIA_CPTS_EVENT_FIFO (STD_ON)
155 
157 #define ETH_PHY_FAULT_DETECTION_ENABLE (STD_ON)
158 
160 #define ETH_ENABLE_MII_API (STD_ON)
161 
163 #define ETH_UPDATE_PHYS_ADDR_FILTER_API (STD_ON)
164 
166 #define ETH_ENABLE_IRQ_PACING (STD_OFF)
167 
169 #define ETH_VIRTUALMAC_NOTIFYMSGRECEIVED_API (STD_OFF)
170 
172 #define ETH_VIRTUALMAC_SUBSCRIBEALLTRAFFIC_API (STD_OFF)
173 
175 #define ETH_VIRTUALMAC_UNSUBSCRIBEALLTRAFFIC_API (STD_OFF)
176 
178 #define ETH_VIRTUALMAC_SUBSCRIBEDSTMAC_API (STD_OFF)
179 
181 #define ETH_VIRTUALMAC_UNSUBSCRIBEDSTMAC_API (STD_OFF)
182 
184 #define ETH_VIRTUALMAC_ASSOCIATEIPV4MACADDR_API (STD_OFF)
185 
187 #define ETH_VIRTUALMAC_DISASSOCIATEIPV4MACADDR_API (STD_OFF)
188 
190 #define ETH_VIRTUALMAC_ADD_MCAST_MACADDR_API (STD_OFF)
191 
193 #define ETH_VIRTUALMAC_DEL_MACADDR_API (STD_OFF)
194 
196 #define ETH_VIRTUALMAC_ADD_VLAN_API (STD_OFF)
197 
199 #define ETH_VIRTUALMAC_DEL_VLAN_API (STD_OFF)
200 
201 
203 #define ETH_ETHIF_CBK_HEADER "EthIf_Cbk.h"
204 
206 #define ETH_ISR_TYPE (ETH_ISR_CAT2)
208 #define ETH_OS_COUNTER_ID ((CounterType)OsCounter_0)
210 #define ETH_OS_COUNTER_FREQ (1000000000U)
211 
213 #define ETH_INVALID_RING_ID (0xFFFFU)
215 #define ETH_INVALID_EVENT_ID (0xFFFFU)
217 #define ETH_INVALID_CHAN_ID (0xFFFFU)
219 #define ETH_INVALID_FLOW_ID (0xFFFFU)
221 #define ETH_INVALID_IRQ_ID (0xFFFFU)
223 #define ETH_DEM_NO_EVENT (0xFFFFU)
224 
226 #define ETH_VIRTUALMAC_SUPPORT (STD_OFF)
228 #define ETH_VIRTUALMAC_FWINFO_TIMEOUT (0U)
229 
230 
236 #define EthConf_EthCtrlConfig_EthConfig_0 (0U)
237 #define ETH_CTRL_ID_0 (0U)
238 /* @} */
239 
244 #define ETH_PRE_COMPILE_VARIANT (STD_ON)
245 #define ETH_LINK_TIME_VARIANT (STD_OFF)
246 #define ETH_POST_BUILD_VARIANT (STD_OFF)
247 /* @} */
248 
252 #define ETH_CTRL_ID_MAX (1U)
253 
254 
261 #define NOP1 asm (" NOP ")
262 #define NOP5 NOP1; NOP1; NOP1; NOP1; NOP1
263 #define NOP10 NOP5; NOP5
264 #define NOP20 NOP10; NOP10
265 #define NOP30 NOP20; NOP10
266 #define NOP40 NOP30; NOP10
267 #define NOP50 NOP40; NOP10
268 #define NOP100 NOP50; NOP50
269 #define NOP200 NOP100; NOP100
270 #define NOP300 NOP200; NOP100
271 #define NOP400 NOP300; NOP100
272 #define NOP500 NOP400; NOP100
273 /* @} */
274 
279 #define ETH_DMA_IR_SUPPORT (STD_ON)
280 #define ETH_DMA_CQ_RING_SUPPORT (STD_ON)
281 #define ETH_DMA_TEARDOWN_SUPPORT (STD_ON)
282 #define ETH_DMA_PROXY_SUPPORT (STD_ON)
283 #define ETH_DMA_RX_CH_SPERATE (STD_OFF)
284 /* @} */
285 
290 #define UDMA_DEVICE_ID_RING (235U)
291 #define UDMA_DEVICE_ID_UDMA (236U)
292 #define UDMA_DEVICE_ID_PSIL (232U)
293 #define UDMA_DEVICE_ID_IA (233U)
294 #define UDMA_DEVICE_ID_IR (237U)
295 #define UDMA_DEVICE_ID_CORE (250U)
296 #define UDMA_DEVICE_ID_PROXY (234U)
297 /* @} */
298 
303 #define UDMA_TX_CHANNEL_PEER_OFFSET (0xf000U)
304 #define UDMA_RX_CHANNEL_PEER_OFFSET (0x7000U)
305 #define UDMA_SOURCE_THREAD_OFFSET (0x6000U)
306 #define UDMA_DEST_THREAD_OFFSET (0xe000U)
307 /* @} */
308 
313 #define ETH_DMA_TX_BASE_REG (0x2aa00000U)
314 #define ETH_DMA_RX_BASE_REG (0x2a800000U)
315 #define ETH_DMA_RINGRT_BASE (0x2b800000U)
316 #define ETH_DMA_RINGCFG_BASE (0x28440000U)
317 #define ETH_DMA_INTAGGR_INTR_BASE (0x2a700000U)
318 /* @} */
319 
324 #define ETH_DMA_TXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U))
325 #define ETH_DMA_TXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U))
326 #define ETH_DMA_RXCRT_CHAN_CTL(CHAN) (0x00000000U + ((CHAN) * 0x1000U))
327 #define ETH_DMA_RXCRT_CHAN_PEER8(CHAN) (0x00000220U + ((CHAN) * 0x1000U))
328 
329 #define ETH_DMA_RINGRT_RING_FDB(RING) (0x00000010U + ((RING) * 0x1000U))
330 #define ETH_DMA_RINGRT_RING_FOCC(RING) (0x00000018U + ((RING) * 0x1000U))
331 #define ETH_DMA_RINGRT_RING_RDB(RING) (0x00000010U + ((RING) * 0x1000U))
332 #define ETH_DMA_RINGRT_RING_ROCC(RING) (0x00000018U + ((RING) * 0x1000U))
333 #define ETH_DMA_RINGRT_RING_HWOCC(RING) (0x00000020U + ((RING) * 0x1000U))
334 #define ETH_DMA_RINGCFG_RING_SIZE(RING) (0x00000048U + ((RING) * 0x100U))
335 
336 #define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000000U + ((VINT) * 0x1000U))
337 #define ETH_DMA_INTAGGR_INTR_VINT_ENABLE_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000008U + ((VINT) * 0x1000U))
338 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_SET(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000010U + ((VINT) * 0x1000U))
339 #define ETH_DMA_INTAGGR_INTR_VINT_STATUS_CLEAR(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000018U + ((VINT) * 0x1000U))
340 #define ETH_DMA_INTAGGR_INTR_VINT_STATUSM(VINT) (ETH_DMA_INTAGGR_INTR_BASE + 0x00000020U + ((VINT) * 0x1000U))
341 
342 #define Eth_GetRingFDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FDB((RingNum)))
343 #define Eth_GetRingFOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_FOCC((RingNum)))
344 #define Eth_GetRingRDBReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_RDB((RingNum)))
345 #define Eth_GetRingROCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_ROCC((RingNum)))
346 #define Eth_GetRingHWOCCReg(RingNum) (ETH_DMA_RINGRT_BASE + ETH_DMA_RINGRT_RING_HWOCC((RingNum)))
347 #define Eth_GetRingSizeReg(RingNum) (ETH_DMA_RINGCFG_BASE + ETH_DMA_RINGCFG_RING_SIZE((RingNum)))
348 #define ETH_CSL_PROXY0_TARGET0_DATA_BASE (0x2a500000U)
349 #define ETH_CSL_PROXY_TARGET0_PROXY_CTL(PROXY) (ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000000U + ((PROXY)*0x1000U))
350 #define ETH_CSL_PROXY_TARGET0_PROXY_DATA_FIELD(PROXY) (ETH_CSL_PROXY0_TARGET0_DATA_BASE + 0x00000200U + ((PROXY)*0x1000U))
351 /* @} */
352 
356 #define UDMA_WAIT_TEARDOWN_COUNTER (10000u)
357 
358 
362 #define ETH_DEM_EVENT_SUPPORT (STD_OFF)
363 
368 #define ETH_RX_MTU_HOST_PORT_LENGTH (1522U)
369 
370 
371 
376 #define Eth_Cpsw_GetPhyMacRegAddr() ( 0x40f00200U )
377 #define Eth_Cpsw_GetAleRegAddr() ( 0x4603e000U )
378 #define Eth_Cpsw_GetCptsRegAddr() ( 0x4603d000U )
379 #define Eth_Cpsw_GetMdioRegAddr() ( 0x46000f00U )
380 #define Eth_Cpsw_GetCtrlRegAddr() ( 0x46020000U )
381 #define Eth_Cpsw_GetCppiClockFreq() ( 333333333U )
382 
383 #define Eth_Cpsw_GetCptsRefClockFreq() ( 1U )
384 #define Eth_Cpsw_GetMdioBusClockFreq() ( 2200000U )
385 #define Eth_Cpsw_GetMdioOpMode() ( ETH_MDIO_OPMODE_MANUAL )
386 #define Eth_Cpsw_GetMdioEnableInterrupt() ( TRUE )
387 /* @} */
388 
393 #define Eth_GetDem_E_HARDWARE_ERROR(CtrlIndex) ( ETH_DEM_NO_EVENT )
394 #define Eth_GetDem_E_LATECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )
395 #define Eth_GetDem_E_MULTIPLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )
396 #define Eth_GetDem_E_SINGLECOLLISION(CtrlIndex) ( ETH_DEM_NO_EVENT )
397 #define Eth_GetDem_E_ALIGNMENT(CtrlIndex) ( ETH_DEM_NO_EVENT )
398 #define Eth_GetDem_E_OVERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT )
399 #define Eth_GetDem_E_UNDERSIZEFRAME(CtrlIndex) ( ETH_DEM_NO_EVENT )
400 #define Eth_GetDem_E_CRC(CtrlIndex) ( ETH_DEM_NO_EVENT )
401 #define Eth_GetDem_E_RX_FRAMES_LOST(CtrlIndex) ( ETH_DEM_NO_EVENT )
402 #define Eth_GetDem_E_ACCESS(CtrlIndex) ( ETH_DEM_NO_EVENT )
403 #define Eth_GetDem_E_TX_INTERNAL(CtrlIndex) ( ETH_DEM_NO_EVENT )
404 /* @} */
405 
410 #define Eth_IsVirtualMacModeEnable(CtrlIndex) ( FALSE )
411 #define Eth_GetTxChannelThreadOffset(CtrlIndex) ( 0xf000U )
412 #define Eth_VirtMacGetEthFwRpcComChannelId(CtrlIndex) ( 0xFFFFU )
413 #define Eth_VirtMacGetEthPollRecvMsgInEthMain(CtrlIndex) ( FALSE )
414 #define Eth_VirtMacGetRpcCmdCompleteFuncPtr(CtrlIndex) ( (Eth_RpcCmdComplete)NULL_PTR )
415 #define Eth_VirtMacGetFwRegisterFuncPtr(CtrlIndex) ( (Eth_RpcFwRegistered)NULL_PTR )
416 #define Eth_VirtMacGetRemoteVirtPort(CtrlIndex) ( ETHREMOTECFG_SWITCH_PORT_1 )
417 
418 #define Eth_VirtMacGetDmaTxChannelPairAll(CtrlIdx) ( (EthVirtMacDmaTxChannelPair)NULL_PTR )
419 #define Eth_VirtMacGetDmaTxChannelUnpairAll(CtrlIdx) ( (EthVirtMacDmaTxChannelUnpair)NULL_PTR )
420 #define Eth_VirtMacGetDmaFlowCfgAll(CtrlIdx) ( (EthVirtMacDmaFLowCfg)NULL_PTR )
421 #define Eth_VirtMacGetDmaFlowResetAll(CtrlIdx) ( (EthVirtMacDmaFLowReset)NULL_PTR )
422 
423 #define Eth_GetTxEnableInterrupt(CtrlIndex) ( TRUE )
424 #define Eth_GetRxEnableInterrupt(CtrlIndex) ( TRUE )
425 #define Eth_GetEnetType(CtrlIndex) ( ETH_ENETTYPE_CPSW2G )
426 #define Eth_GetMacPortNum(CtrlIndex) ( ETH_PORT_MAC_PORT_1 )
427 #define Eth_GetMacAddressHigh(CtrlIndex) ( 0xaabbccddU )
428 #define Eth_GetMacAddressLow(CtrlIndex) ( 0xeeffU )
429 #define Eth_UseDefaultMacAddress(CtrlIndex) ( TRUE )
430 #define Eth_GetMiiConnectionType(CtrlIndex) ( ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND )
431 #define Eth_GetLoopBackMode(CtrlIndex) ( FALSE )
432 #define Eth_GetHardwareLoopTimeout(CtrlIndex) ( 32000U )
433 #define Eth_IsPacketMemCacheable(CtrlIndex) ( TRUE )
434 #define Eth_IsRingMemCacheable(CtrlIndex) ( TRUE )
435 #define Eth_IsDescMemCacheable(CtrlIndex) ( TRUE )
436 
437 #define Eth_GetRxMtuLength(CtrlIndex) ( 1522U )
438 #define Eth_GetTxChanStartNum(CtrlIndex) ( 30U )
439 #define Eth_GetRxChanStartNum(CtrlIndex) ( 30U )
440 #define Eth_GetEgressFifoTotalNum(CtrlIndex) ( 1U )
441 #define Eth_GetIngressFifoTotalNum(CtrlIndex) ( 1U )
442 #define Eth_GetRingTotalNum(CtrlIndex) ( 6U )
443 #define Eth_GetTxChanTotalNum(CtrlIndex) ( 1U )
444 #define Eth_GetRxChanTotalNum(CtrlIndex) ( 1U )
445 #define Eth_GetFlowTotalNumber(CtrlIndex) ( 1U )
446 #define Eth_GetEventTotalNum(CtrlIndex) ( 2U )
447 #define Eth_GetRingEventTotalNum(CtrlIndex) ( 2U )
448 #define Eth_GetTxDmaThresholdNum(CtrlIndex) ( 1U )
449 #define Eth_GetRxDmaThresholdNum(CtrlIndex) ( 1U )
450 
451 #define Eth_GetEgressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U )
452 #define Eth_GetEgressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U )
453 
454 #define Eth_GetIngressFifoPacketNum(CtrlIndex, FifoIdx) ( 16U )
455 #define Eth_GetIngressFifoPacketSize(CtrlIndex, FifoIdx) ( 1522U )
456 
457 #define Eth_GetEgressFifoPriorityAsignment(CtrlIndex, Prio) ( 0U )
458 #define Eth_GetIngressFifoPriorirtyAsignment(CtrlIndex, Prio) ( 0U )
459 
460 #define Eth_GetEgressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)] )
461 #define Eth_GetEgressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_Descriptor_0[(DescIdx)].bufferInfo )
462 #define Eth_GetEgressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Egress_BufferMem_0[(DescIdx) * 1536U] )
463 #define Eth_GetEgressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Egress_Queue_0 )
464 #define Eth_GetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] )
465 #define Eth_SetEgressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Egress_BufferState_0[BufferIdx] = Val )
466 
467 #define Eth_GetIngressFifoDescAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)] )
468 #define Eth_GetIngressFifoDescUserInfoAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_Descriptor_0[(DescIdx)].bufferInfo )
469 #define Eth_GetIngressFifoBufferDataAddress(CtrlIndex, FifoIdx, DescIdx) (&Eth_Ctrl_0_Ingress_BufferMem_0[(DescIdx) * 1536U] )
470 #define Eth_GetIngressFifoQueueAddress(CtrlIndex, FifoIdx) ( Eth_Ctrl_0_Ingress_Queue_0 )
471 #define Eth_GetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] )
472 #define Eth_SetIngressFifoBufferState(CtrlIndex, FifoIdx, BufferIdx, Val) ( Eth_Ctrl_0_Ingress_BufferState_0[(BufferIdx)] = Val )
473 
474 #define Eth_GetEgressFifoCqIdx(CtrlIndex, FifoIdx) ( 0U )
475 #define Eth_GetEgressFifoFqIdx(CtrlIndex, FifoIdx) ( 2U )
476 #define Eth_GetIngressFifoCqIdx(CtrlIndex, FifoIdx) ( 1U )
477 #define Eth_GetIngressFifoFqIdx(CtrlIndex, FifoIdx) ( 3U )
478 
479 #define Eth_GetTxChanId(CtrlIndex, ChIdx) ( 30U )
480 #define Eth_GetTxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 4U )
481 #define Eth_GetTxChanDepth(CtrlIndex, ChIdx) ( 128U )
482 
483 #define Eth_GetRxChanId(CtrlIndex, ChIdx) ( 30U )
484 #define Eth_GetRxChanTdCqRingIdx(CtrlIndex, ChIdx) ( 5U )
485 #define Eth_GetRxChanFlowTotalNum(CtrlIndex, ChIdx) ( 1U )
486 #define Eth_GetRxChanFlowStartNum(CtrlIndex, ChIdx) ( 60U )
487 
488 #define Eth_GetFlowId(CtrlIndex, FlowIdx) ( 60U )
489 #define Eth_GetFlowCqRingIdx(CtrlIndex, FlowIdx) ( 1U )
490 #define Eth_GetFlowFqRingIdx(CtrlIndex, FlowIdx) ( 3U )
491 
492 #define Eth_GetDynRingElemAddress(CtrlIndex, RingIdx) ( &Eth_RingDyn_Ctrl_0[(RingIdx)] )
493 
494 #define Eth_GetRingHwId(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].hwId )
495 #define Eth_GetRingTotalElemNum(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].size )
496 #define Eth_GetRingPriority(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].priority )
497 #define Eth_GetRingMemBaseAddress(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].memPtr )
498 
499 #define Eth_GetRingEventRingIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].ringIdx )
500 #define Eth_GetRingEventGlobalEventNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].globalEvent )
501 #define Eth_GetRingEventVirtBitNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].virtBitNum )
502 #define Eth_GetRingEventEventIdx(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].eventIdx )
503 #define Eth_GetRingEventSrcOffsetNum(CtrlIndex, RingEvtIdx) ( Eth_RingEventCfg_Ctrl_0[(RingEvtIdx)].srcOffset )
504 
505 #define Eth_GetEventCoreIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].coreIntrNum )
506 #define Eth_GetEventVirtIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].virtIntrNum )
507 #define Eth_GetEventIrIntrNum(CtrlIndex, EvtIdx) ( Eth_EventCfg_Ctrl_0[(EvtIdx)].IrIntrNum )
508 #define Eth_GetTxEventCoreIntrNum(CtrlIndex) ( 80U )
509 #define Eth_GetRxEventCoreIntrNum(CtrlIndex) ( 81U )
510 
511 #define Eth_GetHwTimerTotalNum(CtrlIndex) ( 0U )
512 #define Eth_GetHwTimerId(CtrlIndex, Index) ( 0xFFU )
513 #define Eth_GetHwTimerCounter(CtrlIndex, Index) ( 0xFFU )
514 #define Eth_GetHwTimerBaseAddr(CtrlIndex, Index) ( 0xFFFFFFFFU )
515 
516 #define Eth_GetHwTimerDynRunningState(CtrlIndex, Index) ( FALSE )
517 #define Eth_SetHwTimerDynRunningState(CtrlIndex, Index, Val) ( (void)(CtrlIndex) )
518 
519 #define Eth_GetRxIrqPacingEnable(CtrlIndex) ( FALSE )
520 #define Eth_GetTxIrqPacingEnable(CtrlIndex) ( FALSE )
521 
522 #define Eth_GetRxHwTimerIdx(CtrlIndex) ( 255U )
523 #define Eth_GetTxHwTimerIdx(CtrlIndex) ( 255U )
524 #define Eth_GetIrqPacingEnable(CtrlIndex) ( (Eth_GetTxIrqPacingEnable(CtrlIndex) == TRUE) || (Eth_GetRxIrqPacingEnable(CtrlIndex) == TRUE) )
525 
526 #define Eth_GetProxyTotalNum(CtrlIndex) ( 1U )
527 #define Eth_GetProxyThreadNum(CtrlIndex, ProxyIdx) ( 9U )
528 #define Eth_GetProxyTargetRingNum(CtrlIndex, ProxyIdx) ( 0U )
529 #define Eth_GetRingProxyIdx(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].proxyIdx )
530 #define Eth_GetRingMode(CtrlIndex, RingIdx) ( Eth_Udma_RingCfg_0[(RingIdx)].ringMode )
531 
532 #define Eth_GetDmaRingCfg(CtrlIdx) ( (Eth_DmaRingCfg)&AppUtils_EthRingCfg )
533 
534 #define Eth_GetTxChannelCtlRegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_CTL((ChanId)))
535 #define Eth_GetTxChannelPeer8RegAddress(ChanId) (ETH_DMA_TX_BASE_REG + ETH_DMA_TXCRT_CHAN_PEER8((ChanId)))
536 #define Eth_GetRxChannelCtlRegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_CTL((ChanId)))
537 #define Eth_GetRxChannelPeer8RegAddress(ChanId) (ETH_DMA_RX_BASE_REG + ETH_DMA_RXCRT_CHAN_PEER8((ChanId)))
538 
539 /* @} */
540 
541 /* ========================================================================== */
542 /* Structures and Enums */
543 /* ========================================================================== */
544 
552 typedef void (*Eth_RpcCmdComplete)(uint8 CtrlIdx,
553  uint8 sid,
554  sint32 status);
555 
560 typedef void (*Eth_RpcFwRegistered)(uint8 CtrlIdx);
561 
563 typedef Std_ReturnType (*Eth_DmaRingCfg)(uint8 ctrlIdx, uint8 ringIdx);
564 
566 typedef void (*Eth_MdioDelayNsecFunc)(void);
567 
569 typedef Std_ReturnType (*EthVirtMacDmaTxChannelPair)(uint8 ctrlIdx);
570 
572 typedef Std_ReturnType (*EthVirtMacDmaTxChannelUnPair)(uint8 ctrlIdx);
573 
575 typedef Std_ReturnType (*EthVirtMacDmaFLowCfg)(uint8 ctrlIdx);
576 
578 typedef Std_ReturnType (*EthVirtMacDmaFLowReset)(uint8 ctrlIdx);
579 
586 typedef enum
587 {
588  ETH_PORT_HOST_PORT = 0x00U,
590  ETH_MAC_PORT_FIRST = 0x01U,
592  ETH_PORT_MAC_PORT_1 = 0x01U,
594  ETH_PORT_MAC_PORT_2 = 0x02U,
596  ETH_PORT_MAC_PORT_3 = 0x03U,
598  ETH_PORT_MAC_PORT_4 = 0x04U,
600  ETH_PORT_MAC_PORT_5 = 0x05U,
602  ETH_PORT_MAC_PORT_6 = 0x06U,
604  ETH_PORT_MAC_PORT_7 = 0x07U,
606  ETH_PORT_MAC_PORT_8 = 0x08U,
610 } Eth_PortType;
611 
618 typedef enum
619 {
634 
640 typedef enum
641 {
642  ETH_ENETTYPE_CPSW2G = 0x00U,
644  ETH_ENETTYPE_CPSW9G = 0x01U,
646  ETH_ENETTYPE_CPSW5G = 0x02U,
648  ETH_ENETTYPE_CPSW3G = 0x03U,
652 } Eth_EnetType;
653 
659 typedef enum
660 {
661  ETH_MDIO_OPMODE_NORMAL = 0x00U,
663  ETH_MDIO_OPMODE_MANUAL = 0x01U,
666 
671 typedef struct Eth_CpswConfigType_s
672 {
673  uint32 phyMacAddr;
675  uint32 aleAddr;
677  uint32 cptsAddr;
679  uint32 mdioAddr;
681  uint32 ctrlAddr;
685  boolean enableMdioIrq;
694 
699 typedef struct Eth_Udma_RingCfgType_s
700 {
701  uint64 *memPtr;
703  uint32 hwId;
705  uint32 size;
707  uint32 priority;
709  uint32 proxyIdx;
711  uint32 ringMode;
714 
719 typedef struct Eth_Udma_ProxyCfgType_s
720 {
721  uint32 proxyId;
726 
731 typedef struct Eth_Udma_EventCfgType_s
732 {
733  uint32 coreIntrNum;
735  uint32 virtIntrNum;
737  uint32 IrIntrNum;
740 
745 typedef struct Eth_Udma_RingEventCfgType_s
746 {
747  uint8 ringIdx;
749  uint8 eventIdx;
751  uint8 virtBitNum;
753  uint32 globalEvent;
755  uint32 srcOffset;
758 
763 typedef struct Eth_FifoRingMapCfgType_s
764 {
765  uint8 cqRingIdx;
767  uint8 fqRingIdx;
770 
775 typedef struct Eth_ChannelCfgType_s
776 {
777  uint8 tdCqRingIdx;
779  uint16 chId;
782 
787 typedef struct Eth_FlowCfgType_s
788 {
789  uint8 cqRingIdx;
791  uint8 fqRingIdx;
793  uint16 flowId;
796 
801 typedef struct Eth_ChannelFlowCfgType_s
802 {
803  uint8 flowNum;
805  uint16 startFlowId;
808 
813 typedef struct Eth_FifoHandleType_s
814 {
817  Eth_DescType *descPtr;
819  Eth_QueueType *queuePtr;
821  uint8 *bufferState;
823  uint16 fifoNum;
825  uint16 elemSize;
827  uint16 pktSize;
829  uint32 totalSize;
832 
837 typedef struct Eth_Udma_CfgType_s
838 {
843  Eth_Udma_RingDynType *ringDynPtr;
873  uint16 startTxNum;
875  uint16 startRxNum;
899  uint16 txCoreIrq;
901  uint16 rxCoreIrq;
903  uint16 rxMtuLength;
908 
913 typedef struct Eth_VirtualMacConfigType_s
914 {
917  EthRemoteCfg_VirtPort remoteVirtPort;
934 
939 typedef struct Eth_HwTimerConfigType_s
940 {
941  uint8 hwTimerId;
948 
953 typedef struct Eth_ControlerConfigType_s
954 {
955  uint32 ctrlIdx;
961  uint32 macAddrHigh;
963  uint32 macAddrLow;
965  boolean useDefaultMac;
969  boolean loopback;
973  boolean enableTxIrq;
975  boolean enableRxIrq;
985  uint16 demEventNum;
999  uint16 *demEventCfg;
1007  boolean *hwTimerDynPtr;
1018 
1023 typedef struct Eth_ConfigType_s
1024 {
1027 } Eth_ConfigType;
1028 
1029 /* ========================================================================== */
1030 /* Generate Configuration */
1031 /* ========================================================================== */
1032 
1033 #define ETH_START_SEC_CONST_UNSPECIFIED
1034 #include "Eth_MemMap.h"
1035 
1036 extern CONST(Eth_Udma_RingCfgType, ETH_VAR_NO_INIT) Eth_Udma_RingCfg_0[6U];
1037 extern CONST(Eth_Udma_EventCfgType, ETH_VAR_NO_INIT) Eth_EventCfg_Ctrl_0[2U];
1038 extern CONST(Eth_Udma_RingEventCfgType, ETH_VAR_NO_INIT) Eth_RingEventCfg_Ctrl_0[2U];
1039 
1040 
1041 #define ETH_STOP_SEC_CONST_UNSPECIFIED
1042 #include "Eth_MemMap.h"
1043 
1044 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED_128
1045 #include "Eth_MemMap.h"
1046 
1047 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U];
1048 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_Descriptor_0[16U];
1049 
1050 extern VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_BufferMem_0[24576U];
1051 extern VAR(Eth_DescType, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Ingress_Descriptor_0[16U];
1052 
1053 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED_128
1054 #include "Eth_MemMap.h"
1055 
1056 #define ETH_START_SEC_VAR_NO_INIT_8
1057 #include "Eth_MemMap.h"
1058 
1059 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_BufferState_0[16U];
1060 extern VAR(uint8, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_BufferState_0[16U];
1061 
1062 #define ETH_STOP_SEC_VAR_NO_INIT_8
1063 #include "Eth_MemMap.h"
1064 
1065 #define ETH_START_SEC_VAR_NO_INIT_UNSPECIFIED
1066 #include "Eth_MemMap.h"
1067 
1068 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Egress_Queue_0[1U];
1069 extern VAR(Eth_QueueType, ETH_VAR_NO_INIT) Eth_Ctrl_0_Ingress_Queue_0[1U];
1070 
1071 extern VAR(Eth_Udma_RingDynType, ETH_VAR_NO_INIT) Eth_RingDyn_Ctrl_0[6U];
1072 #define ETH_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
1073 #include "Eth_MemMap.h"
1074 
1075 /* ========================================================================== */
1076 /* Function Declarations */
1077 /* ========================================================================== */
1078 
1079 /* ========================================================================== */
1080 /* External Function Prototype */
1081 /* ========================================================================== */
1082 #define ETH_START_SEC_CODE
1083 #include "Eth_MemMap.h"
1084 
1085 
1086 
1088 extern Std_ReturnType AppUtils_EthRingCfg(uint8 ctrlIdx, uint8 Id);
1089 
1090 #define ETH_STOP_SEC_CODE
1091 #include "Eth_MemMap.h"
1092 
1093 
1094 /* ========================================================================== */
1095 /* Internal Function Declarations */
1096 /* ========================================================================== */
1097 
1098 
1103 #define Eth_GetMdioWriteLowBaseNsec() do { \
1104  NOP50;\
1105  NOP30;\
1106  } while(TRUE == FALSE)
1107 #define Eth_GetMdioWriteHighBaseNsec() do { \
1108  NOP100;\
1109  } while(TRUE == FALSE)
1110 #define Eth_GetMdioReadLowBaseNsec() do { \
1111  NOP50;\
1112  NOP30;\
1113  } while(TRUE == FALSE)
1114 #define Eth_GetMdioReadHighBaseNsec() do { \
1115  NOP100;\
1116  NOP50;\
1117  NOP30;\
1118  } while(TRUE == FALSE)
1119 /* @} */
1120 
1125 #define Eth_GetMdioWriteLowDelayNsec(CtrlIdx) do { \
1126  NOP100;\
1127  NOP50;\
1128  NOP20;\
1129  } while(TRUE == FALSE)
1130 #define Eth_GetMdioWriteHighDelayNsec(CtrlIdx) do { \
1131  NOP100;\
1132  NOP50;\
1133  } while(TRUE == FALSE)
1134 #define Eth_GetMdioReadLowDelayNsec(CtrlIdx) do { \
1135  NOP100;\
1136  NOP50;\
1137  NOP20;\
1138  } while(TRUE == FALSE)
1139 #define Eth_GetMdioReadHighDelayNsec(CtrlIdx) do { \
1140  NOP50;\
1141  NOP20;\
1142  } while(TRUE == FALSE)
1143 /* @} */
1144 
1145 #ifdef __cplusplus
1146 }
1147 #endif
1148 
1149 #endif /* #ifndef ETH_CFG_H_ */
1150 
1151 /* @} */
Eth_Udma_EventCfgType * eventCfgPtr
Definition: Eth_Cfg.h:839
Eth_QueueType * queuePtr
Definition: Eth_Cfg.h:819
boolean enableTxIrq
Definition: Eth_Cfg.h:973
Eth_DescType * descPtr
Definition: Eth_Cfg.h:817
Eth_ChannelCfgType * txChanCfgPtr
Definition: Eth_Cfg.h:859
uint32 cppiClockFreqHz
Definition: Eth_Cfg.h:683
boolean isRingMemCacheable
Definition: Eth_Cfg.h:979
uint16 fifoNum
Definition: Eth_Cfg.h:823
Eth_HwTimerConfigType * hwTimerCfgPtr
Definition: Eth_Cfg.h:1005
uint8 * egressFifoPrioAssignCfgPtr
Definition: Eth_Cfg.h:855
uint16 flowId
Definition: Eth_Cfg.h:793
uint32 hwLoopTimeout
Definition: Eth_Cfg.h:971
uint16 rxCoreIrq
Definition: Eth_Cfg.h:901
uint32 macAddrLow
Definition: Eth_Cfg.h:963
boolean loopback
Definition: Eth_Cfg.h:969
uint32 size
Definition: Eth_Cfg.h:705
boolean useDefaultMac
Definition: Eth_Cfg.h:965
uint8 totalHwTimerNum
Definition: Eth_Cfg.h:991
uint8 * bufferState
Definition: Eth_Cfg.h:821
uint32 phyMacAddr
Definition: Eth_Cfg.h:673
boolean enableVirtualMac
Definition: Eth_Cfg.h:983
Eth_MdioOperModeType mdioOpMode
Definition: Eth_Cfg.h:689
Std_ReturnType(* Eth_DmaRingCfg)(uint8 ctrlIdx, uint8 ringIdx)
Mdio delay in nsec function pointer.
Definition: Eth_Cfg.h:563
Eth_FifoRingMapCfgType * ingressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:853
uint8 rxThresholdNum
Definition: Eth_Cfg.h:885
Eth_MdioDelayNsecFunc mdioWriteHighDelayNsec
Definition: Eth_Cfg.h:1011
uint32 ethfwRpcComChId
Definition: Eth_Cfg.h:915
uint16 pktSize
Definition: Eth_Cfg.h:827
#define ETH_CTRL_ID_MAX
Eth max controller ID.
Definition: Eth_Cfg.h:252
Eth_MdioDelayNsecFunc mdioReadLowDelayNsec
Definition: Eth_Cfg.h:1013
uint8 totalRxChanNum
Definition: Eth_Cfg.h:893
uint8 * fifoBufferPtr
Definition: Eth_Cfg.h:815
uint16 startTxNum
Definition: Eth_Cfg.h:873
uint32 ctrlIdx
Definition: Eth_Cfg.h:955
uint16 startRxNum
Definition: Eth_Cfg.h:875
uint8 totalRingEventNum
Definition: Eth_Cfg.h:881
Eth_ChannelCfgType * rxChanCfgPtr
Definition: Eth_Cfg.h:861
uint8 totalRingNum
Definition: Eth_Cfg.h:879
uint8 hwTimerId
Definition: Eth_Cfg.h:941
Eth_Udma_ProxyCfgType * proxyCfgPtr
Definition: Eth_Cfg.h:867
boolean enableRxIrqPacing
Definition: Eth_Cfg.h:987
uint16 demEventNum
Definition: Eth_Cfg.h:985
uint8 fqRingIdx
Definition: Eth_Cfg.h:791
Eth_Udma_RingDynType * ringDynPtr
Definition: Eth_Cfg.h:843
Eth_Udma_RingCfgType * ringCfgPtr
Definition: Eth_Cfg.h:841
uint32 totalSize
Definition: Eth_Cfg.h:829
boolean isDescMemCacheable
Definition: Eth_Cfg.h:981
void(* Eth_MdioDelayNsecFunc)(void)
Pair PSIL TX channel function pointer.
Definition: Eth_Cfg.h:566
uint16 startFlowId
Definition: Eth_Cfg.h:805
uint16 txCoreIrq
Definition: Eth_Cfg.h:899
uint8 txHwTimerIdx
Definition: Eth_Cfg.h:995
Eth_MdioOperModeType
MDIO operating mode.
Definition: Eth_Cfg.h:660
uint16 * demEventCfg
Definition: Eth_Cfg.h:999
Eth_ChannelFlowCfgType * rxChanFlowCfgPtr
Definition: Eth_Cfg.h:863
uint32 txChDmaBaseAddr
Definition: Eth_Cfg.h:869
Eth_PortType macPort
Definition: Eth_Cfg.h:959
Eth_DmaRingCfg EthDmaRingCfgOps
Definition: Eth_Cfg.h:905
uint8 rxHwTimerIdx
Definition: Eth_Cfg.h:993
Std_ReturnType(* EthVirtMacDmaTxChannelUnPair)(uint8 ctrlIdx)
Flow config function pointer.
Definition: Eth_Cfg.h:572
Eth_FifoRingMapCfgType * egressFifoRingMapCfgPtr
Definition: Eth_Cfg.h:851
uint16 elemSize
Definition: Eth_Cfg.h:825
uint32 ctrlAddr
Definition: Eth_Cfg.h:681
uint8 totalTxChanNum
Definition: Eth_Cfg.h:891
uint32 hwTimerCounter
Definition: Eth_Cfg.h:943
Eth_MacConnectionType connType
Definition: Eth_Cfg.h:967
uint8 virtBitNum
Definition: Eth_Cfg.h:751
uint8 cqRingIdx
Definition: Eth_Cfg.h:765
uint8 totalFlowNum
Definition: Eth_Cfg.h:895
Eth_FlowCfgType * flowCfgPtr
Definition: Eth_Cfg.h:865
Std_ReturnType(* EthVirtMacDmaTxChannelPair)(uint8 ctrlIdx)
Unpair PSIL TX channel function pointer.
Definition: Eth_Cfg.h:569
const Eth_Udma_RingCfgType Eth_Udma_RingCfg_0[6U]
uint32 hwId
Definition: Eth_Cfg.h:703
uint32 mdioBusFreqHz
Definition: Eth_Cfg.h:687
uint8 fqRingIdx
Definition: Eth_Cfg.h:767
uint8 totalIngressFifoNum
Definition: Eth_Cfg.h:889
uint8 tdCqRingIdx
Definition: Eth_Cfg.h:777
void(* Eth_RpcCmdComplete)(uint8 CtrlIdx, uint8 sid, sint32 status)
Application callback to indicate Rpc dispatch command completion.
Definition: Eth_Cfg.h:552
boolean enableRxIrq
Definition: Eth_Cfg.h:975
VAR(uint8, ETH_VAR_NO_INIT_128) Eth_Ctrl_0_Egress_BufferMem_0[24576U]
uint32 IrIntrNum
Definition: Eth_Cfg.h:737
const Eth_Udma_RingEventCfgType Eth_RingEventCfg_Ctrl_0[2U]
uint32 aleAddr
Definition: Eth_Cfg.h:675
uint16 rxMtuLength
Definition: Eth_Cfg.h:903
Eth_MdioDelayNsecFunc mdioWriteLowDelayNsec
Definition: Eth_Cfg.h:1009
Eth_CpswConfigType * cpswCfg
Definition: Eth_Cfg.h:1001
Std_ReturnType(* EthVirtMacDmaFLowReset)(uint8 ctrlIdx)
Definition: Eth_Cfg.h:578
Std_ReturnType(* EthVirtMacDmaFLowCfg)(uint8 ctrlIdx)
Flow reset function pointer.
Definition: Eth_Cfg.h:575
uint32 srcOffset
Definition: Eth_Cfg.h:755
Eth_RpcFwRegistered fwRegisteredCb
Definition: Eth_Cfg.h:923
boolean pollRecvMsgInEthMain
Definition: Eth_Cfg.h:921
uint32 globalEvent
Definition: Eth_Cfg.h:753
uint8 flowNum
Definition: Eth_Cfg.h:803
uint32 cptsAddr
Definition: Eth_Cfg.h:677
const Eth_Udma_EventCfgType Eth_EventCfg_Ctrl_0[2U]
EthVirtMacDmaFLowReset dmaFLowReset
Definition: Eth_Cfg.h:931
boolean enableTxIrqPacing
Definition: Eth_Cfg.h:989
uint32 ringMode
Definition: Eth_Cfg.h:711
Eth_FifoHandleType * egressFifoCfgPtr
Definition: Eth_Cfg.h:847
Eth_EnetType
Enet Cpsw Type identifier.
Definition: Eth_Cfg.h:641
uint32 coreIntrNum
Definition: Eth_Cfg.h:733
Std_ReturnType AppUtils_EthRingCfg(uint8 ctrlIdx, uint8 Id)
EthVirtMacDmaTxChannelPair txChannelPair
Definition: Eth_Cfg.h:925
uint8 eventIdx
Definition: Eth_Cfg.h:749
Eth_FifoHandleType * ingressFifoCfgPtr
Definition: Eth_Cfg.h:849
Eth_Udma_RingEventCfgType * ringEvenCfgPtr
Definition: Eth_Cfg.h:845
uint8 ringIdx
Definition: Eth_Cfg.h:747
EthVirtMacDmaFLowCfg dmaFLowCfg
Definition: Eth_Cfg.h:929
uint32 rxChDmaBaseAddr
Definition: Eth_Cfg.h:871
uint16 totalProxyNum
Definition: Eth_Cfg.h:897
uint32 proxyId
Definition: Eth_Cfg.h:721
uint32 hwTimerBaseAddr
Definition: Eth_Cfg.h:945
uint32 virtIntrNum
Definition: Eth_Cfg.h:735
void(* Eth_RpcFwRegistered)(uint8 CtrlIdx)
Application callback to indicate Ethernet firmware registered with the Eth RPC client.
Definition: Eth_Cfg.h:560
boolean * hwTimerDynPtr
Definition: Eth_Cfg.h:1007
uint8 totalEventNum
Definition: Eth_Cfg.h:877
uint8 txThresholdNum
Definition: Eth_Cfg.h:883
uint32 cptsRefClockFreq
Definition: Eth_Cfg.h:691
EthRemoteCfg_VirtPort remoteVirtPort
Definition: Eth_Cfg.h:917
Eth_VirtualMacConfigType * virtualMacCfg
Definition: Eth_Cfg.h:997
uint64 * memPtr
Definition: Eth_Cfg.h:701
Eth_MacConnectionType
Type/Speed/Duplex connection type.
Definition: Eth_Cfg.h:619
Eth_MdioDelayNsecFunc mdioReadHighDelayNsec
Definition: Eth_Cfg.h:1015
Eth_EnetType enetType
Definition: Eth_Cfg.h:957
EthVirtMacDmaTxChannelUnPair txChannelUnPair
Definition: Eth_Cfg.h:927
uint32 macAddrHigh
Definition: Eth_Cfg.h:961
boolean isPacketMemCacheable
Definition: Eth_Cfg.h:977
uint8 * ingressFifoPrioAssignCfgPtr
Definition: Eth_Cfg.h:857
uint32 mdioAddr
Definition: Eth_Cfg.h:679
uint32 proxyIdx
Definition: Eth_Cfg.h:709
Eth_Udma_CfgType * dmaCfgPtr
Definition: Eth_Cfg.h:1003
uint8 cqRingIdx
Definition: Eth_Cfg.h:789
Eth_RpcCmdComplete rpcCmdComplete
Definition: Eth_Cfg.h:919
uint8 totalEgressFifoNum
Definition: Eth_Cfg.h:887
uint32 targetNumRingId
Definition: Eth_Cfg.h:723
uint32 priority
Definition: Eth_Cfg.h:707
Eth_PortType
Port identifier.
Definition: Eth_Cfg.h:587
uint16 chId
Definition: Eth_Cfg.h:779
boolean enableMdioIrq
Definition: Eth_Cfg.h:685
@ ETH_MDIO_OPMODE_NORMAL
Definition: Eth_Cfg.h:661
@ ETH_MDIO_OPMODE_MANUAL
Definition: Eth_Cfg.h:663
@ ETH_ENETTYPE_CPSW5G
Definition: Eth_Cfg.h:646
@ ETH_ENETTYPE_CPSWLAST
Definition: Eth_Cfg.h:650
@ ETH_ENETTYPE_CPSW2G
Definition: Eth_Cfg.h:642
@ ETH_ENETTYPE_CPSW3G
Definition: Eth_Cfg.h:648
@ ETH_ENETTYPE_CPSW9G
Definition: Eth_Cfg.h:644
@ ETH_MAC_CONN_TYPE_RGMII_DETECT_INBAND
Definition: Eth_Cfg.h:630
@ ETH_MAC_CONN_TYPE_RMII_100
Definition: Eth_Cfg.h:622
@ ETH_MAC_CONN_TYPE_RGMII_FORCE_1000_FULL
Definition: Eth_Cfg.h:628
@ ETH_MAC_CONN_TYPE_RGMII_FORCE_100_FULL
Definition: Eth_Cfg.h:626
@ ETH_MAC_CONN_TYPE_RGMII_FORCE_100_HALF
Definition: Eth_Cfg.h:624
@ ETH_MAC_CONN_TYPE_RMII_10
Definition: Eth_Cfg.h:620
@ ETH_PORT_MAC_PORT_3
Definition: Eth_Cfg.h:596
@ ETH_PORT_MAC_PORT_7
Definition: Eth_Cfg.h:604
@ ETH_PORT_MAC_PORT_6
Definition: Eth_Cfg.h:602
@ ETH_PORT_MAC_PORT_8
Definition: Eth_Cfg.h:606
@ ETH_PORT_MAC_PORT_1
Definition: Eth_Cfg.h:592
@ ETH_PORT_MAC_PORT_LAST
Definition: Eth_Cfg.h:608
@ ETH_PORT_MAC_PORT_5
Definition: Eth_Cfg.h:600
@ ETH_PORT_HOST_PORT
Definition: Eth_Cfg.h:588
@ ETH_MAC_PORT_FIRST
Definition: Eth_Cfg.h:590
@ ETH_PORT_MAC_PORT_2
Definition: Eth_Cfg.h:594
@ ETH_PORT_MAC_PORT_4
Definition: Eth_Cfg.h:598
Eth channel configuration type Configuration related to channel.
Definition: Eth_Cfg.h:776
Eth channel flow configuration type Configuration related to channel flow.
Definition: Eth_Cfg.h:802
Eth configuration type Configuration data of all controller.
Definition: Eth_Cfg.h:1024
Eth controller configuration type Configuration related to Eth controller configuration.
Definition: Eth_Cfg.h:954
Eth Cpsw Configurations type Configuration related to Cpsw data.
Definition: Eth_Cfg.h:672
Eth Fifo configuration type Configuration related to Fifo.
Definition: Eth_Cfg.h:814
Eth Fifo ring map configuration type Configuration related to fifo map to ring.
Definition: Eth_Cfg.h:764
Eth flow configuration type Configuration related to flow.
Definition: Eth_Cfg.h:788
Eth driver hardware timer configuration data Configuration related to hardware timer.
Definition: Eth_Cfg.h:940
Eth Udma configuration type Configuration related to Udma.
Definition: Eth_Cfg.h:838
Eth Udma event Configurations type Configuration related to Udma event.
Definition: Eth_Cfg.h:732
Eth Udma Proxy Configurations type Configuration related to Udma proxy.
Definition: Eth_Cfg.h:720
Eth Udma ring Configurations type Configuration related to Udma ring.
Definition: Eth_Cfg.h:700
Eth ring event configuration type Configuration related to ring event.
Definition: Eth_Cfg.h:746
Eth driver virtual mac configuration data Configuration related to virtual MAC configuration.
Definition: Eth_Cfg.h:914