#### 9.5.4 Pseudo Instructions

The only available pseudo-instruction `__gcc_isr` can be activated by option `-mgcc-isr`.

`__gcc_isr 1`

  Emit code chunk to be used in avr-gcc ISR prologue. It will expand to at most six 1-word instructions, all optional: push of `tmp_reg`, push of `SREG`, push and clear of `zero_reg`, push of Reg.

`__gcc_isr 2`

  Emit code chunk to be used in an avr-gcc ISR epilogue. It will expand to at most five 1-word instructions, all optional: pop of Reg, pop of `zero_reg`, pop of `SREG`, pop of `tmp_reg`.

`__gcc_isr 0, Reg`

  Finish avr-gcc ISR function. Scan code since the last prologue for usage of: `SREG`, `tmp_reg`, `zero_reg`. Prologue chunk and epilogue chunks will be replaced by appropriate code to save / restore `SREG`, `tmp_reg`, `zero_reg` and Reg.

Example input:

    __vector1:
        __gcc_isr 1
        lds r24, var
        inc r24
        sts var, r24
        __gcc_isr 2
        reti
        __gcc_isr 0, r24

Example output:

    00000000 <__vector1>:
       0:   8f 93           push    r24
       2:   8f b7           in      r24, 0x3f
       4:   8f 93           push    r24
       6:   80 91 60 00     lds     r24, 0x0060     ; 0x800060 <var>
       a:   83 95           inc     r24
       c:   80 93 60 00     sts     0x0060, r24     ; 0x800060 <var>
      10:   8f 91           pop     r24
      12:   8f bf           out     0x3f, r24
      14:   8f 91           pop     r24
      16:   18 95           reti