TCAN4550  1p2
TCAN4x5x_Data_Structs.h
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1 /*
2  * TCAN4550.h
3  * Description: This file contains TCAN4550 functions, and relies on the TCAN4x5x_SPI abstraction functions
4  * Additional Feature Sets of TCAN4550 vs TCAN4x5x:
5  * - Watchdog Timer Functions
6  *
7  * Created on: Oct 1, 2017
8  * Author: Texas Instruments
9  *
10  *
11  * Copyright (c) 2017 Texas Instruments Incorporated. All rights reserved.
12  * Software License Agreement
13  *
14  * Redistribution and use in source and binary forms, with or without
15  * modification, are permitted provided that the following conditions
16  * are met:
17  *
18  * Redistributions of source code must retain the above copyright
19  * notice, this list of conditions and the following disclaimer.
20  *
21  * Redistributions in binary form must reproduce the above copyright
22  * notice, this list of conditions and the following disclaimer in the
23  * documentation and/or other materials provided with the
24  * distribution.
25  *
26  * Neither the name of Texas Instruments Incorporated nor the names of
27  * its contributors may be used to endorse or promote products derived
28  * from this software without specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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41  */
42 
43 #ifndef TCAN4X5X_DATA_STRUCTS_H_
44 #define TCAN4X5X_DATA_STRUCTS_H_
45 
46 // ~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*
47 // Starting with the MCAN Data Structures
48 // ~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*
49 
50 
51 
56 typedef struct
57 {
60  uint8_t DataBitRatePrescaler : 6;
61 
65 
69 
71 
72 
77 typedef struct
78 {
81  uint8_t DataBitRatePrescaler : 5;
82 
85  uint8_t DataTimeSeg1andProp : 5;
86 
89  uint8_t DataTimeSeg2 : 4;
90 
93  uint8_t DataSyncJumpWidth : 4;
94 
97  uint8_t TDCOffset : 7;
98 
101  uint8_t TDCFilter : 7;
102 
104 
105 
110 typedef struct
111 {
114  uint16_t NominalBitRatePrescaler : 10;
115 
119 
123 
125 
126 
131 typedef struct
132 {
136 
140 
143  uint8_t NominalTimeSeg2 : 7;
144 
147  uint8_t NominalSyncJumpWidth : 7;
149 
150 
154 typedef enum
155 {
158 
161 
164 
167 
170 
173 
176 
180 
184 typedef struct
185 {
186  /************************
187  * Filter Elements *
188  ************************/
189 
192  uint8_t SIDNumElements : 8;
193 
196  uint8_t XIDNumElements : 7;
197 
198 
199  /************************
200  * RX FIFO Elements *
201  ************************/
202 
205  uint8_t Rx0NumElements : 7;
206 
209 
212  uint8_t Rx1NumElements : 7;
213 
216 
219  uint8_t RxBufNumElements : 7;
220 
223 
224  /************************
225  * TX Buffer Elements *
226  ************************/
227 
231 
234  uint8_t TxBufferNumElements : 6;
235 
238 
240 
241 
245 typedef struct
246 {
247  union
248  {
250  uint32_t word;
251 
252  struct
253  {
255  uint8_t reserved : 2;
256 
258  uint8_t ASM : 1;
259 
261  uint8_t reserved2 : 1;
262 
264  uint8_t CSR : 1;
265 
267  uint8_t MON : 1;
268 
270  uint8_t DAR : 1;
271 
273  uint8_t TEST : 1;
274 
276  uint8_t FDOE : 1;
277 
279  uint8_t BRSE : 1;
280 
282  uint8_t reserved3 : 2;
283 
287  uint8_t PXHD : 1;
288 
290  uint8_t EFBI : 1;
291 
293  uint8_t TXP : 1;
294 
298  uint8_t NISO : 1;
299  };
300  };
302 
303 
304 
308 typedef struct
309 {
310  union
311  {
313  uint32_t word;
314  struct
315  {
317  uint8_t RF0N : 1;
318 
320  uint8_t RF0W : 1;
321 
323  uint8_t RF0F : 1;
324 
326  uint8_t RF0L : 1;
327 
329  uint8_t RF1N : 1;
330 
332  uint8_t RF1W : 1;
333 
335  uint8_t RF1F : 1;
336 
338  uint8_t RF1L : 1;
339 
341  uint8_t HPM : 1;
342 
344  uint8_t TC : 1;
345 
347  uint8_t TCF : 1;
348 
350  uint8_t TFE : 1;
351 
353  uint8_t TEFN : 1;
354 
356  uint8_t TEFW : 1;
357 
359  uint8_t TEFF : 1;
360 
362  uint8_t TEFL : 1;
363 
365  uint8_t TSW : 1;
366 
368  uint8_t MRAF : 1;
369 
371  uint8_t TOO : 1;
372 
374  uint8_t DRX : 1;
375 
377  uint8_t BEC : 1;
378 
380  uint8_t BEU : 1;
381 
383  uint8_t ELO : 1;
384 
386  uint8_t EP : 1;
387 
389  uint8_t EW : 1;
390 
392  uint8_t BO : 1;
393 
395  uint8_t WDI : 1;
396 
398  uint8_t PEA : 1;
399 
401  uint8_t PED : 1;
402 
404  uint8_t ARA : 1;
405 
407  uint8_t reserved : 2;
408  };
409  };
411 
412 
416 typedef struct
417 {
418  union
419  {
421  uint32_t word;
422  struct
423  {
425  uint8_t RF0NE : 1;
426 
428  uint8_t RF0WE : 1;
429 
431  uint8_t RF0FE : 1;
432 
434  uint8_t RF0LE : 1;
435 
437  uint8_t RF1NE : 1;
438 
440  uint8_t RF1WE : 1;
441 
443  uint8_t RF1FE : 1;
444 
446  uint8_t RF1LE : 1;
447 
449  uint8_t HPME : 1;
450 
452  uint8_t TCE : 1;
453 
455  uint8_t TCFE : 1;
456 
458  uint8_t TFEE : 1;
459 
461  uint8_t TEFNE : 1;
462 
464  uint8_t TEFWE : 1;
465 
467  uint8_t TEFFE : 1;
468 
470  uint8_t TEFLE : 1;
471 
473  uint8_t TSWE : 1;
474 
476  uint8_t MRAFE : 1;
477 
479  uint8_t TOOE : 1;
480 
482  uint8_t DRXE : 1;
483 
485  uint8_t BECE : 1;
486 
488  uint8_t BEUE : 1;
489 
491  uint8_t ELOE : 1;
492 
494  uint8_t EPE : 1;
495 
497  uint8_t EWE : 1;
498 
500  uint8_t BOE : 1;
501 
503  uint8_t WDIE : 1;
504 
506  uint8_t PEAE : 1;
507 
509  uint8_t PEDE : 1;
510 
512  uint8_t ARAE : 1;
513 
515  uint8_t reserved : 2;
516  };
517  };
519 
520 
524 typedef struct
525 {
527  uint32_t ID : 29;
528 
530  uint8_t RTR : 1;
531 
533  uint8_t XTD : 1;
534 
536  uint8_t ESI : 1;
537 
539  uint16_t RXTS : 16;
540 
542  uint8_t DLC : 4;
543 
545  uint8_t BRS : 1;
546 
548  uint8_t FDF : 1;
549 
551  uint8_t reserved : 2;
552 
554  uint8_t FIDX : 7;
555 
557  uint8_t ANMF : 1;
558 
560 
561 
565 typedef struct
566 {
568  uint32_t ID : 29;
569 
571  uint8_t RTR : 1;
572 
574  uint8_t XTD : 1;
575 
577  uint8_t ESI : 1;
578 
580  uint8_t DLC : 4;
581 
583  uint8_t BRS : 1;
584 
586  uint8_t FDF : 1;
587 
589  uint8_t reserved : 1;
590 
592  uint8_t EFC : 1;
593 
595  uint8_t MM : 8;
596 
598 
599 
600 typedef enum
601 {
604 
607 
610 
613 
616 
619 
622 
626 
627 typedef enum
628 {
631 
634 
637 
641 
642 
646 typedef struct
647 {
648  union
649  {
651  uint32_t word;
652 
653  struct
654  {
656  uint16_t SFID2 : 11;
657 
659  uint8_t reserved : 5;
660 
662  uint16_t SFID1 : 11;
663 
666 
669  };
670  };
672 
673 
674 
675 typedef enum
676 {
679 
682 
685 
688 
691 
694 
697 
701 
702 typedef enum
703 {
706 
709 
712 
716 
717 
721 typedef struct
722 {
723 
725  uint32_t EFID2 : 29;
726 
728  uint8_t reserved : 1;
729 
732 
734  uint32_t EFID1 : 29;
735 
739 
740 
741 typedef enum {
746 
750 typedef struct
751 {
752  union
753  {
755  uint32_t word;
756 
757  struct {
759  uint8_t RRFE : 1;
760 
762  uint8_t RRFS : 1;
763 
770 
777 
779  uint32_t reserved : 26;
780  };
781  };
783 
784 
785 
786 // ~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*
787 // TCAN4x5x Device Structures
788 // ~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*~*
789 
790 
794 typedef struct
795 {
796  union
797  {
799  uint32_t word;
800 
801  struct
802  {
804  uint8_t VTWD : 1;
805 
807  uint8_t M_CAN_INT : 1;
808 
810  uint8_t SWERR : 1;
811 
813  uint8_t SPIERR : 1;
814 
816  uint8_t CBF : 1;
817 
819  uint8_t CANERR : 1;
820 
822  uint8_t WKRQ : 1;
823 
825  uint8_t GLOBALERR : 1;
826 
828  uint8_t CANDOM : 1;
829 
831  uint8_t RESERVED : 1;
832 
834  uint8_t CANTO : 1;
835 
837  uint8_t RESERVED2 : 1;
838 
840  uint8_t FRAME_OVF : 1;
841 
843  uint8_t WKERR : 1;
844 
846  uint8_t LWU : 1;
847 
849  uint8_t CANINT : 1;
850 
852  uint8_t ECCERR : 1;
853 
855  uint8_t RESERVED3 : 1;
856 
858  uint8_t WDTO : 1;
859 
861  uint8_t TSD : 1;
862 
864  uint8_t PWRON : 1;
865 
867  uint8_t UVIO : 1;
868 
870  uint8_t UVSUP : 1;
871 
873  uint8_t SMS : 1;
874 
876  uint8_t CANBUSBAT : 1;
877 
879  uint8_t CANBUSGND : 1;
880 
882  uint8_t CANBUSOPEN : 1;
883 
885  uint8_t CANLGND : 1;
886 
888  uint8_t CANHBAT : 1;
889 
891  uint8_t CANHCANL : 1;
892 
894  uint8_t CANBUSTERMOPEN : 1;
895 
897  uint8_t CANBUSNORM : 1;
898  };
899  };
901 
905 typedef struct
906 {
907  union
908  {
910  uint32_t word;
911 
912  struct
913  {
915  uint8_t RESERVED1 : 8;
916 
918  uint8_t CANDOMEN : 1;
919 
921  uint8_t RESERVED2 : 1;
922 
924  uint8_t CANTOEN : 1;
925 
927  uint8_t RESERVED3 : 1;
928 
930  uint8_t FRAME_OVFEN : 1;
931 
933  uint8_t WKERREN : 1;
934 
936  uint8_t LWUEN : 1;
937 
939  uint8_t CANINTEN : 1;
940 
942  uint8_t ECCERREN : 1;
943 
945  uint8_t RESERVED4 : 1;
946 
948  uint8_t WDTOEN : 1;
949 
951  uint8_t TSDEN : 1;
952 
954  uint8_t PWRONEN : 1;
955 
957  uint8_t UVIOEN : 1;
958 
960  uint8_t UVSUPEN : 1;
961 
963  uint8_t SMSEN : 1;
964 
966  uint8_t CANBUSBATEN : 1;
967 
969  uint8_t CANBUSGNDEN : 1;
970 
972  uint8_t CANBUSOPENEN : 1;
973 
975  uint8_t CANLGNDEN : 1;
976 
978  uint8_t CANHBATEN : 1;
979 
981  uint8_t CANHCANLEN : 1;
982 
984  uint8_t CANBUSTERMOPENEN : 1;
985 
987  uint8_t CANBUSNORMEN : 1;
988  };
989  };
991 
992 
993 typedef enum
994 {
999 
1000 typedef enum
1001 {
1005 
1006 typedef enum
1007 {
1012 
1013 typedef enum
1014 {
1020 
1021 typedef enum
1022 {
1028 
1029 typedef struct
1030 {
1031  union
1032  {
1034  uint32_t word;
1035 
1036  struct
1037  {
1040  uint8_t RESERVED0 : 1;
1041 
1044  uint8_t SWE_DIS: 1;
1045 
1047  uint8_t DEVICE_RESET : 1;
1048 
1050  uint8_t WD_EN : 1;
1051 
1054  uint8_t RESERVED1 : 4;
1055 
1059  uint8_t nWKRQ_CONFIG : 1;
1060 
1062  uint8_t INH_DIS : 1;
1063 
1071 
1073  uint8_t RESERVED2 : 1;
1074 
1076  uint8_t FAIL_SAFE_EN : 1;
1077 
1084 
1092 
1093 
1096  uint8_t WD_BIT_RESET : 1;
1097 
1102  uint8_t nWKRQ_VOLTAGE : 1;
1103 
1105  uint8_t RESERVED3 : 2;
1106 
1114 
1116  uint8_t RESERVED4 : 3;
1117 
1122  uint8_t CLK_REF : 1;
1123 
1125  uint8_t RESERVED5 : 2;
1126 
1127 
1135  };
1136  };
1138 
1139 
1140 #endif /* TCAN4X5X_DATA_STRUCTS_H_ */
uint8_t EFC
Event FIFO Control flag, to store tx events or not.
uint8_t RF1W
IR[5] RF1W: RX FIFO 1 watermark reached.
uint8_t PXHD
PXHD: Protocol exception handling disable 0 = Protocol exception handling enabled [default] 1 = p...
Dual ID filter, where both SFID1 and SFID2 hold IDs that can match (must match exactly) ...
uint8_t LWUEN
DEV_IE[14] : LWU, Local Wake Up.
uint8_t DataTimeSeg1andProp
DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1 ...
uint8_t ECCERREN
DEV_IE[16] : ECCERR, MRAM ECC Error.
uint8_t GLOBALERR
DEV_IR[7] : GLOBALERR, Global Error. Is the OR output of all interrupts.
uint8_t DataTqBeforeSamplePoint
DTQBSP: Number of time quanta before sample point Valid values are: 2 to 33.
uint8_t CANHCANL
DEV_IR[29] : CANHCANL, CANH and CANL shorted.
uint8_t RESERVED1
Reserved.
64 bytes of data payload
Reject the packet (do not store, do not notify MCU) if the filter matches the incoming message...
TCAN4x5x_MRAM_Element_Data_Size TxBufferElementSize
TX Buffers element size: The number of bytes for the TX Buffers (data payload)
TCAN4x5x_GFC_NO_MATCH_BEHAVIOR ANFS
GFC[5:4] : Accept Non-matching Frames Standard Valid values: TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accep...
uint8_t TSD
DEV_IR[19] : TSD, Thermal Shut Down.
uint8_t FAIL_SAFE_EN
DEV_MODE_PINS[13] : Fail safe mode enable. Excludes power up fail safe.
uint8_t SIDNumElements
Standard ID Number of Filter Elements: The number of 11-bit filters the user would like Valid range...
uint8_t PED
IR[28] PED: Protocol error in data phase (data bit time is used)
uint8_t CANHCANLEN
DEV_IE[29] : CANHCANL, CANH and CANL shorted.
uint8_t FDOE
FDOE: Can FD mode enabled, master enable for CAN FD support.
uint8_t CANLGNDEN
DEV_IE[27] : CANLGND, CANL GND.
uint8_t BECE
IE[20] BECE: MRAM Bit error corrected.
uint8_t TEFWE
IE[13] TEFWE: Tx Event FIFO watermark reached.
Classic Filter, EFID1 is the ID/filter, and EFID2 is the mask.
uint8_t BEU
IR[21] BEU: MRAM Bit error uncorrected.
uint8_t FRAME_OVF
DEV_IR[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
uint8_t RF1FE
IE[6] RF1FE: Rx FIFO 1 full.
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x Valid range is: 1 to...
uint8_t NominalTimeSeg2
NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
TCAN4x5x_GFC_NO_MATCH_BEHAVIOR
uint8_t RF0WE
IE[1] RF0WE: Rx FIFO 0 watermark reached.
uint8_t ESI
Error state indicator flag.
Used to setup the timing parameters of the MCAN module This is the raw MCAN form of the struct which ...
uint8_t FDF
CAN FD Format flag.
Struct containing the device interrupt enable bit field.
uint32_t word
Full register as single 32-bit word.
uint8_t TFE
IR[11] TFE: Tx FIFO Empty.
uint8_t BEUE
IE[21] BEUE: MRAM Bit error uncorrected.
uint8_t TEST
TEST: MCAN Test mode enable.
uint8_t RF1F
IR[6] RF1F: Rx FIFO 1 full.
uint8_t DataTimeSeg2
DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
CAN message header for transmitted messages.
uint32_t word
full register as single 32-bit word
uint8_t HPME
IE[8] HPME: High priority message.
TCAN4x5x_MRAM_Element_Data_Size
Data payload defines for the different MRAM sections, used by the TCAN4x5x_MRAM_Config struct...
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
uint8_t ECCERR
DEV_IR[16] : ECCERR, MRAM ECC Error.
uint8_t PWRON
DEV_IR[20] : PWRON, Power On Interrupt.
Dual ID filter matches if the incoming ID matches EFID1 or EFID2.
uint8_t WKERREN
DEV_IE[13] : WKERR, Wake Error.
uint8_t UVSUPEN
DEV_IE[22] : UVSUP, Undervoltage on VSUP and VCCOUT.
uint8_t NominalTqAfterSamplePoint
NTQASP: The total number of time quanta after the sample point Valid values are: 2 to 128...
uint8_t reserved2
Reserved (0)
uint8_t RESERVED2
Reserved.
uint8_t TxBufferNumElements
TX Buffers number of elements: The number of elements for the TX Buffers Valid range is: 0 to 32...
TCAN4x5x_DEV_CONFIG_GPO2_CONFIG
uint8_t DRX
IR[19] DRX: Message stored to dedicated RX buffer.
uint8_t TEFLE
IE[15] TEFLE: Tx Event FIFO element lost.
TCAN4x5x_XID_EFT_Values EFT
EFT[1:0].
Store in RX FIFO 0 if the filter matches the incoming message.
uint8_t RF0NE
IE[0] RF0NE: Rx FIFO 0 new message.
uint8_t TCFE
IE[10] TCFE: Transmission cancellation finished.
uint32_t ID
CAN ID received.
uint8_t DEVICE_RESET
DEV_MODE_PINS[2] : Device reset. Write a 1 to perform a reset on the part.
uint8_t WDTO
DEV_IR[18] : WDTO, Watchdog Time Out.
uint8_t ASM
ASM: Restricted Operation Mode. The device can only listen to CAN traffic and acknowledge, but not send anything.
uint8_t TSWE
IE[16] TSWE: Timestamp wraparound.
TCAN4x5x_XID_EFT_Values
uint8_t XTD
Extended Identifier flag.
uint8_t CANBUSGNDEN
DEV_IE[25] : CANBUSGND, CAN Shorted to GND.
uint8_t DLC
Data length code.
Struct containing the register values for the Global Filter Configuration Register.
Store in RX FIFO 0 if the filter matches the incoming message.
uint8_t RF0LE
IE[3] RF0LE: Rx FIFO 0 message lost.
uint8_t NominalSyncJumpWidth
NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 ...
uint8_t CANDOM
DEV_IR[8] : CANDOM, Can bus stuck dominant.
Used to setup the nominal timing parameters of the MCAN module This is the raw MCAN form of the struc...
uint8_t PEAE
IE[27] PEAE Protocol Error in arbitration phase (nominal bit time used)
uint8_t MON
MON: Bus monitoring mode. The device may only listen to CAN traffic, and is not allowed to acknowledg...
12 bytes of data payload
uint8_t TEFW
IR[13] TEFW: Tx Event FIFO water mark reached.
uint8_t WKRQ
DEV_IR[6] : WKRQ, Wake Request.
TCAN4x5x_DEV_CONFIG_GPO2_CONFIG GPO2_CONFIG
DEV_MODE_PINS[23:22] : nWKRQ_VOLTAGE, set the voltage rail used by the nWKRQ pin Available values are...
uint8_t CANBUSOPENEN
DEV_IE[26] : CANBUSOPEN, CAN Open fault.
uint8_t BEC
IR[20] BEC: MRAM Bit error corrected.
uint8_t ESI
Error state indicator flag.
Reject the packet (do not store, do not notify MCU) if the filter matches the incoming message...
uint8_t CANLGND
DEV_IR[27] : CANLGND, CANL GND.
uint8_t NominalTimeSeg1andProp
NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1 ...
24 bytes of data payload
uint8_t RF1LE
IE[7] RF1LE: Rx FIFO 1 message lost.
uint32_t word
Full word for register.
TCAN4x5x_DEV_CONFIG_WDT_ACTION
Disabled filter. This filter will do nothing if it matches a packet.
uint8_t Rx1NumElements
RX FIFO 1 number of elements: The number of elements for the RX FIFO 1 Valid range is: 0 to 64...
uint8_t WD_BIT_RESET
DEV_MODE_PINS[18] : Watchdog reset bit Write a 1 to reset the watchdog timer. It's recommended to use...
TCAN4x5x_SID_SFEC_Values
uint8_t RF1NE
IE[4] RF1NE: Rx FIFO 1 new message.
TCAN4x5x_DEV_CONFIG_GPIO1_CONFIG GPIO1_CONFIG
DEV_MODE_PINS[15:14] : GPIO1 configuration Configures the mode of the GPIO1 pin as an input or output...
uint8_t TSDEN
DEV_IE[19] : TSD, Thermal Shut Down.
uint8_t TOO
IR[18] TOO: Time out occurred.
uint8_t EWE
IE[24] EWE: Error_warning status changed.
uint8_t BO
IR[25] BO: Bus_off status changed.
uint8_t DataSyncJumpWidth
DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 Valid v...
uint16_t RXTS
Receive time stamp.
Range filter from EFID1 to EFID2, The XIDAM mask is not applied.
uint8_t RF0W
IR[1] RF0W: Rx FIFO 0 watermark reached.
uint8_t TEFL
IR[15] TEFL: Tx Event FIFO element lost.
uint8_t EW
IR[24] EW: Error_warning status changed.
uint8_t nWKRQ_CONFIG
DEV_MODE_PINS[8] : nWKRQ Configuration 0: Mirrors INH function 1: Wake request interrupt.
uint8_t SPIERR
DEV_IR[3] : SPI Error.
uint8_t RTR
Remote Transmission Request flag.
uint8_t RxBufNumElements
RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO) Valid range...
TCAN4x5x_SID_SFEC_Values SFEC
SFEC[2:0] Standard filter element configuration.
uint8_t PEA
IR[27] PEA Protocol Error in arbitration phase (nominal bit time used)
uint8_t PWRONEN
DEV_IE[20] : PWRON, Power On Interrupt.
uint32_t word
Full register as single 32-bit word.
uint8_t HPM
IR[8] HPM: High priority message.
uint32_t EFID2
EFID2[28:0].
uint8_t CANBUSGND
DEV_IR[25] : CANBUSGND, CAN Shorted to GND.
uint8_t XTD
Extended Identifier flag.
8 bytes of data payload
uint8_t EFBI
EFBI: Edge filtering during bus integration. 0 Disables this [default].
TCAN4x5x_DEV_CONFIG_GPO1_CONFIG
Store in RX Buffer for debug if the filter matches the incoming message. SFT is ignored if this is se...
uint8_t TXP
TXP: Transmit Pause Enable: Pause for 2 can bit times before next transmission.
uint8_t BRS
Bit rate switch used flag.
uint8_t UVIO
DEV_IR[21] : UVIO, Undervoltage on UVIO.
Standard ID filter struct.
Store in default location but set a high priority message interrupt if the filter matches the incomin...
uint8_t CANTOEN
DEV_IE[10] : CANTO, CAN Timeout.
uint32_t EFID1
EFID1[28:0].
Store in RX FIFO 1 if the filter matches the incoming message.
uint8_t FRAME_OVFEN
DEV_IE[12] : FRAME_OVF, Frame Error Overflow (If Selective Wake is equipped)
uint32_t word
Full register as single 32-bit word.
uint16_t SFID2
SFID2[10:0].
TCAN4x5x_XID_EFEC_Values EFEC
SFT Standard Filter Type.
uint8_t BRS
Bit rate switch used flag.
uint8_t CANHBATEN
DEV_IE[28] : CANHBAT, CANH to VBAT.
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
Classic filter with SFID1 as the ID to match, and SFID2 as the bit mask that applies to SFID1...
uint8_t CANINT
DEV_IR[15] : CANINT, CAN Bus Wake Up Interrupt.
uint8_t WD_EN
DEV_MODE_PINS[3] : Watchdog Enable. Use the watchdog functions to control enabling the watchdog...
uint8_t RESERVED3
DEV_IR[17] : Reserved.
uint8_t RTR
Remote Transmission Request flag.
uint8_t RESERVED3
DEV_MODE_PINS[21:20] : RESERVED. Use test mode functions to enable test modes.
TCAN4x5x_DEV_CONFIG_WAKE_CONFIG WAKE_CONFIG
uint8_t SMSEN
DEV_IE[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults.
uint8_t SMS
DEV_IR[23] : SMS, Sleep Mode Status Flag. Set when sleep mode is entered due to WKERR, UVIO, or TSD faults.
uint8_t MM
Message Marker, used if EFC is set to 1.
TCAN4x5x_DEV_CONFIG_WDT_ACTION WD_ACTION
DEV_MODE_PINS[17:16] : Watchdog action. Defines the behavior of the watchdog timer when it times out ...
uint8_t RF1L
IR[7] RF1L: Rx FIFO 1 message lost.
Range filter from EFID1 to EFID2.
uint8_t TEFN
IR[12] TEFN: Tx Event FIFO new entry.
uint8_t ARAE
IE[29] ARAE: Access to reserved address.
Store in default location but set a high priority message interrupt if the filter matches the incomin...
48 bytes of data payload
TCAN4x5x_DEV_CONFIG_WAKE_CONFIG
Store in RX FIFO 1 if the filter matches the incoming message.
uint8_t TCF
IR[10] TCF: Transmission cancellation finished.
uint8_t RESERVED2
DEV_IE[9] : RESERVED.
uint8_t FDF
CAN FD Format flag.
uint8_t FIDX
Filter index that this message matched.
Defines the number of MRAM elements and the size of the elements.
Struct containing the MCAN interrupt enable bit field.
uint8_t DataBitRatePrescaler
DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
uint8_t reserved
IR[30:31] Reserved, not writable.
uint8_t CANDOMEN
DEV_IE[8] : CANDOM, Can bus stuck dominant.
uint8_t RF1WE
IE[5] RF1WE: RX FIFO 1 watermark reached.
struct containing the bit fields of the MCAN CCCR register
uint8_t CANBUSTERMOPEN
DEV_IR[30] : CANBUSTERMOPEN, CAN Bus has termination point open.
uint8_t Rx0NumElements
RX FIFO 0 number of elements: The number of elements for the RX FIFO 0 Valid range is: 0 to 64...
uint32_t word
Full register as single 32-bit word.
uint8_t MRAFE
IE[17] MRAFE: Message RAM access failure.
uint8_t reserved3
Reserved (0)
uint8_t RESERVED1
DEV_IE[0:7] : RESERVED.
Used to setup the data timing parameters of the MCAN module This is a simplified struct, requiring only the prescaler value (1:x), number of time quanta before and after the sample point.
uint8_t RF0FE
IE[2] RF0FE: Rx FIFO 0 full.
uint8_t TxEventFIFONumElements
TX Event FIFO number of elements: The number of elements for the TX Event FIFO Valid range is: 0 to...
uint8_t INH_DIS
DEV_MODE_PINS[9] : Inhibit pin disable.
uint8_t reserved
IE[30:31] Reserved, not writable.
uint8_t RF1N
IR[4] RF1N: Rx FIFO 1 new message.
uint8_t ELOE
IE[22] ELOE: Error logging overflow.
Store in RX FIFO 1 and set a high priority message interrupt if the filter matches the incoming messa...
uint8_t TOOE
IE[18] TOOE: Time out occured.
uint8_t RESERVED4
DEV_IE[17] : Reserved.
TCAN4x5x_MRAM_Element_Data_Size RxBufElementSize
RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO...
uint8_t CANBUSNORM
DEV_IR[31] : CANBUSNOM, CAN Bus is normal flag.
uint8_t TDCFilter
TDCFilter: Transmitter delay compensation Filter Window Length Valid values are 0 to 127 mtq...
uint8_t CANBUSOPEN
DEV_IR[26] : CANBUSOPEN, CAN Open fault.
uint16_t SFID1
SFID1[10:0].
uint8_t TDCOffset
TDCO: Transmitter delay compensation offset Valid values are 0 to 127 mtq.
uint8_t TFEE
IE[11] TFEE: Tx FIFO Empty.
uint8_t nWKRQ_VOLTAGE
DEV_MODE_PINS[19] : nWKRQ_VOLTAGE, set the voltage rail used by the nWKRQ pin Available values are: 0...
TCAN4x5x_XID_EFEC_Values
Struct containing the device interrupt bit field.
Disabled filter. This filter will do nothing if it matches a packet.
uint8_t CSR
CSR: Clock stop request.
TCAN4x5x_DEV_CONFIG_GPO1_CONFIG GPIO1_GPO_CONFIG
DEV_MODE_PINS[11:10] : GPIO1 pin as a GPO function configuration Configures the behavior of GPIO1 if ...
uint8_t DataTqAfterSamplePoint
DTQASP: Number of time quanta after sample point Valid values are: 1 to 16.
uint8_t TEFFE
IE[14] TEFFE: Tx Event FIFO full.
Store in RX FIFO 1 and set a high priority message interrupt if the filter matches the incoming messa...
uint8_t MRAF
IR[17] MRAF: Message RAM access failure.
uint8_t RESERVED5
DEV_MODE_PINS[29:28] : RESERVED. Use watchdog functions to set watchdog parameters.
uint8_t ANMF
Accepted non matching frame flag.
uint8_t SWE_DIS
DEV_MODE_PINS[1] : Sleep wake error disable. Setting this to 1 will disable the 4 minute timer that p...
uint32_t word
Full register as single 32-bit word.
uint8_t RESERVED4
DEV_MODE_PINS[26:24] : RESERVED.
uint8_t PEDE
IE[28] PEDE: Protocol error in data phase (data bit time is used)
uint8_t UVSUP
DEV_IR[22] : UVSUP, Undervoltage on VSUP and VCCOUT.
Disabled filter. This filter will match nothing.
uint16_t NominalTqBeforeSamplePoint
NTQBSP: The total number of time quanta prior to sample point Valid values are: 2 to 257...
uint8_t SWERR
DEV_IR[2] : Selective Wake Error (If equipped)
uint8_t RESERVED2
DEV_IR[11] : RESERVED.
Extended ID filter struct.
Store in RX Buffer for debug if the filter matches the incoming message.
uint8_t TEFF
IR[14] TEFF: Tx Event FIFO full.
uint8_t XIDNumElements
Extended ID Number of Filter Elements: The number of 29-bit filters the user would like Valid range...
uint8_t RF0N
IR[0] RF0N: Rx FIFO 0 new message.
uint8_t CANBUSNORMEN
DEV_IE[31] : CANBUSNOM, CAN Bus is normal flag.
uint8_t TEFNE
IE[12] TEFNE: Tx Event FIFO new entry.
uint8_t WDIE
IE[26] WDIE: MRAM Watchdog Interrupt.
20 bytes of data payload
uint8_t RESERVED
DEV_IR[9] : RESERVED.
uint8_t LWU
DEV_IR[14] : LWU, Local Wake Up.
uint8_t CLK_REF
DEV_MODE_PINS[27] : CLK_REF, used to tell the device what the input clock/crystal frequency is Availa...
uint8_t reserved
Reserved (0)
uint8_t CANINTEN
DEV_IE[15] : CANINT, CAN Bus Wake Up Interrupt.
uint8_t DataBitRatePrescaler
Prescaler value, interpreted as 1:x Valid range is: 1 to 32.
uint8_t RESERVED3
DEV_IE[11] : RESERVED.
32 bytes of data payload
TCAN4x5x_MRAM_Element_Data_Size Rx0ElementSize
RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
uint8_t UVIOEN
DEV_IE[21] : UVIO, Undervoltage on UVIO.
uint8_t EP
IR[23] EP: Error_passive status changed.
uint8_t WKERR
DEV_IR[13] : WKERR, Wake Error.
uint8_t CANBUSBAT
DEV_IR[24] : CANBUSBAT, CAN Shorted to VBAT.
uint8_t WDTOEN
DEV_IE[18] : WDTO, Watchdog Time Out.
TCAN4x5x_GFC_NO_MATCH_BEHAVIOR ANFE
GFC[3:2] : Accept Non-matching Frames Extended Valid values: TCAN4x5x_GFC_ACCEPT_INTO_RXFIFO0 : Accep...
uint8_t CANBUSTERMOPENEN
DEV_IE[30] : CANBUSTERMOPEN, CAN Bus has termination point open.
uint8_t RF0L
IR[3] RF0L: Rx FIFO 0 message lost.
uint8_t CBF
DEV_IR[4] : CBF, CAN Bus Fault.
uint8_t CANERR
DEV_IR[5] : CANERR, CAN Error.
uint8_t M_CAN_INT
DEV_IR[1] M_CAN_INT: There are MCAN interrupts pending.
uint8_t CANTO
DEV_IR[10] : CANTO, CAN Timeout.
uint8_t BOE
IE[25] BOE: Bus_off status changed.
Struct containing the MCAN interrupt bit field.
uint8_t DRXE
IE[19] DRXE: Message stored to dedicated RX buffer.
uint8_t TSW
IR[16] TSW: Timestamp wrapped around.
Range Filter. SFID1 holds the start address, and SFID2 holds the end address. Any address in between ...
uint8_t DLC
Data length code.
uint8_t BRSE
BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support.
uint8_t RRFE
GFC[0] : Reject Remote Frames for Extended IDs.
uint8_t CANBUSBATEN
DEV_IE[24] : CANBUSBAT, CAN Shorted to VBAT.
16 bytes of data payload
TCAN4x5x_MRAM_Element_Data_Size Rx1ElementSize
RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
uint8_t RRFS
GFC[1] : Reject Remote Frames for Standard IDs.
TCAN4x5x_DEV_CONFIG_GPIO1_CONFIG
uint8_t TCE
IE[9] TCE: Transmission completed.
TCAN4x5x_SID_SFT_Values
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
uint8_t ARA
IR[29] ARA: Access to reserved address.
uint8_t VTWD
DEV_IR[0] VTWD: Global Voltage, Temp, or Watchdog (if equipped) Interrupt.
uint8_t EPE
IE[23] EPE: Error_passive status changed.
uint8_t NISO
NSIO: Non Iso Operation 0: CAN FD frame format according to ISO 11898-1:2015 [default] 1: CAN FD ...
uint8_t RF0F
IR[2] RF0F: Rx FIFO 0 full.
uint8_t WDI
IR[26] WDI: MRAM Watchdog Interrupt.
uint8_t ELO
IR[22] ELO: Error logging overflow.
uint8_t CANHBAT
DEV_IR[28] : CANHBAT, CANH to VBAT.
uint8_t RESERVED0
DEV_MODE_PINS[0] : Test mode configuration. Reserved in this struct It is recommended to use the test...
TCAN4x5x_SID_SFT_Values SFT
SFT Standard Filter Type.
uint8_t TC
IR[9] TC: Transmission completed.
uint8_t DAR
DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration...
Used to setup the nominal timing parameters of the MCAN module This is a simplified struct...
uint32_t ID
CAN ID to send.