TCAN4550  1p2
TCAN4550.c
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1 /*
2  * TCAN4550.c
3  * Description: This file contains TCAN4550 functions, and relies on the TCAN4x5x_SPI abstraction functions
4  * Additional Feature Sets of TCAN4550 vs TCAN4x5x:
5  * - Watchdog Timer Functions
6  *
7  * Version: 1.2.0
8  * Date: 5/1/2019
9  *
10  * Change Log
11  * 1.2.0 (5/1/2019)
12  * - Added the MCAN_ConfigureGlobalFilter function for changing default packet behavior
13  * - Added a define to allow caching of MCAN configuration registers to reduce the number of SPI reads
14  * - Added a FIFO fill level checker to the MCAN_ReadNextFIFO method to exit if there is no new element to read
15  * - Added a read function for SID and XID filters
16  * - Added a SPIERR clear function
17  *
18  * 1.1.1 (6/12/2018)
19  * - Minor typo correction for the ConfigureNominalTiming_Simple() function
20  *
21  * 1.1 (6/6/2018)
22  * - Updates to code for readability, and consistency
23  * - Some function names updated for consistency
24  * - Added functionality and abstraction for interrupts
25  * - Bit fields updated for final silicon
26  *
27  *
28  * Created on: Oct 1, 2017
29  * Author: Texas Instruments
30  *
31  *
32  * Copyright (c) 2017 Texas Instruments Incorporated. All rights reserved.
33  * Software License Agreement
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  *
39  * Redistributions of source code must retain the above copyright
40  * notice, this list of conditions and the following disclaimer.
41  *
42  * Redistributions in binary form must reproduce the above copyright
43  * notice, this list of conditions and the following disclaimer in the
44  * documentation and/or other materials provided with the
45  * distribution.
46  *
47  * Neither the name of Texas Instruments Incorporated nor the names of
48  * its contributors may be used to endorse or promote products derived
49  * from this software without specific prior written permission.
50  *
51  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
52  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
53  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
54  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
55  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
56  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
57  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
58  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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60  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
61  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
62  */
63 #include "TCAN4550.h"
64 
65 
66 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
67 // If caching is enabled, define the necessary variables
68 uint32_t TCAN4x5x_MCAN_CACHE[9];
69 #endif
70 
78 bool
80 {
81  uint8_t i;
82  uint32_t readValue, firstRead;
83 
84  firstRead = AHB_READ_32(REG_MCAN_CCCR);
86  return true;
87 
88  // Unset the CSA and CSR bits since those will be set if we're in standby mode. Writing a 1 to these bits will force a clock stop event and prevent the return to normal mode
90  // Try up to 5 times to set the CCCR register, if not, then fail config, since we need these bits set to configure the device.
91  for (i = 5; i > 0; i--)
92  {
94  readValue = AHB_READ_32(REG_MCAN_CCCR);
95 
97  return true;
98  else if (i == 1) // Ran out of tries, give up
99  return false;
100  }
101  return true;
102 }
103 
104 
112 bool
114 {
115  uint8_t i;
116  uint32_t readValue;
117 
118  readValue = AHB_READ_32(REG_MCAN_CCCR);
119  if ((readValue & REG_BITS_MCAN_CCCR_CCE) == 0)
120  return true;
121 
122  // Try up to 5 times to unset the CCCR register, if not, then fail config, since we need these bits set to configure the device.
123  for (i = 5; i > 0; i--)
124  {
126  readValue = AHB_READ_32(REG_MCAN_CCCR);
127 
128  if ((readValue & REG_BITS_MCAN_CCCR_CCE) == 0)
129  return true;
130  else if (i == 1)
131  return false;
132  }
133  return true;
134 }
135 
136 
149 bool
151 {
152  uint32_t value, readValue;
153 
154 
155  value = cccrConfig->word;
156  value &= ~(REG_BITS_MCAN_CCCR_RESERVED_MASK | REG_BITS_MCAN_CCCR_CSA | REG_BITS_MCAN_CCCR_CCE | REG_BITS_MCAN_CCCR_INIT); // Bitwise AND to get the valid bits (ignore reserved bits and the CCE and INIT)
157 
158  // If we made it here, we can update the value so that our protected write stays enabled
160 
161 
162  AHB_WRITE_32(REG_MCAN_CCCR, value);
163 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
164  readValue = AHB_READ_32(REG_MCAN_CCCR);
165 
166  // Need to do these bitwise ANDs to make this work for clock stop requests and not trigger a false failure when comparing read back value
169  {
170  // If our written value and read back value aren't the same, then we return a failure.
171  return false;
172  }
173 
174  // Check to see if the CSR bits are not as expected, since this can be set by the hardware.
175  if ((readValue & REG_BITS_MCAN_CCCR_CSR) != cccrConfig->CSR)
176  {
177  // Then there's a difference in the CSR bits, which may not be a failure.
179  {
180  // CSR bit is set due to being in standby mode. Not a failure.
181  return true;
182  } else {
183  // It's not matching for some other reason, we've got a real failure.
184  return false;
185  }
186  }
187 #endif
188  return true;
189 }
190 
191 
199 void
201 {
202  cccrConfig->word = AHB_READ_32(REG_MCAN_CCCR);
203 }
204 
205 
216 void
218 {
219  uint32_t regData;
220 
221  // Read the data timing register
222  regData = AHB_READ_32(REG_MCAN_DBTP);
223 
224  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
225  dataTiming->DataBitRatePrescaler = ((regData >> 16) & 0x1F) + 1;
226  dataTiming->DataTqBeforeSamplePoint = ((regData >> 8) & 0x1F) + 2;
227  dataTiming->DataTqAfterSamplePoint = ((regData >> 4) & 0xF) + 1;
228 }
229 
230 
238 void
240 {
241  uint32_t regData;
242 
243  // Read the data timing register
244  regData = AHB_READ_32(REG_MCAN_DBTP);
245 
246  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
247  dataTiming->DataBitRatePrescaler = ((regData >> 16) & 0x1F);
248  dataTiming->DataTimeSeg1andProp = ((regData >> 8) & 0x1F);
249  dataTiming->DataTimeSeg2 = ((regData >> 4) & 0xF);
250  dataTiming->DataSyncJumpWidth = (regData & 0xF);
251 
252  if (regData & REG_BITS_MCAN_DBTP_TDC_EN)
253  {
254  // If TDC is set, then read the TDC register
255  regData = AHB_READ_32(REG_MCAN_TDCR);
256  dataTiming->TDCOffset = ((regData >> 8) & 0x7F);
257  dataTiming->TDCFilter = (regData & 0x7F);
258  } else {
259  dataTiming->TDCOffset = 0;
260  dataTiming->TDCFilter = 0;
261  }
262 }
263 
264 
276 bool
278 {
279  uint32_t writeValue, TDCOWriteValue;
280  uint32_t tempValue;
281 
282  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
283  // Check to make sure prescaler is in range 1-32
284  tempValue = dataTiming->DataBitRatePrescaler;
285  if (tempValue > 32)
286  tempValue = 32;
287  else if (tempValue == 0)
288  tempValue = 1;
289 
290  writeValue = ((uint32_t)(tempValue - 1)) << 16; // Subtract 1 because MCAN expects 1 less than actual value
291 
292  // Check Tq before sample point is within valid range of 2-33
293  tempValue = dataTiming->DataTqBeforeSamplePoint;
294  if (tempValue > 33)
295  tempValue = 33;
296  else if (tempValue < 2)
297  tempValue = 2;
298 
299  writeValue |= ((uint32_t)(tempValue - 2)) << 8; // Subtract 2 for the Sync bit and because MCAN expects 1 less than actual
300  TDCOWriteValue = (uint32_t)(tempValue - 1) << 8; // Subtract 1 to make secondary sample point match primary. We take the sync bit out. See below note as to why
301  // Check Tq after the sample point is within valid range of 1-16
302  tempValue = dataTiming->DataTqAfterSamplePoint;
303  if (tempValue > 16)
304  tempValue = 16;
305  else if (tempValue == 0)
306  tempValue = 1;
307 
308  writeValue |= ((uint32_t)(tempValue - 1)) << 4; // Subtract 1 because MCAN expects 1 less than actual value
309 
310  //Copy SJW from tq after sample point in most cases
311  writeValue |= ((uint32_t)(tempValue - 1)); // Subtract 1 because MCAN expects 1 less than actual value
312 
313  // NOTE: In most cases, you want to enable Transceiver Delay Compensation Offset and set it to 1 more than what's in the DTSEG1 register in MCAN.
314  // Doing this ensures that the secondary sample point is the same as the primary sample point
315  writeValue |= REG_BITS_MCAN_DBTP_TDC_EN;
316  AHB_WRITE_32(REG_MCAN_DBTP, writeValue); // Write the value to the DBTP register
317 
318 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
319  // Check to see if the write was successful.
320  tempValue = AHB_READ_32(REG_MCAN_DBTP);
321  if (tempValue != writeValue)
322  return false;
323 #endif
324 
325  AHB_WRITE_32(REG_MCAN_TDCR, TDCOWriteValue);
326 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
327  // Check to see if the write was successful.
328  tempValue = AHB_READ_32(REG_MCAN_TDCR);
329  if (tempValue != TDCOWriteValue)
330  return false;
331 #endif
332 
333  // Configure the Timestamp counter to use an external time stamp value. This is required to use time stamps with CAN FD
335  return true;
336 }
337 
338 
351 bool
353 {
354  uint32_t writeValue;
355 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
356  uint32_t tempValue;
357 #endif
358 
359  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
360  writeValue = ((uint32_t)(dataTiming->DataBitRatePrescaler & 0x1F)) << 16;
361  writeValue |= ((uint32_t)(dataTiming->DataTimeSeg1andProp & 0x1F)) << 8;
362  writeValue |= ((uint32_t)(dataTiming->DataTimeSeg2 & 0x0F)) << 4;
363  writeValue |= ((uint32_t)(dataTiming->DataSyncJumpWidth & 0x0F));
364  if ((dataTiming->TDCOffset > 0) || (dataTiming->TDCFilter > 0))
365  {
366  // If either of these are set, then enable transmitter delay compensation
367  writeValue |= REG_BITS_MCAN_DBTP_TDC_EN;
368  AHB_WRITE_32(REG_MCAN_DBTP, writeValue);
369 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
370  // Check to see if the write was successful.
371  tempValue = AHB_READ_32(REG_MCAN_DBTP);
372  if (tempValue != writeValue)
373  return false;
374 #endif
375 
376  writeValue = (uint32_t)(dataTiming->TDCOffset & 0x7F) << 8;
377  writeValue |= (uint32_t)(dataTiming->TDCFilter & 0x7F);
378  AHB_WRITE_32(REG_MCAN_TDCR, writeValue);
379 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
380  // Check to see if the write was successful.
381  tempValue = AHB_READ_32(REG_MCAN_TDCR);
382  if (tempValue != writeValue)
383  return false;
384 #endif
385  } else {
386  AHB_WRITE_32(REG_MCAN_DBTP, writeValue);
387 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
388  // Check to see if the write was successful.
389  tempValue = AHB_READ_32(REG_MCAN_DBTP);
390  if (tempValue != writeValue)
391  return false;
392 #endif
393  }
394 
395  // Configure the Timestamp counter to use an external time stamp value. This is required to use time stamps with CAN FD
397 
398  return true;
399 }
400 
401 
409 void
411 {
412  uint32_t readValue;
413 
414  readValue = AHB_READ_32(REG_MCAN_NBTP);
415 
416  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
417  nomTiming->NominalBitRatePrescaler = ((readValue >> 16) & 0x1FF) + 1;
418  nomTiming->NominalTqBeforeSamplePoint = ((readValue >> 8) & 0xFF) + 2;
419  nomTiming->NominalTqAfterSamplePoint = (readValue & 0x7F) + 1;
420 }
421 
422 
430 void
432 {
433  uint32_t readValue;
434 
435  readValue = AHB_READ_32(REG_MCAN_NBTP);
436 
437  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
438  nomTiming->NominalSyncJumpWidth = ((readValue >> 25) & 0x7F);
439  nomTiming->NominalBitRatePrescaler = ((readValue >> 16) & 0x1FF);
440  nomTiming->NominalTimeSeg1andProp = ((readValue >> 8) & 0xFF);
441  nomTiming->NominalTimeSeg2 = (readValue & 0x7F);
442 }
443 
444 
456 bool
458 {
459  uint32_t writeValue, tempValue;
460 
461 
462  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
463  // Check that prescaler is in valid range of 1-512
464  tempValue = nomTiming->NominalBitRatePrescaler;
465  if (tempValue > 512)
466  tempValue = 512;
467  else if (tempValue == 0)
468  tempValue = 1;
469  writeValue = ((uint32_t)(tempValue - 1)) << 16; // Subtract 1 because MCAN expects 1 less than actual value
470 
471 
472  // Check that prescaler is in valid range of 2-257
473  tempValue = nomTiming->NominalTqBeforeSamplePoint;
474  if (tempValue > 257)
475  tempValue = 257;
476  else if (tempValue < 2)
477  tempValue = 2;
478  writeValue |= ((uint32_t)(tempValue - 2)) << 8; // Subtract 2, 1 for sync, and 1 because MCAN expects 1 less than actual value
479 
480  // Check that prescaler is in valid range of 2-257
481  tempValue = nomTiming->NominalTqAfterSamplePoint;
482  if (tempValue > 128)
483  tempValue = 128;
484  else if (tempValue < 2)
485  tempValue = 2;
486  writeValue |= ((uint32_t)(tempValue - 1)); // Subtract 1 because MCAN expects 1 less than actual value
487  writeValue |= ((uint32_t)(tempValue - 1)) << 25; // NSJW is made to match the MCAN after bit time value
488 
489  // Write value to the NBTP register
490  AHB_WRITE_32(REG_MCAN_NBTP, writeValue);
491 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
492  // Check the write was successful
493  tempValue = AHB_READ_32(REG_MCAN_NBTP);
494  if (tempValue != writeValue)
495  return false;
496 #endif
497 
498  return true;
499 }
500 
501 
513 bool
515 {
516  uint32_t writeValue;
517 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
518  uint32_t tempValue;
519 #endif
520  // These registers are only writable if CCE and INIT are both set. Sets the nominal bit timing and prescaler information
521  writeValue = ((uint32_t)(nomTiming->NominalSyncJumpWidth & 0x7F)) << 25;
522  writeValue |= ((uint32_t)(nomTiming->NominalBitRatePrescaler & 0x1FF)) << 16;
523  writeValue |= ((uint32_t)(nomTiming->NominalTimeSeg1andProp)) << 8;
524  writeValue |= ((uint32_t)(nomTiming->NominalTimeSeg2 & 0x7F));
525  AHB_WRITE_32(REG_MCAN_NBTP, writeValue);
526 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
527  // Check that the write was successful
528  tempValue = AHB_READ_32(REG_MCAN_NBTP);
529  if (tempValue != writeValue)
530  return false;
531 #endif
532  return true;
533 }
534 
546 bool
548 {
549  uint32_t writeValue, readValue;
550 
551 
552  writeValue = (gfc->word & REG_BITS_MCAN_GFC_MASK);
553  AHB_WRITE_32(REG_MCAN_GFC, writeValue);
554 
555 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
556  readValue = AHB_READ_32(REG_MCAN_GFC);
557 
558  // Need to do these bitwise ANDs to make this work for clock stop requests and not trigger a false failure when comparing read back value
559  if (readValue != writeValue)
560  {
561  // If our written value and read back value aren't the same, then we return a failure.
562  return false;
563  }
564 #endif
565  return true;
566 }
567 
568 
583 bool
585 {
586  uint16_t startAddress = 0x0000; // Used to hold the start and end addresses for each section as we write them into the appropriate registers
587  uint32_t registerValue = 0; // Used to create the 32-bit word to write to each register
588  uint32_t readValue = 0;
589  uint8_t MRAMValue;
590 
591 
592  // First the 11-bit filter section can be setup.
593  MRAMValue = MRAMConfig->SIDNumElements;
594  if (MRAMValue > 128)
595  MRAMValue = 128;
596 
597  registerValue = 0;
598  if (MRAMValue > 0)
599  {
600  registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
601  }
602  startAddress += (4 * (uint16_t)MRAMValue);
603  AHB_WRITE_32(REG_MCAN_SIDFC, registerValue);
604 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
606 #endif
607 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
608  // Verify content of register
609  readValue = AHB_READ_32(REG_MCAN_SIDFC);
610  if (readValue != registerValue)
611  return false;
612 #endif
613 
614 
615  // The 29-bit extended filter section
616  MRAMValue = MRAMConfig->XIDNumElements;
617  if (MRAMValue > 64)
618  MRAMValue = 64;
619 
620  registerValue = 0;
621  if (MRAMValue > 0)
622  {
623  registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
624  }
625  startAddress += (8 * (uint16_t)MRAMValue);
626  AHB_WRITE_32(REG_MCAN_XIDFC, registerValue);
627 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
629 #endif
630 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
631  // Verify content of register
632  readValue = AHB_READ_32(REG_MCAN_XIDFC);
633  if (readValue != registerValue)
634  return false;
635 #endif
636 
637 
638  // RX FIFO 0
639  MRAMValue = MRAMConfig->Rx0NumElements;
640  if (MRAMValue > 64)
641  MRAMValue = 64;
642 
643  registerValue = 0;
644  if (MRAMValue > 0)
645  {
646  registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress); // Write start address and the number of elements
647  registerValue |= REG_BITS_MCAN_RXF0C_F0OM_OVERWRITE; // Also enable overwrite mode when FIFO is full
648  }
649  startAddress += (((uint32_t)TCAN4x5x_MCAN_TXRXESC_DataByteValue((uint8_t)MRAMConfig->Rx0ElementSize) + 8) * (uint16_t)MRAMValue);
650  AHB_WRITE_32(REG_MCAN_RXF0C, registerValue);
651 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
653 #endif
654 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
655  // Verify content of register
656  readValue = AHB_READ_32(REG_MCAN_RXF0C);
657  if (readValue != registerValue)
658  return false;
659 #endif
660 
661  // RX FIFO 1
662  MRAMValue = MRAMConfig->Rx1NumElements;
663  if (MRAMValue > 64)
664  MRAMValue = 64;
665 
666  registerValue = 0;
667  if (MRAMValue > 0)
668  {
669  registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
670  }
671  startAddress += (((uint32_t)TCAN4x5x_MCAN_TXRXESC_DataByteValue((uint8_t)MRAMConfig->Rx1ElementSize) + 8) * (uint16_t)MRAMValue);
672  AHB_WRITE_32(REG_MCAN_RXF1C, registerValue);
673 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
675 #endif
676 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
677  // Verify content of register
678  readValue = AHB_READ_32(REG_MCAN_RXF1C);
679  if (readValue != registerValue)
680  return false;
681 #endif
682 
683  // RX Buffers
684  // Since RXBuffers are a little weird, you don't actually tell MCAN how many elements you have. Instead, you tell it indirectly through filters.
685  // For example, you would have to setup a filter to tell it which value to go to
686  MRAMValue = MRAMConfig->RxBufNumElements;
687  if (MRAMValue > 64)
688  MRAMValue = 64;
689 
690  registerValue = 0;
691  if (MRAMValue > 0)
692  {
693  registerValue = ((uint32_t)startAddress);
694  }
695  startAddress += (((uint32_t)TCAN4x5x_MCAN_TXRXESC_DataByteValue((uint8_t)MRAMConfig->RxBufElementSize) + 8) * (uint16_t)MRAMValue);
696  AHB_WRITE_32(REG_MCAN_RXBC, registerValue);
697 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
699 #endif
700 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
701  // Verify content of register
702  readValue = AHB_READ_32(REG_MCAN_RXBC);
703 
704  if (readValue != registerValue)
705  return false;
706 #endif
707 
708  // TX Event FIFO
709  MRAMValue = MRAMConfig->TxEventFIFONumElements;
710  if (MRAMValue > 32)
711  MRAMValue = 32;
712 
713  registerValue = 0;
714  if (MRAMValue > 0)
715  {
716  registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
717  }
718  startAddress += (8 * (uint16_t)MRAMValue);
719  AHB_WRITE_32(REG_MCAN_TXEFC, registerValue);
720 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
722 #endif
723 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
724  // Verify content of register
725  readValue = AHB_READ_32(REG_MCAN_TXEFC);
726  if (readValue != registerValue)
727  return false;
728 #endif
729 
730  // TX Buffer
731  MRAMValue = MRAMConfig->TxBufferNumElements;
732  if (MRAMValue > 32)
733  MRAMValue = 32;
734 
735 
736  registerValue = 0;
737  if (MRAMValue > 0)
738  {
739  registerValue = ((uint32_t)(MRAMValue) << 24) | ((uint32_t)startAddress);
740  registerValue |= REG_BITS_MCAN_TXBC_TFQM; // Sets TFQM to 1 (Queue mode), and sets all registers to be generic non-dedicated buffers.
741  }
742  startAddress += (((uint32_t)TCAN4x5x_MCAN_TXRXESC_DataByteValue((uint8_t)MRAMConfig->TxBufferElementSize) + 8) * (uint16_t)MRAMValue);
743  AHB_WRITE_32(REG_MCAN_TXBC, registerValue);
744 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
746 #endif
747 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
748  // Verify content of register
749  readValue = AHB_READ_32(REG_MCAN_TXBC);
750  if (readValue != registerValue)
751  return false;
752 #endif
753 
754 
755  // Check and make sure we did not go out of memory bounds. If it is, return fail
756  if ((startAddress - 1) > (MRAM_SIZE + REG_MRAM))
757  return false;
758 
759  // Set the RX Element Size Register
760  registerValue = ((uint32_t)(MRAMConfig->RxBufElementSize) << 8) | ((uint32_t)(MRAMConfig->Rx1ElementSize) << 4) | (uint32_t)(MRAMConfig->Rx0ElementSize);
761  AHB_WRITE_32(REG_MCAN_RXESC, registerValue);
762 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
764 #endif
765 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
766  // Verify content of register
767  readValue = AHB_READ_32(REG_MCAN_RXESC);
768  if (readValue != registerValue)
769  return false;
770 #endif
771 
772 
773  // Set the TX Element Size Register
774  registerValue = (uint32_t)(MRAMConfig->TxBufferElementSize);
775  AHB_WRITE_32(REG_MCAN_TXESC, registerValue);
776 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
778 #endif
779 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES
780  // Verify content of register
781  readValue = AHB_READ_32(REG_MCAN_TXESC);
782  if (readValue != registerValue)
783  return false;
784 #endif
785 
786  return true;
787 }
788 
789 
795 void
797 {
798  uint16_t curAddr;
799  const uint16_t endAddr = REG_MRAM + MRAM_SIZE;
800 
801  // Need to write 0's to the entire MRAM
802  curAddr = REG_MRAM;
803 
804  while (curAddr < endAddr)
805  {
806  AHB_WRITE_32(curAddr, 0);
807  curAddr += 4;
808  }
809 
810 }
811 
812 
827 uint8_t
829 {
830  uint32_t readData;
831  uint16_t startAddress;
832  uint8_t i, getIndex, elementSize;
833 
834  // Get the get buffer location and size, depending on the source type
835  switch (FIFODefine)
836  {
837  default: // RXFIFO0 is default
838  {
839  readData = AHB_READ_32(REG_MCAN_RXF0S);
840  if ((readData & 0x0000007F) == 0)
841  return 0;
842  getIndex = (uint8_t) ((readData & 0x3F00) >> 8);
843  // Get the RX 0 Start location and size...
844 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
846 #else
847  readData = AHB_READ_32(REG_MCAN_RXF0C);
848 #endif
849  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
850 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
852 #else
853  readData = AHB_READ_32(REG_MCAN_RXESC);
854 #endif
855  readData &= 0x07;
856  elementSize = TCAN4x5x_MCAN_TXRXESC_DataByteValue(readData); // Maximum theoretical data payload supported by this MCAN configuration
857  // Calculate the actual start address for the latest index
858  startAddress += (((uint32_t)elementSize + 8) * getIndex);
859  break;
860  }
861 
862  case RXFIFO1:
863  {
864  readData = AHB_READ_32(REG_MCAN_RXF1S);
865  if ((readData & 0x0000007F) == 0)
866  return 0;
867  getIndex = (uint8_t) ((readData & 0x3F00) >> 8);
868  // Get the RX 1 Start location and size...
869 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
871 #else
872  readData = AHB_READ_32(REG_MCAN_RXF1C);
873 #endif
874  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
875 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
877 #else
878  readData = AHB_READ_32(REG_MCAN_RXESC);
879 #endif
880  readData = (readData & 0x70) >> 4;
881  elementSize = TCAN4x5x_MCAN_TXRXESC_DataByteValue(readData); // Maximum theoretical data payload supported by this MCAN configuration
882  // Calculate the actual start address for the latest index
883  startAddress += (((uint32_t)elementSize + 8) * getIndex);
884  break;
885  }
886  }
887 
888 
889  // Read the data, start with a burst read
890  AHB_READ_BURST_START(startAddress, 2);
891  readData = AHB_READ_BURST_READ(); // First header
892  header->ESI = (readData & 0x80000000) >> 31;
893  header->XTD = (readData & 0x40000000) >> 30;
894  header->RTR = (readData & 0x20000000) >> 29;
895 
896  if (header->XTD)
897  header->ID = (readData & 0x1FFFFFFF);
898  else
899  header->ID = (readData & 0x1FFC0000) >> 18;
900 
901  readData = AHB_READ_BURST_READ(); // Second header
902  AHB_READ_BURST_END(); // Terminate the burst read
903  header->RXTS = (readData & 0x0000FFFF);
904  header->DLC = (readData & 0x000F0000) >> 16;
905  header->BRS = (readData & 0x00100000) >> 20;
906  header->FDF = (readData & 0x00200000) >> 21;
907  header->FIDX = (readData & 0x7F000000) >> 24;
908  header->ANMF = (readData & 0x80000000) >> 31;
909 
910  // Get the actual data
911  // If the data payload size of the header is smaller than the maximum we can store, then update the new element size to read only what we need to (prevents accidental overflow reading)
912  if (TCAN4x5x_MCAN_DLCtoBytes(header->DLC) < elementSize )
913  elementSize = TCAN4x5x_MCAN_DLCtoBytes(header->DLC); // Returns the number of data bytes
914 
915  // Start a burst read for the number of data bytes we require at the data payload area of the MRAM
916  // The equation below ensures that we will always read the correct number of words since the divide truncates any remainders, and we need a ceil()-like function
917  if (elementSize > 0) {
918  AHB_READ_BURST_START(startAddress + 8, (elementSize + 3) >> 2);
919  i = 0; // Used to count the number of bytes we have read.
920  while (i < elementSize) {
921  if ((i % 4) == 0) {
922  readData = AHB_READ_BURST_READ();
923  }
924 
925  dataPayload[i] = (uint8_t)((readData >> ((i % 4) * 8)) & 0xFF);
926  i++;
927  if (i > elementSize)
928  i = elementSize;
929  }
930  AHB_READ_BURST_END(); // Terminate the burst read
931  }
932  // Acknowledge the FIFO read
933  switch (FIFODefine)
934  {
935  default: // RXFIFO0
936  AHB_WRITE_32(REG_MCAN_RXF0A, getIndex);
937  break;
938 
939  case RXFIFO1:
940  AHB_WRITE_32(REG_MCAN_RXF1A, getIndex);
941  break;
942  }
943 
944 
945  return i; // Return the number of bytes retrieved
946 }
947 
948 
963 uint8_t
964 TCAN4x5x_MCAN_ReadRXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
965 {
966  uint32_t readData;
967  uint16_t startAddress;
968  uint8_t i, getIndex, elementSize;
969 
970  // Get the get buffer location and size
971  getIndex = bufIndex;
972  if (getIndex > 64)
973  getIndex = 64;
974 
975  // Get the RX Buffer Start location and size...
976 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
978 #else
979  readData = AHB_READ_32(REG_MCAN_RXBC);
980 #endif
981  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
982 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
984 #else
985  readData = AHB_READ_32(REG_MCAN_RXESC);
986 #endif
987  readData = (readData & 0x0700) >> 8;
988  elementSize = TCAN4x5x_MCAN_TXRXESC_DataByteValue(readData); // Maximum theoretical data payload supported by this MCAN configuration
989  // Calculate the actual start address for the latest index
990  startAddress += (((uint32_t)elementSize + 8) * getIndex);
991 
992 
993 
994  // Read the data, start with a burst read
995  AHB_READ_BURST_START(startAddress, 2);
996  readData = AHB_READ_BURST_READ(); // First header
997  header->ESI = (readData & 0x80000000) >> 31;
998  header->XTD = (readData & 0x40000000) >> 30;
999  header->RTR = (readData & 0x20000000) >> 29;
1000 
1001  if (header->XTD)
1002  header->ID = (readData & 0x1FFFFFFF);
1003  else
1004  header->ID = (readData & 0x1FFC0000) >> 18;
1005 
1006  readData = AHB_READ_BURST_READ(); // Second header
1007  AHB_READ_BURST_END(); // Terminate the burst read
1008  header->RXTS = (readData & 0x0000FFFF);
1009  header->DLC = (readData & 0x000F0000) >> 16;
1010  header->BRS = (readData & 0x00100000) >> 20;
1011  header->FDF = (readData & 0x00200000) >> 21;
1012  header->FIDX = (readData & 0x7F000000) >> 24;
1013  header->ANMF = (readData & 0x80000000) >> 31;
1014 
1015  // Get the actual data
1016  // If the data payload size of the header is smaller than the maximum we can store, then update the new element size to read only what we need to (prevents accidentical overflow reading)
1017  if (TCAN4x5x_MCAN_DLCtoBytes(header->DLC) < elementSize )
1018  elementSize = TCAN4x5x_MCAN_DLCtoBytes(header->DLC); // Returns the number of data bytes
1019 
1020  // Start a burst read for the number of data bytes we require at the data payload area of the MRAM
1021  // The equation below ensures that we will always read the correct number of words since the divide truncates any remainders, and we need a ceil()-like function
1022  if (elementSize > 0) {
1023  AHB_READ_BURST_START(startAddress + 8, (elementSize + 3) >> 2);
1024  i = 0; // Used to count the number of bytes we have read.
1025  while (i < elementSize) {
1026  if ((i % 4) == 0) {
1027  readData = AHB_READ_BURST_READ();
1028  }
1029 
1030  dataPayload[i] = (uint8_t)((readData >> ((i % 4) * 8)) & 0xFF);
1031  i++;
1032  if (i > elementSize)
1033  i = elementSize;
1034  }
1035  AHB_READ_BURST_END(); // Terminate the burst read
1036  }
1037  // Acknowledge the FIFO read
1038  if (getIndex < 32)
1039  {
1040  AHB_WRITE_32(REG_MCAN_NDAT1, 1 << getIndex);
1041  } else {
1042  AHB_WRITE_32(REG_MCAN_NDAT2, 1 << (getIndex-32));
1043  }
1044 
1045 
1046  return i; // Return the number of bytes retrieved
1047 }
1048 
1049 
1063 uint32_t
1064 TCAN4x5x_MCAN_WriteTXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_TX_Header *header, uint8_t dataPayload[])
1065 {
1066  // Step 1: Get the start address of the
1067  uint32_t SPIData;
1068  uint16_t startAddress;
1069  uint8_t i, elementSize, temp;
1070 
1071 
1072  // Get the TX Start location and size...
1073 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1075 #else
1076  SPIData = AHB_READ_32(REG_MCAN_TXBC);
1077 #endif
1078  startAddress = (uint16_t)(SPIData & 0x0000FFFF) + 0x8000;
1079  // Transmit FIFO and queue numbers
1080  temp = (uint8_t)((SPIData >> 24) & 0x3F);
1081  elementSize = temp > 32 ? 32 : temp;
1082  // Dedicated transmit buffers
1083  temp = (uint8_t)((SPIData >> 16) & 0x3F);
1084  elementSize += temp > 32 ? 32 : temp;
1085 
1086  if (bufIndex > (elementSize-1)) {
1087  return 0;
1088  }
1089 
1090  // Get the actual element size of each TX element
1091 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1093 #else
1094  SPIData = AHB_READ_32(REG_MCAN_TXESC);
1095 #endif
1096  elementSize = TCAN4x5x_MCAN_TXRXESC_DataByteValue(SPIData & 0x07) + 8;
1097 
1098  // Calculate the actual start address for the latest index
1099  startAddress += ((uint32_t)elementSize * bufIndex);
1100 
1101  // Now we need to actually check how much data we are writing (because we don't need to fill a 64-byte FIFO if we are sending an 8 byte can packet)
1102  elementSize = (TCAN4x5x_MCAN_DLCtoBytes(header->DLC & 0x0F) + 8) >> 2; // Convert it to words for easier reading by dividing by 4, and only look at data payload
1103  if (TCAN4x5x_MCAN_DLCtoBytes(header->DLC & 0x0F) % 4) { // If we don't have a whole word worth of data... We need to round up to the nearest word (by default it truncates). Can be done by simply adding another word.
1104  elementSize += 1;
1105  }
1106  // Read the data, start with a burst read
1107  AHB_WRITE_BURST_START(startAddress, elementSize);
1108  SPIData = 0;
1109 
1110  SPIData |= ((uint32_t)header->ESI & 0x01) << 31;
1111  SPIData |= ((uint32_t)header->XTD & 0x01) << 30;
1112  SPIData |= ((uint32_t)header->RTR & 0x01) << 29;
1113 
1114  if (header->XTD)
1115  SPIData |= ((uint32_t)header->ID & 0x1FFFFFFF);
1116  else
1117  SPIData |= ((uint32_t)header->ID & 0x07FF) << 18;
1118 
1119  AHB_WRITE_BURST_WRITE(SPIData);
1120 
1121  SPIData = 0;
1122  SPIData |= ((uint32_t)header->DLC & 0x0F) << 16;
1123  SPIData |= ((uint32_t)header->BRS & 0x01) << 20;
1124  SPIData |= ((uint32_t)header->FDF & 0x01) << 21;
1125  SPIData |= ((uint32_t)header->EFC & 0x01) << 23;
1126  SPIData |= ((uint32_t)header->MM & 0xFF) << 24;
1127  AHB_WRITE_BURST_WRITE(SPIData);
1128 
1129  // Get the actual data
1130  elementSize = TCAN4x5x_MCAN_DLCtoBytes(header->DLC & 0x0F); // Returns the number of data bytes
1131  i = 0; // Used to count the number of bytes we have read.
1132  while (i < elementSize) {
1133  SPIData = 0;
1134  // If elementSize - i < 4, then this means we are on our last word, with a word that is less than 4 bytes long
1135  if ((elementSize - i) < 4) {
1136  while (i < elementSize)
1137  {
1138  SPIData |= ((uint32_t)dataPayload[i] << ((i % 4) * 8));
1139  i++;
1140  }
1141 
1142  AHB_WRITE_BURST_WRITE(SPIData);
1143  } else {
1144  SPIData |= ((uint32_t)dataPayload[i++]);
1145  SPIData |= ((uint32_t)dataPayload[i++]) << 8;
1146  SPIData |= ((uint32_t)dataPayload[i++]) << 16;
1147  SPIData |= ((uint32_t)dataPayload[i++]) << 24;
1148 
1149  AHB_WRITE_BURST_WRITE(SPIData);
1150  }
1151 
1152  if (i > elementSize)
1153  i = elementSize;
1154  }
1155  AHB_WRITE_BURST_END(); // Terminate the burst read
1156 
1157  return (uint32_t)1 << bufIndex; // Return the number of bytes retrieved
1158 }
1159 
1160 
1172 bool
1174 {
1175  uint32_t writeValue;
1176  uint8_t requestedBuf = bufIndex;
1177 
1178  if (requestedBuf > 31)
1179  return false;
1180 
1181  writeValue = 1 << requestedBuf;
1182 
1183  AHB_WRITE_32(REG_MCAN_TXBAR, writeValue);
1184  return true;
1185 }
1186 
1187 
1198 bool
1200 {
1201  uint32_t readData;
1202  uint16_t startAddress;
1203  uint8_t getIndex;
1204 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1206 #else
1207  readData = AHB_READ_32(REG_MCAN_SIDFC);
1208 #endif
1209  getIndex = (readData & 0x00FF0000) >> 16;
1210  if (filterIndex > getIndex) // Check if the fifo number is valid and within range. If not, then fail
1211  return false;
1212  else
1213  getIndex = filterIndex;
1214 
1215  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
1216  // Calculate the actual start address for the latest index
1217  startAddress += (getIndex << 2); // Multiply by 4 and add to start address
1218 
1219  AHB_WRITE_32(startAddress, filter->word); // Write the value to the register
1220 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1221  // Verify that write was successful
1222  readData = AHB_READ_32(startAddress);
1223  if (readData != filter->word)
1224  return false;
1225 #endif
1226  return true;
1227 }
1228 
1229 
1240 bool
1242 {
1243  uint32_t readData;
1244  uint16_t startAddress;
1245  uint8_t getIndex;
1246 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1248 #else
1249  readData = AHB_READ_32(REG_MCAN_SIDFC);
1250 #endif
1251  getIndex = (readData & 0x00FF0000) >> 16;
1252  if (filterIndex > getIndex) // Check if the fifo number is valid and within range. If not, then fail
1253  return false;
1254  else
1255  getIndex = filterIndex;
1256 
1257  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
1258  // Calculate the actual start address for the latest index
1259  startAddress += (getIndex << 2); // Multiply by 4 and add to start address
1260 
1261  filter->word = AHB_READ_32(startAddress); // Read the value from the MRAM
1262  return true;
1263 }
1264 
1265 
1276 bool
1278 {
1279  uint32_t readData, writeData;
1280  uint16_t startAddress;
1281  uint8_t getIndex;
1282 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1284 #else
1285  readData = AHB_READ_32(REG_MCAN_XIDFC);
1286 #endif
1287  getIndex = (readData & 0x00FF0000) >> 16;
1288  if (filterIndex > getIndex) // Check if the fifo number is valid and within range. If not, then fail
1289  return false;
1290  else
1291  getIndex = filterIndex;
1292 
1293  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
1294  // Calculate the actual start address for the latest index
1295  startAddress += (getIndex << 3); // Multiply by 4 and add to start address
1296 
1297  // Write the 2 words to memory
1298  writeData = (uint32_t)(filter->EFEC) << 29;
1299  writeData |= (uint32_t)(filter->EFID1);
1300  AHB_WRITE_32(startAddress, writeData); // Write the value to the register
1301 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1302  readData = AHB_READ_32(startAddress);
1303  if (readData != writeData)
1304  return false;
1305 #endif
1306 
1307  startAddress += 4;
1308  writeData = (uint32_t)(filter->EFT) << 30;
1309  writeData |= (uint32_t)(filter->EFID2);
1310  AHB_WRITE_32(startAddress, writeData); // Write the value to the register
1311 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1312  readData = AHB_READ_32(startAddress);
1313  if (readData != writeData)
1314  return false;
1315 #endif
1316 
1317  return true;
1318 }
1319 
1320 
1331 bool
1333 {
1334  uint32_t readData;
1335  uint16_t startAddress;
1336  uint8_t getIndex;
1337 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION
1339 #else
1340  readData = AHB_READ_32(REG_MCAN_XIDFC);
1341 #endif
1342  getIndex = (readData & 0x00FF0000) >> 16;
1343  if (filterIndex > getIndex) // Check if the fifo number is valid and within range. If not, then fail
1344  return false;
1345  else
1346  getIndex = filterIndex;
1347 
1348  startAddress = (uint16_t)(readData & 0x0000FFFF) + REG_MRAM;
1349  // Calculate the actual start address for the latest index
1350  startAddress += (getIndex << 3); // Multiply by 4 and add to start address
1351 
1352  AHB_READ_BURST_START(startAddress, 2); // Send SPI header for a burst SPI read of 2 words
1353  readData = AHB_READ_BURST_READ(); // Read first word from MRAM
1354 
1355  filter->EFEC = (TCAN4x5x_XID_EFEC_Values)((readData >> 29) & 0x07);
1356  filter->EFID1 = readData & 0x1FFFFFFF;
1357 
1358  readData = AHB_READ_BURST_READ(); // Read second word from MRAM
1359  filter->EFT = (TCAN4x5x_XID_EFT_Values)((readData >> 30) & 0x03);
1360  filter->EFID2 = readData & 0x1FFFFFFF;
1361 
1362  return true;
1363 }
1364 
1365 
1373 void
1375 {
1376  ir->word = AHB_READ_32(REG_MCAN_IR);
1377 }
1378 
1379 
1387 void
1389 {
1391 }
1392 
1393 
1399 void
1401 {
1402  AHB_WRITE_32(REG_MCAN_IR, 0xFFFFFFFF);
1403 }
1404 
1405 
1413 void
1415 {
1416  ie->word = AHB_READ_32(REG_MCAN_IE);
1417 }
1418 
1419 
1428 void
1430 {
1432  AHB_WRITE_32(REG_MCAN_ILE, REG_BITS_MCAN_ILE_EINT0); // This is necessary to enable the MCAN Int mux to the output nINT pin
1433 }
1434 
1435 
1442 uint8_t
1443 TCAN4x5x_MCAN_DLCtoBytes(uint8_t inputDLC)
1444 {
1445  static const uint8_t lookup[7] = {12, 16, 20, 24, 32, 48, 64};
1446 
1447  if (inputDLC < 9)
1448  return inputDLC;
1449 
1450  if (inputDLC < 16)
1451  return lookup[(unsigned int)(inputDLC-9)];
1452 
1453  return 0;
1454 
1455 }
1456 
1457 
1464 uint8_t
1466 {
1467  static const uint8_t lookup[8] = {8, 12, 16, 20, 24, 32, 48, 64};
1468  return lookup[(unsigned int)(inputESCValue & 0x07)];
1469 }
1470 
1471 
1472 
1473 
1474 
1475 /* ************************************** *
1476  * Start of Device (Non-MCAN) Functions *
1477  * ************************************** */
1478 
1484 uint16_t
1486 {
1487  uint32_t readValue;
1488 
1489  readValue = AHB_READ_32(REG_SPI_REVISION);
1490 
1491  return (uint16_t)(readValue & 0xFFFF);
1492 }
1493 
1494 
1504 bool
1506 {
1507  // First we must read the register
1508  uint32_t readDevice = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1509 
1510  // Then mask the bits that will be set by the struct
1516 
1517  // Copy to a temporary location in memory, so we don't modify the incoming struct
1518  TCAN4x5x_DEV_CONFIG tempCfg;
1519  tempCfg.word = devCfg->word;
1520 
1521  // Clear the reserved flags.
1522  tempCfg.RESERVED0 = 0;
1523  tempCfg.RESERVED1 = 0;
1524  tempCfg.RESERVED2 = 0;
1525  tempCfg.RESERVED3 = 0;
1526  tempCfg.RESERVED4 = 0;
1527  tempCfg.RESERVED5 = 0;
1528 
1529 
1530  // Set the bits according to the incoming struct
1531  readDevice |= (REG_BITS_DEVICE_MODE_FORCED_SET_BITS | tempCfg.word);
1532 
1533  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, readDevice);
1534 
1535 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1536  // Check to see if the write was successful.
1537  uint32_t readValue = AHB_READ_32(REG_DEV_MODES_AND_PINS); // Read value
1538  if (readValue != readDevice)
1539  return false;
1540 #endif
1541  return true;
1542 }
1543 
1544 
1552 void
1554 {
1556 }
1557 
1558 
1566 void
1568 {
1569  ir->word = AHB_READ_32(REG_DEV_IR);
1570 }
1571 
1572 
1580 void
1582 {
1584 }
1585 
1586 
1592 void
1594 {
1595  AHB_WRITE_32(REG_DEV_IR, 0xFFFFFFFF);
1596 }
1597 
1598 
1602 void
1604 {
1605  AHB_WRITE_32(REG_SPI_STATUS, 0xFFFFFFFF); // Simply write all 1s to attempt to clear a SPIERR that was set
1606 }
1607 
1608 
1616 void
1618 {
1619  ie->word = AHB_READ_32(REG_DEV_IE);
1620 }
1621 
1622 
1632 bool
1634 {
1636 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1637  // Check to see if the write was successful.
1638  uint32_t readValue = AHB_READ_32(REG_DEV_IE); // Read value
1639  readValue &= REG_BITS_DEVICE_IE_MASK; // Apply mask to ignore reserved
1640  if (readValue != (ie->word & REG_BITS_DEVICE_IE_MASK))
1641  return false;
1642 #endif
1643  return true;
1644 }
1645 
1646 
1656 bool
1658 {
1660 
1661  switch (modeDefine) {
1664  break;
1665 
1668  break;
1669 
1672  break;
1673 
1674  default:
1675  return false;
1676  }
1677 
1678  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, writeValue);
1679 
1680 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1681  // Check to see if the write was successful.
1682  writeValue &= REG_BITS_DEVICE_MODE_DEVICEMODE_MASK; // Mask out the part we care about verifying
1684  return false;
1685 #endif
1686  return true;
1687 }
1688 
1689 
1699 {
1701 
1702  switch (readValue) {
1705 
1708 
1711 
1712  default:
1714  }
1715 }
1716 
1717 
1727 bool
1729 {
1730  uint32_t readWriteValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1731  readWriteValue &= ~REG_BITS_DEVICE_MODE_TESTMODE_MASK; // Clear the bits that we are setting
1732 
1733  // Set the appropriate bits depending on the passed in value
1734  switch (modeDefine)
1735  {
1738  break;
1739 
1742  break;
1743 
1746  break;
1747 
1748  default: return false; // If an invalid value was passed, then we will return fail
1749  }
1750  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, readWriteValue); // Write the updated values
1751 
1752 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1753  // Check to see if the write was successful.
1754  if (AHB_READ_32(REG_DEV_MODES_AND_PINS) != readWriteValue)
1755  return false;
1756 #endif
1757  return true;
1758 }
1759 
1760 
1766 bool
1768 {
1769  uint32_t readWriteValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1770  readWriteValue &= ~(REG_BITS_DEVICE_MODE_TESTMODE_MASK | REG_BITS_DEVICE_MODE_TESTMODE_ENMASK); // Clear the bits
1771  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, readWriteValue); // Write the updated values
1772 
1773 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1774  // Check to see if the write was successful.
1775  if (AHB_READ_32(REG_DEV_MODES_AND_PINS) != readWriteValue)
1776  return false;
1777 #endif
1778  return true;
1779 }
1780 
1781 
1789 {
1790  uint32_t readValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1791 
1792  // If Test mode is enabled...
1793  if (readValue & REG_BITS_DEVICE_MODE_TESTMODE_ENMASK)
1794  {
1796  {
1798  } else {
1800  }
1801  }
1803 }
1804 
1805 
1813 bool
1815 {
1816  uint32_t readWriteValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1817  readWriteValue &= ~REG_BITS_DEVICE_MODE_WD_TIMER_MASK; // Clear the bits that we are setting
1818 
1819  // Set the appropriate bits depending on the passed in value
1820  switch (WDTtimeout)
1821  {
1822  case TCAN4x5x_WDT_60MS:
1823  readWriteValue |= REG_BITS_DEVICE_MODE_WD_TIMER_60MS;
1824  break;
1825 
1826  case TCAN4x5x_WDT_600MS:
1827  readWriteValue |= REG_BITS_DEVICE_MODE_WD_TIMER_600MS;
1828  break;
1829 
1830  case TCAN4x5x_WDT_3S:
1831  readWriteValue |= REG_BITS_DEVICE_MODE_WD_TIMER_3S;
1832  break;
1833 
1834  case TCAN4x5x_WDT_6S:
1835  readWriteValue |= REG_BITS_DEVICE_MODE_WD_TIMER_6S;
1836  break;
1837 
1838  default: return false; // If an invalid value was passed, then we will return fail
1839  }
1840  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, readWriteValue); // Write the updated values
1841 
1842 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1843  // Check to see if the write was successful.
1844  if (AHB_READ_32(REG_DEV_MODES_AND_PINS) != readWriteValue)
1845  return false;
1846 #endif
1847  return true;
1848 }
1849 
1850 
1858 {
1859  uint32_t readValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1861 
1862  switch (readValue)
1863  {
1865  return TCAN4x5x_WDT_60MS;
1866 
1868  return TCAN4x5x_WDT_600MS;
1869 
1871  return TCAN4x5x_WDT_3S;
1872 
1874  return TCAN4x5x_WDT_6S;
1875 
1876  default: return TCAN4x5x_WDT_60MS; // If an invalid value was passed, then we will return the POR default
1877  }
1878 }
1879 
1880 
1886 bool
1888 {
1889  uint32_t readWriteValue = AHB_READ_32(REG_DEV_MODES_AND_PINS) | REG_BITS_DEVICE_MODE_WDT_EN;
1890  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, readWriteValue); // Enable the watch dog timer
1891 
1892 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1893  // Check to see if the write was successful.
1894  if (AHB_READ_32(REG_DEV_MODES_AND_PINS) != readWriteValue)
1895  return false;
1896 #endif
1897 
1898  return true;
1899 }
1900 
1901 
1907 bool
1909 {
1910  uint32_t writeValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1911  writeValue &= ~REG_BITS_DEVICE_MODE_WDT_EN; // Clear the EN bit
1912  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, writeValue); // Disable the watch dog timer
1913 
1914 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES
1915  // Check to see if the write was successful.
1916  if (AHB_READ_32(REG_DEV_MODES_AND_PINS) != writeValue)
1917  return false;
1918 #endif
1919  return true;
1920 }
1921 
1922 
1926 void
1928 {
1929  uint32_t writeValue = AHB_READ_32(REG_DEV_MODES_AND_PINS);
1930  writeValue |= REG_BITS_DEVICE_MODE_WDT_RESET_BIT;
1931  AHB_WRITE_32(REG_DEV_MODES_AND_PINS, writeValue); // Reset the watch dog timer
1932 }
bool TCAN4x5x_Device_EnableTestMode(TCAN4x5x_Device_Test_Mode_Enum modeDefine)
Sets the TCAN4x5x device test mode.
Definition: TCAN4550.c:1728
uint8_t EFC
Event FIFO Control flag, to store tx events or not.
bool TCAN4x5x_MCAN_DisableProtectedRegisters(void)
Disable Protected MCAN Registers.
Definition: TCAN4550.c:113
#define REG_BITS_DEVICE_MODE_WDT_EN
Definition: TCAN4x5x_Reg.h:587
uint8_t DataTimeSeg1andProp
DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1 ...
bool TCAN4x5x_MCAN_WriteSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Write MCAN Standard ID filter into MRAM.
Definition: TCAN4550.c:1199
uint8_t DataTqBeforeSamplePoint
DTQBSP: Number of time quanta before sample point Valid values are: 2 to 33.
uint8_t RESERVED1
Reserved.
TCAN4x5x_Device_Mode_Enum
Definition: TCAN4550.h:72
TCAN4x5x_MRAM_Element_Data_Size TxBufferElementSize
TX Buffers element size: The number of bytes for the TX Buffers (data payload)
#define REG_BITS_DEVICE_MODE_DEVICEMODE_STANDBY
Definition: TCAN4x5x_Reg.h:582
#define REG_BITS_DEVICE_MODE_TESTMODE_MASK
Definition: TCAN4x5x_Reg.h:599
uint8_t TCAN4x5x_MCAN_ReadRXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the specified RX buffer element.
Definition: TCAN4550.c:964
#define REG_MCAN_CCCR
Definition: TCAN4x5x_Reg.h:94
uint8_t SIDNumElements
Standard ID Number of Filter Elements: The number of 11-bit filters the user would like Valid range...
#define REG_BITS_DEVICE_MODE_WDT_ACTION_MASK
Definition: TCAN4x5x_Reg.h:542
#define REG_MCAN_RXF1C
Definition: TCAN4x5x_Reg.h:118
#define REG_BITS_DEVICE_MODE_NWKRQ_VOLT_MASK
Definition: TCAN4x5x_Reg.h:534
#define REG_BITS_MCAN_DBTP_TDC_EN
Definition: TCAN4x5x_Reg.h:167
#define REG_BITS_DEVICE_MODE_TESTMODE_PHY
Definition: TCAN4x5x_Reg.h:600
uint32_t AHB_READ_BURST_READ(void)
Definition: TCAN4x5x_SPI.c:183
void TCAN4x5x_Device_ClearInterruptsAll(void)
Clear all device interrupts.
Definition: TCAN4550.c:1593
bool TCAN4x5x_MCAN_WriteXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Write MCAN Extended ID filter into MRAM.
Definition: TCAN4550.c:1277
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x Valid range is: 1 to...
uint8_t NominalTimeSeg2
NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
#define REG_BITS_MCAN_TSCC_COUNTER_EXTERNAL
Definition: TCAN4x5x_Reg.h:354
uint8_t ESI
Error state indicator flag.
Used to setup the timing parameters of the MCAN module This is the raw MCAN form of the struct which ...
uint8_t FDF
CAN FD Format flag.
Struct containing the device interrupt enable bit field.
uint32_t word
Full register as single 32-bit word.
#define REG_BITS_DEVICE_MODE_FORCED_SET_BITS
Definition: TCAN4x5x_Reg.h:500
uint8_t DataTimeSeg2
DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
void TCAN4x5x_MCAN_ConfigureInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Configures the MCAN interrupt enable register.
Definition: TCAN4550.c:1429
CAN message header for transmitted messages.
uint32_t word
full register as single 32-bit word
TCAN4x5x_MCAN_FIFO_Enum
Definition: TCAN4550.h:69
void TCAN4x5x_MCAN_ReadDataTimingFD_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Reads the MCAN data time settings, using the simple struct.
Definition: TCAN4550.c:217
#define REG_MCAN_RXF0C
Definition: TCAN4x5x_Reg.h:114
#define REG_DEV_IE
Definition: TCAN4x5x_Reg.h:82
#define REG_MCAN_RXF0S
Definition: TCAN4x5x_Reg.h:115
#define REG_DEV_MODES_AND_PINS
Definition: TCAN4x5x_Reg.h:78
void AHB_READ_BURST_END(void)
Definition: TCAN4x5x_SPI.c:223
#define TCAN4x5x_MCAN_CACHE_RXF1C
Definition: TCAN4550.h:61
#define REG_DEV_IR
Definition: TCAN4x5x_Reg.h:81
#define REG_BITS_DEVICE_MODE_INH_MASK
Definition: TCAN4x5x_Reg.h:570
bool TCAN4x5x_MCAN_ConfigureGlobalFilter(TCAN4x5x_MCAN_Global_Filter_Configuration *gfc)
Configures the MCAN global filter configuration register, using the passed Global Filter Configuratio...
Definition: TCAN4550.c:547
uint8_t NominalTqAfterSamplePoint
NTQASP: The total number of time quanta after the sample point Valid values are: 2 to 128...
uint8_t RESERVED2
Reserved.
uint8_t TxBufferNumElements
TX Buffers number of elements: The number of elements for the TX Buffers Valid range is: 0 to 32...
uint16_t TCAN4x5x_Device_ReadDeviceVersion(void)
Read the TCAN4x5x device version register.
Definition: TCAN4550.c:1485
void AHB_READ_BURST_START(uint16_t address, uint8_t words)
Definition: TCAN4x5x_SPI.c:155
uint32_t TCAN4x5x_MCAN_CACHE[9]
Definition: TCAN4550.c:68
#define REG_BITS_DEVICE_MODE_WD_TIMER_60MS
Definition: TCAN4x5x_Reg.h:511
#define REG_BITS_DEVICE_MODE_GPO1_MODE_MASK
Definition: TCAN4x5x_Reg.h:548
TCAN4x5x_XID_EFT_Values EFT
EFT[1:0].
#define REG_MCAN_TSCC
Definition: TCAN4x5x_Reg.h:96
uint32_t ID
CAN ID received.
#define REG_BITS_DEVICE_MODE_WD_TIMER_6S
Definition: TCAN4x5x_Reg.h:514
#define REG_MCAN_XIDFC
Definition: TCAN4x5x_Reg.h:109
TCAN4x5x_XID_EFT_Values
uint8_t XTD
Extended Identifier flag.
uint8_t DLC
Data length code.
Struct containing the register values for the Global Filter Configuration Register.
#define TCAN4x5x_MCAN_CACHE_RXBC
Definition: TCAN4550.h:62
void TCAN4x5x_MCAN_ReadCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Read the MCAN CCCR configuration register.
Definition: TCAN4550.c:200
uint8_t TCAN4x5x_MCAN_DLCtoBytes(uint8_t inputDLC)
Converts the CAN message DLC hex value to the number of bytes it corresponds to.
Definition: TCAN4550.c:1443
uint8_t NominalSyncJumpWidth
NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 ...
Used to setup the nominal timing parameters of the MCAN module This is the raw MCAN form of the struc...
#define REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_MASK
Definition: TCAN4x5x_Reg.h:575
#define REG_MCAN_RXF0A
Definition: TCAN4x5x_Reg.h:116
uint8_t ESI
Error state indicator flag.
bool TCAN4x5x_MCAN_ConfigureDataTiming_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Writes the MCAN data time settings, using the simple data timing struct.
Definition: TCAN4550.c:277
#define REG_BITS_DEVICE_MODE_WDT_RESET_BIT
Definition: TCAN4x5x_Reg.h:539
uint8_t NominalTimeSeg1andProp
NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1 ...
uint32_t word
Full word for register.
uint8_t Rx1NumElements
RX FIFO 1 number of elements: The number of elements for the RX FIFO 1 Valid range is: 0 to 64...
#define REG_BITS_DEVICE_MODE_GPO1_FUNC_MASK
Definition: TCAN4x5x_Reg.h:564
#define REG_BITS_MCAN_CCCR_CSR
Definition: TCAN4x5x_Reg.h:189
void TCAN4x5x_MCAN_ReadInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Read the MCAN interrupts.
Definition: TCAN4550.c:1374
TCAN4x5x_WDT_Timer_Enum
Definition: TCAN4550.h:70
#define REG_BITS_MCAN_ILE_EINT0
Definition: TCAN4x5x_Reg.h:293
bool TCAN4x5x_MCAN_ReadSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Read a MCAN Standard ID filter from MRAM.
Definition: TCAN4550.c:1241
#define TCAN4x5x_MCAN_CACHE_TXEFC
Definition: TCAN4550.h:63
#define REG_BITS_DEVICE_MODE_TESTMODE_ENMASK
Definition: TCAN4x5x_Reg.h:529
uint8_t DataSyncJumpWidth
DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 Valid v...
uint16_t RXTS
Receive time stamp.
#define REG_MCAN_TXESC
Definition: TCAN4x5x_Reg.h:124
#define TCAN4x5x_MCAN_CACHE_SIDFC
Definition: TCAN4550.h:58
void TCAN4x5x_Device_ClearInterrupts(TCAN4x5x_Device_Interrupts *ir)
Clear the device interrupts.
Definition: TCAN4550.c:1581
#define REG_BITS_DEVICE_MODE_DEVICEMODE_SLEEP
Definition: TCAN4x5x_Reg.h:581
#define REG_MCAN_TDCR
Definition: TCAN4x5x_Reg.h:102
uint8_t RTR
Remote Transmission Request flag.
uint8_t RxBufNumElements
RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO) Valid range...
void TCAN4x5x_MCAN_ReadNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Reads the MCAN nominal/arbitration time settings, using the simple timing struct. ...
Definition: TCAN4550.c:410
uint32_t word
Full register as single 32-bit word.
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Raw(TCAN4x5x_MCAN_Nominal_Timing_Raw *nomTiming)
Writes the MCAN nominal timing settings, using the raw MCAN nominal timing struct.
Definition: TCAN4550.c:514
#define REG_MCAN_TXBAR
Definition: TCAN4x5x_Reg.h:126
#define TCAN4x5x_MCAN_CACHE_XIDFC
Definition: TCAN4550.h:59
#define REG_MCAN_RXF1S
Definition: TCAN4x5x_Reg.h:119
uint32_t EFID2
EFID2[28:0].
#define REG_BITS_DEVICE_MODE_GPO2_MASK
Definition: TCAN4x5x_Reg.h:522
#define REG_BITS_DEVICE_MODE_DEVICEMODE_NORMAL
Definition: TCAN4x5x_Reg.h:583
void TCAN4x5x_MCAN_ClearInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Clear the MCAN interrupts.
Definition: TCAN4550.c:1388
void TCAN4x5x_MCAN_ReadInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Read the MCAN interrupt enable register.
Definition: TCAN4550.c:1414
void TCAN4x5x_Device_ReadConfig(TCAN4x5x_DEV_CONFIG *devCfg)
Reads the device mode and pin register.
Definition: TCAN4550.c:1553
uint8_t XTD
Extended Identifier flag.
#define REG_BITS_MCAN_CCCR_CSA
Definition: TCAN4x5x_Reg.h:190
uint8_t BRS
Bit rate switch used flag.
Standard ID filter struct.
#define REG_BITS_DEVICE_IE_MASK
Definition: TCAN4x5x_Reg.h:654
#define REG_MCAN_NDAT2
Definition: TCAN4x5x_Reg.h:113
#define REG_BITS_DEVICE_MODE_WD_TIMER_MASK
Definition: TCAN4x5x_Reg.h:510
uint32_t EFID1
EFID1[28:0].
#define TCAN4x5x_MCAN_CACHE_RXESC
Definition: TCAN4550.h:65
uint32_t word
Full register as single 32-bit word.
bool TCAN4x5x_Device_ConfigureInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Configures the device interrupt enable register.
Definition: TCAN4550.c:1633
TCAN4x5x_XID_EFEC_Values EFEC
SFT Standard Filter Type.
uint8_t BRS
Bit rate switch used flag.
#define REG_BITS_MCAN_CCCR_INIT
Definition: TCAN4x5x_Reg.h:193
#define REG_MCAN_NBTP
Definition: TCAN4x5x_Reg.h:95
uint8_t RTR
Remote Transmission Request flag.
#define REG_MRAM
Definition: TCAN4x5x_Reg.h:62
#define REG_BITS_MCAN_RXF0C_F0OM_OVERWRITE
Definition: TCAN4x5x_Reg.h:309
uint8_t RESERVED3
DEV_MODE_PINS[21:20] : RESERVED. Use test mode functions to enable test modes.
#define REG_BITS_MCAN_GFC_MASK
Definition: TCAN4x5x_Reg.h:302
void TCAN4x5x_Device_ClearSPIERR(void)
Clears a SPIERR flag that may be set.
Definition: TCAN4550.c:1603
uint8_t MM
Message Marker, used if EFC is set to 1.
uint8_t TCAN4x5x_MCAN_ReadNextFIFO(TCAN4x5x_MCAN_FIFO_Enum FIFODefine, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the next MCAN FIFO element.
Definition: TCAN4550.c:828
#define REG_MCAN_SIDFC
Definition: TCAN4x5x_Reg.h:108
uint32_t TCAN4x5x_MCAN_WriteTXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_TX_Header *header, uint8_t dataPayload[])
Write CAN message to the specified TX buffer.
Definition: TCAN4550.c:1064
void TCAN4x5x_Device_ReadInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Read the device interrupt enable register.
Definition: TCAN4550.c:1617
uint8_t FDF
CAN FD Format flag.
#define REG_BITS_DEVICE_MODE_WAKE_PIN_MASK
Definition: TCAN4x5x_Reg.h:503
#define REG_BITS_DEVICE_MODE_SWE_MASK
Definition: TCAN4x5x_Reg.h:594
uint8_t FIDX
Filter index that this message matched.
Defines the number of MRAM elements and the size of the elements.
Struct containing the MCAN interrupt enable bit field.
uint8_t DataBitRatePrescaler
DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
#define REG_BITS_DEVICE_MODE_DEVICEMODE_MASK
Definition: TCAN4x5x_Reg.h:580
bool TCAN4x5x_Device_SetMode(TCAN4x5x_Device_Mode_Enum modeDefine)
Sets the TCAN4x5x device mode.
Definition: TCAN4550.c:1657
struct containing the bit fields of the MCAN CCCR register
#define REG_MCAN_IR
Definition: TCAN4x5x_Reg.h:103
bool TCAN4x5x_WDT_Disable(void)
Disable the watchdog timer.
Definition: TCAN4550.c:1908
uint8_t Rx0NumElements
RX FIFO 0 number of elements: The number of elements for the RX FIFO 0 Valid range is: 0 to 64...
#define REG_MCAN_ILE
Definition: TCAN4x5x_Reg.h:106
#define REG_BITS_MCAN_CCCR_RESERVED_MASK
Definition: TCAN4x5x_Reg.h:178
uint32_t word
Full register as single 32-bit word.
#define REG_MCAN_RXESC
Definition: TCAN4x5x_Reg.h:121
void AHB_WRITE_BURST_WRITE(uint32_t data)
Definition: TCAN4x5x_SPI.c:118
TCAN4x5x_Device_Test_Mode_Enum TCAN4x5x_Device_ReadTestMode(void)
Reads the TCAN4x5x device test mode.
Definition: TCAN4550.c:1788
Used to setup the data timing parameters of the MCAN module This is a simplified struct, requiring only the prescaler value (1:x), number of time quanta before and after the sample point.
uint8_t TxEventFIFONumElements
TX Event FIFO number of elements: The number of elements for the TX Event FIFO Valid range is: 0 to...
#define REG_BITS_DEVICE_MODE_TESTMODE_EN
Definition: TCAN4x5x_Reg.h:530
bool TCAN4x5x_MCAN_ReadXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Read MCAN Extended ID filter from MRAM.
Definition: TCAN4550.c:1332
TCAN4x5x_MRAM_Element_Data_Size RxBufElementSize
RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO...
void TCAN4x5x_MCAN_ReadNominalTiming_Raw(TCAN4x5x_MCAN_Nominal_Timing_Raw *nomTiming)
Reads the MCAN nominal/arbitration time settings, using the raw MCAN timing struct.
Definition: TCAN4550.c:431
uint8_t TDCFilter
TDCFilter: Transmitter delay compensation Filter Window Length Valid values are 0 to 127 mtq...
uint8_t TDCOffset
TDCO: Transmitter delay compensation offset Valid values are 0 to 127 mtq.
#define MRAM_SIZE
Definition: TCAN4x5x_Reg.h:54
#define REG_SPI_REVISION
Definition: TCAN4x5x_Reg.h:70
TCAN4x5x_XID_EFEC_Values
Struct containing the device interrupt bit field.
#define REG_MCAN_DBTP
Definition: TCAN4x5x_Reg.h:91
void AHB_WRITE_BURST_END(void)
Definition: TCAN4x5x_SPI.c:138
uint8_t CSR
CSR: Clock stop request.
void TCAN4x5x_MCAN_ClearInterruptsAll(void)
Clear all MCAN interrupts.
Definition: TCAN4550.c:1400
uint8_t DataTqAfterSamplePoint
DTQASP: Number of time quanta after sample point Valid values are: 1 to 16.
#define REG_MCAN_GFC
Definition: TCAN4x5x_Reg.h:107
TCAN4x5x_Device_Test_Mode_Enum
Definition: TCAN4550.h:71
uint8_t RESERVED5
DEV_MODE_PINS[29:28] : RESERVED. Use watchdog functions to set watchdog parameters.
uint8_t ANMF
Accepted non matching frame flag.
uint32_t word
Full register as single 32-bit word.
uint32_t AHB_READ_32(uint16_t address)
Definition: TCAN4x5x_SPI.c:66
#define REG_MCAN_IE
Definition: TCAN4x5x_Reg.h:104
#define REG_MCAN_RXF1A
Definition: TCAN4x5x_Reg.h:120
#define TCAN4x5x_MCAN_CACHE_TXBC
Definition: TCAN4550.h:64
uint8_t RESERVED4
DEV_MODE_PINS[26:24] : RESERVED.
void TCAN4x5x_MCAN_ReadDataTimingFD_Raw(TCAN4x5x_MCAN_Data_Timing_Raw *dataTiming)
Reads the MCAN data time settings, using the raw MCAN struct.
Definition: TCAN4550.c:239
#define REG_BITS_DEVICE_MODE_TESTMODE_CONTROLLER
Definition: TCAN4x5x_Reg.h:601
uint16_t NominalTqBeforeSamplePoint
NTQBSP: The total number of time quanta prior to sample point Valid values are: 2 to 257...
void TCAN4x5x_WDT_Reset(void)
Reset the watchdog timer.
Definition: TCAN4550.c:1927
bool TCAN4x5x_Device_DisableTestMode(void)
Disables the TCAN4x5x device test mode.
Definition: TCAN4550.c:1767
#define REG_SPI_STATUS
Definition: TCAN4x5x_Reg.h:71
Extended ID filter struct.
#define REG_BITS_DEVICE_MODE_FAIL_SAFE_MASK
Definition: TCAN4x5x_Reg.h:554
#define REG_MCAN_TXEFC
Definition: TCAN4x5x_Reg.h:132
uint8_t XIDNumElements
Extended ID Number of Filter Elements: The number of 29-bit filters the user would like Valid range...
#define TCAN4x5x_MCAN_CACHE_RXF0C
Definition: TCAN4550.h:60
bool TCAN4x5x_MRAM_Configure(TCAN4x5x_MRAM_Config *MRAMConfig)
Configures the MRAM registers.
Definition: TCAN4550.c:584
uint8_t DataBitRatePrescaler
Prescaler value, interpreted as 1:x Valid range is: 1 to 32.
bool TCAN4x5x_WDT_Configure(TCAN4x5x_WDT_Timer_Enum WDTtimeout)
Configure the watchdog.
Definition: TCAN4550.c:1814
bool TCAN4x5x_WDT_Enable(void)
Enable the watchdog timer.
Definition: TCAN4550.c:1887
TCAN4x5x_MRAM_Element_Data_Size Rx0ElementSize
RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
void AHB_WRITE_BURST_START(uint16_t address, uint8_t words)
Definition: TCAN4x5x_SPI.c:88
bool TCAN4x5x_MCAN_EnableProtectedRegisters(void)
Enable Protected MCAN Registers.
Definition: TCAN4550.c:79
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Writes the MCAN nominal timing settings, using the simple nominal timing struct.
Definition: TCAN4550.c:457
#define REG_BITS_DEVICE_MODE_WD_TIMER_3S
Definition: TCAN4x5x_Reg.h:513
#define REG_MCAN_RXBC
Definition: TCAN4x5x_Reg.h:117
Struct containing the MCAN interrupt bit field.
#define REG_BITS_DEVICE_MODE_WD_CLK_MASK
Definition: TCAN4x5x_Reg.h:517
uint8_t DLC
Data length code.
#define REG_BITS_DEVICE_MODE_DEVICE_RESET
Definition: TCAN4x5x_Reg.h:591
void TCAN4x5x_Device_ReadInterrupts(TCAN4x5x_Device_Interrupts *ir)
Read the device interrupts.
Definition: TCAN4550.c:1567
bool TCAN4x5x_MCAN_TransmitBufferContents(uint8_t bufIndex)
Transmit TX buffer contents of the specified tx buffer.
Definition: TCAN4550.c:1173
void TCAN4x5x_MRAM_Clear(void)
Clear (Zero-fill) the contents of MRAM.
Definition: TCAN4550.c:796
TCAN4x5x_MRAM_Element_Data_Size Rx1ElementSize
RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
TCAN4x5x_WDT_Timer_Enum TCAN4x5x_WDT_Read(void)
Read the watchdog configuration.
Definition: TCAN4550.c:1857
#define TCAN4x5x_MCAN_CACHE_TXESC
Definition: TCAN4550.h:66
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
#define REG_BITS_DEVICE_MODE_WDT_MASK
Definition: TCAN4x5x_Reg.h:586
#define REG_BITS_MCAN_TXBC_TFQM
Definition: TCAN4x5x_Reg.h:338
#define REG_BITS_DEVICE_MODE_WD_TIMER_600MS
Definition: TCAN4x5x_Reg.h:512
TCAN4x5x_Device_Mode_Enum TCAN4x5x_Device_ReadMode(void)
Reads the TCAN4x5x device mode.
Definition: TCAN4550.c:1698
#define REG_MCAN_NDAT1
Definition: TCAN4x5x_Reg.h:112
uint8_t RESERVED0
DEV_MODE_PINS[0] : Test mode configuration. Reserved in this struct It is recommended to use the test...
uint8_t TCAN4x5x_MCAN_TXRXESC_DataByteValue(uint8_t inputESCValue)
Converts the MCAN ESC (Element Size) value to number of bytes that it corresponds to...
Definition: TCAN4550.c:1465
#define REG_BITS_MCAN_CCCR_CCE
Definition: TCAN4x5x_Reg.h:192
Used to setup the nominal timing parameters of the MCAN module This is a simplified struct...
bool TCAN4x5x_Device_Configure(TCAN4x5x_DEV_CONFIG *devCfg)
Configures the device mode and pin register.
Definition: TCAN4550.c:1505
uint32_t ID
CAN ID to send.
#define REG_MCAN_TXBC
Definition: TCAN4x5x_Reg.h:122
bool TCAN4x5x_MCAN_ConfigureDataTiming_Raw(TCAN4x5x_MCAN_Data_Timing_Raw *dataTiming)
Writes the MCAN data time settings, using the raw MCAN data timing struct.
Definition: TCAN4550.c:352
bool TCAN4x5x_MCAN_ConfigureCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Configure the MCAN CCCR Register.
Definition: TCAN4550.c:150
void AHB_WRITE_32(uint16_t address, uint32_t data)
Definition: TCAN4x5x_SPI.c:50