TCAN4550  1p2
TCAN4x5x_Reg.h
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1 /*
2  * TCAN4x5x_Reg.h
3  * Description: This file contains the register definitions for the TCAN4x5x Family
4  *
5  * There are a few different define domains:
6  * - REG_MCAN_x: MCAN register address defines
7  * - MCAN_DLC_x: DLC values for the RX and TX FIFO element defines
8  * - REG_SPI_x : SPI Controller register address defines
9  * - REG_DEV_x : TCAN4x5x Device-specific register address defines
10  * - REG_BITS_x: Register bit defines in a similar manner as above.
11  * EX: REG_BITS_MCAN_CCCR_INIT is the hex value corresponding to the REG_MCAN_CCCR register's INIT bit
12  *
13  * Created on: Oct 1, 2017
14  * Author: Texas Instruments
15  *
16  * Updated 10/12/2018
17  * - 1.0.1: Added Device IE Mask define
18  *
19  * Copyright (c) 2017 Texas Instruments Incorporated. All rights reserved.
20  * Software License Agreement
21  *
22  * Redistribution and use in source and binary forms, with or without
23  * modification, are permitted provided that the following conditions
24  * are met:
25  *
26  * Redistributions of source code must retain the above copyright
27  * notice, this list of conditions and the following disclaimer.
28  *
29  * Redistributions in binary form must reproduce the above copyright
30  * notice, this list of conditions and the following disclaimer in the
31  * documentation and/or other materials provided with the
32  * distribution.
33  *
34  * Neither the name of Texas Instruments Incorporated nor the names of
35  * its contributors may be used to endorse or promote products derived
36  * from this software without specific prior written permission.
37  *
38  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
39  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
40  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
41  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
42  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
43  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
44  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
45  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
46  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
47  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
48  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
49  */
50 
51 #ifndef TCAN4X5X_REG_H_
52 #define TCAN4X5X_REG_H_
53 
54 #define MRAM_SIZE 2048
55 
56 //*****************************************************************************
57 // Register Address Sections
58 //*****************************************************************************
59 #define REG_SPI_CONFIG 0x0000
60 #define REG_DEV_CONFIG 0x0800
61 #define REG_MCAN 0x1000
62 #define REG_MRAM 0x8000
63 
64 
65 //*****************************************************************************
66 // SPI Registers and Device ID Register Addresses: 0x0000 Prefix
67 //*****************************************************************************
68 #define REG_SPI_DEVICE_ID0 0x0000
69 #define REG_SPI_DEVICE_ID1 0x0004
70 #define REG_SPI_REVISION 0x0008
71 #define REG_SPI_STATUS 0x000C
72 #define REG_SPI_ERROR_STATUS_MASK 0x0010
73 
74 
75 //*****************************************************************************
76 // Device Configuration Register Addresses: 0x0800 Prefix
77 //*****************************************************************************
78 #define REG_DEV_MODES_AND_PINS 0x0800
79 #define REG_DEV_TIMESTAMP_PRESCALER 0x0804
80 #define REG_DEV_TEST_REGISTERS 0x0808
81 #define REG_DEV_IR 0x0820
82 #define REG_DEV_IE 0x0830
83 
84 
85 //*****************************************************************************
86 // MCAN Register Addresses: 0x1000 Prefix
87 //*****************************************************************************
88 #define REG_MCAN_CREL 0x1000
89 #define REG_MCAN_ENDN 0x1004
90 #define REG_MCAN_CUST 0x1008
91 #define REG_MCAN_DBTP 0x100C
92 #define REG_MCAN_TEST 0x1010
93 #define REG_MCAN_RWD 0x1014
94 #define REG_MCAN_CCCR 0x1018
95 #define REG_MCAN_NBTP 0x101C
96 #define REG_MCAN_TSCC 0x1020
97 #define REG_MCAN_TSCV 0x1024
98 #define REG_MCAN_TOCC 0x1028
99 #define REG_MCAN_TOCV 0x102C
100 #define REG_MCAN_ECR 0x1040
101 #define REG_MCAN_PSR 0x1044
102 #define REG_MCAN_TDCR 0x1048
103 #define REG_MCAN_IR 0x1050
104 #define REG_MCAN_IE 0x1054
105 #define REG_MCAN_ILS 0x1058
106 #define REG_MCAN_ILE 0x105C
107 #define REG_MCAN_GFC 0x1080
108 #define REG_MCAN_SIDFC 0x1084
109 #define REG_MCAN_XIDFC 0x1088
110 #define REG_MCAN_XIDAM 0x1090
111 #define REG_MCAN_HPMS 0x1094
112 #define REG_MCAN_NDAT1 0x1098
113 #define REG_MCAN_NDAT2 0x109C
114 #define REG_MCAN_RXF0C 0x10A0
115 #define REG_MCAN_RXF0S 0x10A4
116 #define REG_MCAN_RXF0A 0x10A8
117 #define REG_MCAN_RXBC 0x10AC
118 #define REG_MCAN_RXF1C 0x10B0
119 #define REG_MCAN_RXF1S 0x10B4
120 #define REG_MCAN_RXF1A 0x10B8
121 #define REG_MCAN_RXESC 0x10BC
122 #define REG_MCAN_TXBC 0x10C0
123 #define REG_MCAN_TXFQS 0x10C4
124 #define REG_MCAN_TXESC 0x10C8
125 #define REG_MCAN_TXBRP 0x10CC
126 #define REG_MCAN_TXBAR 0x10D0
127 #define REG_MCAN_TXBCR 0x10D4
128 #define REG_MCAN_TXBTO 0x10D8
129 #define REG_MCAN_TXBCF 0x10DC
130 #define REG_MCAN_TXBTIE 0x10E0
131 #define REG_MCAN_TXBCIE 0x10E4
132 #define REG_MCAN_TXEFC 0x10F0
133 #define REG_MCAN_TXEFS 0x10F4
134 #define REG_MCAN_TXEFA 0x10F8
135 //*****************************************************************************
136 
137 
138 //*****************************************************************************
139 // DLC Value Defines: Used for RX and TX elements. The DLC[3:0] bit field
140 //*****************************************************************************
141 #define MCAN_DLC_0B 0x00000000
142 #define MCAN_DLC_1B 0x00000001
143 #define MCAN_DLC_2B 0x00000002
144 #define MCAN_DLC_3B 0x00000003
145 #define MCAN_DLC_4B 0x00000004
146 #define MCAN_DLC_5B 0x00000005
147 #define MCAN_DLC_6B 0x00000006
148 #define MCAN_DLC_7B 0x00000007
149 #define MCAN_DLC_8B 0x00000008
150 #define MCAN_DLC_12B 0x00000009
151 #define MCAN_DLC_16B 0x0000000A
152 #define MCAN_DLC_20B 0x0000000B
153 #define MCAN_DLC_24B 0x0000000C
154 #define MCAN_DLC_32B 0x0000000D
155 #define MCAN_DLC_48B 0x0000000E
156 #define MCAN_DLC_64B 0x0000000F
157 //*****************************************************************************
158 
159 
160 
161 
162 //*****************************************************************************
163 // MCAN Register Bit Field Defines
164 //*****************************************************************************
165 
166 // DBTP
167 #define REG_BITS_MCAN_DBTP_TDC_EN 0x00800000
168 
169 // TEST
170 #define REG_BITS_MCAN_TEST_RX_DOM 0x00000000
171 #define REG_BITS_MCAN_TEST_RX_REC 0x00000080
172 #define REG_BITS_MCAN_TEST_TX_SP 0x00000020
173 #define REG_BITS_MCAN_TEST_TX_DOM 0x00000040
174 #define REG_BITS_MCAN_TEST_TX_REC 0x00000060
175 #define REG_BITS_MCAN_TEST_LOOP_BACK 0x00000010
176 
177 // CCCR
178 #define REG_BITS_MCAN_CCCR_RESERVED_MASK 0xFFFF0C00
179 #define REG_BITS_MCAN_CCCR_NISO_ISO 0x00000000
180 #define REG_BITS_MCAN_CCCR_NISO_BOSCH 0x00008000
181 #define REG_BITS_MCAN_CCCR_TXP 0x00004000
182 #define REG_BITS_MCAN_CCCR_EFBI 0x00002000
183 #define REG_BITS_MCAN_CCCR_PXHD_DIS 0x00001000
184 #define REG_BITS_MCAN_CCCR_BRSE 0x00000200
185 #define REG_BITS_MCAN_CCCR_FDOE 0x00000100
186 #define REG_BITS_MCAN_CCCR_TEST 0x00000080
187 #define REG_BITS_MCAN_CCCR_DAR_DIS 0x00000040
188 #define REG_BITS_MCAN_CCCR_MON 0x00000020
189 #define REG_BITS_MCAN_CCCR_CSR 0x00000010
190 #define REG_BITS_MCAN_CCCR_CSA 0x00000008
191 #define REG_BITS_MCAN_CCCR_ASM 0x00000004
192 #define REG_BITS_MCAN_CCCR_CCE 0x00000002
193 #define REG_BITS_MCAN_CCCR_INIT 0x00000001
194 
195 // IE
196 #define REG_BITS_MCAN_IE_ARAE 0x20000000
197 #define REG_BITS_MCAN_IE_PEDE 0x10000000
198 #define REG_BITS_MCAN_IE_PEAE 0x08000000
199 #define REG_BITS_MCAN_IE_WDIE 0x04000000
200 #define REG_BITS_MCAN_IE_BOE 0x02000000
201 #define REG_BITS_MCAN_IE_EWE 0x01000000
202 #define REG_BITS_MCAN_IE_EPE 0x00800000
203 #define REG_BITS_MCAN_IE_ELOE 0x00400000
204 #define REG_BITS_MCAN_IE_BEUE 0x00200000
205 #define REG_BITS_MCAN_IE_BECE 0x00100000
206 #define REG_BITS_MCAN_IE_DRXE 0x00080000
207 #define REG_BITS_MCAN_IE_TOOE 0x00040000
208 #define REG_BITS_MCAN_IE_MRAFE 0x00020000
209 #define REG_BITS_MCAN_IE_TSWE 0x00010000
210 #define REG_BITS_MCAN_IE_TEFLE 0x00008000
211 #define REG_BITS_MCAN_IE_TEFFE 0x00004000
212 #define REG_BITS_MCAN_IE_TEFWE 0x00002000
213 #define REG_BITS_MCAN_IE_TEFNE 0x00001000
214 #define REG_BITS_MCAN_IE_TFEE 0x00000800
215 #define REG_BITS_MCAN_IE_TCFE 0x00000400
216 #define REG_BITS_MCAN_IE_TCE 0x00000200
217 #define REG_BITS_MCAN_IE_HPME 0x00000100
218 #define REG_BITS_MCAN_IE_RF1LE 0x00000080
219 #define REG_BITS_MCAN_IE_RF1FE 0x00000040
220 #define REG_BITS_MCAN_IE_RF1WE 0x00000020
221 #define REG_BITS_MCAN_IE_RF1NE 0x00000010
222 #define REG_BITS_MCAN_IE_RF0LE 0x00000008
223 #define REG_BITS_MCAN_IE_RF0FE 0x00000004
224 #define REG_BITS_MCAN_IE_RF0WE 0x00000002
225 #define REG_BITS_MCAN_IE_RF0NE 0x00000001
226 
227 // IR
228 #define REG_BITS_MCAN_IR_ARA 0x20000000
229 #define REG_BITS_MCAN_IR_PED 0x10000000
230 #define REG_BITS_MCAN_IR_PEA 0x08000000
231 #define REG_BITS_MCAN_IR_WDI 0x04000000
232 #define REG_BITS_MCAN_IR_BO 0x02000000
233 #define REG_BITS_MCAN_IR_EW 0x01000000
234 #define REG_BITS_MCAN_IR_EP 0x00800000
235 #define REG_BITS_MCAN_IR_ELO 0x00400000
236 #define REG_BITS_MCAN_IR_BEU 0x00200000
237 #define REG_BITS_MCAN_IR_BEC 0x00100000
238 #define REG_BITS_MCAN_IR_DRX 0x00080000
239 #define REG_BITS_MCAN_IR_TOO 0x00040000
240 #define REG_BITS_MCAN_IR_MRAF 0x00020000
241 #define REG_BITS_MCAN_IR_TSW 0x00010000
242 #define REG_BITS_MCAN_IR_TEFL 0x00008000
243 #define REG_BITS_MCAN_IR_TEFF 0x00004000
244 #define REG_BITS_MCAN_IR_TEFW 0x00002000
245 #define REG_BITS_MCAN_IR_TEFN 0x00001000
246 #define REG_BITS_MCAN_IR_TFE 0x00000800
247 #define REG_BITS_MCAN_IR_TCF 0x00000400
248 #define REG_BITS_MCAN_IR_TC 0x00000200
249 #define REG_BITS_MCAN_IR_HPM 0x00000100
250 #define REG_BITS_MCAN_IR_RF1L 0x00000080
251 #define REG_BITS_MCAN_IR_RF1F 0x00000040
252 #define REG_BITS_MCAN_IR_RF1W 0x00000020
253 #define REG_BITS_MCAN_IR_RF1N 0x00000010
254 #define REG_BITS_MCAN_IR_RF0L 0x00000008
255 #define REG_BITS_MCAN_IR_RF0F 0x00000004
256 #define REG_BITS_MCAN_IR_RF0W 0x00000002
257 #define REG_BITS_MCAN_IR_RF0N 0x00000001
258 
259 // ILS
260 #define REG_BITS_MCAN_IE_ARAL 0x20000000
261 #define REG_BITS_MCAN_IE_PEDL 0x10000000
262 #define REG_BITS_MCAN_IE_PEAL 0x08000000
263 #define REG_BITS_MCAN_IE_WDIL 0x04000000
264 #define REG_BITS_MCAN_IE_BOL 0x02000000
265 #define REG_BITS_MCAN_IE_EWL 0x01000000
266 #define REG_BITS_MCAN_IE_EPL 0x00800000
267 #define REG_BITS_MCAN_IE_ELOL 0x00400000
268 #define REG_BITS_MCAN_IE_BEUL 0x00200000
269 #define REG_BITS_MCAN_IE_BECL 0x00100000
270 #define REG_BITS_MCAN_IE_DRXL 0x00080000
271 #define REG_BITS_MCAN_IE_TOOL 0x00040000
272 #define REG_BITS_MCAN_IE_MRAFL 0x00020000
273 #define REG_BITS_MCAN_IE_TSWL 0x00010000
274 #define REG_BITS_MCAN_IE_TEFLL 0x00008000
275 #define REG_BITS_MCAN_IE_TEFFL 0x00004000
276 #define REG_BITS_MCAN_IE_TEFWL 0x00002000
277 #define REG_BITS_MCAN_IE_TEFNL 0x00001000
278 #define REG_BITS_MCAN_IE_TFEL 0x00000800
279 #define REG_BITS_MCAN_IE_TCFL 0x00000400
280 #define REG_BITS_MCAN_IE_TCL 0x00000200
281 #define REG_BITS_MCAN_IE_HPML 0x00000100
282 #define REG_BITS_MCAN_IE_RF1LL 0x00000080
283 #define REG_BITS_MCAN_IE_RF1FL 0x00000040
284 #define REG_BITS_MCAN_IE_RF1WL 0x00000020
285 #define REG_BITS_MCAN_IE_RF1NL 0x00000010
286 #define REG_BITS_MCAN_IE_RF0LL 0x00000008
287 #define REG_BITS_MCAN_IE_RF0FL 0x00000004
288 #define REG_BITS_MCAN_IE_RF0WL 0x00000002
289 #define REG_BITS_MCAN_IE_RF0NL 0x00000001
290 
291 // ILE
292 #define REG_BITS_MCAN_ILE_EINT1 0x00000002
293 #define REG_BITS_MCAN_ILE_EINT0 0x00000001
294 
295 // GFC
296 #define REG_BITS_MCAN_GFC_ANFS_FIFO0 0x00000000
297 #define REG_BITS_MCAN_GFC_ANFS_FIFO1 0x00000010
298 #define REG_BITS_MCAN_GFC_ANFE_FIFO0 0x00000000
299 #define REG_BITS_MCAN_GFC_ANFE_FIFO1 0x00000004
300 #define REG_BITS_MCAN_GFC_RRFS 0x00000002
301 #define REG_BITS_MCAN_GFC_RRFE 0x00000001
302 #define REG_BITS_MCAN_GFC_MASK 0x0000003F
303 
304 // NDAT1
305 
306 // NDAT2
307 
308 // RXF0C
309 #define REG_BITS_MCAN_RXF0C_F0OM_OVERWRITE 0x80000000
310 
311 // RXESC
312 #define REG_BITS_MCAN_RXESC_RBDS_8B 0x00000000
313 #define REG_BITS_MCAN_RXESC_RBDS_12B 0x00000100
314 #define REG_BITS_MCAN_RXESC_RBDS_16B 0x00000200
315 #define REG_BITS_MCAN_RXESC_RBDS_20B 0x00000300
316 #define REG_BITS_MCAN_RXESC_RBDS_24B 0x00000400
317 #define REG_BITS_MCAN_RXESC_RBDS_32B 0x00000500
318 #define REG_BITS_MCAN_RXESC_RBDS_48B 0x00000600
319 #define REG_BITS_MCAN_RXESC_RBDS_64B 0x00000700
320 #define REG_BITS_MCAN_RXESC_F1DS_8B 0x00000000
321 #define REG_BITS_MCAN_RXESC_F1DS_12B 0x00000010
322 #define REG_BITS_MCAN_RXESC_F1DS_16B 0x00000020
323 #define REG_BITS_MCAN_RXESC_F1DS_20B 0x00000030
324 #define REG_BITS_MCAN_RXESC_F1DS_24B 0x00000040
325 #define REG_BITS_MCAN_RXESC_F1DS_32B 0x00000050
326 #define REG_BITS_MCAN_RXESC_F1DS_48B 0x00000060
327 #define REG_BITS_MCAN_RXESC_F1DS_64B 0x00000070
328 #define REG_BITS_MCAN_RXESC_F0DS_8B 0x00000000
329 #define REG_BITS_MCAN_RXESC_F0DS_12B 0x00000001
330 #define REG_BITS_MCAN_RXESC_F0DS_16B 0x00000002
331 #define REG_BITS_MCAN_RXESC_F0DS_20B 0x00000003
332 #define REG_BITS_MCAN_RXESC_F0DS_24B 0x00000004
333 #define REG_BITS_MCAN_RXESC_F0DS_32B 0x00000005
334 #define REG_BITS_MCAN_RXESC_F0DS_48B 0x00000006
335 #define REG_BITS_MCAN_RXESC_F0DS_64B 0x00000007
336 
337 // TXBC
338 #define REG_BITS_MCAN_TXBC_TFQM 0x40000000
339 
340 // TXESC
341 #define REG_BITS_MCAN_TXESC_TBDS_8 0x00000000
342 #define REG_BITS_MCAN_TXESC_TBDS_12 0x00000001
343 #define REG_BITS_MCAN_TXESC_TBDS_16 0x00000002
344 #define REG_BITS_MCAN_TXESC_TBDS_20 0x00000003
345 #define REG_BITS_MCAN_TXESC_TBDS_24 0x00000004
346 #define REG_BITS_MCAN_TXESC_TBDS_32 0x00000005
347 #define REG_BITS_MCAN_TXESC_TBDS_48 0x00000006
348 #define REG_BITS_MCAN_TXESC_TBDS_64 0x00000007
349 
350 // TSCC
351 #define REG_BITS_MCAN_TSCC_PRESCALER_MASK 0x000F0000
352 #define REG_BITS_MCAN_TSCC_COUNTER_ALWAYS_0 0x00000000
353 #define REG_BITS_MCAN_TSCC_COUNTER_USE_TCP 0x00000001
354 #define REG_BITS_MCAN_TSCC_COUNTER_EXTERNAL 0x00000002
355 
356 // TXBAR
357 #define REG_BITS_MCAN_TXBAR_AR31 0x80000000
358 #define REG_BITS_MCAN_TXBAR_AR30 0x40000000
359 #define REG_BITS_MCAN_TXBAR_AR29 0x20000000
360 #define REG_BITS_MCAN_TXBAR_AR28 0x10000000
361 #define REG_BITS_MCAN_TXBAR_AR27 0x08000000
362 #define REG_BITS_MCAN_TXBAR_AR26 0x04000000
363 #define REG_BITS_MCAN_TXBAR_AR25 0x02000000
364 #define REG_BITS_MCAN_TXBAR_AR24 0x01000000
365 #define REG_BITS_MCAN_TXBAR_AR23 0x00800000
366 #define REG_BITS_MCAN_TXBAR_AR22 0x00400000
367 #define REG_BITS_MCAN_TXBAR_AR21 0x00200000
368 #define REG_BITS_MCAN_TXBAR_AR20 0x00100000
369 #define REG_BITS_MCAN_TXBAR_AR19 0x00080000
370 #define REG_BITS_MCAN_TXBAR_AR18 0x00040000
371 #define REG_BITS_MCAN_TXBAR_AR17 0x00020000
372 #define REG_BITS_MCAN_TXBAR_AR16 0x00010000
373 #define REG_BITS_MCAN_TXBAR_AR15 0x00008000
374 #define REG_BITS_MCAN_TXBAR_AR14 0x00004000
375 #define REG_BITS_MCAN_TXBAR_AR13 0x00002000
376 #define REG_BITS_MCAN_TXBAR_AR12 0x00001000
377 #define REG_BITS_MCAN_TXBAR_AR11 0x00000800
378 #define REG_BITS_MCAN_TXBAR_AR10 0x00000400
379 #define REG_BITS_MCAN_TXBAR_AR9 0x00000200
380 #define REG_BITS_MCAN_TXBAR_AR8 0x00000100
381 #define REG_BITS_MCAN_TXBAR_AR7 0x00000080
382 #define REG_BITS_MCAN_TXBAR_AR6 0x00000040
383 #define REG_BITS_MCAN_TXBAR_AR5 0x00000020
384 #define REG_BITS_MCAN_TXBAR_AR4 0x00000010
385 #define REG_BITS_MCAN_TXBAR_AR3 0x00000008
386 #define REG_BITS_MCAN_TXBAR_AR2 0x00000004
387 #define REG_BITS_MCAN_TXBAR_AR1 0x00000002
388 #define REG_BITS_MCAN_TXBAR_AR0 0x00000001
389 
390 // TXBCR
391 #define REG_BITS_MCAN_TXBCR_CR31 0x80000000
392 #define REG_BITS_MCAN_TXBCR_CR30 0x40000000
393 #define REG_BITS_MCAN_TXBCR_CR29 0x20000000
394 #define REG_BITS_MCAN_TXBCR_CR28 0x10000000
395 #define REG_BITS_MCAN_TXBCR_CR27 0x08000000
396 #define REG_BITS_MCAN_TXBCR_CR26 0x04000000
397 #define REG_BITS_MCAN_TXBCR_CR25 0x02000000
398 #define REG_BITS_MCAN_TXBCR_CR24 0x01000000
399 #define REG_BITS_MCAN_TXBCR_CR23 0x00800000
400 #define REG_BITS_MCAN_TXBCR_CR22 0x00400000
401 #define REG_BITS_MCAN_TXBCR_CR21 0x00200000
402 #define REG_BITS_MCAN_TXBCR_CR20 0x00100000
403 #define REG_BITS_MCAN_TXBCR_CR19 0x00080000
404 #define REG_BITS_MCAN_TXBCR_CR18 0x00040000
405 #define REG_BITS_MCAN_TXBCR_CR17 0x00020000
406 #define REG_BITS_MCAN_TXBCR_CR16 0x00010000
407 #define REG_BITS_MCAN_TXBCR_CR15 0x00008000
408 #define REG_BITS_MCAN_TXBCR_CR14 0x00004000
409 #define REG_BITS_MCAN_TXBCR_CR13 0x00002000
410 #define REG_BITS_MCAN_TXBCR_CR12 0x00001000
411 #define REG_BITS_MCAN_TXBCR_CR11 0x00000800
412 #define REG_BITS_MCAN_TXBCR_CR10 0x00000400
413 #define REG_BITS_MCAN_TXBCR_CR9 0x00000200
414 #define REG_BITS_MCAN_TXBCR_CR8 0x00000100
415 #define REG_BITS_MCAN_TXBCR_CR7 0x00000080
416 #define REG_BITS_MCAN_TXBCR_CR6 0x00000040
417 #define REG_BITS_MCAN_TXBCR_CR5 0x00000020
418 #define REG_BITS_MCAN_TXBCR_CR4 0x00000010
419 #define REG_BITS_MCAN_TXBCR_CR3 0x00000008
420 #define REG_BITS_MCAN_TXBCR_CR2 0x00000004
421 #define REG_BITS_MCAN_TXBCR_CR1 0x00000002
422 #define REG_BITS_MCAN_TXBCR_CR0 0x00000001
423 
424 // TXBTIE
425 #define REG_BITS_MCAN_TXBTIE_TIE31 0x80000000
426 #define REG_BITS_MCAN_TXBTIE_TIE30 0x40000000
427 #define REG_BITS_MCAN_TXBTIE_TIE29 0x20000000
428 #define REG_BITS_MCAN_TXBTIE_TIE28 0x10000000
429 #define REG_BITS_MCAN_TXBTIE_TIE27 0x08000000
430 #define REG_BITS_MCAN_TXBTIE_TIE26 0x04000000
431 #define REG_BITS_MCAN_TXBTIE_TIE25 0x02000000
432 #define REG_BITS_MCAN_TXBTIE_TIE24 0x01000000
433 #define REG_BITS_MCAN_TXBTIE_TIE23 0x00800000
434 #define REG_BITS_MCAN_TXBTIE_TIE22 0x00400000
435 #define REG_BITS_MCAN_TXBTIE_TIE21 0x00200000
436 #define REG_BITS_MCAN_TXBTIE_TIE20 0x00100000
437 #define REG_BITS_MCAN_TXBTIE_TIE19 0x00080000
438 #define REG_BITS_MCAN_TXBTIE_TIE18 0x00040000
439 #define REG_BITS_MCAN_TXBTIE_TIE17 0x00020000
440 #define REG_BITS_MCAN_TXBTIE_TIE16 0x00010000
441 #define REG_BITS_MCAN_TXBTIE_TIE15 0x00008000
442 #define REG_BITS_MCAN_TXBTIE_TIE14 0x00004000
443 #define REG_BITS_MCAN_TXBTIE_TIE13 0x00002000
444 #define REG_BITS_MCAN_TXBTIE_TIE12 0x00001000
445 #define REG_BITS_MCAN_TXBTIE_TIE11 0x00000800
446 #define REG_BITS_MCAN_TXBTIE_TIE10 0x00000400
447 #define REG_BITS_MCAN_TXBTIE_TIE9 0x00000200
448 #define REG_BITS_MCAN_TXBTIE_TIE8 0x00000100
449 #define REG_BITS_MCAN_TXBTIE_TIE7 0x00000080
450 #define REG_BITS_MCAN_TXBTIE_TIE6 0x00000040
451 #define REG_BITS_MCAN_TXBTIE_TIE5 0x00000020
452 #define REG_BITS_MCAN_TXBTIE_TIE4 0x00000010
453 #define REG_BITS_MCAN_TXBTIE_TIE3 0x00000008
454 #define REG_BITS_MCAN_TXBTIE_TIE2 0x00000004
455 #define REG_BITS_MCAN_TXBTIE_TIE1 0x00000002
456 #define REG_BITS_MCAN_TXBTIE_TIE0 0x00000001
457 
458 // TXBCIE
459 #define REG_BITS_MCAN_TXBCIE_CFIE31 0x80000000
460 #define REG_BITS_MCAN_TXBCIE_CFIE30 0x40000000
461 #define REG_BITS_MCAN_TXBCIE_CFIE29 0x20000000
462 #define REG_BITS_MCAN_TXBCIE_CFIE28 0x10000000
463 #define REG_BITS_MCAN_TXBCIE_CFIE27 0x08000000
464 #define REG_BITS_MCAN_TXBCIE_CFIE26 0x04000000
465 #define REG_BITS_MCAN_TXBCIE_CFIE25 0x02000000
466 #define REG_BITS_MCAN_TXBCIE_CFIE24 0x01000000
467 #define REG_BITS_MCAN_TXBCIE_CFIE23 0x00800000
468 #define REG_BITS_MCAN_TXBCIE_CFIE22 0x00400000
469 #define REG_BITS_MCAN_TXBCIE_CFIE21 0x00200000
470 #define REG_BITS_MCAN_TXBCIE_CFIE20 0x00100000
471 #define REG_BITS_MCAN_TXBCIE_CFIE19 0x00080000
472 #define REG_BITS_MCAN_TXBCIE_CFIE18 0x00040000
473 #define REG_BITS_MCAN_TXBCIE_CFIE17 0x00020000
474 #define REG_BITS_MCAN_TXBCIE_CFIE16 0x00010000
475 #define REG_BITS_MCAN_TXBCIE_CFIE15 0x00008000
476 #define REG_BITS_MCAN_TXBCIE_CFIE14 0x00004000
477 #define REG_BITS_MCAN_TXBCIE_CFIE13 0x00002000
478 #define REG_BITS_MCAN_TXBCIE_CFIE12 0x00001000
479 #define REG_BITS_MCAN_TXBCIE_CFIE11 0x00000800
480 #define REG_BITS_MCAN_TXBCIE_CFIE10 0x00000400
481 #define REG_BITS_MCAN_TXBCIE_CFIE9 0x00000200
482 #define REG_BITS_MCAN_TXBCIE_CFIE8 0x00000100
483 #define REG_BITS_MCAN_TXBCIE_CFIE7 0x00000080
484 #define REG_BITS_MCAN_TXBCIE_CFIE6 0x00000040
485 #define REG_BITS_MCAN_TXBCIE_CFIE5 0x00000020
486 #define REG_BITS_MCAN_TXBCIE_CFIE4 0x00000010
487 #define REG_BITS_MCAN_TXBCIE_CFIE3 0x00000008
488 #define REG_BITS_MCAN_TXBCIE_CFIE2 0x00000004
489 #define REG_BITS_MCAN_TXBCIE_CFIE1 0x00000002
490 #define REG_BITS_MCAN_TXBCIE_CFIE0 0x00000001
491 //*****************************************************************************
492 
493 
494 //*****************************************************************************
495 // Device Register Bit Field Defines
496 //*****************************************************************************
497 
498 // Modes of Operation and Pin Configuration Registers (0x0800)
499 // Generic masks
500 #define REG_BITS_DEVICE_MODE_FORCED_SET_BITS 0x00000020
501 
502 // Wake pin
503 #define REG_BITS_DEVICE_MODE_WAKE_PIN_MASK 0xC0000000
504 #define REG_BITS_DEVICE_MODE_WAKE_PIN_DIS 0x00000000
505 #define REG_BITS_DEVICE_MODE_WAKE_PIN_RISING 0x40000000
506 #define REG_BITS_DEVICE_MODE_WAKE_PIN_FALLING 0x80000000
507 #define REG_BITS_DEVICE_MODE_WAKE_PIN_BOTHEDGES 0xC0000000
508 
509 // WD_Timer (If applicable)
510 #define REG_BITS_DEVICE_MODE_WD_TIMER_MASK 0x30000000
511 #define REG_BITS_DEVICE_MODE_WD_TIMER_60MS 0x00000000
512 #define REG_BITS_DEVICE_MODE_WD_TIMER_600MS 0x10000000
513 #define REG_BITS_DEVICE_MODE_WD_TIMER_3S 0x20000000
514 #define REG_BITS_DEVICE_MODE_WD_TIMER_6S 0x30000000
515 
516 // WD_TIMER_CLK_REF
517 #define REG_BITS_DEVICE_MODE_WD_CLK_MASK 0x08000000
518 #define REG_BITS_DEVICE_MODE_WD_CLK_20MHZ 0x00000000
519 #define REG_BITS_DEVICE_MODE_WD_CLK_40MHZ 0x08000000
520 
521 // GPO2 Pin Configuration
522 #define REG_BITS_DEVICE_MODE_GPO2_MASK 0x00C00000
523 #define REG_BITS_DEVICE_MODE_GPO2_CAN_FAULT 0x00000000
524 #define REG_BITS_DEVICE_MODE_GPO2_MCAN_INT0 0x00400000
525 #define REG_BITS_DEVICE_MODE_GPO2_WDT 0x00800000
526 #define REG_BITS_DEVICE_MODE_GPO2_NINT 0x00C00000
527 
528 // Test Mode Enable Bit
529 #define REG_BITS_DEVICE_MODE_TESTMODE_ENMASK 0x00200000
530 #define REG_BITS_DEVICE_MODE_TESTMODE_EN 0x00200000
531 #define REG_BITS_DEVICE_MODE_TESTMODE_DIS 0x00000000
532 
533 // nWKRQ Pin GPO Voltage Rail COnfiguration
534 #define REG_BITS_DEVICE_MODE_NWKRQ_VOLT_MASK 0x00080000
535 #define REG_BITS_DEVICE_MODE_NWKRQ_VOLT_INTERNAL 0x00000000
536 #define REG_BITS_DEVICE_MODE_NWKRQ_VOLT_VIO 0x00080000
537 
538 // WD_BIT
539 #define REG_BITS_DEVICE_MODE_WDT_RESET_BIT 0x00040000
540 
541 // WD_ACTION
542 #define REG_BITS_DEVICE_MODE_WDT_ACTION_MASK 0x00020000
543 #define REG_BITS_DEVICE_MODE_WDT_ACTION_INT 0x00000000
544 #define REG_BITS_DEVICE_MODE_WDT_ACTION_INH_PULSE 0x00010000
545 #define REG_BITS_DEVICE_MODE_WDT_ACTION_WDT_PULSE 0x00020000
546 
547 // CLKOUT/GPO1 Pin Mode Select
548 #define REG_BITS_DEVICE_MODE_GPO1_MODE_MASK 0x0000C000
549 #define REG_BITS_DEVICE_MODE_GPO1_MODE_GPO 0x00000000
550 #define REG_BITS_DEVICE_MODE_GPO1_MODE_CLKOUT 0x00004000
551 #define REG_BITS_DEVICE_MODE_GPO1_MODE_GPI 0x00008000
552 
553 // Fail Safe Enable
554 #define REG_BITS_DEVICE_MODE_FAIL_SAFE_MASK 0x00002000
555 #define REG_BITS_DEVICE_MODE_FAIL_SAFE_EN 0x00002000
556 #define REG_BITS_DEVICE_MODE_FAIL_SAFE_DIS 0x00000000
557 
558 // CLKOUT Prescaler
559 #define REG_BITS_DEVICE_MODE_CLKOUT_MASK 0x00001000
560 #define REG_BITS_DEVICE_MODE_CLKOUT_DIV1 0x00000000
561 #define REG_BITS_DEVICE_MODE_CLKOUT_DIV2 0x00001000
562 
563 // GPO1 Function Select
564 #define REG_BITS_DEVICE_MODE_GPO1_FUNC_MASK 0x00000C00
565 #define REG_BITS_DEVICE_MODE_GPO1_FUNC_SPI_INT 0x00000000
566 #define REG_BITS_DEVICE_MODE_GPO1_FUNC_MCAN_INT1 0x00000400
567 #define REG_BITS_DEVICE_MODE_GPO1_FUNC_UVLO_THERM 0x00000800
568 
569 // INH Pin Disable
570 #define REG_BITS_DEVICE_MODE_INH_MASK 0x00000200
571 #define REG_BITS_DEVICE_MODE_INH_DIS 0x00000200
572 #define REG_BITS_DEVICE_MODE_INH_EN 0x00000000
573 
574 // nWKRQ Pin Configuration
575 #define REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_MASK 0x00000100
576 #define REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_INH 0x00000000
577 #define REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_WKRQ 0x00000100
578 
579 // Mode of Operation
580 #define REG_BITS_DEVICE_MODE_DEVICEMODE_MASK 0x000000C0
581 #define REG_BITS_DEVICE_MODE_DEVICEMODE_SLEEP 0x00000000
582 #define REG_BITS_DEVICE_MODE_DEVICEMODE_STANDBY 0x00000040
583 #define REG_BITS_DEVICE_MODE_DEVICEMODE_NORMAL 0x00000080
584 
585 // WDT_EN
586 #define REG_BITS_DEVICE_MODE_WDT_MASK 0x00000008
587 #define REG_BITS_DEVICE_MODE_WDT_EN 0x00000008
588 #define REG_BITS_DEVICE_MODE_WDT_DIS 0x00000000
589 
590 // Dev Reset
591 #define REG_BITS_DEVICE_MODE_DEVICE_RESET 0x00000004
592 
593 // SWE_DIS: Sleep Wake Error Disable
594 #define REG_BITS_DEVICE_MODE_SWE_MASK 0x00000002
595 #define REG_BITS_DEVICE_MODE_SWE_DIS 0x00000002
596 #define REG_BITS_DEVICE_MODE_SWE_EN 0x00000000
597 
598 // Test Mode Configuration
599 #define REG_BITS_DEVICE_MODE_TESTMODE_MASK 0x00000001
600 #define REG_BITS_DEVICE_MODE_TESTMODE_PHY 0x00000000
601 #define REG_BITS_DEVICE_MODE_TESTMODE_CONTROLLER 0x00000001
602 
603 
604 // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
605 // Device Interrupt Register values (0x0820)
606 #define REG_BITS_DEVICE_IR_CANLGND 0x08000000
607 #define REG_BITS_DEVICE_IR_CANBUSOPEN 0x04000000
608 #define REG_BITS_DEVICE_IR_CANBUSGND 0x02000000
609 #define REG_BITS_DEVICE_IR_CANBUSBAT 0x01000000
610 //Reserved 0x00800000
611 #define REG_BITS_DEVICE_IR_UVSUP 0x00400000
612 #define REG_BITS_DEVICE_IR_UVIO 0x00200000
613 #define REG_BITS_DEVICE_IR_PWRON 0x00100000
614 #define REG_BITS_DEVICE_IR_TSD 0x00080000
615 #define REG_BITS_DEVICE_IR_WDTO 0x00040000
616 //Reserved 0x00020000
617 #define REG_BITS_DEVICE_IR_ECCERR 0x00010000
618 #define REG_BITS_DEVICE_IR_CANINT 0x00008000
619 #define REG_BITS_DEVICE_IR_LWU 0x00004000
620 #define REG_BITS_DEVICE_IR_WKERR 0x00002000
621 #define REG_BITS_DEVICE_IR_FRAME_OVF 0x00001000
622 //Reserved 0x00000800
623 #define REG_BITS_DEVICE_IR_CANSLNT 0x00000400
624 //Reserved 0x00000200
625 #define REG_BITS_DEVICE_IR_CANDOM 0x00000100
626 #define REG_BITS_DEVICE_IR_GLOBALERR 0x00000080
627 #define REG_BITS_DEVICE_IR_nWKRQ 0x00000040
628 #define REG_BITS_DEVICE_IR_CANERR 0x00000020
629 #define REG_BITS_DEVICE_IR_CANBUSFAULT 0x00000010
630 #define REG_BITS_DEVICE_IR_SPIERR 0x00000008
631 #define REG_BITS_DEVICE_IR_SWERR 0x00000004
632 #define REG_BITS_DEVICE_IR_M_CAN_INT 0x00000002
633 #define REG_BITS_DEVICE_IR_VTWD 0x00000001
634 
635 // ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
636 // Device Interrupt Enable Values (0x0830)
637 #define REG_BITS_DEVICE_IE_UVCCOUT 0x00800000
638 #define REG_BITS_DEVICE_IE_UVSUP 0x00400000
639 #define REG_BITS_DEVICE_IE_UVIO 0x00200000
640 #define REG_BITS_DEVICE_IE_PWRON 0x00100000
641 #define REG_BITS_DEVICE_IE_TSD 0x00080000
642 #define REG_BITS_DEVICE_IE_WDTO 0x00040000
643 // Reserved
644 #define REG_BITS_DEVICE_IE_ECCERR 0x00010000
645 #define REG_BITS_DEVICE_IE_CANINT 0x00008000
646 #define REG_BITS_DEVICE_IE_LWU 0x00004000
647 #define REG_BITS_DEVICE_IE_WKERR 0x00002000
648 #define REG_BITS_DEVICE_IE_FRAME_OVF 0x00001000
649 //Reserved 0x00000800
650 #define REG_BITS_DEVICE_IE_CANSLNT 0x00000400
651 //Reserved 0x00000200
652 #define REG_BITS_DEVICE_IE_CANDOM 0x00000100
653 // Reserved 0x80-00
654 #define REG_BITS_DEVICE_IE_MASK 0xFF69D700
655 
656 #endif /* TCAN4X5X_REG_H_ */