52 #include <driverlib.h> 71 WDT_A_hold(__MSP430_BASEADDRESS_WDT_A__);
75 GPIO_clearInterrupt(GPIO_PORT_P1, GPIO_PIN5);
87 uint8_t data[4] = {0x55, 0x66, 0x77, 0x88};
135 uint8_t numBytes = 0;
136 uint8_t dataPayload[64] = {0};
144 if (MsgHeader.
ID == 0x0AA)
231 SID_ID.
SFID1 = 0x055;
232 SID_ID.
SFID2 = 0x7FF;
240 XID_ID.
EFID1 = 0x12345678;
241 XID_ID.
EFID2 = 0x1FFFFFFF;
257 GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
258 GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
259 GPIO_setOutputLowOnPin(GPIO_PORT_P3, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
260 GPIO_setOutputLowOnPin(GPIO_PORT_P4, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
261 GPIO_setOutputLowOnPin(GPIO_PORT_P5, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
262 GPIO_setOutputLowOnPin(GPIO_PORT_P6, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
263 GPIO_setOutputLowOnPin(GPIO_PORT_P7, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
264 GPIO_setOutputLowOnPin(GPIO_PORT_P8, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
265 GPIO_setOutputLowOnPin(GPIO_PORT_P9, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
267 GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
268 GPIO_setAsOutputPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
269 GPIO_setAsOutputPin(GPIO_PORT_P3, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
270 GPIO_setAsOutputPin(GPIO_PORT_P4, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
271 GPIO_setAsOutputPin(GPIO_PORT_P5, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
272 GPIO_setAsOutputPin(GPIO_PORT_P6, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
273 GPIO_setAsOutputPin(GPIO_PORT_P7, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
274 GPIO_setAsOutputPin(GPIO_PORT_P8, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
275 GPIO_setAsOutputPin(GPIO_PORT_P9, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
277 GPIO_setAsInputPin(GPIO_PORT_P1, GPIO_PIN5);
280 GPIO_selectInterruptEdge(GPIO_PORT_P1, GPIO_PIN5, GPIO_HIGH_TO_LOW_TRANSITION);
281 GPIO_setAsInputPinWithPullUpResistor(GPIO_PORT_P1, GPIO_PIN5);
282 GPIO_clearInterrupt(GPIO_PORT_P1, GPIO_PIN5);
283 GPIO_enableInterrupt(GPIO_PORT_P1, GPIO_PIN5);
286 GPIO_setAsPeripheralModuleFunctionInputPin(
288 GPIO_PIN4 + GPIO_PIN5,
289 GPIO_PRIMARY_MODULE_FUNCTION
296 GPIO_setAsPeripheralModuleFunctionOutputPin(
299 GPIO_PRIMARY_MODULE_FUNCTION
303 GPIO_setAsPeripheralModuleFunctionOutputPin(
306 GPIO_PRIMARY_MODULE_FUNCTION
310 GPIO_setAsPeripheralModuleFunctionInputPin(
313 GPIO_PRIMARY_MODULE_FUNCTION
317 GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_PIN5);
318 GPIO_setOutputHighOnPin(GPIO_PORT_P2, GPIO_PIN5);
331 CS_setDCOFreq(CS_DCORSEL_0, CS_DCOFSEL_6);
334 CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
335 CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
338 CS_turnOnLFXT(CS_LFXT_DRIVE_3);
347 struct EUSCI_B_SPI_initMasterParam SPIParam = {0};
349 SPIParam.selectClockSource=EUSCI_B_SPI_CLOCKSOURCE_SMCLK;
350 SPIParam.clockSourceFrequency=8000000;
351 SPIParam.desiredSpiClock=2000000;
352 SPIParam.msbFirst=EUSCI_B_SPI_MSB_FIRST;
353 SPIParam.clockPhase=EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT;
354 SPIParam.clockPolarity=EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW;
355 SPIParam.spiMode=EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH;
358 EUSCI_B_SPI_initMaster(EUSCI_B0_BASE, &SPIParam);
359 EUSCI_B_SPI_select4PinFunctionality(EUSCI_B0_BASE,0x00);
361 EUSCI_B_SPI_enable(EUSCI_B0_BASE);
369 #pragma vector = PORT1_VECTOR 372 switch(__even_in_range(P1IV, P1IV_P1IFG7))
374 case P1IV_NONE :
break;
375 case P1IV_P1IFG0 :
break;
376 case P1IV_P1IFG1 :
break;
377 case P1IV_P1IFG2 :
break;
378 case P1IV_P1IFG3 :
break;
379 case P1IV_P1IFG4 :
break;
381 case P1IV_P1IFG6 :
break;
382 case P1IV_P1IFG7 :
break;
bool TCAN4x5x_MCAN_DisableProtectedRegisters(void)
Disable Protected MCAN Registers.
uint32_t ID
CAN ID to send.
uint8_t DataTqBeforeSamplePoint
DTQBSP: Number of time quanta before sample point Valid values are: 2 to 33.
uint8_t FDF
CAN FD Format flag.
TCAN4x5x_MRAM_Element_Data_Size TxBufferElementSize
TX Buffers element size: The number of bytes for the TX Buffers (data payload)
TCAN4x5x_SID_SFT_Values SFT
SFT Standard Filter Type.
uint8_t ESI
Error state indicator flag.
uint8_t SIDNumElements
Standard ID Number of Filter Elements: The number of 11-bit filters the user would like Valid range...
__interrupt void PORT1_ISR(void)
CAN message header for transmitted messages.
uint8_t FDOE
FDOE: Can FD mode enabled, master enable for CAN FD support.
uint32_t EFID1
EFID1[28:0].
Extended ID filter struct.
Classic Filter, EFID1 is the ID/filter, and EFID2 is the mask.
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x Valid range is: 1 to...
Struct containing the device interrupt enable bit field.
void TCAN4x5x_MCAN_ConfigureInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Configures the MCAN interrupt enable register.
volatile uint8_t TCAN_Int_Cnt
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
uint32_t TCAN4x5x_MCAN_WriteTXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_TX_Header *header, uint8_t dataPayload[])
Write CAN message to the specified TX buffer.
uint8_t PWRON
DEV_IR[20] : PWRON, Power On Interrupt.
uint8_t NominalTqAfterSamplePoint
NTQASP: The total number of time quanta after the sample point Valid values are: 2 to 128...
uint8_t TxBufferNumElements
TX Buffers number of elements: The number of elements for the TX Buffers Valid range is: 0 to 32...
uint8_t RF0NE
IE[0] RF0NE: Rx FIFO 0 new message.
bool TCAN4x5x_MCAN_ConfigureDataTiming_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Writes the MCAN data time settings, using the simple data timing struct.
uint32_t EFID2
EFID2[28:0].
uint8_t EFC
Event FIFO Control flag, to store tx events or not.
uint8_t Rx1NumElements
RX FIFO 1 number of elements: The number of elements for the RX FIFO 1 Valid range is: 0 to 64...
void TCAN4x5x_MCAN_ReadInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Read the MCAN interrupts.
void TCAN4x5x_Device_ClearInterrupts(TCAN4x5x_Device_Interrupts *ir)
Clear the device interrupts.
uint8_t RxBufNumElements
RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO) Valid range...
void TCAN4x5x_MCAN_ClearInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Clear the MCAN interrupts.
Standard ID filter struct.
bool TCAN4x5x_Device_ConfigureInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Configures the device interrupt enable register.
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
Classic filter with SFID1 as the ID to match, and SFID2 as the bit mask that applies to SFID1...
uint32_t ID
CAN ID received.
bool TCAN4x5x_MCAN_WriteXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Write MCAN Extended ID filter into MRAM.
uint8_t XTD
Extended Identifier flag.
Defines the number of MRAM elements and the size of the elements.
Struct containing the MCAN interrupt enable bit field.
bool TCAN4x5x_Device_SetMode(TCAN4x5x_Device_Mode_Enum modeDefine)
Sets the TCAN4x5x device mode.
bool TCAN4x5x_MCAN_WriteSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Write MCAN Standard ID filter into MRAM.
struct containing the bit fields of the MCAN CCCR register
uint8_t Rx0NumElements
RX FIFO 0 number of elements: The number of elements for the RX FIFO 0 Valid range is: 0 to 64...
uint16_t SFID1
SFID1[10:0].
uint8_t RTR
Remote Transmission Request flag.
TCAN4x5x_SID_SFEC_Values SFEC
SFEC[2:0] Standard filter element configuration.
Used to setup the data timing parameters of the MCAN module This is a simplified struct, requiring only the prescaler value (1:x), number of time quanta before and after the sample point.
uint8_t TxEventFIFONumElements
TX Event FIFO number of elements: The number of elements for the TX Event FIFO Valid range is: 0 to...
TCAN4x5x_MRAM_Element_Data_Size RxBufElementSize
RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO...
Struct containing the device interrupt bit field.
uint8_t TCAN4x5x_MCAN_ReadNextFIFO(TCAN4x5x_MCAN_FIFO_Enum FIFODefine, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the next MCAN FIFO element.
uint16_t SFID2
SFID2[10:0].
void TCAN4x5x_MCAN_ClearInterruptsAll(void)
Clear all MCAN interrupts.
uint8_t DataTqAfterSamplePoint
DTQASP: Number of time quanta after sample point Valid values are: 1 to 16.
uint16_t NominalTqBeforeSamplePoint
NTQBSP: The total number of time quanta prior to sample point Valid values are: 2 to 257...
uint8_t XIDNumElements
Extended ID Number of Filter Elements: The number of 29-bit filters the user would like Valid range...
uint8_t RF0N
IR[0] RF0N: Rx FIFO 0 new message.
bool TCAN4x5x_MRAM_Configure(TCAN4x5x_MRAM_Config *MRAMConfig)
Configures the MRAM registers.
uint8_t DataBitRatePrescaler
Prescaler value, interpreted as 1:x Valid range is: 1 to 32.
TCAN4x5x_MRAM_Element_Data_Size Rx0ElementSize
RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
bool TCAN4x5x_MCAN_EnableProtectedRegisters(void)
Enable Protected MCAN Registers.
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Writes the MCAN nominal timing settings, using the simple nominal timing struct.
Struct containing the MCAN interrupt bit field.
void TCAN4x5x_Device_ReadInterrupts(TCAN4x5x_Device_Interrupts *ir)
Read the device interrupts.
uint8_t BRSE
BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support.
bool TCAN4x5x_MCAN_TransmitBufferContents(uint8_t bufIndex)
Transmit TX buffer contents of the specified tx buffer.
void TCAN4x5x_MRAM_Clear(void)
Clear (Zero-fill) the contents of MRAM.
TCAN4x5x_MRAM_Element_Data_Size Rx1ElementSize
RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
TCAN4x5x_XID_EFT_Values EFT
EFT[1:0].
uint8_t DLC
Data length code.
uint8_t BRS
Bit rate switch used flag.
uint8_t MM
Message Marker, used if EFC is set to 1.
TCAN4x5x_XID_EFEC_Values EFEC
SFT Standard Filter Type.
uint8_t DAR
DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration...
Used to setup the nominal timing parameters of the MCAN module This is a simplified struct...
bool TCAN4x5x_MCAN_ConfigureCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Configure the MCAN CCCR Register.