TCAN4550  1p2
TCAN4x5x_SPI.c
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1 /*
2  * TCAN4x5x_SPI.c
3  * Description: This file is responsible for abstracting the lower-level microcontroller SPI read and write functions
4  *
5  * Created on: October 1, 2017
6  * Author: Texas Instruments
7  *
8  *
9  * Copyright (c) 2017 Texas Instruments Incorporated. All rights reserved.
10  * Software License Agreement
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  *
16  * Redistributions of source code must retain the above copyright
17  * notice, this list of conditions and the following disclaimer.
18  *
19  * Redistributions in binary form must reproduce the above copyright
20  * notice, this list of conditions and the following disclaimer in the
21  * documentation and/or other materials provided with the
22  * distribution.
23  *
24  * Neither the name of Texas Instruments Incorporated nor the names of
25  * its contributors may be used to endorse or promote products derived
26  * from this software without specific prior written permission.
27  *
28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  */
40 
41 #include "TCAN4x5x_SPI.h"
42 
43 /*
44  * @brief Single word write
45  *
46  * @param address A 16-bit address of the destination register
47  * @param data A 32-bit word of data to write to the destination register
48  */
49 void
50 AHB_WRITE_32(uint16_t address, uint32_t data)
51 {
52  AHB_WRITE_BURST_START(address, 1);
55 }
56 
57 
58 /*
59  * @brief Single word read
60  *
61  * @param address A 16-bit address of the source register
62  *
63  * @return Returns 32-bit word of data from source register
64  */
65 uint32_t
66 AHB_READ_32(uint16_t address)
67 {
68  uint32_t returnData;
69 
70  AHB_READ_BURST_START(address, 1);
71  returnData = AHB_READ_BURST_READ();
73 
74  return returnData;
75 }
76 
77 
78 /*
79  * @brief Burst write start
80  *
81  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
82  * This function is the start, where the register address and number of words are transmitted
83  *
84  * @param address A 16-bit address of the destination register
85  * @param words The number of 4-byte words that will be transferred. 0 = 256 words
86  */
87 void
88 AHB_WRITE_BURST_START(uint16_t address, uint8_t words)
89 {
90  //set the CS low to start the transaction
91  GPIO_setOutputLowOnPin(SPI_CS_GPIO_PORT, SPI_CS_GPIO_PIN);
92 
93  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, AHB_WRITE_OPCODE);
94 
95  // Send the 16-bit address
97  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&address + 1));
99  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&address));
100 
101 
103  // Send the number of words to read
104  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, words);
105 
106 }
107 
108 
109 /*
110  * @brief Burst write
111  *
112  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
113  * This function writes a single word at a time
114  *
115  * @param data A 32-bit word of data to write to the destination register
116  */
117 void
118 AHB_WRITE_BURST_WRITE(uint32_t data)
119 {
121  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&data + 3));
123  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&data + 2));
125  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&data + 1));
127  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&data));
128 }
129 
130 
131 /*
132  * @brief Burst write end
133  *
134  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
135  * This function ends the burst transaction by pulling nCS high
136  */
137 void
139 {
141  GPIO_setOutputHighOnPin(SPI_CS_GPIO_PORT, SPI_CS_GPIO_PIN);
142 }
143 
144 
145 /*
146  * @brief Burst read start
147  *
148  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
149  * This function is the start, where the register address and number of words are transmitted
150  *
151  * @param address A 16-bit start address to begin the burst read
152  * @param words The number of 4-byte words that will be transferred. 0 = 256 words
153  */
154 void
155 AHB_READ_BURST_START(uint16_t address, uint8_t words)
156 {
157  // Set the CS low to start the transaction
158  GPIO_setOutputLowOnPin(SPI_CS_GPIO_PORT, SPI_CS_GPIO_PIN);
159  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, AHB_READ_OPCODE);
160 
161  // Send the 16-bit address
163  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&address + 1));
165  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, HWREG8(&address));
166 
167  // Send the number of words to read
169  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, words);
170 
171 }
172 
173 
174 /*
175  * @brief Burst read start
176  *
177  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
178  * This function where each word of data is read from the TCAN4x5x
179  *
180  * @return A 32-bit single data word that is read at a time
181  */
182 uint32_t
184 {
185  uint8_t readData;
186  uint8_t readData1;
187  uint8_t readData2;
188  uint8_t readData3;
189  uint32_t returnData;
190 
192  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, 0x00); // pause after this
194 
195  readData = HWREG8(SPI_HW_ADDR + OFS_UCBxRXBUF);
196  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, 0x00);
197 
198 
200  readData1 = HWREG8(SPI_HW_ADDR + OFS_UCBxRXBUF);
201  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, 0x00);
202 
204  readData2 = HWREG8(SPI_HW_ADDR + OFS_UCBxRXBUF);
205  EUSCI_B_SPI_transmitData(SPI_HW_ADDR, 0x00);
206 
208  readData3 = HWREG8(SPI_HW_ADDR + OFS_UCBxRXBUF);
209 
210 
211  returnData = (((uint32_t)readData) << 24) | (((uint32_t)readData1 << 16)) | (((uint32_t)readData2) << 8) | readData3;
212  return returnData;
213 }
214 
215 
216 /*
217  * @brief Burst write end
218  *
219  * The SPI transaction contains 3 parts: the header (start), the payload, and the end of data (end)
220  * This function ends the burst transaction by pulling nCS high
221  */
222 void
224 {
226  GPIO_setOutputHighOnPin(SPI_CS_GPIO_PORT, SPI_CS_GPIO_PIN);
227 }
uint32_t AHB_READ_BURST_READ(void)
Definition: TCAN4x5x_SPI.c:183
#define SPI_HW_ADDR
Definition: TCAN4x5x_SPI.h:52
void AHB_READ_BURST_END(void)
Definition: TCAN4x5x_SPI.c:223
#define WAIT_FOR_TRANSMIT
Definition: TCAN4x5x_SPI.h:54
void AHB_READ_BURST_START(uint16_t address, uint8_t words)
Definition: TCAN4x5x_SPI.c:155
#define AHB_WRITE_OPCODE
Definition: TCAN4x5x_SPI.h:61
#define AHB_READ_OPCODE
Definition: TCAN4x5x_SPI.h:62
void AHB_WRITE_BURST_WRITE(uint32_t data)
Definition: TCAN4x5x_SPI.c:118
#define SPI_CS_GPIO_PORT
Definition: TCAN4x5x_SPI.h:50
void AHB_WRITE_BURST_END(void)
Definition: TCAN4x5x_SPI.c:138
uint32_t AHB_READ_32(uint16_t address)
Definition: TCAN4x5x_SPI.c:66
#define SPI_CS_GPIO_PIN
Definition: TCAN4x5x_SPI.h:51
void AHB_WRITE_BURST_START(uint16_t address, uint8_t words)
Definition: TCAN4x5x_SPI.c:88
#define WAIT_FOR_IDLE
Definition: TCAN4x5x_SPI.h:55
void AHB_WRITE_32(uint16_t address, uint32_t data)
Definition: TCAN4x5x_SPI.c:50