TCAN4550  1p1
main.c
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1 /*
2  * main.c
3  * Author: Texas Instruments
4  * Date: 5/18/2018
5  *
6  * Description: A stripped down version of the code to simply set up and receive a packet
7  * - It assumes TCAN4550 Oscillator of 40 MHz
8  * - Sets CAN arbitration rate at 500 kBaud
9  * - Sets CAN FD data phase for 2 MBaud
10  *
11  *
12  * Pinout
13  * - P1.4 SPI Clock
14  * - P1.6 MOSI
15  * - P1.7 MISO
16  * - P4.7 SPI Chip Select
17  *
18  * - P1.5 MCAN Interrupt 1
19  *
20  *
21  * Copyright (c) 2017 Texas Instruments Incorporated. All rights reserved.
22  * Software License Agreement
23  *
24  * Redistribution and use in source and binary forms, with or without
25  * modification, are permitted provided that the following conditions
26  * are met:
27  *
28  * Redistributions of source code must retain the above copyright
29  * notice, this list of conditions and the following disclaimer.
30  *
31  * Redistributions in binary form must reproduce the above copyright
32  * notice, this list of conditions and the following disclaimer in the
33  * documentation and/or other materials provided with the
34  * distribution.
35  *
36  * Neither the name of Texas Instruments Incorporated nor the names of
37  * its contributors may be used to endorse or promote products derived
38  * from this software without specific prior written permission.
39  *
40  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
41  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
42  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
43  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
44  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
45  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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49  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51  */
52 #include <driverlib.h>
53 #include <msp430.h>
54 
55 #include <TCAN4550.h>
56 
57 
58 void Init_GPIO(void);
59 void Init_Clock(void);
60 void Init_SPI(void);
61 void Init_CAN(void);
62 
63 volatile uint8_t TCAN_Int_Cnt = 0; // A variable used to keep track of interrupts on P1.3 (MCAN Interrupt pin)
64 
65 
66 int main(void)
67 {
68  /***********************************
69  * MSP430 Specific Initializations *
70  ***********************************/
71  WDT_A_hold(__MSP430_BASEADDRESS_WDT_A__);
72  Init_GPIO(); // Set up GPIOs for SPI and TCAN4550 connections
73  Init_Clock(); // Set up the system clocks for 16 MHz (on the MSP430)
74  Init_SPI(); // Initialize the SPI hardware module for 2 MHz SPI
75  GPIO_clearInterrupt(GPIO_PORT_P1, GPIO_PIN5); // Clear any interrupts on pin 1.5 before we enable global interrupts
76  __enable_interrupt();
77 
78 
79  /*********************************************
80  * Everything at this point is for TCAN4550 *
81  *********************************************/
82  Init_CAN(); // Run the main MCAN configuration sequence. The bulk of the configuration is in this!
83 
84 
85  TCAN4x5x_MCAN_TX_Header header = {0}; // Remember to initialize to 0, or you'll get random garbage!
86 
87  uint8_t data[4] = {0x55, 0x66, 0x77, 0x88}; // Define the data payload
88  header.DLC = MCAN_DLC_4B; // Set the DLC to be equal to or less than the data payload (it is ok to pass a 64 byte data array into the WriteTXFIFO function if your DLC is 8 bytes, only the first 8 bytes will be read)
89  header.ID = 0x144; // Set the ID
90  header.FDF = 1; // CAN FD frame enabled
91  header.BRS = 1; // Bit rate switch enabled
92  header.EFC = 0;
93  header.MM = 0;
94  header.RTR = 0;
95  header.XTD = 0; // We are not using an extended ID in this example
96  header.ESI = 0; // Error state indicator
97 
98 
99  TCAN4x5x_MCAN_WriteTXBuffer(0, &header, data); // This function actually writes the header and data payload to the specified TX Fifo number. It returns the bit necessary to write to TXBAR,
100  // but does not necessarily require you to use it. In this example, we won't, so that we can send the data queued up at a later point.
101 
102  // Let's make another packet
103  data[0] = 0x11;
104  data[1] = 0x22;
105  data[2] = 0x33;
106  data[3] = 0x44; // Define the data payload
107 
108  header.DLC = MCAN_DLC_4B; // Set the DLC to be equal to or less than the data payload (it is ok to pass a 64 byte data array into the WriteTXFIFO function if your DLC is 8 bytes, only the first 8 bytes will be read)
109  header.ID = 0x123; // Set the ID
110  header.FDF = 1; // CAN FD frame enabled
111  header.BRS = 1; // Bit rate switch enabled
112  header.EFC = 0;
113  header.MM = 0;
114  header.RTR = 0;
115  header.XTD = 0; // We are not using an extended ID in this example
116  header.ESI = 0; // Error state indicator
117 
118  TCAN4x5x_MCAN_WriteTXBuffer(1, &header, data); // This line writes the data and header to TX FIFO 1
119  TCAN4x5x_MCAN_TransmitBufferContents(1); // Request that TX Buffer 1 be transmitted
120 
121 
122  TCAN4x5x_MCAN_TransmitBufferContents(0); // Now we can send the TX FIFO element 0 data that we had queued up earlier but didn't send.
123 
124  while (1)
125  {
126  if (TCAN_Int_Cnt > 0 )
127  {
128  TCAN_Int_Cnt--;
129  TCAN4x5x_MCAN_Interrupts mcan_ir = {0}; // Setup a new MCAN IR object for easy interrupt checking
130  TCAN4x5x_MCAN_ReadInterrupts(&mcan_ir); // Read the interrupt register
131 
132  if (mcan_ir.RF0N) // If a new message in RX FIFO 0
133  {
134  TCAN4x5x_MCAN_RX_Header MsgHeader = {0}; // Initialize to 0 or you'll get garbage
135  uint8_t numBytes = 0;
136  uint8_t dataPayload[64] = {0};
137 
138  TCAN4x5x_MCAN_ClearInterrupts(&mcan_ir); // Clear any of the interrupt bits that are set.
139 
140  numBytes = TCAN4x5x_MCAN_ReadNextFIFO( RXFIFO0, &MsgHeader, dataPayload); // This will read the next element in the RX FIFO 0
141 
142  // numBytes will have the number of bytes it transfered in it. Or you can decode the DLC value in MsgHeader.DLC
143  // The data is now in dataPayload[], and message specific information is in the MsgHeader struct.
144  if (MsgHeader.ID == 0x0AA) // Example of how you can do an action based off a received address
145  {
146  // Do something
147  }
148  }
149  }
150  }
151 }
152 
153 /*
154  * Configure the TCAN4550
155  */
156 void Init_CAN(void)
157 {
158  // Step one attempt to clear all interrupts
159  TCAN4x5x_Device_Interrupt_Enable dev_ie = {0}; // Initialize to 0 to all bits are set to 0.
160  TCAN4x5x_Device_ConfigureInterruptEnable(&dev_ie); // Disable all non-MCAN related interrupts for simplicity
161 
162  TCAN4x5x_Device_Interrupts dev_ir = {0}; // Setup a new MCAN IR object for easy interrupt checking
163  TCAN4x5x_Device_ReadInterrupts(&dev_ir); // Request that the struct be updated with current DEVICE (not MCAN) interrupt values
164 
165  if (dev_ir.PWRON)
167 
168  // Configure the CAN bus speeds
169  TCAN4x5x_MCAN_Nominal_Timing_Simple TCANNomTiming = {0}; // 500k arbitration with a 40 MHz crystal ((40E6 / 2) / (32 + 8) = 500E3)
170  TCANNomTiming.NominalBitRatePrescaler = 2;
171  TCANNomTiming.NominalTqBeforeSamplePoint = 32;
172  TCANNomTiming.NominalTqAfterSamplePoint = 8;
173 
174  TCAN4x5x_MCAN_Data_Timing_Simple TCANDataTiming = {0}; // 2 Mbps CAN FD with a 40 MHz crystal (40E6 / (15 + 5) = 2E6)
175  TCANDataTiming.DataBitRatePrescaler = 1;
176  TCANDataTiming.DataTqBeforeSamplePoint = 15;
177  TCANDataTiming.DataTqAfterSamplePoint = 5;
178 
179  // Configure the MCAN core settings
180  TCAN4x5x_MCAN_CCCR_Config cccrConfig = {0}; // Remember to initialize to 0, or you'll get random garbage!
181  cccrConfig.FDOE = 1; // CAN FD mode enable
182  cccrConfig.BRSE = 1; // CAN FD Bit rate switch enable
183  cccrConfig.DAR = 1; // Disable automatic transmission
184 
185 
186  /* ************************************************************************
187  * In the next configuration block, we will set the MCAN core up to have:
188  * - 1 SID filter element
189  * - 1 XID Filter element
190  * - 5 RX FIFO 0 elements
191  * - RX FIFO 0 supports data payloads up to 64 bytes
192  * - RX FIFO 1 and RX Buffer will not have any elements, but we still set their data payload sizes, even though it's not required
193  * - No TX Event FIFOs
194  * - 2 Transmit buffers supporting up to 64 bytes of data payload
195  */
196  TCAN4x5x_MRAM_Config MRAMConfiguration = {0};
197  MRAMConfiguration.SIDNumElements = 1; // Standard ID number of elements
198  MRAMConfiguration.XIDNumElements = 1; // Extended ID number of elements
199  MRAMConfiguration.Rx0NumElements = 5; // RX0 Number of elements
200  MRAMConfiguration.Rx0ElementSize = MRAM_64_Byte_Data; // RX0 data payload size
201  MRAMConfiguration.Rx1NumElements = 0; // RX1 number of elements
202  MRAMConfiguration.Rx1ElementSize = MRAM_64_Byte_Data; // RX1 data payload size
203  MRAMConfiguration.RxBufNumElements = 0; // RX buffer number of elements
204  MRAMConfiguration.RxBufElementSize = MRAM_64_Byte_Data; // RX buffer data payload size
205  MRAMConfiguration.TxEventFIFONumElements = 0; // TX Event FIFO number of elements
206  MRAMConfiguration.TxBufferNumElements = 2; // TX buffer number of elements
207  MRAMConfiguration.TxBufferElementSize = MRAM_64_Byte_Data; // TX buffer data payload size
208 
209 
210  // Configure the MCAN core with the settings above, these changes in this block all are protected write registers, so we just knock them out at once
211  TCAN4x5x_MCAN_EnableProtectedRegisters(); // Start by making protected registers accessible
212  TCAN4x5x_MCAN_ConfigureCCCRRegister(&cccrConfig); // Enable FD mode and Bit rate switching
213  TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(&TCANNomTiming);// Setup nominal/arbitration bit timing
214  TCAN4x5x_MCAN_ConfigureDataTiming_Simple(&TCANDataTiming); // Setup CAN FD timing
215  TCAN4x5x_MRAM_Clear(); // Clear all of MRAM (Writes 0's to all of it)
216  TCAN4x5x_MRAM_Configure(&MRAMConfiguration); // Set up the applicable registers related to MRAM configuration
217  TCAN4x5x_MCAN_DisableProtectedRegisters(); // Disable protected write and take device out of INIT mode
218 
219 
220  // Set the interrupts we want to enable for MCAN
221  TCAN4x5x_MCAN_Interrupt_Enable mcan_ie = {0}; // Remember to initialize to 0, or you'll get random garbage!
222  mcan_ie.RF0NE = 1; // RX FIFO 0 new message enable
223 
224  TCAN4x5x_MCAN_ConfigureInterruptEnable(&mcan_ie); // Enable the appropriate registers
225 
226 
227  // Setup filters, this filter will mark any message with ID 0x055 as a priority message
228  TCAN4x5x_MCAN_SID_Filter SID_ID = {0};
229  SID_ID.SFT = TCAN4x5x_SID_SFT_CLASSIC; // SFT: Standard filter type. Configured as a classic filter
230  SID_ID.SFEC = TCAN4x5x_SID_SFEC_PRIORITYSTORERX0; // Standard filter element configuration, store it in RX fifo 0 as a priority message
231  SID_ID.SFID1 = 0x055; // SFID1 (Classic mode Filter)
232  SID_ID.SFID2 = 0x7FF; // SFID2 (Classic mode Mask)
233  TCAN4x5x_MCAN_WriteSIDFilter(0, &SID_ID); // Write to the MRAM
234 
235 
236  // Store ID 0x12345678 as a priority message
237  TCAN4x5x_MCAN_XID_Filter XID_ID = {0};
238  XID_ID.EFT = TCAN4x5x_XID_EFT_CLASSIC; // EFT
239  XID_ID.EFEC = TCAN4x5x_XID_EFEC_PRIORITYSTORERX0; // EFEC
240  XID_ID.EFID1 = 0x12345678; // EFID1 (Classic mode filter)
241  XID_ID.EFID2 = 0x1FFFFFFF; // EFID2 (Classic mode mask)
242  TCAN4x5x_MCAN_WriteXIDFilter(0, &XID_ID); // Write to the MRAM
243 
244 
245  TCAN4x5x_Device_SetMode(TCAN4x5x_DEVICE_MODE_NORMAL); // Set to normal mode, since configuration is done. This line turns on the transceiver
246 
247  TCAN4x5x_MCAN_ClearInterruptsAll(); // Resets all MCAN interrupts
248 }
249 
250 
251 /*
252  * GPIO Initialization
253  */
254 void Init_GPIO()
255 {
256  // Set all GPIO pins to output low to prevent floating input and reduce power consumption
257  GPIO_setOutputLowOnPin(GPIO_PORT_P1, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
258  GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
259  GPIO_setOutputLowOnPin(GPIO_PORT_P3, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
260  GPIO_setOutputLowOnPin(GPIO_PORT_P4, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
261  GPIO_setOutputLowOnPin(GPIO_PORT_P5, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
262  GPIO_setOutputLowOnPin(GPIO_PORT_P6, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
263  GPIO_setOutputLowOnPin(GPIO_PORT_P7, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
264  GPIO_setOutputLowOnPin(GPIO_PORT_P8, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
265  GPIO_setOutputLowOnPin(GPIO_PORT_P9, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
266 
267  GPIO_setAsOutputPin(GPIO_PORT_P1, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
268  GPIO_setAsOutputPin(GPIO_PORT_P2, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
269  GPIO_setAsOutputPin(GPIO_PORT_P3, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
270  GPIO_setAsOutputPin(GPIO_PORT_P4, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
271  GPIO_setAsOutputPin(GPIO_PORT_P5, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
272  GPIO_setAsOutputPin(GPIO_PORT_P6, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
273  GPIO_setAsOutputPin(GPIO_PORT_P7, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
274  GPIO_setAsOutputPin(GPIO_PORT_P8, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
275  GPIO_setAsOutputPin(GPIO_PORT_P9, GPIO_PIN0|GPIO_PIN1|GPIO_PIN2|GPIO_PIN3|GPIO_PIN4|GPIO_PIN5|GPIO_PIN6|GPIO_PIN7);
276 
277  GPIO_setAsInputPin(GPIO_PORT_P1, GPIO_PIN5);
278 
279  // Configure P1.3 interrupt for MCAN Interrupt 1
280  GPIO_selectInterruptEdge(GPIO_PORT_P1, GPIO_PIN5, GPIO_HIGH_TO_LOW_TRANSITION);
281  GPIO_setAsInputPinWithPullUpResistor(GPIO_PORT_P1, GPIO_PIN5);
282  GPIO_clearInterrupt(GPIO_PORT_P1, GPIO_PIN5);
283  GPIO_enableInterrupt(GPIO_PORT_P1, GPIO_PIN5);
284 
285  // Set P4.1 and P4.2 as Secondary Module Function Input, LFXT.
286  GPIO_setAsPeripheralModuleFunctionInputPin(
287  GPIO_PORT_PJ,
288  GPIO_PIN4 + GPIO_PIN5,
289  GPIO_PRIMARY_MODULE_FUNCTION
290  );
291 
292  /*********************************************************
293  * SPI Interface Pins
294  *********************************************************/
295  //P1.4(SPI CLK on UCB0CLK)
296  GPIO_setAsPeripheralModuleFunctionOutputPin(
297  GPIO_PORT_P1,
298  GPIO_PIN4,
299  GPIO_PRIMARY_MODULE_FUNCTION
300  );
301 
302  //P1.6(MOSI on UCB0SIMO)
303  GPIO_setAsPeripheralModuleFunctionOutputPin(
304  GPIO_PORT_P1,
305  GPIO_PIN6,
306  GPIO_PRIMARY_MODULE_FUNCTION
307  );
308 
309  //P1.7(MISO on UCB0SOMI)
310  GPIO_setAsPeripheralModuleFunctionInputPin(
311  GPIO_PORT_P1,
312  GPIO_PIN7,
313  GPIO_PRIMARY_MODULE_FUNCTION
314  );
315 
316  //set P4.7 as SPI CS, already set to output above
317  GPIO_setOutputLowOnPin(GPIO_PORT_P2, GPIO_PIN5);
318  GPIO_setOutputHighOnPin(GPIO_PORT_P2, GPIO_PIN5);
319 
320  // Disable the GPIO power-on default high-impedance mode
321  // to activate previously configured port settings
322  PMM_unlockLPM5();
323 }
324 
325 /*
326  * Clock System Initialization
327  */
329 {
330  // Set DCO frequency to default 8MHz
331  CS_setDCOFreq(CS_DCORSEL_0, CS_DCOFSEL_6);
332 
333  // Configure MCLK and SMCLK to 8MHz
334  CS_initClockSignal(CS_MCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
335  CS_initClockSignal(CS_SMCLK, CS_DCOCLK_SELECT, CS_CLOCK_DIVIDER_1);
336 
337  // Initializes the XT1 crystal oscillator
338  CS_turnOnLFXT(CS_LFXT_DRIVE_3);
339 }
340 
341 
342 /*
343  * Initialize the EUSCI B SPI
344  */
345 void Init_SPI()
346 {
347  struct EUSCI_B_SPI_initMasterParam SPIParam = {0};
348 
349  SPIParam.selectClockSource=EUSCI_B_SPI_CLOCKSOURCE_SMCLK;
350  SPIParam.clockSourceFrequency=8000000;
351  SPIParam.desiredSpiClock=2000000;
352  SPIParam.msbFirst=EUSCI_B_SPI_MSB_FIRST;
353  SPIParam.clockPhase=EUSCI_B_SPI_PHASE_DATA_CAPTURED_ONFIRST_CHANGED_ON_NEXT;
354  SPIParam.clockPolarity=EUSCI_B_SPI_CLOCKPOLARITY_INACTIVITY_LOW;
355  SPIParam.spiMode=EUSCI_B_SPI_4PIN_UCxSTE_ACTIVE_HIGH;
356 
357 
358  EUSCI_B_SPI_initMaster(EUSCI_B0_BASE, &SPIParam);
359  EUSCI_B_SPI_select4PinFunctionality(EUSCI_B0_BASE,0x00);
360 
361  EUSCI_B_SPI_enable(EUSCI_B0_BASE);
362 }
363 
364 
365 /*
366  * PORT1 Interrupt Service Routine
367  * Handles Interrupt from the TCAN4550 on P1.5
368  */
369 #pragma vector = PORT1_VECTOR
370 __interrupt void PORT1_ISR(void)
371 {
372  switch(__even_in_range(P1IV, P1IV_P1IFG7))
373  {
374  case P1IV_NONE : break;
375  case P1IV_P1IFG0 : break;
376  case P1IV_P1IFG1 : break;
377  case P1IV_P1IFG2 : break;
378  case P1IV_P1IFG3 : break;
379  case P1IV_P1IFG4 : break;
380  case P1IV_P1IFG5 : TCAN_Int_Cnt++; break;
381  case P1IV_P1IFG6 : break;
382  case P1IV_P1IFG7 : break;
383  }
384 }
bool TCAN4x5x_MCAN_DisableProtectedRegisters(void)
Disable Protected MCAN Registers.
Definition: TCAN4550.c:96
uint32_t ID
CAN ID to send.
uint8_t DataTqBeforeSamplePoint
DTQBSP: Number of time quanta before sample point Valid values are: 2 to 33.
64 bytes of data payload
uint8_t FDF
CAN FD Format flag.
void Init_SPI(void)
Definition: main.c:345
TCAN4x5x_MRAM_Element_Data_Size TxBufferElementSize
TX Buffers element size: The number of bytes for the TX Buffers (data payload)
TCAN4x5x_SID_SFT_Values SFT
SFT Standard Filter Type.
uint8_t ESI
Error state indicator flag.
uint8_t SIDNumElements
Standard ID Number of Filter Elements: The number of 11-bit filters the user would like Valid range...
__interrupt void PORT1_ISR(void)
Definition: main.c:370
CAN message header for transmitted messages.
uint8_t FDOE
FDOE: Can FD mode enabled, master enable for CAN FD support.
uint32_t EFID1
EFID1[28:0].
Extended ID filter struct.
Classic Filter, EFID1 is the ID/filter, and EFID2 is the mask.
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x Valid range is: 1 to...
Struct containing the device interrupt enable bit field.
void TCAN4x5x_MCAN_ConfigureInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Configures the MCAN interrupt enable register.
Definition: TCAN4550.c:1191
volatile uint8_t TCAN_Int_Cnt
Definition: main.c:63
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
uint32_t TCAN4x5x_MCAN_WriteTXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_TX_Header *header, uint8_t dataPayload[])
Write CAN message to the specified TX buffer.
Definition: TCAN4550.c:926
uint8_t PWRON
DEV_IR[20] : PWRON, Power On Interrupt.
uint8_t NominalTqAfterSamplePoint
NTQASP: The total number of time quanta after the sample point Valid values are: 2 to 128...
uint8_t TxBufferNumElements
TX Buffers number of elements: The number of elements for the TX Buffers Valid range is: 0 to 32...
void Init_Clock(void)
Definition: main.c:328
uint8_t RF0NE
IE[0] RF0NE: Rx FIFO 0 new message.
void Init_GPIO(void)
Definition: main.c:254
bool TCAN4x5x_MCAN_ConfigureDataTiming_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Writes the MCAN data time settings, using the simple data timing struct.
Definition: TCAN4550.c:233
uint32_t EFID2
EFID2[28:0].
uint8_t EFC
Event FIFO Control flag, to store tx events or not.
uint8_t Rx1NumElements
RX FIFO 1 number of elements: The number of elements for the RX FIFO 1 Valid range is: 0 to 64...
void TCAN4x5x_MCAN_ReadInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Read the MCAN interrupts.
Definition: TCAN4550.c:1136
void TCAN4x5x_Device_ClearInterrupts(TCAN4x5x_Device_Interrupts *ir)
Clear the device interrupts.
Definition: TCAN4550.c:1278
uint8_t RxBufNumElements
RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO) Valid range...
void TCAN4x5x_MCAN_ClearInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Clear the MCAN interrupts.
Definition: TCAN4550.c:1150
Standard ID filter struct.
bool TCAN4x5x_Device_ConfigureInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Configures the device interrupt enable register.
Definition: TCAN4550.c:1320
Store in RX FIFO 0 and set a high priority message interrupt if the filter matches the incoming messa...
Classic filter with SFID1 as the ID to match, and SFID2 as the bit mask that applies to SFID1...
uint32_t ID
CAN ID received.
#define MCAN_DLC_4B
Definition: TCAN4x5x_Reg.h:143
bool TCAN4x5x_MCAN_WriteXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Write MCAN Extended ID filter into MRAM.
Definition: TCAN4550.c:1091
uint8_t XTD
Extended Identifier flag.
Defines the number of MRAM elements and the size of the elements.
Struct containing the MCAN interrupt enable bit field.
bool TCAN4x5x_Device_SetMode(TCAN4x5x_Device_Mode_Enum modeDefine)
Sets the TCAN4x5x device mode.
Definition: TCAN4550.c:1342
bool TCAN4x5x_MCAN_WriteSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Write MCAN Standard ID filter into MRAM.
Definition: TCAN4550.c:1052
struct containing the bit fields of the MCAN CCCR register
uint8_t Rx0NumElements
RX FIFO 0 number of elements: The number of elements for the RX FIFO 0 Valid range is: 0 to 64...
uint16_t SFID1
SFID1[10:0].
uint8_t RTR
Remote Transmission Request flag.
TCAN4x5x_SID_SFEC_Values SFEC
SFEC[2:0] Standard filter element configuration.
Used to setup the data timing parameters of the MCAN module This is a simplified struct, requiring only the prescaler value (1:x), number of time quanta before and after the sample point.
uint8_t TxEventFIFONumElements
TX Event FIFO number of elements: The number of elements for the TX Event FIFO Valid range is: 0 to...
TCAN4x5x_MRAM_Element_Data_Size RxBufElementSize
RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO...
Struct containing the device interrupt bit field.
uint8_t TCAN4x5x_MCAN_ReadNextFIFO(TCAN4x5x_MCAN_FIFO_Enum FIFODefine, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the next MCAN FIFO element.
Definition: TCAN4550.c:721
uint16_t SFID2
SFID2[10:0].
void TCAN4x5x_MCAN_ClearInterruptsAll(void)
Clear all MCAN interrupts.
Definition: TCAN4550.c:1162
uint8_t DataTqAfterSamplePoint
DTQASP: Number of time quanta after sample point Valid values are: 1 to 16.
void Init_CAN(void)
Definition: main.c:156
uint16_t NominalTqBeforeSamplePoint
NTQBSP: The total number of time quanta prior to sample point Valid values are: 2 to 257...
uint8_t XIDNumElements
Extended ID Number of Filter Elements: The number of 29-bit filters the user would like Valid range...
uint8_t RF0N
IR[0] RF0N: Rx FIFO 0 new message.
bool TCAN4x5x_MRAM_Configure(TCAN4x5x_MRAM_Config *MRAMConfig)
Configures the MRAM registers.
Definition: TCAN4550.c:507
uint8_t DataBitRatePrescaler
Prescaler value, interpreted as 1:x Valid range is: 1 to 32.
TCAN4x5x_MRAM_Element_Data_Size Rx0ElementSize
RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
bool TCAN4x5x_MCAN_EnableProtectedRegisters(void)
Enable Protected MCAN Registers.
Definition: TCAN4550.c:62
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Writes the MCAN nominal timing settings, using the simple nominal timing struct.
Definition: TCAN4550.c:413
Struct containing the MCAN interrupt bit field.
void TCAN4x5x_Device_ReadInterrupts(TCAN4x5x_Device_Interrupts *ir)
Read the device interrupts.
Definition: TCAN4550.c:1265
uint8_t BRSE
BRSE: Bit rate switch enabled for can FD. Master enable for bit rate switching support.
int main(void)
Definition: main.c:66
bool TCAN4x5x_MCAN_TransmitBufferContents(uint8_t bufIndex)
Transmit TX buffer contents of the specified tx buffer.
Definition: TCAN4550.c:1027
void TCAN4x5x_MRAM_Clear(void)
Clear (Zero-fill) the contents of MRAM.
Definition: TCAN4550.c:689
TCAN4x5x_MRAM_Element_Data_Size Rx1ElementSize
RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
TCAN4x5x_XID_EFT_Values EFT
EFT[1:0].
uint8_t DLC
Data length code.
uint8_t BRS
Bit rate switch used flag.
uint8_t MM
Message Marker, used if EFC is set to 1.
TCAN4x5x_XID_EFEC_Values EFEC
SFT Standard Filter Type.
uint8_t DAR
DAR: Disable automatic retransmission. If a transmission errors, gets a NACK, or loses arbitration...
Used to setup the nominal timing parameters of the MCAN module This is a simplified struct...
bool TCAN4x5x_MCAN_ConfigureCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Configure the MCAN CCCR Register.
Definition: TCAN4550.c:133