66 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 82 uint32_t readValue, firstRead;
91 for (i = 5; i > 0; i--)
123 for (i = 5; i > 0; i--)
152 uint32_t value, readValue;
155 value = cccrConfig->
word;
163 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 256 dataTiming->
TDCOffset = ((regData >> 8) & 0x7F);
257 dataTiming->
TDCFilter = (regData & 0x7F);
279 uint32_t writeValue, TDCOWriteValue;
287 else if (tempValue == 0)
290 writeValue = ((uint32_t)(tempValue - 1)) << 16;
296 else if (tempValue < 2)
299 writeValue |= ((uint32_t)(tempValue - 2)) << 8;
300 TDCOWriteValue = (uint32_t)(tempValue - 1) << 8;
305 else if (tempValue == 0)
308 writeValue |= ((uint32_t)(tempValue - 1)) << 4;
311 writeValue |= ((uint32_t)(tempValue - 1));
318 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 321 if (tempValue != writeValue)
326 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 329 if (tempValue != TDCOWriteValue)
355 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 362 writeValue |= ((uint32_t)(dataTiming->
DataTimeSeg2 & 0x0F)) << 4;
369 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 372 if (tempValue != writeValue)
376 writeValue = (uint32_t)(dataTiming->
TDCOffset & 0x7F) << 8;
377 writeValue |= (uint32_t)(dataTiming->
TDCFilter & 0x7F);
379 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 382 if (tempValue != writeValue)
387 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 390 if (tempValue != writeValue)
459 uint32_t writeValue, tempValue;
467 else if (tempValue == 0)
469 writeValue = ((uint32_t)(tempValue - 1)) << 16;
476 else if (tempValue < 2)
478 writeValue |= ((uint32_t)(tempValue - 2)) << 8;
484 else if (tempValue < 2)
486 writeValue |= ((uint32_t)(tempValue - 1));
487 writeValue |= ((uint32_t)(tempValue - 1)) << 25;
491 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 494 if (tempValue != writeValue)
517 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 526 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 529 if (tempValue != writeValue)
549 uint32_t writeValue, readValue;
555 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 559 if (readValue != writeValue)
586 uint16_t startAddress = 0x0000;
587 uint32_t registerValue = 0;
588 uint32_t readValue = 0;
600 registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
602 startAddress += (4 * (uint16_t)MRAMValue);
604 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 607 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 610 if (readValue != registerValue)
623 registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
625 startAddress += (8 * (uint16_t)MRAMValue);
627 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 630 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 633 if (readValue != registerValue)
646 registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
651 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 654 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 657 if (readValue != registerValue)
669 registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
673 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 676 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 679 if (readValue != registerValue)
693 registerValue = ((uint32_t)startAddress);
697 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 700 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 704 if (readValue != registerValue)
716 registerValue = ((uint32_t)(MRAMValue) << 16) | ((uint32_t)startAddress);
718 startAddress += (8 * (uint16_t)MRAMValue);
720 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 723 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 726 if (readValue != registerValue)
739 registerValue = ((uint32_t)(MRAMValue) << 24) | ((uint32_t)startAddress);
744 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 747 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 750 if (readValue != registerValue)
762 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 765 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 768 if (readValue != registerValue)
776 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 779 #ifdef TCAN4x5x_MCAN_VERIFY_CONFIGURATION_WRITES 782 if (readValue != registerValue)
804 while (curAddr < endAddr)
831 uint16_t startAddress;
832 uint8_t i, getIndex, elementSize;
840 if ((readData & 0x0000007F) == 0)
842 getIndex = (uint8_t) ((readData & 0x3F00) >> 8);
844 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 849 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
850 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 858 startAddress += (((uint32_t)elementSize + 8) * getIndex);
865 if ((readData & 0x0000007F) == 0)
867 getIndex = (uint8_t) ((readData & 0x3F00) >> 8);
869 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 874 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
875 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 880 readData = (readData & 0x70) >> 4;
883 startAddress += (((uint32_t)elementSize + 8) * getIndex);
892 header->
ESI = (readData & 0x80000000) >> 31;
893 header->
XTD = (readData & 0x40000000) >> 30;
894 header->
RTR = (readData & 0x20000000) >> 29;
897 header->
ID = (readData & 0x1FFFFFFF);
899 header->
ID = (readData & 0x1FFC0000) >> 18;
903 header->
RXTS = (readData & 0x0000FFFF);
904 header->
DLC = (readData & 0x000F0000) >> 16;
905 header->
BRS = (readData & 0x00100000) >> 20;
906 header->
FDF = (readData & 0x00200000) >> 21;
907 header->
FIDX = (readData & 0x7F000000) >> 24;
908 header->
ANMF = (readData & 0x80000000) >> 31;
917 if (elementSize > 0) {
920 while (i < elementSize) {
925 dataPayload[i] = (uint8_t)((readData >> ((i % 4) * 8)) & 0xFF);
967 uint16_t startAddress;
968 uint8_t i, getIndex, elementSize;
976 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 981 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
982 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 987 readData = (readData & 0x0700) >> 8;
990 startAddress += (((uint32_t)elementSize + 8) * getIndex);
997 header->
ESI = (readData & 0x80000000) >> 31;
998 header->
XTD = (readData & 0x40000000) >> 30;
999 header->
RTR = (readData & 0x20000000) >> 29;
1002 header->
ID = (readData & 0x1FFFFFFF);
1004 header->
ID = (readData & 0x1FFC0000) >> 18;
1008 header->
RXTS = (readData & 0x0000FFFF);
1009 header->
DLC = (readData & 0x000F0000) >> 16;
1010 header->
BRS = (readData & 0x00100000) >> 20;
1011 header->
FDF = (readData & 0x00200000) >> 21;
1012 header->
FIDX = (readData & 0x7F000000) >> 24;
1013 header->
ANMF = (readData & 0x80000000) >> 31;
1022 if (elementSize > 0) {
1025 while (i < elementSize) {
1030 dataPayload[i] = (uint8_t)((readData >> ((i % 4) * 8)) & 0xFF);
1032 if (i > elementSize)
1068 uint16_t startAddress;
1069 uint8_t i, elementSize, temp;
1073 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1078 startAddress = (uint16_t)(SPIData & 0x0000FFFF) + 0x8000;
1080 temp = (uint8_t)((SPIData >> 24) & 0x3F);
1081 elementSize = temp > 32 ? 32 : temp;
1083 temp = (uint8_t)((SPIData >> 16) & 0x3F);
1084 elementSize += temp > 32 ? 32 : temp;
1086 if (bufIndex > (elementSize-1)) {
1091 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1099 startAddress += ((uint32_t)elementSize * bufIndex);
1110 SPIData |= ((uint32_t)header->
ESI & 0x01) << 31;
1111 SPIData |= ((uint32_t)header->
XTD & 0x01) << 30;
1112 SPIData |= ((uint32_t)header->
RTR & 0x01) << 29;
1115 SPIData |= ((uint32_t)header->
ID & 0x1FFFFFFF);
1117 SPIData |= ((uint32_t)header->
ID & 0x07FF) << 18;
1122 SPIData |= ((uint32_t)header->
DLC & 0x0F) << 16;
1123 SPIData |= ((uint32_t)header->
BRS & 0x01) << 20;
1124 SPIData |= ((uint32_t)header->
FDF & 0x01) << 21;
1125 SPIData |= ((uint32_t)header->
EFC & 0x01) << 23;
1126 SPIData |= ((uint32_t)header->
MM & 0xFF) << 24;
1132 while (i < elementSize) {
1135 if ((elementSize - i) < 4) {
1136 while (i < elementSize)
1138 SPIData |= ((uint32_t)dataPayload[i] << ((i % 4) * 8));
1144 SPIData |= ((uint32_t)dataPayload[i++]);
1145 SPIData |= ((uint32_t)dataPayload[i++]) << 8;
1146 SPIData |= ((uint32_t)dataPayload[i++]) << 16;
1147 SPIData |= ((uint32_t)dataPayload[i++]) << 24;
1152 if (i > elementSize)
1157 return (uint32_t)1 << bufIndex;
1175 uint32_t writeValue;
1176 uint8_t requestedBuf = bufIndex;
1178 if (requestedBuf > 31)
1181 writeValue = 1 << requestedBuf;
1202 uint16_t startAddress;
1204 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1209 getIndex = (readData & 0x00FF0000) >> 16;
1210 if (filterIndex > getIndex)
1213 getIndex = filterIndex;
1215 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
1217 startAddress += (getIndex << 2);
1220 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1223 if (readData != filter->
word)
1244 uint16_t startAddress;
1246 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1251 getIndex = (readData & 0x00FF0000) >> 16;
1252 if (filterIndex > getIndex)
1255 getIndex = filterIndex;
1257 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
1259 startAddress += (getIndex << 2);
1279 uint32_t readData, writeData;
1280 uint16_t startAddress;
1282 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1287 getIndex = (readData & 0x00FF0000) >> 16;
1288 if (filterIndex > getIndex)
1291 getIndex = filterIndex;
1293 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
1295 startAddress += (getIndex << 3);
1298 writeData = (uint32_t)(filter->
EFEC) << 29;
1299 writeData |= (uint32_t)(filter->
EFID1);
1301 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1303 if (readData != writeData)
1308 writeData = (uint32_t)(filter->
EFT) << 30;
1309 writeData |= (uint32_t)(filter->
EFID2);
1311 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1313 if (readData != writeData)
1335 uint16_t startAddress;
1337 #ifdef TCAN4x5x_MCAN_CACHE_CONFIGURATION 1342 getIndex = (readData & 0x00FF0000) >> 16;
1343 if (filterIndex > getIndex)
1346 getIndex = filterIndex;
1348 startAddress = (uint16_t)(readData & 0x0000FFFF) +
REG_MRAM;
1350 startAddress += (getIndex << 3);
1356 filter->
EFID1 = readData & 0x1FFFFFFF;
1360 filter->
EFID2 = readData & 0x1FFFFFFF;
1445 static const uint8_t lookup[7] = {12, 16, 20, 24, 32, 48, 64};
1451 return lookup[(
unsigned int)(inputDLC-9)];
1467 static const uint8_t lookup[8] = {8, 12, 16, 20, 24, 32, 48, 64};
1468 return lookup[(
unsigned int)(inputESCValue & 0x07)];
1491 return (uint16_t)(readValue & 0xFFFF);
1535 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1538 if (readValue != readDevice)
1636 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1661 switch (modeDefine) {
1680 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1702 switch (readValue) {
1748 default:
return false;
1752 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1773 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1838 default:
return false;
1842 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1892 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES 1914 #ifdef TCAN4x5x_DEVICE_VERIFY_CONFIGURATION_WRITES bool TCAN4x5x_Device_EnableTestMode(TCAN4x5x_Device_Test_Mode_Enum modeDefine)
Sets the TCAN4x5x device test mode.
bool TCAN4x5x_MCAN_DisableProtectedRegisters(void)
Disable Protected MCAN Registers.
#define REG_BITS_DEVICE_MODE_WDT_EN
uint8_t DataTimeSeg1andProp
DTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value in this field + 1 ...
bool TCAN4x5x_MCAN_WriteSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Write MCAN Standard ID filter into MRAM.
uint8_t DataTqBeforeSamplePoint
DTQBSP: Number of time quanta before sample point Valid values are: 2 to 33.
uint8_t RESERVED1
Reserved.
TCAN4x5x_Device_Mode_Enum
TCAN4x5x_MRAM_Element_Data_Size TxBufferElementSize
TX Buffers element size: The number of bytes for the TX Buffers (data payload)
#define REG_BITS_DEVICE_MODE_DEVICEMODE_STANDBY
#define REG_BITS_DEVICE_MODE_TESTMODE_MASK
uint8_t TCAN4x5x_MCAN_ReadRXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the specified RX buffer element.
uint8_t SIDNumElements
Standard ID Number of Filter Elements: The number of 11-bit filters the user would like Valid range...
#define REG_BITS_DEVICE_MODE_WDT_ACTION_MASK
#define REG_BITS_DEVICE_MODE_NWKRQ_VOLT_MASK
#define REG_BITS_MCAN_DBTP_TDC_EN
#define REG_BITS_DEVICE_MODE_TESTMODE_PHY
uint32_t AHB_READ_BURST_READ(void)
void TCAN4x5x_Device_ClearInterruptsAll(void)
Clear all device interrupts.
bool TCAN4x5x_MCAN_WriteXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Write MCAN Extended ID filter into MRAM.
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Value interpreted as 1:x Valid range is: 1 to...
uint8_t NominalTimeSeg2
NTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
#define REG_BITS_MCAN_TSCC_COUNTER_EXTERNAL
Used to setup the timing parameters of the MCAN module This is the raw MCAN form of the struct which ...
Struct containing the device interrupt enable bit field.
uint32_t word
Full register as single 32-bit word.
#define REG_BITS_DEVICE_MODE_FORCED_SET_BITS
uint8_t DataTimeSeg2
DTSEG2: Data time segment 2. Interpreted by MCAN as the value is this field + 1 Valid values are: 0...
void TCAN4x5x_MCAN_ConfigureInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Configures the MCAN interrupt enable register.
uint32_t word
full register as single 32-bit word
void TCAN4x5x_MCAN_ReadDataTimingFD_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Reads the MCAN data time settings, using the simple struct.
#define REG_DEV_MODES_AND_PINS
void AHB_READ_BURST_END(void)
#define TCAN4x5x_MCAN_CACHE_RXF1C
#define REG_BITS_DEVICE_MODE_INH_MASK
bool TCAN4x5x_MCAN_ConfigureGlobalFilter(TCAN4x5x_MCAN_Global_Filter_Configuration *gfc)
Configures the MCAN global filter configuration register, using the passed Global Filter Configuratio...
uint8_t NominalTqAfterSamplePoint
NTQASP: The total number of time quanta after the sample point Valid values are: 2 to 128...
uint8_t RESERVED2
Reserved.
uint8_t TxBufferNumElements
TX Buffers number of elements: The number of elements for the TX Buffers Valid range is: 0 to 32...
uint16_t TCAN4x5x_Device_ReadDeviceVersion(void)
Read the TCAN4x5x device version register.
void AHB_READ_BURST_START(uint16_t address, uint8_t words)
uint32_t TCAN4x5x_MCAN_CACHE[9]
#define REG_BITS_DEVICE_MODE_WD_TIMER_60MS
#define REG_BITS_DEVICE_MODE_GPO1_MODE_MASK
TCAN4x5x_XID_EFT_Values EFT
EFT[1:0].
#define REG_BITS_DEVICE_MODE_WD_TIMER_6S
Struct containing the register values for the Global Filter Configuration Register.
#define TCAN4x5x_MCAN_CACHE_RXBC
void TCAN4x5x_MCAN_ReadCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Read the MCAN CCCR configuration register.
uint8_t TCAN4x5x_MCAN_DLCtoBytes(uint8_t inputDLC)
Converts the CAN message DLC hex value to the number of bytes it corresponds to.
uint8_t NominalSyncJumpWidth
NSJW: Nominal time Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 ...
Used to setup the nominal timing parameters of the MCAN module This is the raw MCAN form of the struc...
#define REG_BITS_DEVICE_MODE_NWKRQ_CONFIG_MASK
bool TCAN4x5x_MCAN_ConfigureDataTiming_Simple(TCAN4x5x_MCAN_Data_Timing_Simple *dataTiming)
Writes the MCAN data time settings, using the simple data timing struct.
#define REG_BITS_DEVICE_MODE_WDT_RESET_BIT
uint8_t NominalTimeSeg1andProp
NTSEG1: Data time segment 1 + prop segment value. Interpreted by MCAN as the value is this field + 1 ...
uint32_t word
Full word for register.
uint8_t Rx1NumElements
RX FIFO 1 number of elements: The number of elements for the RX FIFO 1 Valid range is: 0 to 64...
#define REG_BITS_DEVICE_MODE_GPO1_FUNC_MASK
#define REG_BITS_MCAN_CCCR_CSR
void TCAN4x5x_MCAN_ReadInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Read the MCAN interrupts.
#define REG_BITS_MCAN_ILE_EINT0
bool TCAN4x5x_MCAN_ReadSIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_SID_Filter *filter)
Read a MCAN Standard ID filter from MRAM.
#define TCAN4x5x_MCAN_CACHE_TXEFC
#define REG_BITS_DEVICE_MODE_TESTMODE_ENMASK
uint8_t DataSyncJumpWidth
DSJW: Data Resynchronization jump width. Interpreted by MCAN as the value is this field + 1 Valid v...
#define TCAN4x5x_MCAN_CACHE_SIDFC
void TCAN4x5x_Device_ClearInterrupts(TCAN4x5x_Device_Interrupts *ir)
Clear the device interrupts.
#define REG_BITS_DEVICE_MODE_DEVICEMODE_SLEEP
uint8_t RxBufNumElements
RX Buffers number of elements: The number of elements for the RX Buffers (Not the FIFO) Valid range...
void TCAN4x5x_MCAN_ReadNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Reads the MCAN nominal/arbitration time settings, using the simple timing struct. ...
uint32_t word
Full register as single 32-bit word.
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Raw(TCAN4x5x_MCAN_Nominal_Timing_Raw *nomTiming)
Writes the MCAN nominal timing settings, using the raw MCAN nominal timing struct.
#define TCAN4x5x_MCAN_CACHE_XIDFC
uint32_t EFID2
EFID2[28:0].
#define REG_BITS_DEVICE_MODE_GPO2_MASK
#define REG_BITS_DEVICE_MODE_DEVICEMODE_NORMAL
void TCAN4x5x_MCAN_ClearInterrupts(TCAN4x5x_MCAN_Interrupts *ir)
Clear the MCAN interrupts.
void TCAN4x5x_MCAN_ReadInterruptEnable(TCAN4x5x_MCAN_Interrupt_Enable *ie)
Read the MCAN interrupt enable register.
void TCAN4x5x_Device_ReadConfig(TCAN4x5x_DEV_CONFIG *devCfg)
Reads the device mode and pin register.
#define REG_BITS_MCAN_CCCR_CSA
Standard ID filter struct.
#define REG_BITS_DEVICE_IE_MASK
#define REG_BITS_DEVICE_MODE_WD_TIMER_MASK
uint32_t EFID1
EFID1[28:0].
#define TCAN4x5x_MCAN_CACHE_RXESC
uint32_t word
Full register as single 32-bit word.
bool TCAN4x5x_Device_ConfigureInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Configures the device interrupt enable register.
TCAN4x5x_XID_EFEC_Values EFEC
SFT Standard Filter Type.
uint32_t word
Full word of register.
#define REG_BITS_MCAN_CCCR_INIT
#define REG_BITS_MCAN_RXF0C_F0OM_OVERWRITE
uint8_t RESERVED3
DEV_MODE_PINS[21:20] : RESERVED. Use test mode functions to enable test modes.
#define REG_BITS_MCAN_GFC_MASK
void TCAN4x5x_Device_ClearSPIERR(void)
Clears a SPIERR flag that may be set.
uint8_t TCAN4x5x_MCAN_ReadNextFIFO(TCAN4x5x_MCAN_FIFO_Enum FIFODefine, TCAN4x5x_MCAN_RX_Header *header, uint8_t dataPayload[])
Read the next MCAN FIFO element.
uint32_t TCAN4x5x_MCAN_WriteTXBuffer(uint8_t bufIndex, TCAN4x5x_MCAN_TX_Header *header, uint8_t dataPayload[])
Write CAN message to the specified TX buffer.
void TCAN4x5x_Device_ReadInterruptEnable(TCAN4x5x_Device_Interrupt_Enable *ie)
Read the device interrupt enable register.
#define REG_BITS_DEVICE_MODE_WAKE_PIN_MASK
#define REG_BITS_DEVICE_MODE_SWE_MASK
Defines the number of MRAM elements and the size of the elements.
Struct containing the MCAN interrupt enable bit field.
uint8_t DataBitRatePrescaler
DBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
#define REG_BITS_DEVICE_MODE_DEVICEMODE_MASK
bool TCAN4x5x_Device_SetMode(TCAN4x5x_Device_Mode_Enum modeDefine)
Sets the TCAN4x5x device mode.
struct containing the bit fields of the MCAN CCCR register
bool TCAN4x5x_WDT_Disable(void)
Disable the watchdog timer.
uint8_t Rx0NumElements
RX FIFO 0 number of elements: The number of elements for the RX FIFO 0 Valid range is: 0 to 64...
#define REG_BITS_MCAN_CCCR_RESERVED_MASK
uint32_t word
Full register as single 32-bit word.
void AHB_WRITE_BURST_WRITE(uint32_t data)
TCAN4x5x_Device_Test_Mode_Enum TCAN4x5x_Device_ReadTestMode(void)
Reads the TCAN4x5x device test mode.
Used to setup the data timing parameters of the MCAN module This is a simplified struct, requiring only the prescaler value (1:x), number of time quanta before and after the sample point.
uint8_t TxEventFIFONumElements
TX Event FIFO number of elements: The number of elements for the TX Event FIFO Valid range is: 0 to...
#define REG_BITS_DEVICE_MODE_TESTMODE_EN
bool TCAN4x5x_MCAN_ReadXIDFilter(uint8_t filterIndex, TCAN4x5x_MCAN_XID_Filter *filter)
Read MCAN Extended ID filter from MRAM.
TCAN4x5x_MRAM_Element_Data_Size RxBufElementSize
RX Buffers element size: The number of bytes for the RX Buffers (data payload), not the FIFO...
void TCAN4x5x_MCAN_ReadNominalTiming_Raw(TCAN4x5x_MCAN_Nominal_Timing_Raw *nomTiming)
Reads the MCAN nominal/arbitration time settings, using the raw MCAN timing struct.
uint8_t TDCFilter
TDCFilter: Transmitter delay compensation Filter Window Length Valid values are 0 to 127 mtq...
uint8_t TDCOffset
TDCO: Transmitter delay compensation offset Valid values are 0 to 127 mtq.
Struct containing the device interrupt bit field.
void AHB_WRITE_BURST_END(void)
uint8_t CSR
CSR: Clock stop request.
void TCAN4x5x_MCAN_ClearInterruptsAll(void)
Clear all MCAN interrupts.
uint8_t DataTqAfterSamplePoint
DTQASP: Number of time quanta after sample point Valid values are: 1 to 16.
TCAN4x5x_Device_Test_Mode_Enum
uint8_t RESERVED5
DEV_MODE_PINS[29:28] : RESERVED. Use watchdog functions to set watchdog parameters.
uint32_t word
Full register as single 32-bit word.
uint32_t AHB_READ_32(uint16_t address)
#define TCAN4x5x_MCAN_CACHE_TXBC
uint8_t RESERVED4
DEV_MODE_PINS[26:24] : RESERVED.
void TCAN4x5x_MCAN_ReadDataTimingFD_Raw(TCAN4x5x_MCAN_Data_Timing_Raw *dataTiming)
Reads the MCAN data time settings, using the raw MCAN struct.
#define REG_BITS_DEVICE_MODE_TESTMODE_CONTROLLER
uint16_t NominalTqBeforeSamplePoint
NTQBSP: The total number of time quanta prior to sample point Valid values are: 2 to 257...
void TCAN4x5x_WDT_Reset(void)
Reset the watchdog timer.
bool TCAN4x5x_Device_DisableTestMode(void)
Disables the TCAN4x5x device test mode.
Extended ID filter struct.
#define REG_BITS_DEVICE_MODE_FAIL_SAFE_MASK
uint8_t XIDNumElements
Extended ID Number of Filter Elements: The number of 29-bit filters the user would like Valid range...
#define TCAN4x5x_MCAN_CACHE_RXF0C
bool TCAN4x5x_MRAM_Configure(TCAN4x5x_MRAM_Config *MRAMConfig)
Configures the MRAM registers.
uint8_t DataBitRatePrescaler
Prescaler value, interpreted as 1:x Valid range is: 1 to 32.
bool TCAN4x5x_WDT_Configure(TCAN4x5x_WDT_Timer_Enum WDTtimeout)
Configure the watchdog.
bool TCAN4x5x_WDT_Enable(void)
Enable the watchdog timer.
TCAN4x5x_MRAM_Element_Data_Size Rx0ElementSize
RX FIFO 0 element size: The number of bytes for the RX 0 FIFO (data payload)
void AHB_WRITE_BURST_START(uint16_t address, uint8_t words)
bool TCAN4x5x_MCAN_EnableProtectedRegisters(void)
Enable Protected MCAN Registers.
bool TCAN4x5x_MCAN_ConfigureNominalTiming_Simple(TCAN4x5x_MCAN_Nominal_Timing_Simple *nomTiming)
Writes the MCAN nominal timing settings, using the simple nominal timing struct.
#define REG_BITS_DEVICE_MODE_WD_TIMER_3S
Struct containing the MCAN interrupt bit field.
#define REG_BITS_DEVICE_MODE_WD_CLK_MASK
#define REG_BITS_DEVICE_MODE_DEVICE_RESET
void TCAN4x5x_Device_ReadInterrupts(TCAN4x5x_Device_Interrupts *ir)
Read the device interrupts.
bool TCAN4x5x_MCAN_TransmitBufferContents(uint8_t bufIndex)
Transmit TX buffer contents of the specified tx buffer.
void TCAN4x5x_MRAM_Clear(void)
Clear (Zero-fill) the contents of MRAM.
TCAN4x5x_MRAM_Element_Data_Size Rx1ElementSize
RX FIFO 1 element size: The number of bytes for the RX 1 FIFO (data payload)
TCAN4x5x_WDT_Timer_Enum TCAN4x5x_WDT_Read(void)
Read the watchdog configuration.
#define TCAN4x5x_MCAN_CACHE_TXESC
uint16_t NominalBitRatePrescaler
NBRP: The prescaler value from the MCAN system clock. Interpreted by MCAN as the value is this field ...
#define REG_BITS_DEVICE_MODE_WDT_MASK
#define REG_BITS_MCAN_TXBC_TFQM
#define REG_BITS_DEVICE_MODE_WD_TIMER_600MS
TCAN4x5x_Device_Mode_Enum TCAN4x5x_Device_ReadMode(void)
Reads the TCAN4x5x device mode.
uint8_t RESERVED0
DEV_MODE_PINS[0] : Test mode configuration. Reserved in this struct It is recommended to use the test...
uint8_t TCAN4x5x_MCAN_TXRXESC_DataByteValue(uint8_t inputESCValue)
Converts the MCAN ESC (Element Size) value to number of bytes that it corresponds to...
#define REG_BITS_MCAN_CCCR_CCE
Used to setup the nominal timing parameters of the MCAN module This is a simplified struct...
bool TCAN4x5x_Device_Configure(TCAN4x5x_DEV_CONFIG *devCfg)
Configures the device mode and pin register.
bool TCAN4x5x_MCAN_ConfigureDataTiming_Raw(TCAN4x5x_MCAN_Data_Timing_Raw *dataTiming)
Writes the MCAN data time settings, using the raw MCAN data timing struct.
bool TCAN4x5x_MCAN_ConfigureCCCRRegister(TCAN4x5x_MCAN_CCCR_Config *cccrConfig)
Configure the MCAN CCCR Register.
void AHB_WRITE_32(uint16_t address, uint32_t data)