Altium

Design Rule Verification Report

Date: 6/17/2020
Time: 2:17:19 PM
Elapsed Time: 00:00:14
Filename: C:\Users\a0132932\Desktop\DRV84xx\MD028 DRV8428xEVM design\hardware\E1\MD028E1_PCB.PcbDoc
Warnings: 0
Rule Violations: 0
Waived Violations: 4

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=20mil) (OnCopper and InPoly),(IsKeepOut) 0
Clearance Constraint (Gap=40mil) (OnCopper and InComponentClass('Mounting Holes')),(IsKeepOut) 0
Clearance Constraint (Gap=20mil) (OnCopper and Not InComponentClass('Logo') and not InComponentClass('FiducialMark') and not InRegion(1000,500,4000,800) and Not IsKeepout),(IsKeepOut) 0
Clearance Constraint (Gap=7.874mil) (All),(All) 0
Clearance Constraint (Gap=25mil) (InPolygon),(All) 0
Clearance Constraint (Gap=0mil) (((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut),(((IsTrack Or IsArc) And Not InPoly) And IsFree and IsKeepOut) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Width Constraint (Min=6mil) (Max=100mil) (Preferred=10mil) (All) 0
Routing Layers(All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=40mil) (PreferredHoleWidth=16mil) (MinWidth=19.874mil) (MaxWidth=65mil) (PreferedWidth=34mil) (All) 0
Routing Via (MinHoleWidth=7.874mil) (MaxHoleWidth=12.992mil) (PreferredHoleWidth=7.874mil) (MinWidth=19.685mil) (MaxWidth=23.622mil) (PreferedWidth=19.685mil) (IsVia and InAnyComponent) 0
Differential Pairs Uncoupled Length using the Gap Constraints (Min=10mil) (Max=100mil) (Prefered=10mil) and Width Constraints (Min=15mil) (Max=15mil) (Prefered=15mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=10mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Minimum Annular Ring (Minimum=5mil) (All) 0
Minimum Annular Ring (Minimum=5.906mil) (IsVia and InAnyComponent) 0
Acute Angle Constraint (Minimum=45.000) (All) 0
Hole Size Constraint (Min=7.874mil) (Max=251mil) (All) 0
Pads and Vias to follow the Drill pairs settings 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0.7mil) (InComponentClass('Logo')),(InComponentClass('Logo')) 0
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 0
Silk To Solder Mask (Clearance=3mil) (All),(All) 0
Silk to Silk (Clearance=0mil) ((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))),((HasFootprint('Pb-Free_Overlay_Medium') OR HasFootprint('Pb-Free_Overlay_Small'))) 0
Silk to Silk (Clearance=3mil) (All),(All) 0
Net Antennae (Tolerance=0mil) (All) 0
Component Clearance Constraint ( Horizontal Gap = 5mil, Vertical Gap = 10mil ) ((HasFootprint('NY PMS 440 0025 PH'))),((HasFootprint('Keystone_1902C'))) 0
Component Clearance Constraint ( Horizontal Gap = 250mil, Vertical Gap = Infinite ) (InComponentClass('Mounting Holes')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Logo')),(All) 0
Component Clearance Constraint ( Horizontal Gap = 50mil, Vertical Gap = 10mil ) (InComponentClass('Mounting Holes')),(InComponentClass('FiducialMark')) 0
Component Clearance Constraint ( Horizontal Gap = 0mil, Vertical Gap = 0mil ) (InComponentClass('Header')),(InComponentClass('Shunt')) 0
Component Clearance Constraint ( Horizontal Gap = 118.11mil, Vertical Gap = 30mil ) (IsThruComponent),(IsThruComponent) 0
Component Clearance Constraint ( Horizontal Gap = 40mil, Vertical Gap = 10mil ) (All),(All) 0
Component Clearance Constraint ( Horizontal Gap = 20mil, Vertical Gap = 10mil ) (HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')),(HasFootprint('0201*') or HasFootprint('0402*') or HasFootprint('0508') or HasFootprint('0603*') or HasFootprint('0612') or HasFootprint('0805*') or HasFootprint('0815*') or HasFootprint('0830*') or HasFootprint('1206*') or HasFootprint('1210*') or HasFootprint('1808*') or HasFootprint('1812*') or HasFootprint('1825*') or HasFootprint('2010*') or HasFootprint('2220*') or HasFootprint('2225*') or HasFootprint('2512*') or HasFootprint('2728*') or HasFootprint('3518*')) 0
Component Clearance Constraint ( Horizontal Gap = 100mil, Vertical Gap = 30mil ) (IsThruComponent),(IsSMTComponent) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 0

Waived Violations Count
Clearance Constraint (Gap=7.874mil) (All),(All) 3
Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All) 1
Total 4

Rule Violations

Waived Violations

Clearance Constraint (Gap=7.874mil) (All),(All)
Clearance Constraint: (Collision < 7.874mil) Between Arc (1939mil,2940mil) on Top Layer And Pad FID2-1(1939mil,2940mil) on Top Layer
Waived by Wang Li at 5/14/2020 5:16:00 PM
Clearance Constraint: (Collision < 7.874mil) Between Arc (1940mil,60.153mil) on Top Layer And Pad FID3-1(1940mil,60.153mil) on Top Layer
Waived by Wang Li at 5/14/2020 5:15:45 PM
Clearance Constraint: (Collision < 7.874mil) Between Arc (59mil,2940.315mil) on Top Layer And Pad FID1-1(59mil,2940.315mil) on Top Layer
Waived by Wang Li at 5/14/2020 5:15:04 PM
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Minimum Solder Mask Sliver (Gap=3.937mil) (All),(All)
Minimum Solder Mask Sliver Constraint: (3.937mil < 3.937mil) Between Pad J6-5(1579.771mil,2835.386mil) on Top Layer And Pad J6-6(1534.004mil,2849.166mil) on Top Layer [Top Solder] Mask Sliver [3.937mil]
Waived by James Lockridge at 1/4/2019 1:16:08 PM
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